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[PATCH] Input: convert hdaps to dynamic input_dev allocation.
[linux-2.6/x86.git] / drivers / net / 8139too.c
blob30bee11c48bd2d8364ac8f8e93abe47c5467593e
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.27"
94
95
96 #include <linux/config.h>
97 #include <linux/module.h>
98 #include <linux/kernel.h>
99 #include <linux/compiler.h>
100 #include <linux/pci.h>
101 #include <linux/init.h>
102 #include <linux/ioport.h>
103 #include <linux/netdevice.h>
104 #include <linux/etherdevice.h>
105 #include <linux/rtnetlink.h>
106 #include <linux/delay.h>
107 #include <linux/ethtool.h>
108 #include <linux/mii.h>
109 #include <linux/completion.h>
110 #include <linux/crc32.h>
111 #include <asm/io.h>
112 #include <asm/uaccess.h>
113 #include <asm/irq.h>
114
115 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
116 #define PFX DRV_NAME ": "
117
118 /* Default Message level */
119 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
120 NETIF_MSG_PROBE | \
121 NETIF_MSG_LINK)
122
123
124 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
125 #ifdef CONFIG_8139TOO_PIO
126 #define USE_IO_OPS 1
127 #endif
128
129 /* define to 1, 2 or 3 to enable copious debugging info */
130 #define RTL8139_DEBUG 0
131
132 /* define to 1 to disable lightweight runtime debugging checks */
133 #undef RTL8139_NDEBUG
134
135
136 #if RTL8139_DEBUG
137 /* note: prints function name for you */
138 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
139 #else
140 # define DPRINTK(fmt, args...)
141 #endif
142
143 #ifdef RTL8139_NDEBUG
144 # define assert(expr) do {} while (0)
145 #else
146 # define assert(expr) \
147 if(unlikely(!(expr))) { \
148 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
149 #expr,__FILE__,__FUNCTION__,__LINE__); \
150 }
151 #endif
152
153
154 /* A few user-configurable values. */
155 /* media options */
156 #define MAX_UNITS 8
157 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
158 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
159
160 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
161 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
162 static int multicast_filter_limit = 32;
163
164 /* bitmapped message enable number */
165 static int debug = -1;
166
167 /*
168 * Receive ring size
169 * Warning: 64K ring has hardware issues and may lock up.
170 */
171 #if defined(CONFIG_SH_DREAMCAST)
172 #define RX_BUF_IDX 1 /* 16K ring */
173 #else
174 #define RX_BUF_IDX 2 /* 32K ring */
175 #endif
176 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
177 #define RX_BUF_PAD 16
178 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
179
180 #if RX_BUF_LEN == 65536
181 #define RX_BUF_TOT_LEN RX_BUF_LEN
182 #else
183 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
184 #endif
185
186 /* Number of Tx descriptor registers. */
187 #define NUM_TX_DESC 4
188
189 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
190 #define MAX_ETH_FRAME_SIZE 1536
191
192 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
193 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
194 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
195
196 /* PCI Tuning Parameters
197 Threshold is bytes transferred to chip before transmission starts. */
198 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
199
200 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
201 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
202 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
203 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
204 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
205
206 /* Operational parameters that usually are not changed. */
207 /* Time in jiffies before concluding the transmitter is hung. */
208 #define TX_TIMEOUT (6*HZ)
209
210
211 enum {
212 HAS_MII_XCVR = 0x010000,
213 HAS_CHIP_XCVR = 0x020000,
214 HAS_LNK_CHNG = 0x040000,
215 };
216
217 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
218 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
219 #define RTL_MIN_IO_SIZE 0x80
220 #define RTL8139B_IO_SIZE 256
221
222 #define RTL8129_CAPS HAS_MII_XCVR
223 #define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
224
225 typedef enum {
226 RTL8139 = 0,
227 RTL8129,
228 } board_t;
229
230
231 /* indexed by board_t, above */
232 static struct {
233 const char *name;
234 u32 hw_flags;
235 } board_info[] __devinitdata = {
236 { "RealTek RTL8139", RTL8139_CAPS },
237 { "RealTek RTL8129", RTL8129_CAPS },
238 };
239
240
241 static struct pci_device_id rtl8139_pci_tbl[] = {
242 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
261
262 #ifdef CONFIG_SH_SECUREEDGE5410
263 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
264 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
265 #endif
266 #ifdef CONFIG_8139TOO_8129
267 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
268 #endif
269
270 /* some crazy cards report invalid vendor ids like
271 * 0x0001 here. The other ids are valid and constant,
272 * so we simply don't match on the main vendor id.
273 */
274 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
275 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
276 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
277
278 {0,}
279 };
280 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
281
282 static struct {
283 const char str[ETH_GSTRING_LEN];
284 } ethtool_stats_keys[] = {
285 { "early_rx" },
286 { "tx_buf_mapped" },
287 { "tx_timeouts" },
288 { "rx_lost_in_ring" },
289 };
290
291 /* The rest of these values should never change. */
292
293 /* Symbolic offsets to registers. */
294 enum RTL8139_registers {
295 MAC0 = 0, /* Ethernet hardware address. */
296 MAR0 = 8, /* Multicast filter. */
297 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
298 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
299 RxBuf = 0x30,
300 ChipCmd = 0x37,
301 RxBufPtr = 0x38,
302 RxBufAddr = 0x3A,
303 IntrMask = 0x3C,
304 IntrStatus = 0x3E,
305 TxConfig = 0x40,
306 RxConfig = 0x44,
307 Timer = 0x48, /* A general-purpose counter. */
308 RxMissed = 0x4C, /* 24 bits valid, write clears. */
309 Cfg9346 = 0x50,
310 Config0 = 0x51,
311 Config1 = 0x52,
312 FlashReg = 0x54,
313 MediaStatus = 0x58,
314 Config3 = 0x59,
315 Config4 = 0x5A, /* absent on RTL-8139A */
316 HltClk = 0x5B,
317 MultiIntr = 0x5C,
318 TxSummary = 0x60,
319 BasicModeCtrl = 0x62,
320 BasicModeStatus = 0x64,
321 NWayAdvert = 0x66,
322 NWayLPAR = 0x68,
323 NWayExpansion = 0x6A,
324 /* Undocumented registers, but required for proper operation. */
325 FIFOTMS = 0x70, /* FIFO Control and test. */
326 CSCR = 0x74, /* Chip Status and Configuration Register. */
327 PARA78 = 0x78,
328 PARA7c = 0x7c, /* Magic transceiver parameter register. */
329 Config5 = 0xD8, /* absent on RTL-8139A */
330 };
331
332 enum ClearBitMasks {
333 MultiIntrClear = 0xF000,
334 ChipCmdClear = 0xE2,
335 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
336 };
337
338 enum ChipCmdBits {
339 CmdReset = 0x10,
340 CmdRxEnb = 0x08,
341 CmdTxEnb = 0x04,
342 RxBufEmpty = 0x01,
343 };
344
345 /* Interrupt register bits, using my own meaningful names. */
346 enum IntrStatusBits {
347 PCIErr = 0x8000,
348 PCSTimeout = 0x4000,
349 RxFIFOOver = 0x40,
350 RxUnderrun = 0x20,
351 RxOverflow = 0x10,
352 TxErr = 0x08,
353 TxOK = 0x04,
354 RxErr = 0x02,
355 RxOK = 0x01,
356
357 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
358 };
359
360 enum TxStatusBits {
361 TxHostOwns = 0x2000,
362 TxUnderrun = 0x4000,
363 TxStatOK = 0x8000,
364 TxOutOfWindow = 0x20000000,
365 TxAborted = 0x40000000,
366 TxCarrierLost = 0x80000000,
367 };
368 enum RxStatusBits {
369 RxMulticast = 0x8000,
370 RxPhysical = 0x4000,
371 RxBroadcast = 0x2000,
372 RxBadSymbol = 0x0020,
373 RxRunt = 0x0010,
374 RxTooLong = 0x0008,
375 RxCRCErr = 0x0004,
376 RxBadAlign = 0x0002,
377 RxStatusOK = 0x0001,
378 };
379
380 /* Bits in RxConfig. */
381 enum rx_mode_bits {
382 AcceptErr = 0x20,
383 AcceptRunt = 0x10,
384 AcceptBroadcast = 0x08,
385 AcceptMulticast = 0x04,
386 AcceptMyPhys = 0x02,
387 AcceptAllPhys = 0x01,
388 };
389
390 /* Bits in TxConfig. */
391 enum tx_config_bits {
392
393 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
394 TxIFGShift = 24,
395 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
396 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
397 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
398 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
399
400 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
401 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
402 TxClearAbt = (1 << 0), /* Clear abort (WO) */
403 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
404 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
405
406 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
407 };
408
409 /* Bits in Config1 */
410 enum Config1Bits {
411 Cfg1_PM_Enable = 0x01,
412 Cfg1_VPD_Enable = 0x02,
413 Cfg1_PIO = 0x04,
414 Cfg1_MMIO = 0x08,
415 LWAKE = 0x10, /* not on 8139, 8139A */
416 Cfg1_Driver_Load = 0x20,
417 Cfg1_LED0 = 0x40,
418 Cfg1_LED1 = 0x80,
419 SLEEP = (1 << 1), /* only on 8139, 8139A */
420 PWRDN = (1 << 0), /* only on 8139, 8139A */
421 };
422
423 /* Bits in Config3 */
424 enum Config3Bits {
425 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
426 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
427 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
428 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
429 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
430 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
431 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
432 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
433 };
434
435 /* Bits in Config4 */
436 enum Config4Bits {
437 LWPTN = (1 << 2), /* not on 8139, 8139A */
438 };
439
440 /* Bits in Config5 */
441 enum Config5Bits {
442 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
443 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
444 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
445 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
446 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
447 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
448 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
449 };
450
451 enum RxConfigBits {
452 /* rx fifo threshold */
453 RxCfgFIFOShift = 13,
454 RxCfgFIFONone = (7 << RxCfgFIFOShift),
455
456 /* Max DMA burst */
457 RxCfgDMAShift = 8,
458 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
459
460 /* rx ring buffer length */
461 RxCfgRcv8K = 0,
462 RxCfgRcv16K = (1 << 11),
463 RxCfgRcv32K = (1 << 12),
464 RxCfgRcv64K = (1 << 11) | (1 << 12),
465
466 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
467 RxNoWrap = (1 << 7),
468 };
469
470 /* Twister tuning parameters from RealTek.
471 Completely undocumented, but required to tune bad links on some boards. */
472 enum CSCRBits {
473 CSCR_LinkOKBit = 0x0400,
474 CSCR_LinkChangeBit = 0x0800,
475 CSCR_LinkStatusBits = 0x0f000,
476 CSCR_LinkDownOffCmd = 0x003c0,
477 CSCR_LinkDownCmd = 0x0f3c0,
478 };
479
480 enum Cfg9346Bits {
481 Cfg9346_Lock = 0x00,
482 Cfg9346_Unlock = 0xC0,
483 };
484
485 typedef enum {
486 CH_8139 = 0,
487 CH_8139_K,
488 CH_8139A,
489 CH_8139A_G,
490 CH_8139B,
491 CH_8130,
492 CH_8139C,
493 CH_8100,
494 CH_8100B_8139D,
495 CH_8101,
496 } chip_t;
497
498 enum chip_flags {
499 HasHltClk = (1 << 0),
500 HasLWake = (1 << 1),
501 };
502
503 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
504 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
505 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
506
507 /* directly indexed by chip_t, above */
508 const static struct {
509 const char *name;
510 u32 version; /* from RTL8139C/RTL8139D docs */
511 u32 flags;
512 } rtl_chip_info[] = {
513 { "RTL-8139",
514 HW_REVID(1, 0, 0, 0, 0, 0, 0),
515 HasHltClk,
516 },
517
518 { "RTL-8139 rev K",
519 HW_REVID(1, 1, 0, 0, 0, 0, 0),
520 HasHltClk,
521 },
522
523 { "RTL-8139A",
524 HW_REVID(1, 1, 1, 0, 0, 0, 0),
525 HasHltClk, /* XXX undocumented? */
526 },
527
528 { "RTL-8139A rev G",
529 HW_REVID(1, 1, 1, 0, 0, 1, 0),
530 HasHltClk, /* XXX undocumented? */
531 },
532
533 { "RTL-8139B",
534 HW_REVID(1, 1, 1, 1, 0, 0, 0),
535 HasLWake,
536 },
537
538 { "RTL-8130",
539 HW_REVID(1, 1, 1, 1, 1, 0, 0),
540 HasLWake,
541 },
542
543 { "RTL-8139C",
544 HW_REVID(1, 1, 1, 0, 1, 0, 0),
545 HasLWake,
546 },
547
548 { "RTL-8100",
549 HW_REVID(1, 1, 1, 1, 0, 1, 0),
550 HasLWake,
551 },
552
553 { "RTL-8100B/8139D",
554 HW_REVID(1, 1, 1, 0, 1, 0, 1),
555 HasHltClk /* XXX undocumented? */
556 | HasLWake,
557 },
558
559 { "RTL-8101",
560 HW_REVID(1, 1, 1, 0, 1, 1, 1),
561 HasLWake,
562 },
563 };
564
565 struct rtl_extra_stats {
566 unsigned long early_rx;
567 unsigned long tx_buf_mapped;
568 unsigned long tx_timeouts;
569 unsigned long rx_lost_in_ring;
570 };
571
572 struct rtl8139_private {
573 void __iomem *mmio_addr;
574 int drv_flags;
575 struct pci_dev *pci_dev;
576 u32 msg_enable;
577 struct net_device_stats stats;
578 unsigned char *rx_ring;
579 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
580 unsigned int tx_flag;
581 unsigned long cur_tx;
582 unsigned long dirty_tx;
583 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
584 unsigned char *tx_bufs; /* Tx bounce buffer region. */
585 dma_addr_t rx_ring_dma;
586 dma_addr_t tx_bufs_dma;
587 signed char phys[4]; /* MII device addresses. */
588 char twistie, twist_row, twist_col; /* Twister tune state. */
589 unsigned int default_port:4; /* Last dev->if_port value. */
590 spinlock_t lock;
591 spinlock_t rx_lock;
592 chip_t chipset;
593 pid_t thr_pid;
594 wait_queue_head_t thr_wait;
595 struct completion thr_exited;
596 u32 rx_config;
597 struct rtl_extra_stats xstats;
598 int time_to_die;
599 struct mii_if_info mii;
600 unsigned int regs_len;
601 unsigned long fifo_copy_timeout;
602 };
603
604 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
605 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
606 MODULE_LICENSE("GPL");
607 MODULE_VERSION(DRV_VERSION);
608
609 module_param(multicast_filter_limit, int, 0);
610 module_param_array(media, int, NULL, 0);
611 module_param_array(full_duplex, int, NULL, 0);
612 module_param(debug, int, 0);
613 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
614 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
615 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
616 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
617
618 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
619 static int rtl8139_open (struct net_device *dev);
620 static int mdio_read (struct net_device *dev, int phy_id, int location);
621 static void mdio_write (struct net_device *dev, int phy_id, int location,
622 int val);
623 static void rtl8139_start_thread(struct net_device *dev);
624 static void rtl8139_tx_timeout (struct net_device *dev);
625 static void rtl8139_init_ring (struct net_device *dev);
626 static int rtl8139_start_xmit (struct sk_buff *skb,
627 struct net_device *dev);
628 static int rtl8139_poll(struct net_device *dev, int *budget);
629 #ifdef CONFIG_NET_POLL_CONTROLLER
630 static void rtl8139_poll_controller(struct net_device *dev);
631 #endif
632 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
633 struct pt_regs *regs);
634 static int rtl8139_close (struct net_device *dev);
635 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
636 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
637 static void rtl8139_set_rx_mode (struct net_device *dev);
638 static void __set_rx_mode (struct net_device *dev);
639 static void rtl8139_hw_start (struct net_device *dev);
640 static struct ethtool_ops rtl8139_ethtool_ops;
641
642 /* write MMIO register, with flush */
643 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
644 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
645 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
646 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
647
648
649 #define MMIO_FLUSH_AUDIT_COMPLETE 1
650 #if MMIO_FLUSH_AUDIT_COMPLETE
651
652 /* write MMIO register */
653 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
654 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
655 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
656
657 #else
658
659 /* write MMIO register, then flush */
660 #define RTL_W8 RTL_W8_F
661 #define RTL_W16 RTL_W16_F
662 #define RTL_W32 RTL_W32_F
663
664 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
665
666 /* read MMIO register */
667 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
668 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
669 #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
670
671
672 static const u16 rtl8139_intr_mask =
673 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
674 TxErr | TxOK | RxErr | RxOK;
675
676 static const u16 rtl8139_norx_intr_mask =
677 PCIErr | PCSTimeout | RxUnderrun |
678 TxErr | TxOK | RxErr ;
679
680 #if RX_BUF_IDX == 0
681 static const unsigned int rtl8139_rx_config =
682 RxCfgRcv8K | RxNoWrap |
683 (RX_FIFO_THRESH << RxCfgFIFOShift) |
684 (RX_DMA_BURST << RxCfgDMAShift);
685 #elif RX_BUF_IDX == 1
686 static const unsigned int rtl8139_rx_config =
687 RxCfgRcv16K | RxNoWrap |
688 (RX_FIFO_THRESH << RxCfgFIFOShift) |
689 (RX_DMA_BURST << RxCfgDMAShift);
690 #elif RX_BUF_IDX == 2
691 static const unsigned int rtl8139_rx_config =
692 RxCfgRcv32K | RxNoWrap |
693 (RX_FIFO_THRESH << RxCfgFIFOShift) |
694 (RX_DMA_BURST << RxCfgDMAShift);
695 #elif RX_BUF_IDX == 3
696 static const unsigned int rtl8139_rx_config =
697 RxCfgRcv64K |
698 (RX_FIFO_THRESH << RxCfgFIFOShift) |
699 (RX_DMA_BURST << RxCfgDMAShift);
700 #else
701 #error "Invalid configuration for 8139_RXBUF_IDX"
702 #endif
703
704 static const unsigned int rtl8139_tx_config =
705 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
706
707 static void __rtl8139_cleanup_dev (struct net_device *dev)
708 {
709 struct rtl8139_private *tp = netdev_priv(dev);
710 struct pci_dev *pdev;
711
712 assert (dev != NULL);
713 assert (tp->pci_dev != NULL);
714 pdev = tp->pci_dev;
715
716 #ifdef USE_IO_OPS
717 if (tp->mmio_addr)
718 ioport_unmap (tp->mmio_addr);
719 #else
720 if (tp->mmio_addr)
721 pci_iounmap (pdev, tp->mmio_addr);
722 #endif /* USE_IO_OPS */
723
724 /* it's ok to call this even if we have no regions to free */
725 pci_release_regions (pdev);
726
727 free_netdev(dev);
728 pci_set_drvdata (pdev, NULL);
729 }
730
731
732 static void rtl8139_chip_reset (void __iomem *ioaddr)
733 {
734 int i;
735
736 /* Soft reset the chip. */
737 RTL_W8 (ChipCmd, CmdReset);
738
739 /* Check that the chip has finished the reset. */
740 for (i = 1000; i > 0; i--) {
741 barrier();
742 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
743 break;
744 udelay (10);
745 }
746 }
747
748
749 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
750 struct net_device **dev_out)
751 {
752 void __iomem *ioaddr;
753 struct net_device *dev;
754 struct rtl8139_private *tp;
755 u8 tmp8;
756 int rc, disable_dev_on_err = 0;
757 unsigned int i;
758 unsigned long pio_start, pio_end, pio_flags, pio_len;
759 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
760 u32 version;
761
762 assert (pdev != NULL);
763
764 *dev_out = NULL;
765
766 /* dev and priv zeroed in alloc_etherdev */
767 dev = alloc_etherdev (sizeof (*tp));
768 if (dev == NULL) {
769 printk (KERN_ERR PFX "%s: Unable to alloc new net device\n", pci_name(pdev));
770 return -ENOMEM;
771 }
772 SET_MODULE_OWNER(dev);
773 SET_NETDEV_DEV(dev, &pdev->dev);
774
775 tp = netdev_priv(dev);
776 tp->pci_dev = pdev;
777
778 /* enable device (incl. PCI PM wakeup and hotplug setup) */
779 rc = pci_enable_device (pdev);
780 if (rc)
781 goto err_out;
782
783 pio_start = pci_resource_start (pdev, 0);
784 pio_end = pci_resource_end (pdev, 0);
785 pio_flags = pci_resource_flags (pdev, 0);
786 pio_len = pci_resource_len (pdev, 0);
787
788 mmio_start = pci_resource_start (pdev, 1);
789 mmio_end = pci_resource_end (pdev, 1);
790 mmio_flags = pci_resource_flags (pdev, 1);
791 mmio_len = pci_resource_len (pdev, 1);
792
793 /* set this immediately, we need to know before
794 * we talk to the chip directly */
795 DPRINTK("PIO region size == 0x%02X\n", pio_len);
796 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
797
798 #ifdef USE_IO_OPS
799 /* make sure PCI base addr 0 is PIO */
800 if (!(pio_flags & IORESOURCE_IO)) {
801 printk (KERN_ERR PFX "%s: region #0 not a PIO resource, aborting\n", pci_name(pdev));
802 rc = -ENODEV;
803 goto err_out;
804 }
805 /* check for weird/broken PCI region reporting */
806 if (pio_len < RTL_MIN_IO_SIZE) {
807 printk (KERN_ERR PFX "%s: Invalid PCI I/O region size(s), aborting\n", pci_name(pdev));
808 rc = -ENODEV;
809 goto err_out;
810 }
811 #else
812 /* make sure PCI base addr 1 is MMIO */
813 if (!(mmio_flags & IORESOURCE_MEM)) {
814 printk (KERN_ERR PFX "%s: region #1 not an MMIO resource, aborting\n", pci_name(pdev));
815 rc = -ENODEV;
816 goto err_out;
817 }
818 if (mmio_len < RTL_MIN_IO_SIZE) {
819 printk (KERN_ERR PFX "%s: Invalid PCI mem region size(s), aborting\n", pci_name(pdev));
820 rc = -ENODEV;
821 goto err_out;
822 }
823 #endif
824
825 rc = pci_request_regions (pdev, "8139too");
826 if (rc)
827 goto err_out;
828 disable_dev_on_err = 1;
829
830 /* enable PCI bus-mastering */
831 pci_set_master (pdev);
832
833 #ifdef USE_IO_OPS
834 ioaddr = ioport_map(pio_start, pio_len);
835 if (!ioaddr) {
836 printk (KERN_ERR PFX "%s: cannot map PIO, aborting\n", pci_name(pdev));
837 rc = -EIO;
838 goto err_out;
839 }
840 dev->base_addr = pio_start;
841 tp->mmio_addr = ioaddr;
842 tp->regs_len = pio_len;
843 #else
844 /* ioremap MMIO region */
845 ioaddr = pci_iomap(pdev, 1, 0);
846 if (ioaddr == NULL) {
847 printk (KERN_ERR PFX "%s: cannot remap MMIO, aborting\n", pci_name(pdev));
848 rc = -EIO;
849 goto err_out;
850 }
851 dev->base_addr = (long) ioaddr;
852 tp->mmio_addr = ioaddr;
853 tp->regs_len = mmio_len;
854 #endif /* USE_IO_OPS */
855
856 /* Bring old chips out of low-power mode. */
857 RTL_W8 (HltClk, 'R');
858
859 /* check for missing/broken hardware */
860 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
861 printk (KERN_ERR PFX "%s: Chip not responding, ignoring board\n",
862 pci_name(pdev));
863 rc = -EIO;
864 goto err_out;
865 }
866
867 /* identify chip attached to board */
868 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
869 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
870 if (version == rtl_chip_info[i].version) {
871 tp->chipset = i;
872 goto match;
873 }
874
875 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
876 printk (KERN_DEBUG PFX "%s: unknown chip version, assuming RTL-8139\n",
877 pci_name(pdev));
878 printk (KERN_DEBUG PFX "%s: TxConfig = 0x%lx\n", pci_name(pdev), RTL_R32 (TxConfig));
879 tp->chipset = 0;
880
881 match:
882 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
883 version, i, rtl_chip_info[i].name);
884
885 if (tp->chipset >= CH_8139B) {
886 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
887 DPRINTK("PCI PM wakeup\n");
888 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
889 (tmp8 & LWAKE))
890 new_tmp8 &= ~LWAKE;
891 new_tmp8 |= Cfg1_PM_Enable;
892 if (new_tmp8 != tmp8) {
893 RTL_W8 (Cfg9346, Cfg9346_Unlock);
894 RTL_W8 (Config1, tmp8);
895 RTL_W8 (Cfg9346, Cfg9346_Lock);
896 }
897 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
898 tmp8 = RTL_R8 (Config4);
899 if (tmp8 & LWPTN) {
900 RTL_W8 (Cfg9346, Cfg9346_Unlock);
901 RTL_W8 (Config4, tmp8 & ~LWPTN);
902 RTL_W8 (Cfg9346, Cfg9346_Lock);
903 }
904 }
905 } else {
906 DPRINTK("Old chip wakeup\n");
907 tmp8 = RTL_R8 (Config1);
908 tmp8 &= ~(SLEEP | PWRDN);
909 RTL_W8 (Config1, tmp8);
910 }
911
912 rtl8139_chip_reset (ioaddr);
913
914 *dev_out = dev;
915 return 0;
916
917 err_out:
918 __rtl8139_cleanup_dev (dev);
919 if (disable_dev_on_err)
920 pci_disable_device (pdev);
921 return rc;
922 }
923
924
925 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
926 const struct pci_device_id *ent)
927 {
928 struct net_device *dev = NULL;
929 struct rtl8139_private *tp;
930 int i, addr_len, option;
931 void __iomem *ioaddr;
932 static int board_idx = -1;
933 u8 pci_rev;
934
935 assert (pdev != NULL);
936 assert (ent != NULL);
937
938 board_idx++;
939
940 /* when we're built into the kernel, the driver version message
941 * is only printed if at least one 8139 board has been found
942 */
943 #ifndef MODULE
944 {
945 static int printed_version;
946 if (!printed_version++)
947 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
948 }
949 #endif
950
951 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
952
953 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
954 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {
955 printk(KERN_INFO PFX "pci dev %s (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
956 pci_name(pdev), pdev->vendor, pdev->device, pci_rev);
957 printk(KERN_INFO PFX "Use the \"8139cp\" driver for improved performance and stability.\n");
958 }
959
960 i = rtl8139_init_board (pdev, &dev);
961 if (i < 0)
962 return i;
963
964 assert (dev != NULL);
965 tp = netdev_priv(dev);
966
967 ioaddr = tp->mmio_addr;
968 assert (ioaddr != NULL);
969
970 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
971 for (i = 0; i < 3; i++)
972 ((u16 *) (dev->dev_addr))[i] =
973 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
974 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
975
976 /* The Rtl8139-specific entries in the device structure. */
977 dev->open = rtl8139_open;
978 dev->hard_start_xmit = rtl8139_start_xmit;
979 dev->poll = rtl8139_poll;
980 dev->weight = 64;
981 dev->stop = rtl8139_close;
982 dev->get_stats = rtl8139_get_stats;
983 dev->set_multicast_list = rtl8139_set_rx_mode;
984 dev->do_ioctl = netdev_ioctl;
985 dev->ethtool_ops = &rtl8139_ethtool_ops;
986 dev->tx_timeout = rtl8139_tx_timeout;
987 dev->watchdog_timeo = TX_TIMEOUT;
988 #ifdef CONFIG_NET_POLL_CONTROLLER
989 dev->poll_controller = rtl8139_poll_controller;
990 #endif
991
992 /* note: the hardware is not capable of sg/csum/highdma, however
993 * through the use of skb_copy_and_csum_dev we enable these
994 * features
995 */
996 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
997
998 dev->irq = pdev->irq;
999
1000 /* tp zeroed and aligned in alloc_etherdev */
1001 tp = netdev_priv(dev);
1002
1003 /* note: tp->chipset set in rtl8139_init_board */
1004 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1005 tp->mmio_addr = ioaddr;
1006 tp->msg_enable =
1007 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1008 spin_lock_init (&tp->lock);
1009 spin_lock_init (&tp->rx_lock);
1010 init_waitqueue_head (&tp->thr_wait);
1011 init_completion (&tp->thr_exited);
1012 tp->mii.dev = dev;
1013 tp->mii.mdio_read = mdio_read;
1014 tp->mii.mdio_write = mdio_write;
1015 tp->mii.phy_id_mask = 0x3f;
1016 tp->mii.reg_num_mask = 0x1f;
1017
1018 /* dev is fully set up and ready to use now */
1019 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1020 i = register_netdev (dev);
1021 if (i) goto err_out;
1022
1023 pci_set_drvdata (pdev, dev);
1024
1025 printk (KERN_INFO "%s: %s at 0x%lx, "
1026 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1027 "IRQ %d\n",
1028 dev->name,
1029 board_info[ent->driver_data].name,
1030 dev->base_addr,
1031 dev->dev_addr[0], dev->dev_addr[1],
1032 dev->dev_addr[2], dev->dev_addr[3],
1033 dev->dev_addr[4], dev->dev_addr[5],
1034 dev->irq);
1035
1036 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1037 dev->name, rtl_chip_info[tp->chipset].name);
1038
1039 /* Find the connected MII xcvrs.
1040 Doing this in open() would allow detecting external xcvrs later, but
1041 takes too much time. */
1042 #ifdef CONFIG_8139TOO_8129
1043 if (tp->drv_flags & HAS_MII_XCVR) {
1044 int phy, phy_idx = 0;
1045 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1046 int mii_status = mdio_read(dev, phy, 1);
1047 if (mii_status != 0xffff && mii_status != 0x0000) {
1048 u16 advertising = mdio_read(dev, phy, 4);
1049 tp->phys[phy_idx++] = phy;
1050 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1051 "advertising %4.4x.\n",
1052 dev->name, phy, mii_status, advertising);
1053 }
1054 }
1055 if (phy_idx == 0) {
1056 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1057 "transceiver.\n",
1058 dev->name);
1059 tp->phys[0] = 32;
1060 }
1061 } else
1062 #endif
1063 tp->phys[0] = 32;
1064 tp->mii.phy_id = tp->phys[0];
1065
1066 /* The lower four bits are the media type. */
1067 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1068 if (option > 0) {
1069 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1070 tp->default_port = option & 0xFF;
1071 if (tp->default_port)
1072 tp->mii.force_media = 1;
1073 }
1074 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1075 tp->mii.full_duplex = full_duplex[board_idx];
1076 if (tp->mii.full_duplex) {
1077 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1078 /* Changing the MII-advertised media because might prevent
1079 re-connection. */
1080 tp->mii.force_media = 1;
1081 }
1082 if (tp->default_port) {
1083 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1084 (option & 0x20 ? 100 : 10),
1085 (option & 0x10 ? "full" : "half"));
1086 mdio_write(dev, tp->phys[0], 0,
1087 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1088 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1089 }
1090
1091 /* Put the chip into low-power mode. */
1092 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1093 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1094
1095 return 0;
1096
1097 err_out:
1098 __rtl8139_cleanup_dev (dev);
1099 pci_disable_device (pdev);
1100 return i;
1101 }
1102
1103
1104 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1105 {
1106 struct net_device *dev = pci_get_drvdata (pdev);
1107
1108 assert (dev != NULL);
1109
1110 unregister_netdev (dev);
1111
1112 __rtl8139_cleanup_dev (dev);
1113 pci_disable_device (pdev);
1114 }
1115
1116
1117 /* Serial EEPROM section. */
1118
1119 /* EEPROM_Ctrl bits. */
1120 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1121 #define EE_CS 0x08 /* EEPROM chip select. */
1122 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1123 #define EE_WRITE_0 0x00
1124 #define EE_WRITE_1 0x02
1125 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1126 #define EE_ENB (0x80 | EE_CS)
1127
1128 /* Delay between EEPROM clock transitions.
1129 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1130 */
1131
1132 #define eeprom_delay() RTL_R32(Cfg9346)
1133
1134 /* The EEPROM commands include the alway-set leading bit. */
1135 #define EE_WRITE_CMD (5)
1136 #define EE_READ_CMD (6)
1137 #define EE_ERASE_CMD (7)
1138
1139 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1140 {
1141 int i;
1142 unsigned retval = 0;
1143 int read_cmd = location | (EE_READ_CMD << addr_len);
1144
1145 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1146 RTL_W8 (Cfg9346, EE_ENB);
1147 eeprom_delay ();
1148
1149 /* Shift the read command bits out. */
1150 for (i = 4 + addr_len; i >= 0; i--) {
1151 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1152 RTL_W8 (Cfg9346, EE_ENB | dataval);
1153 eeprom_delay ();
1154 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1155 eeprom_delay ();
1156 }
1157 RTL_W8 (Cfg9346, EE_ENB);
1158 eeprom_delay ();
1159
1160 for (i = 16; i > 0; i--) {
1161 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1162 eeprom_delay ();
1163 retval =
1164 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1165 0);
1166 RTL_W8 (Cfg9346, EE_ENB);
1167 eeprom_delay ();
1168 }
1169
1170 /* Terminate the EEPROM access. */
1171 RTL_W8 (Cfg9346, ~EE_CS);
1172 eeprom_delay ();
1173
1174 return retval;
1175 }
1176
1177 /* MII serial management: mostly bogus for now. */
1178 /* Read and write the MII management registers using software-generated
1179 serial MDIO protocol.
1180 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1181 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1182 "overclocking" issues. */
1183 #define MDIO_DIR 0x80
1184 #define MDIO_DATA_OUT 0x04
1185 #define MDIO_DATA_IN 0x02
1186 #define MDIO_CLK 0x01
1187 #define MDIO_WRITE0 (MDIO_DIR)
1188 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1189
1190 #define mdio_delay() RTL_R8(Config4)
1191
1192
1193 static char mii_2_8139_map[8] = {
1194 BasicModeCtrl,
1195 BasicModeStatus,
1196 0,
1197 0,
1198 NWayAdvert,
1199 NWayLPAR,
1200 NWayExpansion,
1201 0
1202 };
1203
1204
1205 #ifdef CONFIG_8139TOO_8129
1206 /* Syncronize the MII management interface by shifting 32 one bits out. */
1207 static void mdio_sync (void __iomem *ioaddr)
1208 {
1209 int i;
1210
1211 for (i = 32; i >= 0; i--) {
1212 RTL_W8 (Config4, MDIO_WRITE1);
1213 mdio_delay ();
1214 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1215 mdio_delay ();
1216 }
1217 }
1218 #endif
1219
1220 static int mdio_read (struct net_device *dev, int phy_id, int location)
1221 {
1222 struct rtl8139_private *tp = netdev_priv(dev);
1223 int retval = 0;
1224 #ifdef CONFIG_8139TOO_8129
1225 void __iomem *ioaddr = tp->mmio_addr;
1226 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1227 int i;
1228 #endif
1229
1230 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1231 void __iomem *ioaddr = tp->mmio_addr;
1232 return location < 8 && mii_2_8139_map[location] ?
1233 RTL_R16 (mii_2_8139_map[location]) : 0;
1234 }
1235
1236 #ifdef CONFIG_8139TOO_8129
1237 mdio_sync (ioaddr);
1238 /* Shift the read command bits out. */
1239 for (i = 15; i >= 0; i--) {
1240 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1241
1242 RTL_W8 (Config4, MDIO_DIR | dataval);
1243 mdio_delay ();
1244 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1245 mdio_delay ();
1246 }
1247
1248 /* Read the two transition, 16 data, and wire-idle bits. */
1249 for (i = 19; i > 0; i--) {
1250 RTL_W8 (Config4, 0);
1251 mdio_delay ();
1252 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1253 RTL_W8 (Config4, MDIO_CLK);
1254 mdio_delay ();
1255 }
1256 #endif
1257
1258 return (retval >> 1) & 0xffff;
1259 }
1260
1261
1262 static void mdio_write (struct net_device *dev, int phy_id, int location,
1263 int value)
1264 {
1265 struct rtl8139_private *tp = netdev_priv(dev);
1266 #ifdef CONFIG_8139TOO_8129
1267 void __iomem *ioaddr = tp->mmio_addr;
1268 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1269 int i;
1270 #endif
1271
1272 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1273 void __iomem *ioaddr = tp->mmio_addr;
1274 if (location == 0) {
1275 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1276 RTL_W16 (BasicModeCtrl, value);
1277 RTL_W8 (Cfg9346, Cfg9346_Lock);
1278 } else if (location < 8 && mii_2_8139_map[location])
1279 RTL_W16 (mii_2_8139_map[location], value);
1280 return;
1281 }
1282
1283 #ifdef CONFIG_8139TOO_8129
1284 mdio_sync (ioaddr);
1285
1286 /* Shift the command bits out. */
1287 for (i = 31; i >= 0; i--) {
1288 int dataval =
1289 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1290 RTL_W8 (Config4, dataval);
1291 mdio_delay ();
1292 RTL_W8 (Config4, dataval | MDIO_CLK);
1293 mdio_delay ();
1294 }
1295 /* Clear out extra bits. */
1296 for (i = 2; i > 0; i--) {
1297 RTL_W8 (Config4, 0);
1298 mdio_delay ();
1299 RTL_W8 (Config4, MDIO_CLK);
1300 mdio_delay ();
1301 }
1302 #endif
1303 }
1304
1305
1306 static int rtl8139_open (struct net_device *dev)
1307 {
1308 struct rtl8139_private *tp = netdev_priv(dev);
1309 int retval;
1310 void __iomem *ioaddr = tp->mmio_addr;
1311
1312 retval = request_irq (dev->irq, rtl8139_interrupt, SA_SHIRQ, dev->name, dev);
1313 if (retval)
1314 return retval;
1315
1316 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1317 &tp->tx_bufs_dma);
1318 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1319 &tp->rx_ring_dma);
1320 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1321 free_irq(dev->irq, dev);
1322
1323 if (tp->tx_bufs)
1324 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1325 tp->tx_bufs, tp->tx_bufs_dma);
1326 if (tp->rx_ring)
1327 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1328 tp->rx_ring, tp->rx_ring_dma);
1329
1330 return -ENOMEM;
1331
1332 }
1333
1334 tp->mii.full_duplex = tp->mii.force_media;
1335 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1336
1337 rtl8139_init_ring (dev);
1338 rtl8139_hw_start (dev);
1339 netif_start_queue (dev);
1340
1341 if (netif_msg_ifup(tp))
1342 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#lx IRQ %d"
1343 " GP Pins %2.2x %s-duplex.\n",
1344 dev->name, pci_resource_start (tp->pci_dev, 1),
1345 dev->irq, RTL_R8 (MediaStatus),
1346 tp->mii.full_duplex ? "full" : "half");
1347
1348 rtl8139_start_thread(dev);
1349
1350 return 0;
1351 }
1352
1353
1354 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1355 {
1356 struct rtl8139_private *tp = netdev_priv(dev);
1357
1358 if (tp->phys[0] >= 0) {
1359 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1360 }
1361 }
1362
1363 /* Start the hardware at open or resume. */
1364 static void rtl8139_hw_start (struct net_device *dev)
1365 {
1366 struct rtl8139_private *tp = netdev_priv(dev);
1367 void __iomem *ioaddr = tp->mmio_addr;
1368 u32 i;
1369 u8 tmp;
1370
1371 /* Bring old chips out of low-power mode. */
1372 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1373 RTL_W8 (HltClk, 'R');
1374
1375 rtl8139_chip_reset (ioaddr);
1376
1377 /* unlock Config[01234] and BMCR register writes */
1378 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1379 /* Restore our idea of the MAC address. */
1380 RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1381 RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1382
1383 /* Must enable Tx/Rx before setting transfer thresholds! */
1384 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1385
1386 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1387 RTL_W32 (RxConfig, tp->rx_config);
1388 RTL_W32 (TxConfig, rtl8139_tx_config);
1389
1390 tp->cur_rx = 0;
1391
1392 rtl_check_media (dev, 1);
1393
1394 if (tp->chipset >= CH_8139B) {
1395 /* Disable magic packet scanning, which is enabled
1396 * when PM is enabled in Config1. It can be reenabled
1397 * via ETHTOOL_SWOL if desired. */
1398 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1399 }
1400
1401 DPRINTK("init buffer addresses\n");
1402
1403 /* Lock Config[01234] and BMCR register writes */
1404 RTL_W8 (Cfg9346, Cfg9346_Lock);
1405
1406 /* init Rx ring buffer DMA address */
1407 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1408
1409 /* init Tx buffer DMA addresses */
1410 for (i = 0; i < NUM_TX_DESC; i++)
1411 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1412
1413 RTL_W32 (RxMissed, 0);
1414
1415 rtl8139_set_rx_mode (dev);
1416
1417 /* no early-rx interrupts */
1418 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1419
1420 /* make sure RxTx has started */
1421 tmp = RTL_R8 (ChipCmd);
1422 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1423 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1424
1425 /* Enable all known interrupts by setting the interrupt mask. */
1426 RTL_W16 (IntrMask, rtl8139_intr_mask);
1427 }
1428
1429
1430 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1431 static void rtl8139_init_ring (struct net_device *dev)
1432 {
1433 struct rtl8139_private *tp = netdev_priv(dev);
1434 int i;
1435
1436 tp->cur_rx = 0;
1437 tp->cur_tx = 0;
1438 tp->dirty_tx = 0;
1439
1440 for (i = 0; i < NUM_TX_DESC; i++)
1441 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1442 }
1443
1444
1445 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1446 static int next_tick = 3 * HZ;
1447
1448 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1449 static inline void rtl8139_tune_twister (struct net_device *dev,
1450 struct rtl8139_private *tp) {}
1451 #else
1452 enum TwisterParamVals {
1453 PARA78_default = 0x78fa8388,
1454 PARA7c_default = 0xcb38de43, /* param[0][3] */
1455 PARA7c_xxx = 0xcb38de43,
1456 };
1457
1458 static const unsigned long param[4][4] = {
1459 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1460 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1461 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1462 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1463 };
1464
1465 static void rtl8139_tune_twister (struct net_device *dev,
1466 struct rtl8139_private *tp)
1467 {
1468 int linkcase;
1469 void __iomem *ioaddr = tp->mmio_addr;
1470
1471 /* This is a complicated state machine to configure the "twister" for
1472 impedance/echos based on the cable length.
1473 All of this is magic and undocumented.
1474 */
1475 switch (tp->twistie) {
1476 case 1:
1477 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1478 /* We have link beat, let us tune the twister. */
1479 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1480 tp->twistie = 2; /* Change to state 2. */
1481 next_tick = HZ / 10;
1482 } else {
1483 /* Just put in some reasonable defaults for when beat returns. */
1484 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1485 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1486 RTL_W32 (PARA78, PARA78_default);
1487 RTL_W32 (PARA7c, PARA7c_default);
1488 tp->twistie = 0; /* Bail from future actions. */
1489 }
1490 break;
1491 case 2:
1492 /* Read how long it took to hear the echo. */
1493 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1494 if (linkcase == 0x7000)
1495 tp->twist_row = 3;
1496 else if (linkcase == 0x3000)
1497 tp->twist_row = 2;
1498 else if (linkcase == 0x1000)
1499 tp->twist_row = 1;
1500 else
1501 tp->twist_row = 0;
1502 tp->twist_col = 0;
1503 tp->twistie = 3; /* Change to state 2. */
1504 next_tick = HZ / 10;
1505 break;
1506 case 3:
1507 /* Put out four tuning parameters, one per 100msec. */
1508 if (tp->twist_col == 0)
1509 RTL_W16 (FIFOTMS, 0);
1510 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1511 [(int) tp->twist_col]);
1512 next_tick = HZ / 10;
1513 if (++tp->twist_col >= 4) {
1514 /* For short cables we are done.
1515 For long cables (row == 3) check for mistune. */
1516 tp->twistie =
1517 (tp->twist_row == 3) ? 4 : 0;
1518 }
1519 break;
1520 case 4:
1521 /* Special case for long cables: check for mistune. */
1522 if ((RTL_R16 (CSCR) &
1523 CSCR_LinkStatusBits) == 0x7000) {
1524 tp->twistie = 0;
1525 break;
1526 } else {
1527 RTL_W32 (PARA7c, 0xfb38de03);
1528 tp->twistie = 5;
1529 next_tick = HZ / 10;
1530 }
1531 break;
1532 case 5:
1533 /* Retune for shorter cable (column 2). */
1534 RTL_W32 (FIFOTMS, 0x20);
1535 RTL_W32 (PARA78, PARA78_default);
1536 RTL_W32 (PARA7c, PARA7c_default);
1537 RTL_W32 (FIFOTMS, 0x00);
1538 tp->twist_row = 2;
1539 tp->twist_col = 0;
1540 tp->twistie = 3;
1541 next_tick = HZ / 10;
1542 break;
1543
1544 default:
1545 /* do nothing */
1546 break;
1547 }
1548 }
1549 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1550
1551 static inline void rtl8139_thread_iter (struct net_device *dev,
1552 struct rtl8139_private *tp,
1553 void __iomem *ioaddr)
1554 {
1555 int mii_lpa;
1556
1557 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1558
1559 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1560 int duplex = (mii_lpa & LPA_100FULL)
1561 || (mii_lpa & 0x01C0) == 0x0040;
1562 if (tp->mii.full_duplex != duplex) {
1563 tp->mii.full_duplex = duplex;
1564
1565 if (mii_lpa) {
1566 printk (KERN_INFO
1567 "%s: Setting %s-duplex based on MII #%d link"
1568 " partner ability of %4.4x.\n",
1569 dev->name,
1570 tp->mii.full_duplex ? "full" : "half",
1571 tp->phys[0], mii_lpa);
1572 } else {
1573 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1574 dev->name);
1575 }
1576 #if 0
1577 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1578 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1579 RTL_W8 (Cfg9346, Cfg9346_Lock);
1580 #endif
1581 }
1582 }
1583
1584 next_tick = HZ * 60;
1585
1586 rtl8139_tune_twister (dev, tp);
1587
1588 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1589 dev->name, RTL_R16 (NWayLPAR));
1590 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1591 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1592 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1593 dev->name, RTL_R8 (Config0),
1594 RTL_R8 (Config1));
1595 }
1596
1597 static int rtl8139_thread (void *data)
1598 {
1599 struct net_device *dev = data;
1600 struct rtl8139_private *tp = netdev_priv(dev);
1601 unsigned long timeout;
1602
1603 daemonize("%s", dev->name);
1604 allow_signal(SIGTERM);
1605
1606 while (1) {
1607 timeout = next_tick;
1608 do {
1609 timeout = interruptible_sleep_on_timeout (&tp->thr_wait, timeout);
1610 /* make swsusp happy with our thread */
1611 try_to_freeze();
1612 } while (!signal_pending (current) && (timeout > 0));
1613
1614 if (signal_pending (current)) {
1615 flush_signals(current);
1616 }
1617
1618 if (tp->time_to_die)
1619 break;
1620
1621 if (rtnl_lock_interruptible ())
1622 break;
1623 rtl8139_thread_iter (dev, tp, tp->mmio_addr);
1624 rtnl_unlock ();
1625 }
1626
1627 complete_and_exit (&tp->thr_exited, 0);
1628 }
1629
1630 static void rtl8139_start_thread(struct net_device *dev)
1631 {
1632 struct rtl8139_private *tp = netdev_priv(dev);
1633
1634 tp->thr_pid = -1;
1635 tp->twistie = 0;
1636 tp->time_to_die = 0;
1637 if (tp->chipset == CH_8139_K)
1638 tp->twistie = 1;
1639 else if (tp->drv_flags & HAS_LNK_CHNG)
1640 return;
1641
1642 tp->thr_pid = kernel_thread(rtl8139_thread, dev, CLONE_FS|CLONE_FILES);
1643 if (tp->thr_pid < 0) {
1644 printk (KERN_WARNING "%s: unable to start kernel thread\n",
1645 dev->name);
1646 }
1647 }
1648
1649 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1650 {
1651 tp->cur_tx = 0;
1652 tp->dirty_tx = 0;
1653
1654 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1655 }
1656
1657
1658 static void rtl8139_tx_timeout (struct net_device *dev)
1659 {
1660 struct rtl8139_private *tp = netdev_priv(dev);
1661 void __iomem *ioaddr = tp->mmio_addr;
1662 int i;
1663 u8 tmp8;
1664 unsigned long flags;
1665
1666 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1667 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1668 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1669 /* Emit info to figure out what went wrong. */
1670 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1671 dev->name, tp->cur_tx, tp->dirty_tx);
1672 for (i = 0; i < NUM_TX_DESC; i++)
1673 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1674 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1675 i == tp->dirty_tx % NUM_TX_DESC ?
1676 " (queue head)" : "");
1677
1678 tp->xstats.tx_timeouts++;
1679
1680 /* disable Tx ASAP, if not already */
1681 tmp8 = RTL_R8 (ChipCmd);
1682 if (tmp8 & CmdTxEnb)
1683 RTL_W8 (ChipCmd, CmdRxEnb);
1684
1685 spin_lock(&tp->rx_lock);
1686 /* Disable interrupts by clearing the interrupt mask. */
1687 RTL_W16 (IntrMask, 0x0000);
1688
1689 /* Stop a shared interrupt from scavenging while we are. */
1690 spin_lock_irqsave (&tp->lock, flags);
1691 rtl8139_tx_clear (tp);
1692 spin_unlock_irqrestore (&tp->lock, flags);
1693
1694 /* ...and finally, reset everything */
1695 if (netif_running(dev)) {
1696 rtl8139_hw_start (dev);
1697 netif_wake_queue (dev);
1698 }
1699 spin_unlock(&tp->rx_lock);
1700 }
1701
1702
1703 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1704 {
1705 struct rtl8139_private *tp = netdev_priv(dev);
1706 void __iomem *ioaddr = tp->mmio_addr;
1707 unsigned int entry;
1708 unsigned int len = skb->len;
1709
1710 /* Calculate the next Tx descriptor entry. */
1711 entry = tp->cur_tx % NUM_TX_DESC;
1712
1713 /* Note: the chip doesn't have auto-pad! */
1714 if (likely(len < TX_BUF_SIZE)) {
1715 if (len < ETH_ZLEN)
1716 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1717 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1718 dev_kfree_skb(skb);
1719 } else {
1720 dev_kfree_skb(skb);
1721 tp->stats.tx_dropped++;
1722 return 0;
1723 }
1724
1725 spin_lock_irq(&tp->lock);
1726 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1727 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1728
1729 dev->trans_start = jiffies;
1730
1731 tp->cur_tx++;
1732 wmb();
1733
1734 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1735 netif_stop_queue (dev);
1736 spin_unlock_irq(&tp->lock);
1737
1738 if (netif_msg_tx_queued(tp))
1739 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1740 dev->name, len, entry);
1741
1742 return 0;
1743 }
1744
1745
1746 static void rtl8139_tx_interrupt (struct net_device *dev,
1747 struct rtl8139_private *tp,
1748 void __iomem *ioaddr)
1749 {
1750 unsigned long dirty_tx, tx_left;
1751
1752 assert (dev != NULL);
1753 assert (ioaddr != NULL);
1754
1755 dirty_tx = tp->dirty_tx;
1756 tx_left = tp->cur_tx - dirty_tx;
1757 while (tx_left > 0) {
1758 int entry = dirty_tx % NUM_TX_DESC;
1759 int txstatus;
1760
1761 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1762
1763 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1764 break; /* It still hasn't been Txed */
1765
1766 /* Note: TxCarrierLost is always asserted at 100mbps. */
1767 if (txstatus & (TxOutOfWindow | TxAborted)) {
1768 /* There was an major error, log it. */
1769 if (netif_msg_tx_err(tp))
1770 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1771 dev->name, txstatus);
1772 tp->stats.tx_errors++;
1773 if (txstatus & TxAborted) {
1774 tp->stats.tx_aborted_errors++;
1775 RTL_W32 (TxConfig, TxClearAbt);
1776 RTL_W16 (IntrStatus, TxErr);
1777 wmb();
1778 }
1779 if (txstatus & TxCarrierLost)
1780 tp->stats.tx_carrier_errors++;
1781 if (txstatus & TxOutOfWindow)
1782 tp->stats.tx_window_errors++;
1783 } else {
1784 if (txstatus & TxUnderrun) {
1785 /* Add 64 to the Tx FIFO threshold. */
1786 if (tp->tx_flag < 0x00300000)
1787 tp->tx_flag += 0x00020000;
1788 tp->stats.tx_fifo_errors++;
1789 }
1790 tp->stats.collisions += (txstatus >> 24) & 15;
1791 tp->stats.tx_bytes += txstatus & 0x7ff;
1792 tp->stats.tx_packets++;
1793 }
1794
1795 dirty_tx++;
1796 tx_left--;
1797 }
1798
1799 #ifndef RTL8139_NDEBUG
1800 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1801 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1802 dev->name, dirty_tx, tp->cur_tx);
1803 dirty_tx += NUM_TX_DESC;
1804 }
1805 #endif /* RTL8139_NDEBUG */
1806
1807 /* only wake the queue if we did work, and the queue is stopped */
1808 if (tp->dirty_tx != dirty_tx) {
1809 tp->dirty_tx = dirty_tx;
1810 mb();
1811 netif_wake_queue (dev);
1812 }
1813 }
1814
1815
1816 /* TODO: clean this up! Rx reset need not be this intensive */
1817 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1818 struct rtl8139_private *tp, void __iomem *ioaddr)
1819 {
1820 u8 tmp8;
1821 #ifdef CONFIG_8139_OLD_RX_RESET
1822 int tmp_work;
1823 #endif
1824
1825 if (netif_msg_rx_err (tp))
1826 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1827 dev->name, rx_status);
1828 tp->stats.rx_errors++;
1829 if (!(rx_status & RxStatusOK)) {
1830 if (rx_status & RxTooLong) {
1831 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1832 dev->name, rx_status);
1833 /* A.C.: The chip hangs here. */
1834 }
1835 if (rx_status & (RxBadSymbol | RxBadAlign))
1836 tp->stats.rx_frame_errors++;
1837 if (rx_status & (RxRunt | RxTooLong))
1838 tp->stats.rx_length_errors++;
1839 if (rx_status & RxCRCErr)
1840 tp->stats.rx_crc_errors++;
1841 } else {
1842 tp->xstats.rx_lost_in_ring++;
1843 }
1844
1845 #ifndef CONFIG_8139_OLD_RX_RESET
1846 tmp8 = RTL_R8 (ChipCmd);
1847 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1848 RTL_W8 (ChipCmd, tmp8);
1849 RTL_W32 (RxConfig, tp->rx_config);
1850 tp->cur_rx = 0;
1851 #else
1852 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1853
1854 /* disable receive */
1855 RTL_W8_F (ChipCmd, CmdTxEnb);
1856 tmp_work = 200;
1857 while (--tmp_work > 0) {
1858 udelay(1);
1859 tmp8 = RTL_R8 (ChipCmd);
1860 if (!(tmp8 & CmdRxEnb))
1861 break;
1862 }
1863 if (tmp_work <= 0)
1864 printk (KERN_WARNING PFX "rx stop wait too long\n");
1865 /* restart receive */
1866 tmp_work = 200;
1867 while (--tmp_work > 0) {
1868 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1869 udelay(1);
1870 tmp8 = RTL_R8 (ChipCmd);
1871 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1872 break;
1873 }
1874 if (tmp_work <= 0)
1875 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1876
1877 /* and reinitialize all rx related registers */
1878 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1879 /* Must enable Tx/Rx before setting transfer thresholds! */
1880 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1881
1882 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1883 RTL_W32 (RxConfig, tp->rx_config);
1884 tp->cur_rx = 0;
1885
1886 DPRINTK("init buffer addresses\n");
1887
1888 /* Lock Config[01234] and BMCR register writes */
1889 RTL_W8 (Cfg9346, Cfg9346_Lock);
1890
1891 /* init Rx ring buffer DMA address */
1892 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1893
1894 /* A.C.: Reset the multicast list. */
1895 __set_rx_mode (dev);
1896 #endif
1897 }
1898
1899 #if RX_BUF_IDX == 3
1900 static __inline__ void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1901 u32 offset, unsigned int size)
1902 {
1903 u32 left = RX_BUF_LEN - offset;
1904
1905 if (size > left) {
1906 memcpy(skb->data, ring + offset, left);
1907 memcpy(skb->data+left, ring, size - left);
1908 } else
1909 memcpy(skb->data, ring + offset, size);
1910 }
1911 #endif
1912
1913 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1914 {
1915 void __iomem *ioaddr = tp->mmio_addr;
1916 u16 status;
1917
1918 status = RTL_R16 (IntrStatus) & RxAckBits;
1919
1920 /* Clear out errors and receive interrupts */
1921 if (likely(status != 0)) {
1922 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1923 tp->stats.rx_errors++;
1924 if (status & RxFIFOOver)
1925 tp->stats.rx_fifo_errors++;
1926 }
1927 RTL_W16_F (IntrStatus, RxAckBits);
1928 }
1929 }
1930
1931 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1932 int budget)
1933 {
1934 void __iomem *ioaddr = tp->mmio_addr;
1935 int received = 0;
1936 unsigned char *rx_ring = tp->rx_ring;
1937 unsigned int cur_rx = tp->cur_rx;
1938 unsigned int rx_size = 0;
1939
1940 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1941 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1942 RTL_R16 (RxBufAddr),
1943 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1944
1945 while (netif_running(dev) && received < budget
1946 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1947 u32 ring_offset = cur_rx % RX_BUF_LEN;
1948 u32 rx_status;
1949 unsigned int pkt_size;
1950 struct sk_buff *skb;
1951
1952 rmb();
1953
1954 /* read size+status of next frame from DMA ring buffer */
1955 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1956 rx_size = rx_status >> 16;
1957 pkt_size = rx_size - 4;
1958
1959 if (netif_msg_rx_status(tp))
1960 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1961 " cur %4.4x.\n", dev->name, rx_status,
1962 rx_size, cur_rx);
1963 #if RTL8139_DEBUG > 2
1964 {
1965 int i;
1966 DPRINTK ("%s: Frame contents ", dev->name);
1967 for (i = 0; i < 70; i++)
1968 printk (" %2.2x",
1969 rx_ring[ring_offset + i]);
1970 printk (".\n");
1971 }
1972 #endif
1973
1974 /* Packet copy from FIFO still in progress.
1975 * Theoretically, this should never happen
1976 * since EarlyRx is disabled.
1977 */
1978 if (unlikely(rx_size == 0xfff0)) {
1979 if (!tp->fifo_copy_timeout)
1980 tp->fifo_copy_timeout = jiffies + 2;
1981 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1982 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
1983 rx_size = 0;
1984 goto no_early_rx;
1985 }
1986 if (netif_msg_intr(tp)) {
1987 printk(KERN_DEBUG "%s: fifo copy in progress.",
1988 dev->name);
1989 }
1990 tp->xstats.early_rx++;
1991 break;
1992 }
1993
1994 no_early_rx:
1995 tp->fifo_copy_timeout = 0;
1996
1997 /* If Rx err or invalid rx_size/rx_status received
1998 * (which happens if we get lost in the ring),
1999 * Rx process gets reset, so we abort any further
2000 * Rx processing.
2001 */
2002 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
2003 (rx_size < 8) ||
2004 (!(rx_status & RxStatusOK)))) {
2005 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2006 received = -1;
2007 goto out;
2008 }
2009
2010 /* Malloc up new buffer, compatible with net-2e. */
2011 /* Omit the four octet CRC from the length. */
2012
2013 skb = dev_alloc_skb (pkt_size + 2);
2014 if (likely(skb)) {
2015 skb->dev = dev;
2016 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
2017 #if RX_BUF_IDX == 3
2018 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2019 #else
2020 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
2021 #endif
2022 skb_put (skb, pkt_size);
2023
2024 skb->protocol = eth_type_trans (skb, dev);
2025
2026 dev->last_rx = jiffies;
2027 tp->stats.rx_bytes += pkt_size;
2028 tp->stats.rx_packets++;
2029
2030 netif_receive_skb (skb);
2031 } else {
2032 if (net_ratelimit())
2033 printk (KERN_WARNING
2034 "%s: Memory squeeze, dropping packet.\n",
2035 dev->name);
2036 tp->stats.rx_dropped++;
2037 }
2038 received++;
2039
2040 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2041 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2042
2043 rtl8139_isr_ack(tp);
2044 }
2045
2046 if (unlikely(!received || rx_size == 0xfff0))
2047 rtl8139_isr_ack(tp);
2048
2049 #if RTL8139_DEBUG > 1
2050 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2051 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2052 RTL_R16 (RxBufAddr),
2053 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2054 #endif
2055
2056 tp->cur_rx = cur_rx;
2057
2058 /*
2059 * The receive buffer should be mostly empty.
2060 * Tell NAPI to reenable the Rx irq.
2061 */
2062 if (tp->fifo_copy_timeout)
2063 received = budget;
2064
2065 out:
2066 return received;
2067 }
2068
2069
2070 static void rtl8139_weird_interrupt (struct net_device *dev,
2071 struct rtl8139_private *tp,
2072 void __iomem *ioaddr,
2073 int status, int link_changed)
2074 {
2075 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2076 dev->name, status);
2077
2078 assert (dev != NULL);
2079 assert (tp != NULL);
2080 assert (ioaddr != NULL);
2081
2082 /* Update the error count. */
2083 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2084 RTL_W32 (RxMissed, 0);
2085
2086 if ((status & RxUnderrun) && link_changed &&
2087 (tp->drv_flags & HAS_LNK_CHNG)) {
2088 rtl_check_media(dev, 0);
2089 status &= ~RxUnderrun;
2090 }
2091
2092 if (status & (RxUnderrun | RxErr))
2093 tp->stats.rx_errors++;
2094
2095 if (status & PCSTimeout)
2096 tp->stats.rx_length_errors++;
2097 if (status & RxUnderrun)
2098 tp->stats.rx_fifo_errors++;
2099 if (status & PCIErr) {
2100 u16 pci_cmd_status;
2101 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2102 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2103
2104 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2105 dev->name, pci_cmd_status);
2106 }
2107 }
2108
2109 static int rtl8139_poll(struct net_device *dev, int *budget)
2110 {
2111 struct rtl8139_private *tp = netdev_priv(dev);
2112 void __iomem *ioaddr = tp->mmio_addr;
2113 int orig_budget = min(*budget, dev->quota);
2114 int done = 1;
2115
2116 spin_lock(&tp->rx_lock);
2117 if (likely(RTL_R16(IntrStatus) & RxAckBits)) {
2118 int work_done;
2119
2120 work_done = rtl8139_rx(dev, tp, orig_budget);
2121 if (likely(work_done > 0)) {
2122 *budget -= work_done;
2123 dev->quota -= work_done;
2124 done = (work_done < orig_budget);
2125 }
2126 }
2127
2128 if (done) {
2129 /*
2130 * Order is important since data can get interrupted
2131 * again when we think we are done.
2132 */
2133 local_irq_disable();
2134 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2135 __netif_rx_complete(dev);
2136 local_irq_enable();
2137 }
2138 spin_unlock(&tp->rx_lock);
2139
2140 return !done;
2141 }
2142
2143 /* The interrupt handler does all of the Rx thread work and cleans up
2144 after the Tx thread. */
2145 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
2146 struct pt_regs *regs)
2147 {
2148 struct net_device *dev = (struct net_device *) dev_instance;
2149 struct rtl8139_private *tp = netdev_priv(dev);
2150 void __iomem *ioaddr = tp->mmio_addr;
2151 u16 status, ackstat;
2152 int link_changed = 0; /* avoid bogus "uninit" warning */
2153 int handled = 0;
2154
2155 spin_lock (&tp->lock);
2156 status = RTL_R16 (IntrStatus);
2157
2158 /* shared irq? */
2159 if (unlikely((status & rtl8139_intr_mask) == 0))
2160 goto out;
2161
2162 handled = 1;
2163
2164 /* h/w no longer present (hotplug?) or major error, bail */
2165 if (unlikely(status == 0xFFFF))
2166 goto out;
2167
2168 /* close possible race's with dev_close */
2169 if (unlikely(!netif_running(dev))) {
2170 RTL_W16 (IntrMask, 0);
2171 goto out;
2172 }
2173
2174 /* Acknowledge all of the current interrupt sources ASAP, but
2175 an first get an additional status bit from CSCR. */
2176 if (unlikely(status & RxUnderrun))
2177 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2178
2179 ackstat = status & ~(RxAckBits | TxErr);
2180 if (ackstat)
2181 RTL_W16 (IntrStatus, ackstat);
2182
2183 /* Receive packets are processed by poll routine.
2184 If not running start it now. */
2185 if (status & RxAckBits){
2186 if (netif_rx_schedule_prep(dev)) {
2187 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2188 __netif_rx_schedule (dev);
2189 }
2190 }
2191
2192 /* Check uncommon events with one test. */
2193 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2194 rtl8139_weird_interrupt (dev, tp, ioaddr,
2195 status, link_changed);
2196
2197 if (status & (TxOK | TxErr)) {
2198 rtl8139_tx_interrupt (dev, tp, ioaddr);
2199 if (status & TxErr)
2200 RTL_W16 (IntrStatus, TxErr);
2201 }
2202 out:
2203 spin_unlock (&tp->lock);
2204
2205 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2206 dev->name, RTL_R16 (IntrStatus));
2207 return IRQ_RETVAL(handled);
2208 }
2209
2210 #ifdef CONFIG_NET_POLL_CONTROLLER
2211 /*
2212 * Polling receive - used by netconsole and other diagnostic tools
2213 * to allow network i/o with interrupts disabled.
2214 */
2215 static void rtl8139_poll_controller(struct net_device *dev)
2216 {
2217 disable_irq(dev->irq);
2218 rtl8139_interrupt(dev->irq, dev, NULL);
2219 enable_irq(dev->irq);
2220 }
2221 #endif
2222
2223 static int rtl8139_close (struct net_device *dev)
2224 {
2225 struct rtl8139_private *tp = netdev_priv(dev);
2226 void __iomem *ioaddr = tp->mmio_addr;
2227 int ret = 0;
2228 unsigned long flags;
2229
2230 netif_stop_queue (dev);
2231
2232 if (tp->thr_pid >= 0) {
2233 tp->time_to_die = 1;
2234 wmb();
2235 ret = kill_proc (tp->thr_pid, SIGTERM, 1);
2236 if (ret) {
2237 printk (KERN_ERR "%s: unable to signal thread\n", dev->name);
2238 return ret;
2239 }
2240 wait_for_completion (&tp->thr_exited);
2241 }
2242
2243 if (netif_msg_ifdown(tp))
2244 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2245 dev->name, RTL_R16 (IntrStatus));
2246
2247 spin_lock_irqsave (&tp->lock, flags);
2248
2249 /* Stop the chip's Tx and Rx DMA processes. */
2250 RTL_W8 (ChipCmd, 0);
2251
2252 /* Disable interrupts by clearing the interrupt mask. */
2253 RTL_W16 (IntrMask, 0);
2254
2255 /* Update the error counts. */
2256 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2257 RTL_W32 (RxMissed, 0);
2258
2259 spin_unlock_irqrestore (&tp->lock, flags);
2260
2261 synchronize_irq (dev->irq); /* racy, but that's ok here */
2262 free_irq (dev->irq, dev);
2263
2264 rtl8139_tx_clear (tp);
2265
2266 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
2267 tp->rx_ring, tp->rx_ring_dma);
2268 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
2269 tp->tx_bufs, tp->tx_bufs_dma);
2270 tp->rx_ring = NULL;
2271 tp->tx_bufs = NULL;
2272
2273 /* Green! Put the chip in low-power mode. */
2274 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2275
2276 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2277 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2278
2279 return 0;
2280 }
2281
2282
2283 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2284 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2285 other threads or interrupts aren't messing with the 8139. */
2286 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2287 {
2288 struct rtl8139_private *np = netdev_priv(dev);
2289 void __iomem *ioaddr = np->mmio_addr;
2290
2291 spin_lock_irq(&np->lock);
2292 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2293 u8 cfg3 = RTL_R8 (Config3);
2294 u8 cfg5 = RTL_R8 (Config5);
2295
2296 wol->supported = WAKE_PHY | WAKE_MAGIC
2297 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2298
2299 wol->wolopts = 0;
2300 if (cfg3 & Cfg3_LinkUp)
2301 wol->wolopts |= WAKE_PHY;
2302 if (cfg3 & Cfg3_Magic)
2303 wol->wolopts |= WAKE_MAGIC;
2304 /* (KON)FIXME: See how netdev_set_wol() handles the
2305 following constants. */
2306 if (cfg5 & Cfg5_UWF)
2307 wol->wolopts |= WAKE_UCAST;
2308 if (cfg5 & Cfg5_MWF)
2309 wol->wolopts |= WAKE_MCAST;
2310 if (cfg5 & Cfg5_BWF)
2311 wol->wolopts |= WAKE_BCAST;
2312 }
2313 spin_unlock_irq(&np->lock);
2314 }
2315
2316
2317 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2318 that wol points to kernel memory and other threads or interrupts
2319 aren't messing with the 8139. */
2320 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2321 {
2322 struct rtl8139_private *np = netdev_priv(dev);
2323 void __iomem *ioaddr = np->mmio_addr;
2324 u32 support;
2325 u8 cfg3, cfg5;
2326
2327 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2328 ? (WAKE_PHY | WAKE_MAGIC
2329 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2330 : 0);
2331 if (wol->wolopts & ~support)
2332 return -EINVAL;
2333
2334 spin_lock_irq(&np->lock);
2335 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2336 if (wol->wolopts & WAKE_PHY)
2337 cfg3 |= Cfg3_LinkUp;
2338 if (wol->wolopts & WAKE_MAGIC)
2339 cfg3 |= Cfg3_Magic;
2340 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2341 RTL_W8 (Config3, cfg3);
2342 RTL_W8 (Cfg9346, Cfg9346_Lock);
2343
2344 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2345 /* (KON)FIXME: These are untested. We may have to set the
2346 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2347 documentation. */
2348 if (wol->wolopts & WAKE_UCAST)
2349 cfg5 |= Cfg5_UWF;
2350 if (wol->wolopts & WAKE_MCAST)
2351 cfg5 |= Cfg5_MWF;
2352 if (wol->wolopts & WAKE_BCAST)
2353 cfg5 |= Cfg5_BWF;
2354 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2355 spin_unlock_irq(&np->lock);
2356
2357 return 0;
2358 }
2359
2360 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2361 {
2362 struct rtl8139_private *np = netdev_priv(dev);
2363 strcpy(info->driver, DRV_NAME);
2364 strcpy(info->version, DRV_VERSION);
2365 strcpy(info->bus_info, pci_name(np->pci_dev));
2366 info->regdump_len = np->regs_len;
2367 }
2368
2369 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2370 {
2371 struct rtl8139_private *np = netdev_priv(dev);
2372 spin_lock_irq(&np->lock);
2373 mii_ethtool_gset(&np->mii, cmd);
2374 spin_unlock_irq(&np->lock);
2375 return 0;
2376 }
2377
2378 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2379 {
2380 struct rtl8139_private *np = netdev_priv(dev);
2381 int rc;
2382 spin_lock_irq(&np->lock);
2383 rc = mii_ethtool_sset(&np->mii, cmd);
2384 spin_unlock_irq(&np->lock);
2385 return rc;
2386 }
2387
2388 static int rtl8139_nway_reset(struct net_device *dev)
2389 {
2390 struct rtl8139_private *np = netdev_priv(dev);
2391 return mii_nway_restart(&np->mii);
2392 }
2393
2394 static u32 rtl8139_get_link(struct net_device *dev)
2395 {
2396 struct rtl8139_private *np = netdev_priv(dev);
2397 return mii_link_ok(&np->mii);
2398 }
2399
2400 static u32 rtl8139_get_msglevel(struct net_device *dev)
2401 {
2402 struct rtl8139_private *np = netdev_priv(dev);
2403 return np->msg_enable;
2404 }
2405
2406 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2407 {
2408 struct rtl8139_private *np = netdev_priv(dev);
2409 np->msg_enable = datum;
2410 }
2411
2412 /* TODO: we are too slack to do reg dumping for pio, for now */
2413 #ifdef CONFIG_8139TOO_PIO
2414 #define rtl8139_get_regs_len NULL
2415 #define rtl8139_get_regs NULL
2416 #else
2417 static int rtl8139_get_regs_len(struct net_device *dev)
2418 {
2419 struct rtl8139_private *np = netdev_priv(dev);
2420 return np->regs_len;
2421 }
2422
2423 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2424 {
2425 struct rtl8139_private *np = netdev_priv(dev);
2426
2427 regs->version = RTL_REGS_VER;
2428
2429 spin_lock_irq(&np->lock);
2430 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2431 spin_unlock_irq(&np->lock);
2432 }
2433 #endif /* CONFIG_8139TOO_MMIO */
2434
2435 static int rtl8139_get_stats_count(struct net_device *dev)
2436 {
2437 return RTL_NUM_STATS;
2438 }
2439
2440 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2441 {
2442 struct rtl8139_private *np = netdev_priv(dev);
2443
2444 data[0] = np->xstats.early_rx;
2445 data[1] = np->xstats.tx_buf_mapped;
2446 data[2] = np->xstats.tx_timeouts;
2447 data[3] = np->xstats.rx_lost_in_ring;
2448 }
2449
2450 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2451 {
2452 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2453 }
2454
2455 static struct ethtool_ops rtl8139_ethtool_ops = {
2456 .get_drvinfo = rtl8139_get_drvinfo,
2457 .get_settings = rtl8139_get_settings,
2458 .set_settings = rtl8139_set_settings,
2459 .get_regs_len = rtl8139_get_regs_len,
2460 .get_regs = rtl8139_get_regs,
2461 .nway_reset = rtl8139_nway_reset,
2462 .get_link = rtl8139_get_link,
2463 .get_msglevel = rtl8139_get_msglevel,
2464 .set_msglevel = rtl8139_set_msglevel,
2465 .get_wol = rtl8139_get_wol,
2466 .set_wol = rtl8139_set_wol,
2467 .get_strings = rtl8139_get_strings,
2468 .get_stats_count = rtl8139_get_stats_count,
2469 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2470 .get_perm_addr = ethtool_op_get_perm_addr,
2471 };
2472
2473 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2474 {
2475 struct rtl8139_private *np = netdev_priv(dev);
2476 int rc;
2477
2478 if (!netif_running(dev))
2479 return -EINVAL;
2480
2481 spin_lock_irq(&np->lock);
2482 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2483 spin_unlock_irq(&np->lock);
2484
2485 return rc;
2486 }
2487
2488
2489 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2490 {
2491 struct rtl8139_private *tp = netdev_priv(dev);
2492 void __iomem *ioaddr = tp->mmio_addr;
2493 unsigned long flags;
2494
2495 if (netif_running(dev)) {
2496 spin_lock_irqsave (&tp->lock, flags);
2497 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2498 RTL_W32 (RxMissed, 0);
2499 spin_unlock_irqrestore (&tp->lock, flags);
2500 }
2501
2502 return &tp->stats;
2503 }
2504
2505 /* Set or clear the multicast filter for this adaptor.
2506 This routine is not state sensitive and need not be SMP locked. */
2507
2508 static void __set_rx_mode (struct net_device *dev)
2509 {
2510 struct rtl8139_private *tp = netdev_priv(dev);
2511 void __iomem *ioaddr = tp->mmio_addr;
2512 u32 mc_filter[2]; /* Multicast hash filter */
2513 int i, rx_mode;
2514 u32 tmp;
2515
2516 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2517 dev->name, dev->flags, RTL_R32 (RxConfig));
2518
2519 /* Note: do not reorder, GCC is clever about common statements. */
2520 if (dev->flags & IFF_PROMISC) {
2521 /* Unconditionally log net taps. */
2522 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2523 dev->name);
2524 rx_mode =
2525 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2526 AcceptAllPhys;
2527 mc_filter[1] = mc_filter[0] = 0xffffffff;
2528 } else if ((dev->mc_count > multicast_filter_limit)
2529 || (dev->flags & IFF_ALLMULTI)) {
2530 /* Too many to filter perfectly -- accept all multicasts. */
2531 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2532 mc_filter[1] = mc_filter[0] = 0xffffffff;
2533 } else {
2534 struct dev_mc_list *mclist;
2535 rx_mode = AcceptBroadcast | AcceptMyPhys;
2536 mc_filter[1] = mc_filter[0] = 0;
2537 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2538 i++, mclist = mclist->next) {
2539 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2540
2541 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2542 rx_mode |= AcceptMulticast;
2543 }
2544 }
2545
2546 /* We can safely update without stopping the chip. */
2547 tmp = rtl8139_rx_config | rx_mode;
2548 if (tp->rx_config != tmp) {
2549 RTL_W32_F (RxConfig, tmp);
2550 tp->rx_config = tmp;
2551 }
2552 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2553 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2554 }
2555
2556 static void rtl8139_set_rx_mode (struct net_device *dev)
2557 {
2558 unsigned long flags;
2559 struct rtl8139_private *tp = netdev_priv(dev);
2560
2561 spin_lock_irqsave (&tp->lock, flags);
2562 __set_rx_mode(dev);
2563 spin_unlock_irqrestore (&tp->lock, flags);
2564 }
2565
2566 #ifdef CONFIG_PM
2567
2568 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2569 {
2570 struct net_device *dev = pci_get_drvdata (pdev);
2571 struct rtl8139_private *tp = netdev_priv(dev);
2572 void __iomem *ioaddr = tp->mmio_addr;
2573 unsigned long flags;
2574
2575 pci_save_state (pdev);
2576
2577 if (!netif_running (dev))
2578 return 0;
2579
2580 netif_device_detach (dev);
2581
2582 spin_lock_irqsave (&tp->lock, flags);
2583
2584 /* Disable interrupts, stop Tx and Rx. */
2585 RTL_W16 (IntrMask, 0);
2586 RTL_W8 (ChipCmd, 0);
2587
2588 /* Update the error counts. */
2589 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2590 RTL_W32 (RxMissed, 0);
2591
2592 spin_unlock_irqrestore (&tp->lock, flags);
2593
2594 pci_set_power_state (pdev, PCI_D3hot);
2595
2596 return 0;
2597 }
2598
2599
2600 static int rtl8139_resume (struct pci_dev *pdev)
2601 {
2602 struct net_device *dev = pci_get_drvdata (pdev);
2603
2604 pci_restore_state (pdev);
2605 if (!netif_running (dev))
2606 return 0;
2607 pci_set_power_state (pdev, PCI_D0);
2608 rtl8139_init_ring (dev);
2609 rtl8139_hw_start (dev);
2610 netif_device_attach (dev);
2611 return 0;
2612 }
2613
2614 #endif /* CONFIG_PM */
2615
2616
2617 static struct pci_driver rtl8139_pci_driver = {
2618 .name = DRV_NAME,
2619 .id_table = rtl8139_pci_tbl,
2620 .probe = rtl8139_init_one,
2621 .remove = __devexit_p(rtl8139_remove_one),
2622 #ifdef CONFIG_PM
2623 .suspend = rtl8139_suspend,
2624 .resume = rtl8139_resume,
2625 #endif /* CONFIG_PM */
2626 };
2627
2628
2629 static int __init rtl8139_init_module (void)
2630 {
2631 /* when we're a module, we always print a version message,
2632 * even if no 8139 board is found.
2633 */
2634 #ifdef MODULE
2635 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2636 #endif
2637
2638 return pci_module_init (&rtl8139_pci_driver);
2639 }
2640
2641
2642 static void __exit rtl8139_cleanup_module (void)
2643 {
2644 pci_unregister_driver (&rtl8139_pci_driver);
2645 }
2646
2647
2648 module_init(rtl8139_init_module);
2649 module_exit(rtl8139_cleanup_module);
x86 "subsystem" repository