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e1000: Allow NVM to setup LPLU for IGP2 and IGP3
[linux-2.6/x86.git] / drivers / net / e1000 / e1000_hw.c
blob3728f33045c395f1675958f62480109794a71509
1 /*******************************************************************************
2
3
4 Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
26 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27
28 *******************************************************************************/
29
30 /* e1000_hw.c
31 * Shared functions for accessing and configuring the MAC
32 */
33
34 #include "e1000_hw.h"
35
36 static int32_t e1000_set_phy_type(struct e1000_hw *hw);
37 static void e1000_phy_init_script(struct e1000_hw *hw);
38 static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
39 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
40 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
41 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
42 static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
43 static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
44 static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
45 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
46 uint16_t count);
47 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
48 static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
49 static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
50 uint16_t words, uint16_t *data);
51 static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
52 uint16_t offset, uint16_t words,
53 uint16_t *data);
54 static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
55 static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
56 static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
57 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
58 uint16_t count);
59 static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
60 uint16_t phy_data);
61 static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
62 uint16_t *phy_data);
63 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
64 static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
65 static void e1000_release_eeprom(struct e1000_hw *hw);
66 static void e1000_standby_eeprom(struct e1000_hw *hw);
67 static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
68 static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
69 static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
70 static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
71 static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
72 static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
73 static int32_t e1000_check_downshift(struct e1000_hw *hw);
74 static int32_t e1000_check_polarity(struct e1000_hw *hw, uint16_t *polarity);
75 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
76 static void e1000_clear_vfta(struct e1000_hw *hw);
77 static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
78 static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw,
79 boolean_t link_up);
80 static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
81 static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
82 static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
83 static int32_t e1000_get_cable_length(struct e1000_hw *hw,
84 uint16_t *min_length,
85 uint16_t *max_length);
86 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
87 static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
88 static int32_t e1000_id_led_init(struct e1000_hw * hw);
89 static void e1000_init_rx_addrs(struct e1000_hw *hw);
90 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
91 static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
92 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
93 static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset,
94 uint16_t words, uint16_t *data);
95 static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
96 static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
97 static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
98
99 static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset,
100 uint32_t value);
101
102 #define E1000_WRITE_REG_IO(a, reg, val) \
103 e1000_write_reg_io((a), E1000_##reg, val)
104 static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
105 uint16_t duplex);
106 static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
107
108 /* IGP cable length table */
109 static const
110 uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
111 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
112 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
113 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
114 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
115 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
116 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
117 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
118 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
119
120 static const
121 uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
122 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
123 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
124 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
125 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
126 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
127 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
128 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
129 104, 109, 114, 118, 121, 124};
130
131
132 /******************************************************************************
133 * Set the phy type member in the hw struct.
134 *
135 * hw - Struct containing variables accessed by shared code
136 *****************************************************************************/
137 int32_t
138 e1000_set_phy_type(struct e1000_hw *hw)
139 {
140 DEBUGFUNC("e1000_set_phy_type");
141
142 if(hw->mac_type == e1000_undefined)
143 return -E1000_ERR_PHY_TYPE;
144
145 switch(hw->phy_id) {
146 case M88E1000_E_PHY_ID:
147 case M88E1000_I_PHY_ID:
148 case M88E1011_I_PHY_ID:
149 case M88E1111_I_PHY_ID:
150 hw->phy_type = e1000_phy_m88;
151 break;
152 case IGP01E1000_I_PHY_ID:
153 if(hw->mac_type == e1000_82541 ||
154 hw->mac_type == e1000_82541_rev_2 ||
155 hw->mac_type == e1000_82547 ||
156 hw->mac_type == e1000_82547_rev_2) {
157 hw->phy_type = e1000_phy_igp;
158 break;
159 }
160 case IGP03E1000_E_PHY_ID:
161 hw->phy_type = e1000_phy_igp_3;
162 break;
163 case IFE_E_PHY_ID:
164 case IFE_PLUS_E_PHY_ID:
165 case IFE_C_E_PHY_ID:
166 hw->phy_type = e1000_phy_ife;
167 break;
168 case GG82563_E_PHY_ID:
169 if (hw->mac_type == e1000_80003es2lan) {
170 hw->phy_type = e1000_phy_gg82563;
171 break;
172 }
173 /* Fall Through */
174 default:
175 /* Should never have loaded on this device */
176 hw->phy_type = e1000_phy_undefined;
177 return -E1000_ERR_PHY_TYPE;
178 }
179
180 return E1000_SUCCESS;
181 }
182
183 /******************************************************************************
184 * IGP phy init script - initializes the GbE PHY
185 *
186 * hw - Struct containing variables accessed by shared code
187 *****************************************************************************/
188 static void
189 e1000_phy_init_script(struct e1000_hw *hw)
190 {
191 uint32_t ret_val;
192 uint16_t phy_saved_data;
193
194 DEBUGFUNC("e1000_phy_init_script");
195
196 if(hw->phy_init_script) {
197 msec_delay(20);
198
199 /* Save off the current value of register 0x2F5B to be restored at
200 * the end of this routine. */
201 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
202
203 /* Disabled the PHY transmitter */
204 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
205
206 msec_delay(20);
207
208 e1000_write_phy_reg(hw,0x0000,0x0140);
209
210 msec_delay(5);
211
212 switch(hw->mac_type) {
213 case e1000_82541:
214 case e1000_82547:
215 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
216
217 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
218
219 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
220
221 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
222
223 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
224
225 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
226
227 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
228
229 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
230
231 e1000_write_phy_reg(hw, 0x2010, 0x0008);
232 break;
233
234 case e1000_82541_rev_2:
235 case e1000_82547_rev_2:
236 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
237 break;
238 default:
239 break;
240 }
241
242 e1000_write_phy_reg(hw, 0x0000, 0x3300);
243
244 msec_delay(20);
245
246 /* Now enable the transmitter */
247 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
248
249 if(hw->mac_type == e1000_82547) {
250 uint16_t fused, fine, coarse;
251
252 /* Move to analog registers page */
253 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
254
255 if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
256 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
257
258 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
259 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
260
261 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
262 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
263 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
264 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
265 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
266
267 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
268 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
269 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
270
271 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
272 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
273 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
274 }
275 }
276 }
277 }
278
279 /******************************************************************************
280 * Set the mac type member in the hw struct.
281 *
282 * hw - Struct containing variables accessed by shared code
283 *****************************************************************************/
284 int32_t
285 e1000_set_mac_type(struct e1000_hw *hw)
286 {
287 DEBUGFUNC("e1000_set_mac_type");
288
289 switch (hw->device_id) {
290 case E1000_DEV_ID_82542:
291 switch (hw->revision_id) {
292 case E1000_82542_2_0_REV_ID:
293 hw->mac_type = e1000_82542_rev2_0;
294 break;
295 case E1000_82542_2_1_REV_ID:
296 hw->mac_type = e1000_82542_rev2_1;
297 break;
298 default:
299 /* Invalid 82542 revision ID */
300 return -E1000_ERR_MAC_TYPE;
301 }
302 break;
303 case E1000_DEV_ID_82543GC_FIBER:
304 case E1000_DEV_ID_82543GC_COPPER:
305 hw->mac_type = e1000_82543;
306 break;
307 case E1000_DEV_ID_82544EI_COPPER:
308 case E1000_DEV_ID_82544EI_FIBER:
309 case E1000_DEV_ID_82544GC_COPPER:
310 case E1000_DEV_ID_82544GC_LOM:
311 hw->mac_type = e1000_82544;
312 break;
313 case E1000_DEV_ID_82540EM:
314 case E1000_DEV_ID_82540EM_LOM:
315 case E1000_DEV_ID_82540EP:
316 case E1000_DEV_ID_82540EP_LOM:
317 case E1000_DEV_ID_82540EP_LP:
318 hw->mac_type = e1000_82540;
319 break;
320 case E1000_DEV_ID_82545EM_COPPER:
321 case E1000_DEV_ID_82545EM_FIBER:
322 hw->mac_type = e1000_82545;
323 break;
324 case E1000_DEV_ID_82545GM_COPPER:
325 case E1000_DEV_ID_82545GM_FIBER:
326 case E1000_DEV_ID_82545GM_SERDES:
327 hw->mac_type = e1000_82545_rev_3;
328 break;
329 case E1000_DEV_ID_82546EB_COPPER:
330 case E1000_DEV_ID_82546EB_FIBER:
331 case E1000_DEV_ID_82546EB_QUAD_COPPER:
332 hw->mac_type = e1000_82546;
333 break;
334 case E1000_DEV_ID_82546GB_COPPER:
335 case E1000_DEV_ID_82546GB_FIBER:
336 case E1000_DEV_ID_82546GB_SERDES:
337 case E1000_DEV_ID_82546GB_PCIE:
338 case E1000_DEV_ID_82546GB_QUAD_COPPER:
339 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
340 hw->mac_type = e1000_82546_rev_3;
341 break;
342 case E1000_DEV_ID_82541EI:
343 case E1000_DEV_ID_82541EI_MOBILE:
344 case E1000_DEV_ID_82541ER_LOM:
345 hw->mac_type = e1000_82541;
346 break;
347 case E1000_DEV_ID_82541ER:
348 case E1000_DEV_ID_82541GI:
349 case E1000_DEV_ID_82541GI_LF:
350 case E1000_DEV_ID_82541GI_MOBILE:
351 hw->mac_type = e1000_82541_rev_2;
352 break;
353 case E1000_DEV_ID_82547EI:
354 case E1000_DEV_ID_82547EI_MOBILE:
355 hw->mac_type = e1000_82547;
356 break;
357 case E1000_DEV_ID_82547GI:
358 hw->mac_type = e1000_82547_rev_2;
359 break;
360 case E1000_DEV_ID_82571EB_COPPER:
361 case E1000_DEV_ID_82571EB_FIBER:
362 case E1000_DEV_ID_82571EB_SERDES:
363 hw->mac_type = e1000_82571;
364 break;
365 case E1000_DEV_ID_82572EI_COPPER:
366 case E1000_DEV_ID_82572EI_FIBER:
367 case E1000_DEV_ID_82572EI_SERDES:
368 case E1000_DEV_ID_82572EI:
369 hw->mac_type = e1000_82572;
370 break;
371 case E1000_DEV_ID_82573E:
372 case E1000_DEV_ID_82573E_IAMT:
373 case E1000_DEV_ID_82573L:
374 hw->mac_type = e1000_82573;
375 break;
376 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
377 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
378 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
379 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
380 hw->mac_type = e1000_80003es2lan;
381 break;
382 case E1000_DEV_ID_ICH8_IGP_M_AMT:
383 case E1000_DEV_ID_ICH8_IGP_AMT:
384 case E1000_DEV_ID_ICH8_IGP_C:
385 case E1000_DEV_ID_ICH8_IFE:
386 case E1000_DEV_ID_ICH8_IGP_M:
387 hw->mac_type = e1000_ich8lan;
388 break;
389 default:
390 /* Should never have loaded on this device */
391 return -E1000_ERR_MAC_TYPE;
392 }
393
394 switch(hw->mac_type) {
395 case e1000_ich8lan:
396 hw->swfwhw_semaphore_present = TRUE;
397 hw->asf_firmware_present = TRUE;
398 break;
399 case e1000_80003es2lan:
400 hw->swfw_sync_present = TRUE;
401 /* fall through */
402 case e1000_82571:
403 case e1000_82572:
404 case e1000_82573:
405 hw->eeprom_semaphore_present = TRUE;
406 /* fall through */
407 case e1000_82541:
408 case e1000_82547:
409 case e1000_82541_rev_2:
410 case e1000_82547_rev_2:
411 hw->asf_firmware_present = TRUE;
412 break;
413 default:
414 break;
415 }
416
417 return E1000_SUCCESS;
418 }
419
420 /*****************************************************************************
421 * Set media type and TBI compatibility.
422 *
423 * hw - Struct containing variables accessed by shared code
424 * **************************************************************************/
425 void
426 e1000_set_media_type(struct e1000_hw *hw)
427 {
428 uint32_t status;
429
430 DEBUGFUNC("e1000_set_media_type");
431
432 if(hw->mac_type != e1000_82543) {
433 /* tbi_compatibility is only valid on 82543 */
434 hw->tbi_compatibility_en = FALSE;
435 }
436
437 switch (hw->device_id) {
438 case E1000_DEV_ID_82545GM_SERDES:
439 case E1000_DEV_ID_82546GB_SERDES:
440 case E1000_DEV_ID_82571EB_SERDES:
441 case E1000_DEV_ID_82572EI_SERDES:
442 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
443 hw->media_type = e1000_media_type_internal_serdes;
444 break;
445 default:
446 switch (hw->mac_type) {
447 case e1000_82542_rev2_0:
448 case e1000_82542_rev2_1:
449 hw->media_type = e1000_media_type_fiber;
450 break;
451 case e1000_ich8lan:
452 case e1000_82573:
453 /* The STATUS_TBIMODE bit is reserved or reused for the this
454 * device.
455 */
456 hw->media_type = e1000_media_type_copper;
457 break;
458 default:
459 status = E1000_READ_REG(hw, STATUS);
460 if (status & E1000_STATUS_TBIMODE) {
461 hw->media_type = e1000_media_type_fiber;
462 /* tbi_compatibility not valid on fiber */
463 hw->tbi_compatibility_en = FALSE;
464 } else {
465 hw->media_type = e1000_media_type_copper;
466 }
467 break;
468 }
469 }
470 }
471
472 /******************************************************************************
473 * Reset the transmit and receive units; mask and clear all interrupts.
474 *
475 * hw - Struct containing variables accessed by shared code
476 *****************************************************************************/
477 int32_t
478 e1000_reset_hw(struct e1000_hw *hw)
479 {
480 uint32_t ctrl;
481 uint32_t ctrl_ext;
482 uint32_t icr;
483 uint32_t manc;
484 uint32_t led_ctrl;
485 uint32_t timeout;
486 uint32_t extcnf_ctrl;
487 int32_t ret_val;
488
489 DEBUGFUNC("e1000_reset_hw");
490
491 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
492 if(hw->mac_type == e1000_82542_rev2_0) {
493 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
494 e1000_pci_clear_mwi(hw);
495 }
496
497 if(hw->bus_type == e1000_bus_type_pci_express) {
498 /* Prevent the PCI-E bus from sticking if there is no TLP connection
499 * on the last TLP read/write transaction when MAC is reset.
500 */
501 if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
502 DEBUGOUT("PCI-E Master disable polling has failed.\n");
503 }
504 }
505
506 /* Clear interrupt mask to stop board from generating interrupts */
507 DEBUGOUT("Masking off all interrupts\n");
508 E1000_WRITE_REG(hw, IMC, 0xffffffff);
509
510 /* Disable the Transmit and Receive units. Then delay to allow
511 * any pending transactions to complete before we hit the MAC with
512 * the global reset.
513 */
514 E1000_WRITE_REG(hw, RCTL, 0);
515 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
516 E1000_WRITE_FLUSH(hw);
517
518 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
519 hw->tbi_compatibility_on = FALSE;
520
521 /* Delay to allow any outstanding PCI transactions to complete before
522 * resetting the device
523 */
524 msec_delay(10);
525
526 ctrl = E1000_READ_REG(hw, CTRL);
527
528 /* Must reset the PHY before resetting the MAC */
529 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
530 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
531 msec_delay(5);
532 }
533
534 /* Must acquire the MDIO ownership before MAC reset.
535 * Ownership defaults to firmware after a reset. */
536 if(hw->mac_type == e1000_82573) {
537 timeout = 10;
538
539 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
540 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
541
542 do {
543 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
544 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
545
546 if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
547 break;
548 else
549 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
550
551 msec_delay(2);
552 timeout--;
553 } while(timeout);
554 }
555
556 /* Workaround for ICH8 bit corruption issue in FIFO memory */
557 if (hw->mac_type == e1000_ich8lan) {
558 /* Set Tx and Rx buffer allocation to 8k apiece. */
559 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
560 /* Set Packet Buffer Size to 16k. */
561 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
562 }
563
564 /* Issue a global reset to the MAC. This will reset the chip's
565 * transmit, receive, DMA, and link units. It will not effect
566 * the current PCI configuration. The global reset bit is self-
567 * clearing, and should clear within a microsecond.
568 */
569 DEBUGOUT("Issuing a global reset to MAC\n");
570
571 switch(hw->mac_type) {
572 case e1000_82544:
573 case e1000_82540:
574 case e1000_82545:
575 case e1000_82546:
576 case e1000_82541:
577 case e1000_82541_rev_2:
578 /* These controllers can't ack the 64-bit write when issuing the
579 * reset, so use IO-mapping as a workaround to issue the reset */
580 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
581 break;
582 case e1000_82545_rev_3:
583 case e1000_82546_rev_3:
584 /* Reset is performed on a shadow of the control register */
585 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
586 break;
587 case e1000_ich8lan:
588 if (!hw->phy_reset_disable &&
589 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
590 /* e1000_ich8lan PHY HW reset requires MAC CORE reset
591 * at the same time to make sure the interface between
592 * MAC and the external PHY is reset.
593 */
594 ctrl |= E1000_CTRL_PHY_RST;
595 }
596
597 e1000_get_software_flag(hw);
598 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
599 msec_delay(5);
600 break;
601 default:
602 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
603 break;
604 }
605
606 /* After MAC reset, force reload of EEPROM to restore power-on settings to
607 * device. Later controllers reload the EEPROM automatically, so just wait
608 * for reload to complete.
609 */
610 switch(hw->mac_type) {
611 case e1000_82542_rev2_0:
612 case e1000_82542_rev2_1:
613 case e1000_82543:
614 case e1000_82544:
615 /* Wait for reset to complete */
616 udelay(10);
617 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
618 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
619 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
620 E1000_WRITE_FLUSH(hw);
621 /* Wait for EEPROM reload */
622 msec_delay(2);
623 break;
624 case e1000_82541:
625 case e1000_82541_rev_2:
626 case e1000_82547:
627 case e1000_82547_rev_2:
628 /* Wait for EEPROM reload */
629 msec_delay(20);
630 break;
631 case e1000_82573:
632 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
633 udelay(10);
634 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
635 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
636 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
637 E1000_WRITE_FLUSH(hw);
638 }
639 /* fall through */
640 case e1000_82571:
641 case e1000_82572:
642 case e1000_ich8lan:
643 case e1000_80003es2lan:
644 ret_val = e1000_get_auto_rd_done(hw);
645 if(ret_val)
646 /* We don't want to continue accessing MAC registers. */
647 return ret_val;
648 break;
649 default:
650 /* Wait for EEPROM reload (it happens automatically) */
651 msec_delay(5);
652 break;
653 }
654
655 /* Disable HW ARPs on ASF enabled adapters */
656 if(hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
657 manc = E1000_READ_REG(hw, MANC);
658 manc &= ~(E1000_MANC_ARP_EN);
659 E1000_WRITE_REG(hw, MANC, manc);
660 }
661
662 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
663 e1000_phy_init_script(hw);
664
665 /* Configure activity LED after PHY reset */
666 led_ctrl = E1000_READ_REG(hw, LEDCTL);
667 led_ctrl &= IGP_ACTIVITY_LED_MASK;
668 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
669 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
670 }
671
672 /* Clear interrupt mask to stop board from generating interrupts */
673 DEBUGOUT("Masking off all interrupts\n");
674 E1000_WRITE_REG(hw, IMC, 0xffffffff);
675
676 /* Clear any pending interrupt events. */
677 icr = E1000_READ_REG(hw, ICR);
678
679 /* If MWI was previously enabled, reenable it. */
680 if(hw->mac_type == e1000_82542_rev2_0) {
681 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
682 e1000_pci_set_mwi(hw);
683 }
684
685 if (hw->mac_type == e1000_ich8lan) {
686 uint32_t kab = E1000_READ_REG(hw, KABGTXD);
687 kab |= E1000_KABGTXD_BGSQLBIAS;
688 E1000_WRITE_REG(hw, KABGTXD, kab);
689 }
690
691 return E1000_SUCCESS;
692 }
693
694 /******************************************************************************
695 * Performs basic configuration of the adapter.
696 *
697 * hw - Struct containing variables accessed by shared code
698 *
699 * Assumes that the controller has previously been reset and is in a
700 * post-reset uninitialized state. Initializes the receive address registers,
701 * multicast table, and VLAN filter table. Calls routines to setup link
702 * configuration and flow control settings. Clears all on-chip counters. Leaves
703 * the transmit and receive units disabled and uninitialized.
704 *****************************************************************************/
705 int32_t
706 e1000_init_hw(struct e1000_hw *hw)
707 {
708 uint32_t ctrl;
709 uint32_t i;
710 int32_t ret_val;
711 uint16_t pcix_cmd_word;
712 uint16_t pcix_stat_hi_word;
713 uint16_t cmd_mmrbc;
714 uint16_t stat_mmrbc;
715 uint32_t mta_size;
716 uint32_t reg_data;
717 uint32_t ctrl_ext;
718
719 DEBUGFUNC("e1000_init_hw");
720
721 /* Initialize Identification LED */
722 ret_val = e1000_id_led_init(hw);
723 if(ret_val) {
724 DEBUGOUT("Error Initializing Identification LED\n");
725 return ret_val;
726 }
727
728 /* Set the media type and TBI compatibility */
729 e1000_set_media_type(hw);
730
731 /* Disabling VLAN filtering. */
732 DEBUGOUT("Initializing the IEEE VLAN\n");
733 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
734 if (hw->mac_type != e1000_ich8lan) {
735 if (hw->mac_type < e1000_82545_rev_3)
736 E1000_WRITE_REG(hw, VET, 0);
737 e1000_clear_vfta(hw);
738 }
739
740 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
741 if(hw->mac_type == e1000_82542_rev2_0) {
742 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
743 e1000_pci_clear_mwi(hw);
744 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
745 E1000_WRITE_FLUSH(hw);
746 msec_delay(5);
747 }
748
749 /* Setup the receive address. This involves initializing all of the Receive
750 * Address Registers (RARs 0 - 15).
751 */
752 e1000_init_rx_addrs(hw);
753
754 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
755 if(hw->mac_type == e1000_82542_rev2_0) {
756 E1000_WRITE_REG(hw, RCTL, 0);
757 E1000_WRITE_FLUSH(hw);
758 msec_delay(1);
759 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
760 e1000_pci_set_mwi(hw);
761 }
762
763 /* Zero out the Multicast HASH table */
764 DEBUGOUT("Zeroing the MTA\n");
765 mta_size = E1000_MC_TBL_SIZE;
766 if (hw->mac_type == e1000_ich8lan)
767 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
768 for(i = 0; i < mta_size; i++) {
769 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
770 /* use write flush to prevent Memory Write Block (MWB) from
771 * occuring when accessing our register space */
772 E1000_WRITE_FLUSH(hw);
773 }
774
775 /* Set the PCI priority bit correctly in the CTRL register. This
776 * determines if the adapter gives priority to receives, or if it
777 * gives equal priority to transmits and receives. Valid only on
778 * 82542 and 82543 silicon.
779 */
780 if(hw->dma_fairness && hw->mac_type <= e1000_82543) {
781 ctrl = E1000_READ_REG(hw, CTRL);
782 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
783 }
784
785 switch(hw->mac_type) {
786 case e1000_82545_rev_3:
787 case e1000_82546_rev_3:
788 break;
789 default:
790 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
791 if(hw->bus_type == e1000_bus_type_pcix) {
792 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
793 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
794 &pcix_stat_hi_word);
795 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
796 PCIX_COMMAND_MMRBC_SHIFT;
797 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
798 PCIX_STATUS_HI_MMRBC_SHIFT;
799 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
800 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
801 if(cmd_mmrbc > stat_mmrbc) {
802 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
803 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
804 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
805 &pcix_cmd_word);
806 }
807 }
808 break;
809 }
810
811 /* More time needed for PHY to initialize */
812 if (hw->mac_type == e1000_ich8lan)
813 msec_delay(15);
814
815 /* Call a subroutine to configure the link and setup flow control. */
816 ret_val = e1000_setup_link(hw);
817
818 /* Set the transmit descriptor write-back policy */
819 if(hw->mac_type > e1000_82544) {
820 ctrl = E1000_READ_REG(hw, TXDCTL);
821 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
822 switch (hw->mac_type) {
823 default:
824 break;
825 case e1000_82571:
826 case e1000_82572:
827 case e1000_82573:
828 case e1000_ich8lan:
829 case e1000_80003es2lan:
830 ctrl |= E1000_TXDCTL_COUNT_DESC;
831 break;
832 }
833 E1000_WRITE_REG(hw, TXDCTL, ctrl);
834 }
835
836 if (hw->mac_type == e1000_82573) {
837 e1000_enable_tx_pkt_filtering(hw);
838 }
839
840 switch (hw->mac_type) {
841 default:
842 break;
843 case e1000_80003es2lan:
844 /* Enable retransmit on late collisions */
845 reg_data = E1000_READ_REG(hw, TCTL);
846 reg_data |= E1000_TCTL_RTLC;
847 E1000_WRITE_REG(hw, TCTL, reg_data);
848
849 /* Configure Gigabit Carry Extend Padding */
850 reg_data = E1000_READ_REG(hw, TCTL_EXT);
851 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
852 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
853 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
854
855 /* Configure Transmit Inter-Packet Gap */
856 reg_data = E1000_READ_REG(hw, TIPG);
857 reg_data &= ~E1000_TIPG_IPGT_MASK;
858 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
859 E1000_WRITE_REG(hw, TIPG, reg_data);
860
861 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
862 reg_data &= ~0x00100000;
863 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
864 /* Fall through */
865 case e1000_82571:
866 case e1000_82572:
867 case e1000_ich8lan:
868 ctrl = E1000_READ_REG(hw, TXDCTL1);
869 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
870 if(hw->mac_type >= e1000_82571)
871 ctrl |= E1000_TXDCTL_COUNT_DESC;
872 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
873 break;
874 }
875
876
877
878 if (hw->mac_type == e1000_82573) {
879 uint32_t gcr = E1000_READ_REG(hw, GCR);
880 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
881 E1000_WRITE_REG(hw, GCR, gcr);
882 }
883
884 /* Clear all of the statistics registers (clear on read). It is
885 * important that we do this after we have tried to establish link
886 * because the symbol error count will increment wildly if there
887 * is no link.
888 */
889 e1000_clear_hw_cntrs(hw);
890
891 /* ICH8 No-snoop bits are opposite polarity.
892 * Set to snoop by default after reset. */
893 if (hw->mac_type == e1000_ich8lan)
894 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
895
896 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
897 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
898 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
899 /* Relaxed ordering must be disabled to avoid a parity
900 * error crash in a PCI slot. */
901 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
902 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
903 }
904
905 return ret_val;
906 }
907
908 /******************************************************************************
909 * Adjust SERDES output amplitude based on EEPROM setting.
910 *
911 * hw - Struct containing variables accessed by shared code.
912 *****************************************************************************/
913 static int32_t
914 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
915 {
916 uint16_t eeprom_data;
917 int32_t ret_val;
918
919 DEBUGFUNC("e1000_adjust_serdes_amplitude");
920
921 if(hw->media_type != e1000_media_type_internal_serdes)
922 return E1000_SUCCESS;
923
924 switch(hw->mac_type) {
925 case e1000_82545_rev_3:
926 case e1000_82546_rev_3:
927 break;
928 default:
929 return E1000_SUCCESS;
930 }
931
932 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
933 if (ret_val) {
934 return ret_val;
935 }
936
937 if(eeprom_data != EEPROM_RESERVED_WORD) {
938 /* Adjust SERDES output amplitude only. */
939 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
940 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
941 if(ret_val)
942 return ret_val;
943 }
944
945 return E1000_SUCCESS;
946 }
947
948 /******************************************************************************
949 * Configures flow control and link settings.
950 *
951 * hw - Struct containing variables accessed by shared code
952 *
953 * Determines which flow control settings to use. Calls the apropriate media-
954 * specific link configuration function. Configures the flow control settings.
955 * Assuming the adapter has a valid link partner, a valid link should be
956 * established. Assumes the hardware has previously been reset and the
957 * transmitter and receiver are not enabled.
958 *****************************************************************************/
959 int32_t
960 e1000_setup_link(struct e1000_hw *hw)
961 {
962 uint32_t ctrl_ext;
963 int32_t ret_val;
964 uint16_t eeprom_data;
965
966 DEBUGFUNC("e1000_setup_link");
967
968 /* In the case of the phy reset being blocked, we already have a link.
969 * We do not have to set it up again. */
970 if (e1000_check_phy_reset_block(hw))
971 return E1000_SUCCESS;
972
973 /* Read and store word 0x0F of the EEPROM. This word contains bits
974 * that determine the hardware's default PAUSE (flow control) mode,
975 * a bit that determines whether the HW defaults to enabling or
976 * disabling auto-negotiation, and the direction of the
977 * SW defined pins. If there is no SW over-ride of the flow
978 * control setting, then the variable hw->fc will
979 * be initialized based on a value in the EEPROM.
980 */
981 if (hw->fc == e1000_fc_default) {
982 switch (hw->mac_type) {
983 case e1000_ich8lan:
984 case e1000_82573:
985 hw->fc = e1000_fc_full;
986 break;
987 default:
988 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
989 1, &eeprom_data);
990 if (ret_val) {
991 DEBUGOUT("EEPROM Read Error\n");
992 return -E1000_ERR_EEPROM;
993 }
994 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
995 hw->fc = e1000_fc_none;
996 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
997 EEPROM_WORD0F_ASM_DIR)
998 hw->fc = e1000_fc_tx_pause;
999 else
1000 hw->fc = e1000_fc_full;
1001 break;
1002 }
1003 }
1004
1005 /* We want to save off the original Flow Control configuration just
1006 * in case we get disconnected and then reconnected into a different
1007 * hub or switch with different Flow Control capabilities.
1008 */
1009 if(hw->mac_type == e1000_82542_rev2_0)
1010 hw->fc &= (~e1000_fc_tx_pause);
1011
1012 if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1013 hw->fc &= (~e1000_fc_rx_pause);
1014
1015 hw->original_fc = hw->fc;
1016
1017 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1018
1019 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1020 * polarity value for the SW controlled pins, and setup the
1021 * Extended Device Control reg with that info.
1022 * This is needed because one of the SW controlled pins is used for
1023 * signal detection. So this should be done before e1000_setup_pcs_link()
1024 * or e1000_phy_setup() is called.
1025 */
1026 if (hw->mac_type == e1000_82543) {
1027 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1028 1, &eeprom_data);
1029 if (ret_val) {
1030 DEBUGOUT("EEPROM Read Error\n");
1031 return -E1000_ERR_EEPROM;
1032 }
1033 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1034 SWDPIO__EXT_SHIFT);
1035 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1036 }
1037
1038 /* Call the necessary subroutine to configure the link. */
1039 ret_val = (hw->media_type == e1000_media_type_copper) ?
1040 e1000_setup_copper_link(hw) :
1041 e1000_setup_fiber_serdes_link(hw);
1042
1043 /* Initialize the flow control address, type, and PAUSE timer
1044 * registers to their default values. This is done even if flow
1045 * control is disabled, because it does not hurt anything to
1046 * initialize these registers.
1047 */
1048 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1049
1050 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1051 if (hw->mac_type != e1000_ich8lan) {
1052 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1053 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1054 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1055 }
1056
1057 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1058
1059 /* Set the flow control receive threshold registers. Normally,
1060 * these registers will be set to a default threshold that may be
1061 * adjusted later by the driver's runtime code. However, if the
1062 * ability to transmit pause frames in not enabled, then these
1063 * registers will be set to 0.
1064 */
1065 if(!(hw->fc & e1000_fc_tx_pause)) {
1066 E1000_WRITE_REG(hw, FCRTL, 0);
1067 E1000_WRITE_REG(hw, FCRTH, 0);
1068 } else {
1069 /* We need to set up the Receive Threshold high and low water marks
1070 * as well as (optionally) enabling the transmission of XON frames.
1071 */
1072 if(hw->fc_send_xon) {
1073 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1074 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1075 } else {
1076 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1077 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1078 }
1079 }
1080 return ret_val;
1081 }
1082
1083 /******************************************************************************
1084 * Sets up link for a fiber based or serdes based adapter
1085 *
1086 * hw - Struct containing variables accessed by shared code
1087 *
1088 * Manipulates Physical Coding Sublayer functions in order to configure
1089 * link. Assumes the hardware has been previously reset and the transmitter
1090 * and receiver are not enabled.
1091 *****************************************************************************/
1092 static int32_t
1093 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1094 {
1095 uint32_t ctrl;
1096 uint32_t status;
1097 uint32_t txcw = 0;
1098 uint32_t i;
1099 uint32_t signal = 0;
1100 int32_t ret_val;
1101
1102 DEBUGFUNC("e1000_setup_fiber_serdes_link");
1103
1104 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
1105 * until explicitly turned off or a power cycle is performed. A read to
1106 * the register does not indicate its status. Therefore, we ensure
1107 * loopback mode is disabled during initialization.
1108 */
1109 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1110 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1111
1112 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
1113 * set when the optics detect a signal. On older adapters, it will be
1114 * cleared when there is a signal. This applies to fiber media only.
1115 * If we're on serdes media, adjust the output amplitude to value set in
1116 * the EEPROM.
1117 */
1118 ctrl = E1000_READ_REG(hw, CTRL);
1119 if(hw->media_type == e1000_media_type_fiber)
1120 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1121
1122 ret_val = e1000_adjust_serdes_amplitude(hw);
1123 if(ret_val)
1124 return ret_val;
1125
1126 /* Take the link out of reset */
1127 ctrl &= ~(E1000_CTRL_LRST);
1128
1129 /* Adjust VCO speed to improve BER performance */
1130 ret_val = e1000_set_vco_speed(hw);
1131 if(ret_val)
1132 return ret_val;
1133
1134 e1000_config_collision_dist(hw);
1135
1136 /* Check for a software override of the flow control settings, and setup
1137 * the device accordingly. If auto-negotiation is enabled, then software
1138 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1139 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1140 * auto-negotiation is disabled, then software will have to manually
1141 * configure the two flow control enable bits in the CTRL register.
1142 *
1143 * The possible values of the "fc" parameter are:
1144 * 0: Flow control is completely disabled
1145 * 1: Rx flow control is enabled (we can receive pause frames, but
1146 * not send pause frames).
1147 * 2: Tx flow control is enabled (we can send pause frames but we do
1148 * not support receiving pause frames).
1149 * 3: Both Rx and TX flow control (symmetric) are enabled.
1150 */
1151 switch (hw->fc) {
1152 case e1000_fc_none:
1153 /* Flow control is completely disabled by a software over-ride. */
1154 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1155 break;
1156 case e1000_fc_rx_pause:
1157 /* RX Flow control is enabled and TX Flow control is disabled by a
1158 * software over-ride. Since there really isn't a way to advertise
1159 * that we are capable of RX Pause ONLY, we will advertise that we
1160 * support both symmetric and asymmetric RX PAUSE. Later, we will
1161 * disable the adapter's ability to send PAUSE frames.
1162 */
1163 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1164 break;
1165 case e1000_fc_tx_pause:
1166 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1167 * software over-ride.
1168 */
1169 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1170 break;
1171 case e1000_fc_full:
1172 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1173 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1174 break;
1175 default:
1176 DEBUGOUT("Flow control param set incorrectly\n");
1177 return -E1000_ERR_CONFIG;
1178 break;
1179 }
1180
1181 /* Since auto-negotiation is enabled, take the link out of reset (the link
1182 * will be in reset, because we previously reset the chip). This will
1183 * restart auto-negotiation. If auto-neogtiation is successful then the
1184 * link-up status bit will be set and the flow control enable bits (RFCE
1185 * and TFCE) will be set according to their negotiated value.
1186 */
1187 DEBUGOUT("Auto-negotiation enabled\n");
1188
1189 E1000_WRITE_REG(hw, TXCW, txcw);
1190 E1000_WRITE_REG(hw, CTRL, ctrl);
1191 E1000_WRITE_FLUSH(hw);
1192
1193 hw->txcw = txcw;
1194 msec_delay(1);
1195
1196 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1197 * indication in the Device Status Register. Time-out if a link isn't
1198 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1199 * less than 500 milliseconds even if the other end is doing it in SW).
1200 * For internal serdes, we just assume a signal is present, then poll.
1201 */
1202 if(hw->media_type == e1000_media_type_internal_serdes ||
1203 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1204 DEBUGOUT("Looking for Link\n");
1205 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1206 msec_delay(10);
1207 status = E1000_READ_REG(hw, STATUS);
1208 if(status & E1000_STATUS_LU) break;
1209 }
1210 if(i == (LINK_UP_TIMEOUT / 10)) {
1211 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1212 hw->autoneg_failed = 1;
1213 /* AutoNeg failed to achieve a link, so we'll call
1214 * e1000_check_for_link. This routine will force the link up if
1215 * we detect a signal. This will allow us to communicate with
1216 * non-autonegotiating link partners.
1217 */
1218 ret_val = e1000_check_for_link(hw);
1219 if(ret_val) {
1220 DEBUGOUT("Error while checking for link\n");
1221 return ret_val;
1222 }
1223 hw->autoneg_failed = 0;
1224 } else {
1225 hw->autoneg_failed = 0;
1226 DEBUGOUT("Valid Link Found\n");
1227 }
1228 } else {
1229 DEBUGOUT("No Signal Detected\n");
1230 }
1231 return E1000_SUCCESS;
1232 }
1233
1234 /******************************************************************************
1235 * Make sure we have a valid PHY and change PHY mode before link setup.
1236 *
1237 * hw - Struct containing variables accessed by shared code
1238 ******************************************************************************/
1239 static int32_t
1240 e1000_copper_link_preconfig(struct e1000_hw *hw)
1241 {
1242 uint32_t ctrl;
1243 int32_t ret_val;
1244 uint16_t phy_data;
1245
1246 DEBUGFUNC("e1000_copper_link_preconfig");
1247
1248 ctrl = E1000_READ_REG(hw, CTRL);
1249 /* With 82543, we need to force speed and duplex on the MAC equal to what
1250 * the PHY speed and duplex configuration is. In addition, we need to
1251 * perform a hardware reset on the PHY to take it out of reset.
1252 */
1253 if(hw->mac_type > e1000_82543) {
1254 ctrl |= E1000_CTRL_SLU;
1255 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1256 E1000_WRITE_REG(hw, CTRL, ctrl);
1257 } else {
1258 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1259 E1000_WRITE_REG(hw, CTRL, ctrl);
1260 ret_val = e1000_phy_hw_reset(hw);
1261 if(ret_val)
1262 return ret_val;
1263 }
1264
1265 /* Make sure we have a valid PHY */
1266 ret_val = e1000_detect_gig_phy(hw);
1267 if(ret_val) {
1268 DEBUGOUT("Error, did not detect valid phy.\n");
1269 return ret_val;
1270 }
1271 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1272
1273 /* Set PHY to class A mode (if necessary) */
1274 ret_val = e1000_set_phy_mode(hw);
1275 if(ret_val)
1276 return ret_val;
1277
1278 if((hw->mac_type == e1000_82545_rev_3) ||
1279 (hw->mac_type == e1000_82546_rev_3)) {
1280 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1281 phy_data |= 0x00000008;
1282 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1283 }
1284
1285 if(hw->mac_type <= e1000_82543 ||
1286 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1287 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1288 hw->phy_reset_disable = FALSE;
1289
1290 return E1000_SUCCESS;
1291 }
1292
1293
1294 /********************************************************************
1295 * Copper link setup for e1000_phy_igp series.
1296 *
1297 * hw - Struct containing variables accessed by shared code
1298 *********************************************************************/
1299 static int32_t
1300 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1301 {
1302 uint32_t led_ctrl;
1303 int32_t ret_val;
1304 uint16_t phy_data;
1305
1306 DEBUGFUNC("e1000_copper_link_igp_setup");
1307
1308 if (hw->phy_reset_disable)
1309 return E1000_SUCCESS;
1310
1311 ret_val = e1000_phy_reset(hw);
1312 if (ret_val) {
1313 DEBUGOUT("Error Resetting the PHY\n");
1314 return ret_val;
1315 }
1316
1317 /* Wait 10ms for MAC to configure PHY from eeprom settings */
1318 msec_delay(15);
1319 if (hw->mac_type != e1000_ich8lan) {
1320 /* Configure activity LED after PHY reset */
1321 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1322 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1323 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1324 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1325 }
1326
1327 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1328 if (hw->phy_type == e1000_phy_igp) {
1329 /* disable lplu d3 during driver init */
1330 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1331 if (ret_val) {
1332 DEBUGOUT("Error Disabling LPLU D3\n");
1333 return ret_val;
1334 }
1335 }
1336
1337 /* disable lplu d0 during driver init */
1338 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1339 if (ret_val) {
1340 DEBUGOUT("Error Disabling LPLU D0\n");
1341 return ret_val;
1342 }
1343 /* Configure mdi-mdix settings */
1344 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1345 if (ret_val)
1346 return ret_val;
1347
1348 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1349 hw->dsp_config_state = e1000_dsp_config_disabled;
1350 /* Force MDI for earlier revs of the IGP PHY */
1351 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1352 hw->mdix = 1;
1353
1354 } else {
1355 hw->dsp_config_state = e1000_dsp_config_enabled;
1356 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1357
1358 switch (hw->mdix) {
1359 case 1:
1360 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1361 break;
1362 case 2:
1363 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1364 break;
1365 case 0:
1366 default:
1367 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1368 break;
1369 }
1370 }
1371 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1372 if(ret_val)
1373 return ret_val;
1374
1375 /* set auto-master slave resolution settings */
1376 if(hw->autoneg) {
1377 e1000_ms_type phy_ms_setting = hw->master_slave;
1378
1379 if(hw->ffe_config_state == e1000_ffe_config_active)
1380 hw->ffe_config_state = e1000_ffe_config_enabled;
1381
1382 if(hw->dsp_config_state == e1000_dsp_config_activated)
1383 hw->dsp_config_state = e1000_dsp_config_enabled;
1384
1385 /* when autonegotiation advertisment is only 1000Mbps then we
1386 * should disable SmartSpeed and enable Auto MasterSlave
1387 * resolution as hardware default. */
1388 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1389 /* Disable SmartSpeed */
1390 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
1391 if(ret_val)
1392 return ret_val;
1393 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1394 ret_val = e1000_write_phy_reg(hw,
1395 IGP01E1000_PHY_PORT_CONFIG,
1396 phy_data);
1397 if(ret_val)
1398 return ret_val;
1399 /* Set auto Master/Slave resolution process */
1400 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1401 if(ret_val)
1402 return ret_val;
1403 phy_data &= ~CR_1000T_MS_ENABLE;
1404 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1405 if(ret_val)
1406 return ret_val;
1407 }
1408
1409 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1410 if(ret_val)
1411 return ret_val;
1412
1413 /* load defaults for future use */
1414 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1415 ((phy_data & CR_1000T_MS_VALUE) ?
1416 e1000_ms_force_master :
1417 e1000_ms_force_slave) :
1418 e1000_ms_auto;
1419
1420 switch (phy_ms_setting) {
1421 case e1000_ms_force_master:
1422 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1423 break;
1424 case e1000_ms_force_slave:
1425 phy_data |= CR_1000T_MS_ENABLE;
1426 phy_data &= ~(CR_1000T_MS_VALUE);
1427 break;
1428 case e1000_ms_auto:
1429 phy_data &= ~CR_1000T_MS_ENABLE;
1430 default:
1431 break;
1432 }
1433 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1434 if(ret_val)
1435 return ret_val;
1436 }
1437
1438 return E1000_SUCCESS;
1439 }
1440
1441 /********************************************************************
1442 * Copper link setup for e1000_phy_gg82563 series.
1443 *
1444 * hw - Struct containing variables accessed by shared code
1445 *********************************************************************/
1446 static int32_t
1447 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1448 {
1449 int32_t ret_val;
1450 uint16_t phy_data;
1451 uint32_t reg_data;
1452
1453 DEBUGFUNC("e1000_copper_link_ggp_setup");
1454
1455 if(!hw->phy_reset_disable) {
1456
1457 /* Enable CRS on TX for half-duplex operation. */
1458 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1459 &phy_data);
1460 if(ret_val)
1461 return ret_val;
1462
1463 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1464 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
1465 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1466
1467 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1468 phy_data);
1469 if(ret_val)
1470 return ret_val;
1471
1472 /* Options:
1473 * MDI/MDI-X = 0 (default)
1474 * 0 - Auto for all speeds
1475 * 1 - MDI mode
1476 * 2 - MDI-X mode
1477 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1478 */
1479 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
1480 if(ret_val)
1481 return ret_val;
1482
1483 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1484
1485 switch (hw->mdix) {
1486 case 1:
1487 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1488 break;
1489 case 2:
1490 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1491 break;
1492 case 0:
1493 default:
1494 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1495 break;
1496 }
1497
1498 /* Options:
1499 * disable_polarity_correction = 0 (default)
1500 * Automatic Correction for Reversed Cable Polarity
1501 * 0 - Disabled
1502 * 1 - Enabled
1503 */
1504 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1505 if(hw->disable_polarity_correction == 1)
1506 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1507 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1508
1509 if(ret_val)
1510 return ret_val;
1511
1512 /* SW Reset the PHY so all changes take effect */
1513 ret_val = e1000_phy_reset(hw);
1514 if (ret_val) {
1515 DEBUGOUT("Error Resetting the PHY\n");
1516 return ret_val;
1517 }
1518 } /* phy_reset_disable */
1519
1520 if (hw->mac_type == e1000_80003es2lan) {
1521 /* Bypass RX and TX FIFO's */
1522 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1523 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
1524 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1525 if (ret_val)
1526 return ret_val;
1527
1528 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1529 if (ret_val)
1530 return ret_val;
1531
1532 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1533 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1534
1535 if (ret_val)
1536 return ret_val;
1537
1538 reg_data = E1000_READ_REG(hw, CTRL_EXT);
1539 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1540 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
1541
1542 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1543 &phy_data);
1544 if (ret_val)
1545 return ret_val;
1546
1547 /* Do not init these registers when the HW is in IAMT mode, since the
1548 * firmware will have already initialized them. We only initialize
1549 * them if the HW is not in IAMT mode.
1550 */
1551 if (e1000_check_mng_mode(hw) == FALSE) {
1552 /* Enable Electrical Idle on the PHY */
1553 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1554 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1555 phy_data);
1556 if (ret_val)
1557 return ret_val;
1558
1559 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1560 &phy_data);
1561 if (ret_val)
1562 return ret_val;
1563
1564 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1565
1566 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1567 phy_data);
1568 if (ret_val)
1569 return ret_val;
1570 }
1571
1572 /* Workaround: Disable padding in Kumeran interface in the MAC
1573 * and in the PHY to avoid CRC errors.
1574 */
1575 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1576 &phy_data);
1577 if (ret_val)
1578 return ret_val;
1579 phy_data |= GG82563_ICR_DIS_PADDING;
1580 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1581 phy_data);
1582 if (ret_val)
1583 return ret_val;
1584 }
1585
1586 return E1000_SUCCESS;
1587 }
1588
1589 /********************************************************************
1590 * Copper link setup for e1000_phy_m88 series.
1591 *
1592 * hw - Struct containing variables accessed by shared code
1593 *********************************************************************/
1594 static int32_t
1595 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1596 {
1597 int32_t ret_val;
1598 uint16_t phy_data;
1599
1600 DEBUGFUNC("e1000_copper_link_mgp_setup");
1601
1602 if(hw->phy_reset_disable)
1603 return E1000_SUCCESS;
1604
1605 /* Enable CRS on TX. This must be set for half-duplex operation. */
1606 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1607 if(ret_val)
1608 return ret_val;
1609
1610 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1611
1612 /* Options:
1613 * MDI/MDI-X = 0 (default)
1614 * 0 - Auto for all speeds
1615 * 1 - MDI mode
1616 * 2 - MDI-X mode
1617 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1618 */
1619 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1620
1621 switch (hw->mdix) {
1622 case 1:
1623 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1624 break;
1625 case 2:
1626 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1627 break;
1628 case 3:
1629 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1630 break;
1631 case 0:
1632 default:
1633 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1634 break;
1635 }
1636
1637 /* Options:
1638 * disable_polarity_correction = 0 (default)
1639 * Automatic Correction for Reversed Cable Polarity
1640 * 0 - Disabled
1641 * 1 - Enabled
1642 */
1643 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1644 if(hw->disable_polarity_correction == 1)
1645 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1646 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1647 if (ret_val)
1648 return ret_val;
1649
1650 if (hw->phy_revision < M88E1011_I_REV_4) {
1651 /* Force TX_CLK in the Extended PHY Specific Control Register
1652 * to 25MHz clock.
1653 */
1654 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1655 if (ret_val)
1656 return ret_val;
1657
1658 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1659
1660 if ((hw->phy_revision == E1000_REVISION_2) &&
1661 (hw->phy_id == M88E1111_I_PHY_ID)) {
1662 /* Vidalia Phy, set the downshift counter to 5x */
1663 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1664 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1665 ret_val = e1000_write_phy_reg(hw,
1666 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1667 if (ret_val)
1668 return ret_val;
1669 } else {
1670 /* Configure Master and Slave downshift values */
1671 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1672 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1673 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1674 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1675 ret_val = e1000_write_phy_reg(hw,
1676 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1677 if (ret_val)
1678 return ret_val;
1679 }
1680 }
1681
1682 /* SW Reset the PHY so all changes take effect */
1683 ret_val = e1000_phy_reset(hw);
1684 if(ret_val) {
1685 DEBUGOUT("Error Resetting the PHY\n");
1686 return ret_val;
1687 }
1688
1689 return E1000_SUCCESS;
1690 }
1691
1692 /********************************************************************
1693 * Setup auto-negotiation and flow control advertisements,
1694 * and then perform auto-negotiation.
1695 *
1696 * hw - Struct containing variables accessed by shared code
1697 *********************************************************************/
1698 static int32_t
1699 e1000_copper_link_autoneg(struct e1000_hw *hw)
1700 {
1701 int32_t ret_val;
1702 uint16_t phy_data;
1703
1704 DEBUGFUNC("e1000_copper_link_autoneg");
1705
1706 /* Perform some bounds checking on the hw->autoneg_advertised
1707 * parameter. If this variable is zero, then set it to the default.
1708 */
1709 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1710
1711 /* If autoneg_advertised is zero, we assume it was not defaulted
1712 * by the calling code so we set to advertise full capability.
1713 */
1714 if(hw->autoneg_advertised == 0)
1715 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1716
1717 /* IFE phy only supports 10/100 */
1718 if (hw->phy_type == e1000_phy_ife)
1719 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1720
1721 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1722 ret_val = e1000_phy_setup_autoneg(hw);
1723 if(ret_val) {
1724 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1725 return ret_val;
1726 }
1727 DEBUGOUT("Restarting Auto-Neg\n");
1728
1729 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1730 * the Auto Neg Restart bit in the PHY control register.
1731 */
1732 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1733 if(ret_val)
1734 return ret_val;
1735
1736 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1737 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1738 if(ret_val)
1739 return ret_val;
1740
1741 /* Does the user want to wait for Auto-Neg to complete here, or
1742 * check at a later time (for example, callback routine).
1743 */
1744 if(hw->wait_autoneg_complete) {
1745 ret_val = e1000_wait_autoneg(hw);
1746 if(ret_val) {
1747 DEBUGOUT("Error while waiting for autoneg to complete\n");
1748 return ret_val;
1749 }
1750 }
1751
1752 hw->get_link_status = TRUE;
1753
1754 return E1000_SUCCESS;
1755 }
1756
1757
1758 /******************************************************************************
1759 * Config the MAC and the PHY after link is up.
1760 * 1) Set up the MAC to the current PHY speed/duplex
1761 * if we are on 82543. If we
1762 * are on newer silicon, we only need to configure
1763 * collision distance in the Transmit Control Register.
1764 * 2) Set up flow control on the MAC to that established with
1765 * the link partner.
1766 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1767 *
1768 * hw - Struct containing variables accessed by shared code
1769 ******************************************************************************/
1770 static int32_t
1771 e1000_copper_link_postconfig(struct e1000_hw *hw)
1772 {
1773 int32_t ret_val;
1774 DEBUGFUNC("e1000_copper_link_postconfig");
1775
1776 if(hw->mac_type >= e1000_82544) {
1777 e1000_config_collision_dist(hw);
1778 } else {
1779 ret_val = e1000_config_mac_to_phy(hw);
1780 if(ret_val) {
1781 DEBUGOUT("Error configuring MAC to PHY settings\n");
1782 return ret_val;
1783 }
1784 }
1785 ret_val = e1000_config_fc_after_link_up(hw);
1786 if(ret_val) {
1787 DEBUGOUT("Error Configuring Flow Control\n");
1788 return ret_val;
1789 }
1790
1791 /* Config DSP to improve Giga link quality */
1792 if(hw->phy_type == e1000_phy_igp) {
1793 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1794 if(ret_val) {
1795 DEBUGOUT("Error Configuring DSP after link up\n");
1796 return ret_val;
1797 }
1798 }
1799
1800 return E1000_SUCCESS;
1801 }
1802
1803 /******************************************************************************
1804 * Detects which PHY is present and setup the speed and duplex
1805 *
1806 * hw - Struct containing variables accessed by shared code
1807 ******************************************************************************/
1808 static int32_t
1809 e1000_setup_copper_link(struct e1000_hw *hw)
1810 {
1811 int32_t ret_val;
1812 uint16_t i;
1813 uint16_t phy_data;
1814 uint16_t reg_data;
1815
1816 DEBUGFUNC("e1000_setup_copper_link");
1817
1818 switch (hw->mac_type) {
1819 case e1000_80003es2lan:
1820 case e1000_ich8lan:
1821 /* Set the mac to wait the maximum time between each
1822 * iteration and increase the max iterations when
1823 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1824 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1825 if (ret_val)
1826 return ret_val;
1827 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1828 if (ret_val)
1829 return ret_val;
1830 reg_data |= 0x3F;
1831 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1832 if (ret_val)
1833 return ret_val;
1834 default:
1835 break;
1836 }
1837
1838 /* Check if it is a valid PHY and set PHY mode if necessary. */
1839 ret_val = e1000_copper_link_preconfig(hw);
1840 if(ret_val)
1841 return ret_val;
1842
1843 switch (hw->mac_type) {
1844 case e1000_80003es2lan:
1845 /* Kumeran registers are written-only */
1846 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
1847 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1848 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1849 reg_data);
1850 if (ret_val)
1851 return ret_val;
1852 break;
1853 default:
1854 break;
1855 }
1856
1857 if (hw->phy_type == e1000_phy_igp ||
1858 hw->phy_type == e1000_phy_igp_3 ||
1859 hw->phy_type == e1000_phy_igp_2) {
1860 ret_val = e1000_copper_link_igp_setup(hw);
1861 if(ret_val)
1862 return ret_val;
1863 } else if (hw->phy_type == e1000_phy_m88) {
1864 ret_val = e1000_copper_link_mgp_setup(hw);
1865 if(ret_val)
1866 return ret_val;
1867 } else if (hw->phy_type == e1000_phy_gg82563) {
1868 ret_val = e1000_copper_link_ggp_setup(hw);
1869 if(ret_val)
1870 return ret_val;
1871 }
1872
1873 if(hw->autoneg) {
1874 /* Setup autoneg and flow control advertisement
1875 * and perform autonegotiation */
1876 ret_val = e1000_copper_link_autoneg(hw);
1877 if(ret_val)
1878 return ret_val;
1879 } else {
1880 /* PHY will be set to 10H, 10F, 100H,or 100F
1881 * depending on value from forced_speed_duplex. */
1882 DEBUGOUT("Forcing speed and duplex\n");
1883 ret_val = e1000_phy_force_speed_duplex(hw);
1884 if(ret_val) {
1885 DEBUGOUT("Error Forcing Speed and Duplex\n");
1886 return ret_val;
1887 }
1888 }
1889
1890 /* Check link status. Wait up to 100 microseconds for link to become
1891 * valid.
1892 */
1893 for(i = 0; i < 10; i++) {
1894 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1895 if(ret_val)
1896 return ret_val;
1897 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1898 if(ret_val)
1899 return ret_val;
1900
1901 if(phy_data & MII_SR_LINK_STATUS) {
1902 /* Config the MAC and PHY after link is up */
1903 ret_val = e1000_copper_link_postconfig(hw);
1904 if(ret_val)
1905 return ret_val;
1906
1907 DEBUGOUT("Valid link established!!!\n");
1908 return E1000_SUCCESS;
1909 }
1910 udelay(10);
1911 }
1912
1913 DEBUGOUT("Unable to establish link!!!\n");
1914 return E1000_SUCCESS;
1915 }
1916
1917 /******************************************************************************
1918 * Configure the MAC-to-PHY interface for 10/100Mbps
1919 *
1920 * hw - Struct containing variables accessed by shared code
1921 ******************************************************************************/
1922 static int32_t
1923 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
1924 {
1925 int32_t ret_val = E1000_SUCCESS;
1926 uint32_t tipg;
1927 uint16_t reg_data;
1928
1929 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1930
1931 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
1932 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
1933 reg_data);
1934 if (ret_val)
1935 return ret_val;
1936
1937 /* Configure Transmit Inter-Packet Gap */
1938 tipg = E1000_READ_REG(hw, TIPG);
1939 tipg &= ~E1000_TIPG_IPGT_MASK;
1940 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
1941 E1000_WRITE_REG(hw, TIPG, tipg);
1942
1943 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1944
1945 if (ret_val)
1946 return ret_val;
1947
1948 if (duplex == HALF_DUPLEX)
1949 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1950 else
1951 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1952
1953 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1954
1955 return ret_val;
1956 }
1957
1958 static int32_t
1959 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
1960 {
1961 int32_t ret_val = E1000_SUCCESS;
1962 uint16_t reg_data;
1963 uint32_t tipg;
1964
1965 DEBUGFUNC("e1000_configure_kmrn_for_1000");
1966
1967 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
1968 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
1969 reg_data);
1970 if (ret_val)
1971 return ret_val;
1972
1973 /* Configure Transmit Inter-Packet Gap */
1974 tipg = E1000_READ_REG(hw, TIPG);
1975 tipg &= ~E1000_TIPG_IPGT_MASK;
1976 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1977 E1000_WRITE_REG(hw, TIPG, tipg);
1978
1979 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1980
1981 if (ret_val)
1982 return ret_val;
1983
1984 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1985 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1986
1987 return ret_val;
1988 }
1989
1990 /******************************************************************************
1991 * Configures PHY autoneg and flow control advertisement settings
1992 *
1993 * hw - Struct containing variables accessed by shared code
1994 ******************************************************************************/
1995 int32_t
1996 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1997 {
1998 int32_t ret_val;
1999 uint16_t mii_autoneg_adv_reg;
2000 uint16_t mii_1000t_ctrl_reg;
2001
2002 DEBUGFUNC("e1000_phy_setup_autoneg");
2003
2004 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2005 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
2006 if(ret_val)
2007 return ret_val;
2008
2009 if (hw->phy_type != e1000_phy_ife) {
2010 /* Read the MII 1000Base-T Control Register (Address 9). */
2011 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2012 if (ret_val)
2013 return ret_val;
2014 } else
2015 mii_1000t_ctrl_reg=0;
2016
2017 /* Need to parse both autoneg_advertised and fc and set up
2018 * the appropriate PHY registers. First we will parse for
2019 * autoneg_advertised software override. Since we can advertise
2020 * a plethora of combinations, we need to check each bit
2021 * individually.
2022 */
2023
2024 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2025 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2026 * the 1000Base-T Control Register (Address 9).
2027 */
2028 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
2029 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
2030
2031 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2032
2033 /* Do we want to advertise 10 Mb Half Duplex? */
2034 if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
2035 DEBUGOUT("Advertise 10mb Half duplex\n");
2036 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
2037 }
2038
2039 /* Do we want to advertise 10 Mb Full Duplex? */
2040 if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
2041 DEBUGOUT("Advertise 10mb Full duplex\n");
2042 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
2043 }
2044
2045 /* Do we want to advertise 100 Mb Half Duplex? */
2046 if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
2047 DEBUGOUT("Advertise 100mb Half duplex\n");
2048 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2049 }
2050
2051 /* Do we want to advertise 100 Mb Full Duplex? */
2052 if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
2053 DEBUGOUT("Advertise 100mb Full duplex\n");
2054 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
2055 }
2056
2057 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
2058 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
2059 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2060 }
2061
2062 /* Do we want to advertise 1000 Mb Full Duplex? */
2063 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
2064 DEBUGOUT("Advertise 1000mb Full duplex\n");
2065 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2066 if (hw->phy_type == e1000_phy_ife) {
2067 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2068 }
2069 }
2070
2071 /* Check for a software override of the flow control settings, and
2072 * setup the PHY advertisement registers accordingly. If
2073 * auto-negotiation is enabled, then software will have to set the
2074 * "PAUSE" bits to the correct value in the Auto-Negotiation
2075 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
2076 *
2077 * The possible values of the "fc" parameter are:
2078 * 0: Flow control is completely disabled
2079 * 1: Rx flow control is enabled (we can receive pause frames
2080 * but not send pause frames).
2081 * 2: Tx flow control is enabled (we can send pause frames
2082 * but we do not support receiving pause frames).
2083 * 3: Both Rx and TX flow control (symmetric) are enabled.
2084 * other: No software override. The flow control configuration
2085 * in the EEPROM is used.
2086 */
2087 switch (hw->fc) {
2088 case e1000_fc_none: /* 0 */
2089 /* Flow control (RX & TX) is completely disabled by a
2090 * software over-ride.
2091 */
2092 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2093 break;
2094 case e1000_fc_rx_pause: /* 1 */
2095 /* RX Flow control is enabled, and TX Flow control is
2096 * disabled, by a software over-ride.
2097 */
2098 /* Since there really isn't a way to advertise that we are
2099 * capable of RX Pause ONLY, we will advertise that we
2100 * support both symmetric and asymmetric RX PAUSE. Later
2101 * (in e1000_config_fc_after_link_up) we will disable the
2102 *hw's ability to send PAUSE frames.
2103 */
2104 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2105 break;
2106 case e1000_fc_tx_pause: /* 2 */
2107 /* TX Flow control is enabled, and RX Flow control is
2108 * disabled, by a software over-ride.
2109 */
2110 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2111 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2112 break;
2113 case e1000_fc_full: /* 3 */
2114 /* Flow control (both RX and TX) is enabled by a software
2115 * over-ride.
2116 */
2117 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2118 break;
2119 default:
2120 DEBUGOUT("Flow control param set incorrectly\n");
2121 return -E1000_ERR_CONFIG;
2122 }
2123
2124 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
2125 if(ret_val)
2126 return ret_val;
2127
2128 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2129
2130 if (hw->phy_type != e1000_phy_ife) {
2131 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2132 if (ret_val)
2133 return ret_val;
2134 }
2135
2136 return E1000_SUCCESS;
2137 }
2138
2139 /******************************************************************************
2140 * Force PHY speed and duplex settings to hw->forced_speed_duplex
2141 *
2142 * hw - Struct containing variables accessed by shared code
2143 ******************************************************************************/
2144 static int32_t
2145 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2146 {
2147 uint32_t ctrl;
2148 int32_t ret_val;
2149 uint16_t mii_ctrl_reg;
2150 uint16_t mii_status_reg;
2151 uint16_t phy_data;
2152 uint16_t i;
2153
2154 DEBUGFUNC("e1000_phy_force_speed_duplex");
2155
2156 /* Turn off Flow control if we are forcing speed and duplex. */
2157 hw->fc = e1000_fc_none;
2158
2159 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2160
2161 /* Read the Device Control Register. */
2162 ctrl = E1000_READ_REG(hw, CTRL);
2163
2164 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2165 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2166 ctrl &= ~(DEVICE_SPEED_MASK);
2167
2168 /* Clear the Auto Speed Detect Enable bit. */
2169 ctrl &= ~E1000_CTRL_ASDE;
2170
2171 /* Read the MII Control Register. */
2172 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
2173 if(ret_val)
2174 return ret_val;
2175
2176 /* We need to disable autoneg in order to force link and duplex. */
2177
2178 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2179
2180 /* Are we forcing Full or Half Duplex? */
2181 if(hw->forced_speed_duplex == e1000_100_full ||
2182 hw->forced_speed_duplex == e1000_10_full) {
2183 /* We want to force full duplex so we SET the full duplex bits in the
2184 * Device and MII Control Registers.
2185 */
2186 ctrl |= E1000_CTRL_FD;
2187 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
2188 DEBUGOUT("Full Duplex\n");
2189 } else {
2190 /* We want to force half duplex so we CLEAR the full duplex bits in
2191 * the Device and MII Control Registers.
2192 */
2193 ctrl &= ~E1000_CTRL_FD;
2194 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
2195 DEBUGOUT("Half Duplex\n");
2196 }
2197
2198 /* Are we forcing 100Mbps??? */
2199 if(hw->forced_speed_duplex == e1000_100_full ||
2200 hw->forced_speed_duplex == e1000_100_half) {
2201 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2202 ctrl |= E1000_CTRL_SPD_100;
2203 mii_ctrl_reg |= MII_CR_SPEED_100;
2204 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2205 DEBUGOUT("Forcing 100mb ");
2206 } else {
2207 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
2208 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2209 mii_ctrl_reg |= MII_CR_SPEED_10;
2210 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2211 DEBUGOUT("Forcing 10mb ");
2212 }
2213
2214 e1000_config_collision_dist(hw);
2215
2216 /* Write the configured values back to the Device Control Reg. */
2217 E1000_WRITE_REG(hw, CTRL, ctrl);
2218
2219 if ((hw->phy_type == e1000_phy_m88) ||
2220 (hw->phy_type == e1000_phy_gg82563)) {
2221 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2222 if(ret_val)
2223 return ret_val;
2224
2225 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
2226 * forced whenever speed are duplex are forced.
2227 */
2228 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2229 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2230 if(ret_val)
2231 return ret_val;
2232
2233 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
2234
2235 /* Need to reset the PHY or these changes will be ignored */
2236 mii_ctrl_reg |= MII_CR_RESET;
2237 /* Disable MDI-X support for 10/100 */
2238 } else if (hw->phy_type == e1000_phy_ife) {
2239 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2240 if (ret_val)
2241 return ret_val;
2242
2243 phy_data &= ~IFE_PMC_AUTO_MDIX;
2244 phy_data &= ~IFE_PMC_FORCE_MDIX;
2245
2246 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2247 if (ret_val)
2248 return ret_val;
2249 } else {
2250 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2251 * forced whenever speed or duplex are forced.
2252 */
2253 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2254 if(ret_val)
2255 return ret_val;
2256
2257 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2258 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2259
2260 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2261 if(ret_val)
2262 return ret_val;
2263 }
2264
2265 /* Write back the modified PHY MII control register. */
2266 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
2267 if(ret_val)
2268 return ret_val;
2269
2270 udelay(1);
2271
2272 /* The wait_autoneg_complete flag may be a little misleading here.
2273 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
2274 * But we do want to delay for a period while forcing only so we
2275 * don't generate false No Link messages. So we will wait here
2276 * only if the user has set wait_autoneg_complete to 1, which is
2277 * the default.
2278 */
2279 if(hw->wait_autoneg_complete) {
2280 /* We will wait for autoneg to complete. */
2281 DEBUGOUT("Waiting for forced speed/duplex link.\n");
2282 mii_status_reg = 0;
2283
2284 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2285 for(i = PHY_FORCE_TIME; i > 0; i--) {
2286 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2287 * to be set.
2288 */
2289 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2290 if(ret_val)
2291 return ret_val;
2292
2293 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2294 if(ret_val)
2295 return ret_val;
2296
2297 if(mii_status_reg & MII_SR_LINK_STATUS) break;
2298 msec_delay(100);
2299 }
2300 if((i == 0) &&
2301 ((hw->phy_type == e1000_phy_m88) ||
2302 (hw->phy_type == e1000_phy_gg82563))) {
2303 /* We didn't get link. Reset the DSP and wait again for link. */
2304 ret_val = e1000_phy_reset_dsp(hw);
2305 if(ret_val) {
2306 DEBUGOUT("Error Resetting PHY DSP\n");
2307 return ret_val;
2308 }
2309 }
2310 /* This loop will early-out if the link condition has been met. */
2311 for(i = PHY_FORCE_TIME; i > 0; i--) {
2312 if(mii_status_reg & MII_SR_LINK_STATUS) break;
2313 msec_delay(100);
2314 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2315 * to be set.
2316 */
2317 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2318 if(ret_val)
2319 return ret_val;
2320
2321 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2322 if(ret_val)
2323 return ret_val;
2324 }
2325 }
2326
2327 if (hw->phy_type == e1000_phy_m88) {
2328 /* Because we reset the PHY above, we need to re-force TX_CLK in the
2329 * Extended PHY Specific Control Register to 25MHz clock. This value
2330 * defaults back to a 2.5MHz clock when the PHY is reset.
2331 */
2332 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2333 if(ret_val)
2334 return ret_val;
2335
2336 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2337 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2338 if(ret_val)
2339 return ret_val;
2340
2341 /* In addition, because of the s/w reset above, we need to enable CRS on
2342 * TX. This must be set for both full and half duplex operation.
2343 */
2344 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2345 if(ret_val)
2346 return ret_val;
2347
2348 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2349 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2350 if(ret_val)
2351 return ret_val;
2352
2353 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2354 (!hw->autoneg) &&
2355 (hw->forced_speed_duplex == e1000_10_full ||
2356 hw->forced_speed_duplex == e1000_10_half)) {
2357 ret_val = e1000_polarity_reversal_workaround(hw);
2358 if(ret_val)
2359 return ret_val;
2360 }
2361 } else if (hw->phy_type == e1000_phy_gg82563) {
2362 /* The TX_CLK of the Extended PHY Specific Control Register defaults
2363 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
2364 * we're not in a forced 10/duplex configuration. */
2365 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2366 if (ret_val)
2367 return ret_val;
2368
2369 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2370 if ((hw->forced_speed_duplex == e1000_10_full) ||
2371 (hw->forced_speed_duplex == e1000_10_half))
2372 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2373 else
2374 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2375
2376 /* Also due to the reset, we need to enable CRS on Tx. */
2377 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2378
2379 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2380 if (ret_val)
2381 return ret_val;
2382 }
2383 return E1000_SUCCESS;
2384 }
2385
2386 /******************************************************************************
2387 * Sets the collision distance in the Transmit Control register
2388 *
2389 * hw - Struct containing variables accessed by shared code
2390 *
2391 * Link should have been established previously. Reads the speed and duplex
2392 * information from the Device Status register.
2393 ******************************************************************************/
2394 void
2395 e1000_config_collision_dist(struct e1000_hw *hw)
2396 {
2397 uint32_t tctl, coll_dist;
2398
2399 DEBUGFUNC("e1000_config_collision_dist");
2400
2401 if (hw->mac_type < e1000_82543)
2402 coll_dist = E1000_COLLISION_DISTANCE_82542;
2403 else
2404 coll_dist = E1000_COLLISION_DISTANCE;
2405
2406 tctl = E1000_READ_REG(hw, TCTL);
2407
2408 tctl &= ~E1000_TCTL_COLD;
2409 tctl |= coll_dist << E1000_COLD_SHIFT;
2410
2411 E1000_WRITE_REG(hw, TCTL, tctl);
2412 E1000_WRITE_FLUSH(hw);
2413 }
2414
2415 /******************************************************************************
2416 * Sets MAC speed and duplex settings to reflect the those in the PHY
2417 *
2418 * hw - Struct containing variables accessed by shared code
2419 * mii_reg - data to write to the MII control register
2420 *
2421 * The contents of the PHY register containing the needed information need to
2422 * be passed in.
2423 ******************************************************************************/
2424 static int32_t
2425 e1000_config_mac_to_phy(struct e1000_hw *hw)
2426 {
2427 uint32_t ctrl;
2428 int32_t ret_val;
2429 uint16_t phy_data;
2430
2431 DEBUGFUNC("e1000_config_mac_to_phy");
2432
2433 /* 82544 or newer MAC, Auto Speed Detection takes care of
2434 * MAC speed/duplex configuration.*/
2435 if (hw->mac_type >= e1000_82544)
2436 return E1000_SUCCESS;
2437
2438 /* Read the Device Control Register and set the bits to Force Speed
2439 * and Duplex.
2440 */
2441 ctrl = E1000_READ_REG(hw, CTRL);
2442 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2443 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2444
2445 /* Set up duplex in the Device Control and Transmit Control
2446 * registers depending on negotiated values.
2447 */
2448 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2449 if(ret_val)
2450 return ret_val;
2451
2452 if(phy_data & M88E1000_PSSR_DPLX)
2453 ctrl |= E1000_CTRL_FD;
2454 else
2455 ctrl &= ~E1000_CTRL_FD;
2456
2457 e1000_config_collision_dist(hw);
2458
2459 /* Set up speed in the Device Control register depending on
2460 * negotiated values.
2461 */
2462 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2463 ctrl |= E1000_CTRL_SPD_1000;
2464 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2465 ctrl |= E1000_CTRL_SPD_100;
2466
2467 /* Write the configured values back to the Device Control Reg. */
2468 E1000_WRITE_REG(hw, CTRL, ctrl);
2469 return E1000_SUCCESS;
2470 }
2471
2472 /******************************************************************************
2473 * Forces the MAC's flow control settings.
2474 *
2475 * hw - Struct containing variables accessed by shared code
2476 *
2477 * Sets the TFCE and RFCE bits in the device control register to reflect
2478 * the adapter settings. TFCE and RFCE need to be explicitly set by
2479 * software when a Copper PHY is used because autonegotiation is managed
2480 * by the PHY rather than the MAC. Software must also configure these
2481 * bits when link is forced on a fiber connection.
2482 *****************************************************************************/
2483 int32_t
2484 e1000_force_mac_fc(struct e1000_hw *hw)
2485 {
2486 uint32_t ctrl;
2487
2488 DEBUGFUNC("e1000_force_mac_fc");
2489
2490 /* Get the current configuration of the Device Control Register */
2491 ctrl = E1000_READ_REG(hw, CTRL);
2492
2493 /* Because we didn't get link via the internal auto-negotiation
2494 * mechanism (we either forced link or we got link via PHY
2495 * auto-neg), we have to manually enable/disable transmit an
2496 * receive flow control.
2497 *
2498 * The "Case" statement below enables/disable flow control
2499 * according to the "hw->fc" parameter.
2500 *
2501 * The possible values of the "fc" parameter are:
2502 * 0: Flow control is completely disabled
2503 * 1: Rx flow control is enabled (we can receive pause
2504 * frames but not send pause frames).
2505 * 2: Tx flow control is enabled (we can send pause frames
2506 * frames but we do not receive pause frames).
2507 * 3: Both Rx and TX flow control (symmetric) is enabled.
2508 * other: No other values should be possible at this point.
2509 */
2510
2511 switch (hw->fc) {
2512 case e1000_fc_none:
2513 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2514 break;
2515 case e1000_fc_rx_pause:
2516 ctrl &= (~E1000_CTRL_TFCE);
2517 ctrl |= E1000_CTRL_RFCE;
2518 break;
2519 case e1000_fc_tx_pause:
2520 ctrl &= (~E1000_CTRL_RFCE);
2521 ctrl |= E1000_CTRL_TFCE;
2522 break;
2523 case e1000_fc_full:
2524 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2525 break;
2526 default:
2527 DEBUGOUT("Flow control param set incorrectly\n");
2528 return -E1000_ERR_CONFIG;
2529 }
2530
2531 /* Disable TX Flow Control for 82542 (rev 2.0) */
2532 if(hw->mac_type == e1000_82542_rev2_0)
2533 ctrl &= (~E1000_CTRL_TFCE);
2534
2535 E1000_WRITE_REG(hw, CTRL, ctrl);
2536 return E1000_SUCCESS;
2537 }
2538
2539 /******************************************************************************
2540 * Configures flow control settings after link is established
2541 *
2542 * hw - Struct containing variables accessed by shared code
2543 *
2544 * Should be called immediately after a valid link has been established.
2545 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2546 * and autonegotiation is enabled, the MAC flow control settings will be set
2547 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2548 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2549 *****************************************************************************/
2550 static int32_t
2551 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2552 {
2553 int32_t ret_val;
2554 uint16_t mii_status_reg;
2555 uint16_t mii_nway_adv_reg;
2556 uint16_t mii_nway_lp_ability_reg;
2557 uint16_t speed;
2558 uint16_t duplex;
2559
2560 DEBUGFUNC("e1000_config_fc_after_link_up");
2561
2562 /* Check for the case where we have fiber media and auto-neg failed
2563 * so we had to force link. In this case, we need to force the
2564 * configuration of the MAC to match the "fc" parameter.
2565 */
2566 if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2567 ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) ||
2568 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
2569 ret_val = e1000_force_mac_fc(hw);
2570 if(ret_val) {
2571 DEBUGOUT("Error forcing flow control settings\n");
2572 return ret_val;
2573 }
2574 }
2575
2576 /* Check for the case where we have copper media and auto-neg is
2577 * enabled. In this case, we need to check and see if Auto-Neg
2578 * has completed, and if so, how the PHY and link partner has
2579 * flow control configured.
2580 */
2581 if((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2582 /* Read the MII Status Register and check to see if AutoNeg
2583 * has completed. We read this twice because this reg has
2584 * some "sticky" (latched) bits.
2585 */
2586 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2587 if(ret_val)
2588 return ret_val;
2589 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2590 if(ret_val)
2591 return ret_val;
2592
2593 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2594 /* The AutoNeg process has completed, so we now need to
2595 * read both the Auto Negotiation Advertisement Register
2596 * (Address 4) and the Auto_Negotiation Base Page Ability
2597 * Register (Address 5) to determine how flow control was
2598 * negotiated.
2599 */
2600 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2601 &mii_nway_adv_reg);
2602 if(ret_val)
2603 return ret_val;
2604 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2605 &mii_nway_lp_ability_reg);
2606 if(ret_val)
2607 return ret_val;
2608
2609 /* Two bits in the Auto Negotiation Advertisement Register
2610 * (Address 4) and two bits in the Auto Negotiation Base
2611 * Page Ability Register (Address 5) determine flow control
2612 * for both the PHY and the link partner. The following
2613 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2614 * 1999, describes these PAUSE resolution bits and how flow
2615 * control is determined based upon these settings.
2616 * NOTE: DC = Don't Care
2617 *
2618 * LOCAL DEVICE | LINK PARTNER
2619 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2620 *-------|---------|-------|---------|--------------------
2621 * 0 | 0 | DC | DC | e1000_fc_none
2622 * 0 | 1 | 0 | DC | e1000_fc_none
2623 * 0 | 1 | 1 | 0 | e1000_fc_none
2624 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2625 * 1 | 0 | 0 | DC | e1000_fc_none
2626 * 1 | DC | 1 | DC | e1000_fc_full
2627 * 1 | 1 | 0 | 0 | e1000_fc_none
2628 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2629 *
2630 */
2631 /* Are both PAUSE bits set to 1? If so, this implies
2632 * Symmetric Flow Control is enabled at both ends. The
2633 * ASM_DIR bits are irrelevant per the spec.
2634 *
2635 * For Symmetric Flow Control:
2636 *
2637 * LOCAL DEVICE | LINK PARTNER
2638 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2639 *-------|---------|-------|---------|--------------------
2640 * 1 | DC | 1 | DC | e1000_fc_full
2641 *
2642 */
2643 if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2644 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2645 /* Now we need to check if the user selected RX ONLY
2646 * of pause frames. In this case, we had to advertise
2647 * FULL flow control because we could not advertise RX
2648 * ONLY. Hence, we must now check to see if we need to
2649 * turn OFF the TRANSMISSION of PAUSE frames.
2650 */
2651 if(hw->original_fc == e1000_fc_full) {
2652 hw->fc = e1000_fc_full;
2653 DEBUGOUT("Flow Control = FULL.\n");
2654 } else {
2655 hw->fc = e1000_fc_rx_pause;
2656 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2657 }
2658 }
2659 /* For receiving PAUSE frames ONLY.
2660 *
2661 * LOCAL DEVICE | LINK PARTNER
2662 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2663 *-------|---------|-------|---------|--------------------
2664 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2665 *
2666 */
2667 else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2668 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2669 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2670 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2671 hw->fc = e1000_fc_tx_pause;
2672 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2673 }
2674 /* For transmitting PAUSE frames ONLY.
2675 *
2676 * LOCAL DEVICE | LINK PARTNER
2677 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2678 *-------|---------|-------|---------|--------------------
2679 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2680 *
2681 */
2682 else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2683 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2684 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2685 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2686 hw->fc = e1000_fc_rx_pause;
2687 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2688 }
2689 /* Per the IEEE spec, at this point flow control should be
2690 * disabled. However, we want to consider that we could
2691 * be connected to a legacy switch that doesn't advertise
2692 * desired flow control, but can be forced on the link
2693 * partner. So if we advertised no flow control, that is
2694 * what we will resolve to. If we advertised some kind of
2695 * receive capability (Rx Pause Only or Full Flow Control)
2696 * and the link partner advertised none, we will configure
2697 * ourselves to enable Rx Flow Control only. We can do
2698 * this safely for two reasons: If the link partner really
2699 * didn't want flow control enabled, and we enable Rx, no
2700 * harm done since we won't be receiving any PAUSE frames
2701 * anyway. If the intent on the link partner was to have
2702 * flow control enabled, then by us enabling RX only, we
2703 * can at least receive pause frames and process them.
2704 * This is a good idea because in most cases, since we are
2705 * predominantly a server NIC, more times than not we will
2706 * be asked to delay transmission of packets than asking
2707 * our link partner to pause transmission of frames.
2708 */
2709 else if((hw->original_fc == e1000_fc_none ||
2710 hw->original_fc == e1000_fc_tx_pause) ||
2711 hw->fc_strict_ieee) {
2712 hw->fc = e1000_fc_none;
2713 DEBUGOUT("Flow Control = NONE.\n");
2714 } else {
2715 hw->fc = e1000_fc_rx_pause;
2716 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2717 }
2718
2719 /* Now we need to do one last check... If we auto-
2720 * negotiated to HALF DUPLEX, flow control should not be
2721 * enabled per IEEE 802.3 spec.
2722 */
2723 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2724 if(ret_val) {
2725 DEBUGOUT("Error getting link speed and duplex\n");
2726 return ret_val;
2727 }
2728
2729 if(duplex == HALF_DUPLEX)
2730 hw->fc = e1000_fc_none;
2731
2732 /* Now we call a subroutine to actually force the MAC
2733 * controller to use the correct flow control settings.
2734 */
2735 ret_val = e1000_force_mac_fc(hw);
2736 if(ret_val) {
2737 DEBUGOUT("Error forcing flow control settings\n");
2738 return ret_val;
2739 }
2740 } else {
2741 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
2742 }
2743 }
2744 return E1000_SUCCESS;
2745 }
2746
2747 /******************************************************************************
2748 * Checks to see if the link status of the hardware has changed.
2749 *
2750 * hw - Struct containing variables accessed by shared code
2751 *
2752 * Called by any function that needs to check the link status of the adapter.
2753 *****************************************************************************/
2754 int32_t
2755 e1000_check_for_link(struct e1000_hw *hw)
2756 {
2757 uint32_t rxcw = 0;
2758 uint32_t ctrl;
2759 uint32_t status;
2760 uint32_t rctl;
2761 uint32_t icr;
2762 uint32_t signal = 0;
2763 int32_t ret_val;
2764 uint16_t phy_data;
2765
2766 DEBUGFUNC("e1000_check_for_link");
2767
2768 ctrl = E1000_READ_REG(hw, CTRL);
2769 status = E1000_READ_REG(hw, STATUS);
2770
2771 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2772 * set when the optics detect a signal. On older adapters, it will be
2773 * cleared when there is a signal. This applies to fiber media only.
2774 */
2775 if((hw->media_type == e1000_media_type_fiber) ||
2776 (hw->media_type == e1000_media_type_internal_serdes)) {
2777 rxcw = E1000_READ_REG(hw, RXCW);
2778
2779 if(hw->media_type == e1000_media_type_fiber) {
2780 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2781 if(status & E1000_STATUS_LU)
2782 hw->get_link_status = FALSE;
2783 }
2784 }
2785
2786 /* If we have a copper PHY then we only want to go out to the PHY
2787 * registers to see if Auto-Neg has completed and/or if our link
2788 * status has changed. The get_link_status flag will be set if we
2789 * receive a Link Status Change interrupt or we have Rx Sequence
2790 * Errors.
2791 */
2792 if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2793 /* First we want to see if the MII Status Register reports
2794 * link. If so, then we want to get the current speed/duplex
2795 * of the PHY.
2796 * Read the register twice since the link bit is sticky.
2797 */
2798 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2799 if(ret_val)
2800 return ret_val;
2801 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2802 if(ret_val)
2803 return ret_val;
2804
2805 if(phy_data & MII_SR_LINK_STATUS) {
2806 hw->get_link_status = FALSE;
2807 /* Check if there was DownShift, must be checked immediately after
2808 * link-up */
2809 e1000_check_downshift(hw);
2810
2811 /* If we are on 82544 or 82543 silicon and speed/duplex
2812 * are forced to 10H or 10F, then we will implement the polarity
2813 * reversal workaround. We disable interrupts first, and upon
2814 * returning, place the devices interrupt state to its previous
2815 * value except for the link status change interrupt which will
2816 * happen due to the execution of this workaround.
2817 */
2818
2819 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2820 (!hw->autoneg) &&
2821 (hw->forced_speed_duplex == e1000_10_full ||
2822 hw->forced_speed_duplex == e1000_10_half)) {
2823 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2824 ret_val = e1000_polarity_reversal_workaround(hw);
2825 icr = E1000_READ_REG(hw, ICR);
2826 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
2827 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
2828 }
2829
2830 } else {
2831 /* No link detected */
2832 e1000_config_dsp_after_link_change(hw, FALSE);
2833 return 0;
2834 }
2835
2836 /* If we are forcing speed/duplex, then we simply return since
2837 * we have already determined whether we have link or not.
2838 */
2839 if(!hw->autoneg) return -E1000_ERR_CONFIG;
2840
2841 /* optimize the dsp settings for the igp phy */
2842 e1000_config_dsp_after_link_change(hw, TRUE);
2843
2844 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2845 * have Si on board that is 82544 or newer, Auto
2846 * Speed Detection takes care of MAC speed/duplex
2847 * configuration. So we only need to configure Collision
2848 * Distance in the MAC. Otherwise, we need to force
2849 * speed/duplex on the MAC to the current PHY speed/duplex
2850 * settings.
2851 */
2852 if(hw->mac_type >= e1000_82544)
2853 e1000_config_collision_dist(hw);
2854 else {
2855 ret_val = e1000_config_mac_to_phy(hw);
2856 if(ret_val) {
2857 DEBUGOUT("Error configuring MAC to PHY settings\n");
2858 return ret_val;
2859 }
2860 }
2861
2862 /* Configure Flow Control now that Auto-Neg has completed. First, we
2863 * need to restore the desired flow control settings because we may
2864 * have had to re-autoneg with a different link partner.
2865 */
2866 ret_val = e1000_config_fc_after_link_up(hw);
2867 if(ret_val) {
2868 DEBUGOUT("Error configuring flow control\n");
2869 return ret_val;
2870 }
2871
2872 /* At this point we know that we are on copper and we have
2873 * auto-negotiated link. These are conditions for checking the link
2874 * partner capability register. We use the link speed to determine if
2875 * TBI compatibility needs to be turned on or off. If the link is not
2876 * at gigabit speed, then TBI compatibility is not needed. If we are
2877 * at gigabit speed, we turn on TBI compatibility.
2878 */
2879 if(hw->tbi_compatibility_en) {
2880 uint16_t speed, duplex;
2881 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2882 if (ret_val) {
2883 DEBUGOUT("Error getting link speed and duplex\n");
2884 return ret_val;
2885 }
2886 if (speed != SPEED_1000) {
2887 /* If link speed is not set to gigabit speed, we do not need
2888 * to enable TBI compatibility.
2889 */
2890 if(hw->tbi_compatibility_on) {
2891 /* If we previously were in the mode, turn it off. */
2892 rctl = E1000_READ_REG(hw, RCTL);
2893 rctl &= ~E1000_RCTL_SBP;
2894 E1000_WRITE_REG(hw, RCTL, rctl);
2895 hw->tbi_compatibility_on = FALSE;
2896 }
2897 } else {
2898 /* If TBI compatibility is was previously off, turn it on. For
2899 * compatibility with a TBI link partner, we will store bad
2900 * packets. Some frames have an additional byte on the end and
2901 * will look like CRC errors to to the hardware.
2902 */
2903 if(!hw->tbi_compatibility_on) {
2904 hw->tbi_compatibility_on = TRUE;
2905 rctl = E1000_READ_REG(hw, RCTL);
2906 rctl |= E1000_RCTL_SBP;
2907 E1000_WRITE_REG(hw, RCTL, rctl);
2908 }
2909 }
2910 }
2911 }
2912 /* If we don't have link (auto-negotiation failed or link partner cannot
2913 * auto-negotiate), the cable is plugged in (we have signal), and our
2914 * link partner is not trying to auto-negotiate with us (we are receiving
2915 * idles or data), we need to force link up. We also need to give
2916 * auto-negotiation time to complete, in case the cable was just plugged
2917 * in. The autoneg_failed flag does this.
2918 */
2919 else if((((hw->media_type == e1000_media_type_fiber) &&
2920 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2921 (hw->media_type == e1000_media_type_internal_serdes)) &&
2922 (!(status & E1000_STATUS_LU)) &&
2923 (!(rxcw & E1000_RXCW_C))) {
2924 if(hw->autoneg_failed == 0) {
2925 hw->autoneg_failed = 1;
2926 return 0;
2927 }
2928 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
2929
2930 /* Disable auto-negotiation in the TXCW register */
2931 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2932
2933 /* Force link-up and also force full-duplex. */
2934 ctrl = E1000_READ_REG(hw, CTRL);
2935 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2936 E1000_WRITE_REG(hw, CTRL, ctrl);
2937
2938 /* Configure Flow Control after forcing link up. */
2939 ret_val = e1000_config_fc_after_link_up(hw);
2940 if(ret_val) {
2941 DEBUGOUT("Error configuring flow control\n");
2942 return ret_val;
2943 }
2944 }
2945 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2946 * auto-negotiation in the TXCW register and disable forced link in the
2947 * Device Control register in an attempt to auto-negotiate with our link
2948 * partner.
2949 */
2950 else if(((hw->media_type == e1000_media_type_fiber) ||
2951 (hw->media_type == e1000_media_type_internal_serdes)) &&
2952 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2953 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
2954 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2955 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2956
2957 hw->serdes_link_down = FALSE;
2958 }
2959 /* If we force link for non-auto-negotiation switch, check link status
2960 * based on MAC synchronization for internal serdes media type.
2961 */
2962 else if((hw->media_type == e1000_media_type_internal_serdes) &&
2963 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2964 /* SYNCH bit and IV bit are sticky. */
2965 udelay(10);
2966 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2967 if(!(rxcw & E1000_RXCW_IV)) {
2968 hw->serdes_link_down = FALSE;
2969 DEBUGOUT("SERDES: Link is up.\n");
2970 }
2971 } else {
2972 hw->serdes_link_down = TRUE;
2973 DEBUGOUT("SERDES: Link is down.\n");
2974 }
2975 }
2976 if((hw->media_type == e1000_media_type_internal_serdes) &&
2977 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2978 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
2979 }
2980 return E1000_SUCCESS;
2981 }
2982
2983 /******************************************************************************
2984 * Detects the current speed and duplex settings of the hardware.
2985 *
2986 * hw - Struct containing variables accessed by shared code
2987 * speed - Speed of the connection
2988 * duplex - Duplex setting of the connection
2989 *****************************************************************************/
2990 int32_t
2991 e1000_get_speed_and_duplex(struct e1000_hw *hw,
2992 uint16_t *speed,
2993 uint16_t *duplex)
2994 {
2995 uint32_t status;
2996 int32_t ret_val;
2997 uint16_t phy_data;
2998
2999 DEBUGFUNC("e1000_get_speed_and_duplex");
3000
3001 if(hw->mac_type >= e1000_82543) {
3002 status = E1000_READ_REG(hw, STATUS);
3003 if(status & E1000_STATUS_SPEED_1000) {
3004 *speed = SPEED_1000;
3005 DEBUGOUT("1000 Mbs, ");
3006 } else if(status & E1000_STATUS_SPEED_100) {
3007 *speed = SPEED_100;
3008 DEBUGOUT("100 Mbs, ");
3009 } else {
3010 *speed = SPEED_10;
3011 DEBUGOUT("10 Mbs, ");
3012 }
3013
3014 if(status & E1000_STATUS_FD) {
3015 *duplex = FULL_DUPLEX;
3016 DEBUGOUT("Full Duplex\n");
3017 } else {
3018 *duplex = HALF_DUPLEX;
3019 DEBUGOUT(" Half Duplex\n");
3020 }
3021 } else {
3022 DEBUGOUT("1000 Mbs, Full Duplex\n");
3023 *speed = SPEED_1000;
3024 *duplex = FULL_DUPLEX;
3025 }
3026
3027 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
3028 * if it is operating at half duplex. Here we set the duplex settings to
3029 * match the duplex in the link partner's capabilities.
3030 */
3031 if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3032 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3033 if(ret_val)
3034 return ret_val;
3035
3036 if(!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3037 *duplex = HALF_DUPLEX;
3038 else {
3039 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
3040 if(ret_val)
3041 return ret_val;
3042 if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
3043 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3044 *duplex = HALF_DUPLEX;
3045 }
3046 }
3047
3048 if ((hw->mac_type == e1000_80003es2lan) &&
3049 (hw->media_type == e1000_media_type_copper)) {
3050 if (*speed == SPEED_1000)
3051 ret_val = e1000_configure_kmrn_for_1000(hw);
3052 else
3053 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3054 if (ret_val)
3055 return ret_val;
3056 }
3057
3058 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3059 ret_val = e1000_kumeran_lock_loss_workaround(hw);
3060 if (ret_val)
3061 return ret_val;
3062 }
3063
3064 return E1000_SUCCESS;
3065 }
3066
3067 /******************************************************************************
3068 * Blocks until autoneg completes or times out (~4.5 seconds)
3069 *
3070 * hw - Struct containing variables accessed by shared code
3071 ******************************************************************************/
3072 static int32_t
3073 e1000_wait_autoneg(struct e1000_hw *hw)
3074 {
3075 int32_t ret_val;
3076 uint16_t i;
3077 uint16_t phy_data;
3078
3079 DEBUGFUNC("e1000_wait_autoneg");
3080 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3081
3082 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3083 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3084 /* Read the MII Status Register and wait for Auto-Neg
3085 * Complete bit to be set.
3086 */
3087 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3088 if(ret_val)
3089 return ret_val;
3090 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3091 if(ret_val)
3092 return ret_val;
3093 if(phy_data & MII_SR_AUTONEG_COMPLETE) {
3094 return E1000_SUCCESS;
3095 }
3096 msec_delay(100);
3097 }
3098 return E1000_SUCCESS;
3099 }
3100
3101 /******************************************************************************
3102 * Raises the Management Data Clock
3103 *
3104 * hw - Struct containing variables accessed by shared code
3105 * ctrl - Device control register's current value
3106 ******************************************************************************/
3107 static void
3108 e1000_raise_mdi_clk(struct e1000_hw *hw,
3109 uint32_t *ctrl)
3110 {
3111 /* Raise the clock input to the Management Data Clock (by setting the MDC
3112 * bit), and then delay 10 microseconds.
3113 */
3114 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3115 E1000_WRITE_FLUSH(hw);
3116 udelay(10);
3117 }
3118
3119 /******************************************************************************
3120 * Lowers the Management Data Clock
3121 *
3122 * hw - Struct containing variables accessed by shared code
3123 * ctrl - Device control register's current value
3124 ******************************************************************************/
3125 static void
3126 e1000_lower_mdi_clk(struct e1000_hw *hw,
3127 uint32_t *ctrl)
3128 {
3129 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3130 * bit), and then delay 10 microseconds.
3131 */
3132 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3133 E1000_WRITE_FLUSH(hw);
3134 udelay(10);
3135 }
3136
3137 /******************************************************************************
3138 * Shifts data bits out to the PHY
3139 *
3140 * hw - Struct containing variables accessed by shared code
3141 * data - Data to send out to the PHY
3142 * count - Number of bits to shift out
3143 *
3144 * Bits are shifted out in MSB to LSB order.
3145 ******************************************************************************/
3146 static void
3147 e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3148 uint32_t data,
3149 uint16_t count)
3150 {
3151 uint32_t ctrl;
3152 uint32_t mask;
3153
3154 /* We need to shift "count" number of bits out to the PHY. So, the value
3155 * in the "data" parameter will be shifted out to the PHY one bit at a
3156 * time. In order to do this, "data" must be broken down into bits.
3157 */
3158 mask = 0x01;
3159 mask <<= (count - 1);
3160
3161 ctrl = E1000_READ_REG(hw, CTRL);
3162
3163 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3164 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3165
3166 while(mask) {
3167 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3168 * then raising and lowering the Management Data Clock. A "0" is
3169 * shifted out to the PHY by setting the MDIO bit to "0" and then
3170 * raising and lowering the clock.
3171 */
3172 if(data & mask) ctrl |= E1000_CTRL_MDIO;
3173 else ctrl &= ~E1000_CTRL_MDIO;
3174
3175 E1000_WRITE_REG(hw, CTRL, ctrl);
3176 E1000_WRITE_FLUSH(hw);
3177
3178 udelay(10);
3179
3180 e1000_raise_mdi_clk(hw, &ctrl);
3181 e1000_lower_mdi_clk(hw, &ctrl);
3182
3183 mask = mask >> 1;
3184 }
3185 }
3186
3187 /******************************************************************************
3188 * Shifts data bits in from the PHY
3189 *
3190 * hw - Struct containing variables accessed by shared code
3191 *
3192 * Bits are shifted in in MSB to LSB order.
3193 ******************************************************************************/
3194 static uint16_t
3195 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3196 {
3197 uint32_t ctrl;
3198 uint16_t data = 0;
3199 uint8_t i;
3200
3201 /* In order to read a register from the PHY, we need to shift in a total
3202 * of 18 bits from the PHY. The first two bit (turnaround) times are used
3203 * to avoid contention on the MDIO pin when a read operation is performed.
3204 * These two bits are ignored by us and thrown away. Bits are "shifted in"
3205 * by raising the input to the Management Data Clock (setting the MDC bit),
3206 * and then reading the value of the MDIO bit.
3207 */
3208 ctrl = E1000_READ_REG(hw, CTRL);
3209
3210 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3211 ctrl &= ~E1000_CTRL_MDIO_DIR;
3212 ctrl &= ~E1000_CTRL_MDIO;
3213
3214 E1000_WRITE_REG(hw, CTRL, ctrl);
3215 E1000_WRITE_FLUSH(hw);
3216
3217 /* Raise and Lower the clock before reading in the data. This accounts for
3218 * the turnaround bits. The first clock occurred when we clocked out the
3219 * last bit of the Register Address.
3220 */
3221 e1000_raise_mdi_clk(hw, &ctrl);
3222 e1000_lower_mdi_clk(hw, &ctrl);
3223
3224 for(data = 0, i = 0; i < 16; i++) {
3225 data = data << 1;
3226 e1000_raise_mdi_clk(hw, &ctrl);
3227 ctrl = E1000_READ_REG(hw, CTRL);
3228 /* Check to see if we shifted in a "1". */
3229 if(ctrl & E1000_CTRL_MDIO) data |= 1;
3230 e1000_lower_mdi_clk(hw, &ctrl);
3231 }
3232
3233 e1000_raise_mdi_clk(hw, &ctrl);
3234 e1000_lower_mdi_clk(hw, &ctrl);
3235
3236 return data;
3237 }
3238
3239 int32_t
3240 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3241 {
3242 uint32_t swfw_sync = 0;
3243 uint32_t swmask = mask;
3244 uint32_t fwmask = mask << 16;
3245 int32_t timeout = 200;
3246
3247 DEBUGFUNC("e1000_swfw_sync_acquire");
3248
3249 if (hw->swfwhw_semaphore_present)
3250 return e1000_get_software_flag(hw);
3251
3252 if (!hw->swfw_sync_present)
3253 return e1000_get_hw_eeprom_semaphore(hw);
3254
3255 while(timeout) {
3256 if (e1000_get_hw_eeprom_semaphore(hw))
3257 return -E1000_ERR_SWFW_SYNC;
3258
3259 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3260 if (!(swfw_sync & (fwmask | swmask))) {
3261 break;
3262 }
3263
3264 /* firmware currently using resource (fwmask) */
3265 /* or other software thread currently using resource (swmask) */
3266 e1000_put_hw_eeprom_semaphore(hw);
3267 msec_delay_irq(5);
3268 timeout--;
3269 }
3270
3271 if (!timeout) {
3272 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3273 return -E1000_ERR_SWFW_SYNC;
3274 }
3275
3276 swfw_sync |= swmask;
3277 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3278
3279 e1000_put_hw_eeprom_semaphore(hw);
3280 return E1000_SUCCESS;
3281 }
3282
3283 void
3284 e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3285 {
3286 uint32_t swfw_sync;
3287 uint32_t swmask = mask;
3288
3289 DEBUGFUNC("e1000_swfw_sync_release");
3290
3291 if (hw->swfwhw_semaphore_present) {
3292 e1000_release_software_flag(hw);
3293 return;
3294 }
3295
3296 if (!hw->swfw_sync_present) {
3297 e1000_put_hw_eeprom_semaphore(hw);
3298 return;
3299 }
3300
3301 /* if (e1000_get_hw_eeprom_semaphore(hw))
3302 * return -E1000_ERR_SWFW_SYNC; */
3303 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3304 /* empty */
3305
3306 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3307 swfw_sync &= ~swmask;
3308 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3309
3310 e1000_put_hw_eeprom_semaphore(hw);
3311 }
3312
3313 /*****************************************************************************
3314 * Reads the value from a PHY register, if the value is on a specific non zero
3315 * page, sets the page first.
3316 * hw - Struct containing variables accessed by shared code
3317 * reg_addr - address of the PHY register to read
3318 ******************************************************************************/
3319 int32_t
3320 e1000_read_phy_reg(struct e1000_hw *hw,
3321 uint32_t reg_addr,
3322 uint16_t *phy_data)
3323 {
3324 uint32_t ret_val;
3325 uint16_t swfw;
3326
3327 DEBUGFUNC("e1000_read_phy_reg");
3328
3329 if ((hw->mac_type == e1000_80003es2lan) &&
3330 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3331 swfw = E1000_SWFW_PHY1_SM;
3332 } else {
3333 swfw = E1000_SWFW_PHY0_SM;
3334 }
3335 if (e1000_swfw_sync_acquire(hw, swfw))
3336 return -E1000_ERR_SWFW_SYNC;
3337
3338 if ((hw->phy_type == e1000_phy_igp ||
3339 hw->phy_type == e1000_phy_igp_3 ||
3340 hw->phy_type == e1000_phy_igp_2) &&
3341 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3342 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3343 (uint16_t)reg_addr);
3344 if(ret_val) {
3345 e1000_swfw_sync_release(hw, swfw);
3346 return ret_val;
3347 }
3348 } else if (hw->phy_type == e1000_phy_gg82563) {
3349 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3350 (hw->mac_type == e1000_80003es2lan)) {
3351 /* Select Configuration Page */
3352 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3353 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3354 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3355 } else {
3356 /* Use Alternative Page Select register to access
3357 * registers 30 and 31
3358 */
3359 ret_val = e1000_write_phy_reg_ex(hw,
3360 GG82563_PHY_PAGE_SELECT_ALT,
3361 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3362 }
3363
3364 if (ret_val) {
3365 e1000_swfw_sync_release(hw, swfw);
3366 return ret_val;
3367 }
3368 }
3369 }
3370
3371 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3372 phy_data);
3373
3374 e1000_swfw_sync_release(hw, swfw);
3375 return ret_val;
3376 }
3377
3378 int32_t
3379 e1000_read_phy_reg_ex(struct e1000_hw *hw,
3380 uint32_t reg_addr,
3381 uint16_t *phy_data)
3382 {
3383 uint32_t i;
3384 uint32_t mdic = 0;
3385 const uint32_t phy_addr = 1;
3386
3387 DEBUGFUNC("e1000_read_phy_reg_ex");
3388
3389 if(reg_addr > MAX_PHY_REG_ADDRESS) {
3390 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3391 return -E1000_ERR_PARAM;
3392 }
3393
3394 if(hw->mac_type > e1000_82543) {
3395 /* Set up Op-code, Phy Address, and register address in the MDI
3396 * Control register. The MAC will take care of interfacing with the
3397 * PHY to retrieve the desired data.
3398 */
3399 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
3400 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3401 (E1000_MDIC_OP_READ));
3402
3403 E1000_WRITE_REG(hw, MDIC, mdic);
3404
3405 /* Poll the ready bit to see if the MDI read completed */
3406 for(i = 0; i < 64; i++) {
3407 udelay(50);
3408 mdic = E1000_READ_REG(hw, MDIC);
3409 if(mdic & E1000_MDIC_READY) break;
3410 }
3411 if(!(mdic & E1000_MDIC_READY)) {
3412 DEBUGOUT("MDI Read did not complete\n");
3413 return -E1000_ERR_PHY;
3414 }
3415 if(mdic & E1000_MDIC_ERROR) {
3416 DEBUGOUT("MDI Error\n");
3417 return -E1000_ERR_PHY;
3418 }
3419 *phy_data = (uint16_t) mdic;
3420 } else {
3421 /* We must first send a preamble through the MDIO pin to signal the
3422 * beginning of an MII instruction. This is done by sending 32
3423 * consecutive "1" bits.
3424 */
3425 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3426
3427 /* Now combine the next few fields that are required for a read
3428 * operation. We use this method instead of calling the
3429 * e1000_shift_out_mdi_bits routine five different times. The format of
3430 * a MII read instruction consists of a shift out of 14 bits and is
3431 * defined as follows:
3432 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
3433 * followed by a shift in of 18 bits. This first two bits shifted in
3434 * are TurnAround bits used to avoid contention on the MDIO pin when a
3435 * READ operation is performed. These two bits are thrown away
3436 * followed by a shift in of 16 bits which contains the desired data.
3437 */
3438 mdic = ((reg_addr) | (phy_addr << 5) |
3439 (PHY_OP_READ << 10) | (PHY_SOF << 12));
3440
3441 e1000_shift_out_mdi_bits(hw, mdic, 14);
3442
3443 /* Now that we've shifted out the read command to the MII, we need to
3444 * "shift in" the 16-bit value (18 total bits) of the requested PHY
3445 * register address.
3446 */
3447 *phy_data = e1000_shift_in_mdi_bits(hw);
3448 }
3449 return E1000_SUCCESS;
3450 }
3451
3452 /******************************************************************************
3453 * Writes a value to a PHY register
3454 *
3455 * hw - Struct containing variables accessed by shared code
3456 * reg_addr - address of the PHY register to write
3457 * data - data to write to the PHY
3458 ******************************************************************************/
3459 int32_t
3460 e1000_write_phy_reg(struct e1000_hw *hw,
3461 uint32_t reg_addr,
3462 uint16_t phy_data)
3463 {
3464 uint32_t ret_val;
3465 uint16_t swfw;
3466
3467 DEBUGFUNC("e1000_write_phy_reg");
3468
3469 if ((hw->mac_type == e1000_80003es2lan) &&
3470 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3471 swfw = E1000_SWFW_PHY1_SM;
3472 } else {
3473 swfw = E1000_SWFW_PHY0_SM;
3474 }
3475 if (e1000_swfw_sync_acquire(hw, swfw))
3476 return -E1000_ERR_SWFW_SYNC;
3477
3478 if ((hw->phy_type == e1000_phy_igp ||
3479 hw->phy_type == e1000_phy_igp_3 ||
3480 hw->phy_type == e1000_phy_igp_2) &&
3481 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3482 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3483 (uint16_t)reg_addr);
3484 if(ret_val) {
3485 e1000_swfw_sync_release(hw, swfw);
3486 return ret_val;
3487 }
3488 } else if (hw->phy_type == e1000_phy_gg82563) {
3489 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3490 (hw->mac_type == e1000_80003es2lan)) {
3491 /* Select Configuration Page */
3492 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3493 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3494 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3495 } else {
3496 /* Use Alternative Page Select register to access
3497 * registers 30 and 31
3498 */
3499 ret_val = e1000_write_phy_reg_ex(hw,
3500 GG82563_PHY_PAGE_SELECT_ALT,
3501 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3502 }
3503
3504 if (ret_val) {
3505 e1000_swfw_sync_release(hw, swfw);
3506 return ret_val;
3507 }
3508 }
3509 }
3510
3511 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3512 phy_data);
3513
3514 e1000_swfw_sync_release(hw, swfw);
3515 return ret_val;
3516 }
3517
3518 int32_t
3519 e1000_write_phy_reg_ex(struct e1000_hw *hw,
3520 uint32_t reg_addr,
3521 uint16_t phy_data)
3522 {
3523 uint32_t i;
3524 uint32_t mdic = 0;
3525 const uint32_t phy_addr = 1;
3526
3527 DEBUGFUNC("e1000_write_phy_reg_ex");
3528
3529 if(reg_addr > MAX_PHY_REG_ADDRESS) {
3530 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3531 return -E1000_ERR_PARAM;
3532 }
3533
3534 if(hw->mac_type > e1000_82543) {
3535 /* Set up Op-code, Phy Address, register address, and data intended
3536 * for the PHY register in the MDI Control register. The MAC will take
3537 * care of interfacing with the PHY to send the desired data.
3538 */
3539 mdic = (((uint32_t) phy_data) |
3540 (reg_addr << E1000_MDIC_REG_SHIFT) |
3541 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3542 (E1000_MDIC_OP_WRITE));
3543
3544 E1000_WRITE_REG(hw, MDIC, mdic);
3545
3546 /* Poll the ready bit to see if the MDI read completed */
3547 for(i = 0; i < 640; i++) {
3548 udelay(5);
3549 mdic = E1000_READ_REG(hw, MDIC);
3550 if(mdic & E1000_MDIC_READY) break;
3551 }
3552 if(!(mdic & E1000_MDIC_READY)) {
3553 DEBUGOUT("MDI Write did not complete\n");
3554 return -E1000_ERR_PHY;
3555 }
3556 } else {
3557 /* We'll need to use the SW defined pins to shift the write command
3558 * out to the PHY. We first send a preamble to the PHY to signal the
3559 * beginning of the MII instruction. This is done by sending 32
3560 * consecutive "1" bits.
3561 */
3562 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3563
3564 /* Now combine the remaining required fields that will indicate a
3565 * write operation. We use this method instead of calling the
3566 * e1000_shift_out_mdi_bits routine for each field in the command. The
3567 * format of a MII write instruction is as follows:
3568 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3569 */
3570 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3571 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3572 mdic <<= 16;
3573 mdic |= (uint32_t) phy_data;
3574
3575 e1000_shift_out_mdi_bits(hw, mdic, 32);
3576 }
3577
3578 return E1000_SUCCESS;
3579 }
3580
3581 int32_t
3582 e1000_read_kmrn_reg(struct e1000_hw *hw,
3583 uint32_t reg_addr,
3584 uint16_t *data)
3585 {
3586 uint32_t reg_val;
3587 uint16_t swfw;
3588 DEBUGFUNC("e1000_read_kmrn_reg");
3589
3590 if ((hw->mac_type == e1000_80003es2lan) &&
3591 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3592 swfw = E1000_SWFW_PHY1_SM;
3593 } else {
3594 swfw = E1000_SWFW_PHY0_SM;
3595 }
3596 if (e1000_swfw_sync_acquire(hw, swfw))
3597 return -E1000_ERR_SWFW_SYNC;
3598
3599 /* Write register address */
3600 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3601 E1000_KUMCTRLSTA_OFFSET) |
3602 E1000_KUMCTRLSTA_REN;
3603 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3604 udelay(2);
3605
3606 /* Read the data returned */
3607 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
3608 *data = (uint16_t)reg_val;
3609
3610 e1000_swfw_sync_release(hw, swfw);
3611 return E1000_SUCCESS;
3612 }
3613
3614 int32_t
3615 e1000_write_kmrn_reg(struct e1000_hw *hw,
3616 uint32_t reg_addr,
3617 uint16_t data)
3618 {
3619 uint32_t reg_val;
3620 uint16_t swfw;
3621 DEBUGFUNC("e1000_write_kmrn_reg");
3622
3623 if ((hw->mac_type == e1000_80003es2lan) &&
3624 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3625 swfw = E1000_SWFW_PHY1_SM;
3626 } else {
3627 swfw = E1000_SWFW_PHY0_SM;
3628 }
3629 if (e1000_swfw_sync_acquire(hw, swfw))
3630 return -E1000_ERR_SWFW_SYNC;
3631
3632 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3633 E1000_KUMCTRLSTA_OFFSET) | data;
3634 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3635 udelay(2);
3636
3637 e1000_swfw_sync_release(hw, swfw);
3638 return E1000_SUCCESS;
3639 }
3640
3641 /******************************************************************************
3642 * Returns the PHY to the power-on reset state
3643 *
3644 * hw - Struct containing variables accessed by shared code
3645 ******************************************************************************/
3646 int32_t
3647 e1000_phy_hw_reset(struct e1000_hw *hw)
3648 {
3649 uint32_t ctrl, ctrl_ext;
3650 uint32_t led_ctrl;
3651 int32_t ret_val;
3652 uint16_t swfw;
3653
3654 DEBUGFUNC("e1000_phy_hw_reset");
3655
3656 /* In the case of the phy reset being blocked, it's not an error, we
3657 * simply return success without performing the reset. */
3658 ret_val = e1000_check_phy_reset_block(hw);
3659 if (ret_val)
3660 return E1000_SUCCESS;
3661
3662 DEBUGOUT("Resetting Phy...\n");
3663
3664 if(hw->mac_type > e1000_82543) {
3665 if ((hw->mac_type == e1000_80003es2lan) &&
3666 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3667 swfw = E1000_SWFW_PHY1_SM;
3668 } else {
3669 swfw = E1000_SWFW_PHY0_SM;
3670 }
3671 if (e1000_swfw_sync_acquire(hw, swfw)) {
3672 e1000_release_software_semaphore(hw);
3673 return -E1000_ERR_SWFW_SYNC;
3674 }
3675 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3676 * bit. Then, take it out of reset.
3677 * For pre-e1000_82571 hardware, we delay for 10ms between the assert
3678 * and deassert. For e1000_82571 hardware and later, we instead delay
3679 * for 50us between and 10ms after the deassertion.
3680 */
3681 ctrl = E1000_READ_REG(hw, CTRL);
3682 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3683 E1000_WRITE_FLUSH(hw);
3684
3685 if (hw->mac_type < e1000_82571)
3686 msec_delay(10);
3687 else
3688 udelay(100);
3689
3690 E1000_WRITE_REG(hw, CTRL, ctrl);
3691 E1000_WRITE_FLUSH(hw);
3692
3693 if (hw->mac_type >= e1000_82571)
3694 msec_delay_irq(10);
3695 e1000_swfw_sync_release(hw, swfw);
3696 } else {
3697 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3698 * bit to put the PHY into reset. Then, take it out of reset.
3699 */
3700 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3701 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3702 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3703 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3704 E1000_WRITE_FLUSH(hw);
3705 msec_delay(10);
3706 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3707 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3708 E1000_WRITE_FLUSH(hw);
3709 }
3710 udelay(150);
3711
3712 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3713 /* Configure activity LED after PHY reset */
3714 led_ctrl = E1000_READ_REG(hw, LEDCTL);
3715 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3716 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3717 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
3718 }
3719
3720 /* Wait for FW to finish PHY configuration. */
3721 ret_val = e1000_get_phy_cfg_done(hw);
3722 e1000_release_software_semaphore(hw);
3723
3724 if ((hw->mac_type == e1000_ich8lan) &&
3725 (hw->phy_type == e1000_phy_igp_3)) {
3726 ret_val = e1000_init_lcd_from_nvm(hw);
3727 if (ret_val)
3728 return ret_val;
3729 }
3730 return ret_val;
3731 }
3732
3733 /******************************************************************************
3734 * Resets the PHY
3735 *
3736 * hw - Struct containing variables accessed by shared code
3737 *
3738 * Sets bit 15 of the MII Control regiser
3739 ******************************************************************************/
3740 int32_t
3741 e1000_phy_reset(struct e1000_hw *hw)
3742 {
3743 int32_t ret_val;
3744 uint16_t phy_data;
3745
3746 DEBUGFUNC("e1000_phy_reset");
3747
3748 /* In the case of the phy reset being blocked, it's not an error, we
3749 * simply return success without performing the reset. */
3750 ret_val = e1000_check_phy_reset_block(hw);
3751 if (ret_val)
3752 return E1000_SUCCESS;
3753
3754 switch (hw->mac_type) {
3755 case e1000_82541_rev_2:
3756 case e1000_82571:
3757 case e1000_82572:
3758 case e1000_ich8lan:
3759 ret_val = e1000_phy_hw_reset(hw);
3760 if(ret_val)
3761 return ret_val;
3762
3763 break;
3764 default:
3765 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3766 if(ret_val)
3767 return ret_val;
3768
3769 phy_data |= MII_CR_RESET;
3770 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3771 if(ret_val)
3772 return ret_val;
3773
3774 udelay(1);
3775 break;
3776 }
3777
3778 if(hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
3779 e1000_phy_init_script(hw);
3780
3781 return E1000_SUCCESS;
3782 }
3783
3784 /******************************************************************************
3785 * Work-around for 82566 power-down: on D3 entry-
3786 * 1) disable gigabit link
3787 * 2) write VR power-down enable
3788 * 3) read it back
3789 * if successful continue, else issue LCD reset and repeat
3790 *
3791 * hw - struct containing variables accessed by shared code
3792 ******************************************************************************/
3793 void
3794 e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3795 {
3796 int32_t reg;
3797 uint16_t phy_data;
3798 int32_t retry = 0;
3799
3800 DEBUGFUNC("e1000_phy_powerdown_workaround");
3801
3802 if (hw->phy_type != e1000_phy_igp_3)
3803 return;
3804
3805 do {
3806 /* Disable link */
3807 reg = E1000_READ_REG(hw, PHY_CTRL);
3808 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3809 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3810
3811 /* Write VR power-down enable */
3812 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3813 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data |
3814 IGP3_VR_CTRL_MODE_SHUT);
3815
3816 /* Read it back and test */
3817 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3818 if ((phy_data & IGP3_VR_CTRL_MODE_SHUT) || retry)
3819 break;
3820
3821 /* Issue PHY reset and repeat at most one more time */
3822 reg = E1000_READ_REG(hw, CTRL);
3823 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
3824 retry++;
3825 } while (retry);
3826
3827 return;
3828
3829 }
3830
3831 /******************************************************************************
3832 * Work-around for 82566 Kumeran PCS lock loss:
3833 * On link status change (i.e. PCI reset, speed change) and link is up and
3834 * speed is gigabit-
3835 * 0) if workaround is optionally disabled do nothing
3836 * 1) wait 1ms for Kumeran link to come up
3837 * 2) check Kumeran Diagnostic register PCS lock loss bit
3838 * 3) if not set the link is locked (all is good), otherwise...
3839 * 4) reset the PHY
3840 * 5) repeat up to 10 times
3841 * Note: this is only called for IGP3 copper when speed is 1gb.
3842 *
3843 * hw - struct containing variables accessed by shared code
3844 ******************************************************************************/
3845 int32_t
3846 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3847 {
3848 int32_t ret_val;
3849 int32_t reg;
3850 int32_t cnt;
3851 uint16_t phy_data;
3852
3853 if (hw->kmrn_lock_loss_workaround_disabled)
3854 return E1000_SUCCESS;
3855
3856 /* Make sure link is up before proceeding. If not just return.
3857 * Attempting this while link is negotiating fouls up link
3858 * stability */
3859 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3860 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3861
3862 if (phy_data & MII_SR_LINK_STATUS) {
3863 for (cnt = 0; cnt < 10; cnt++) {
3864 /* read once to clear */
3865 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3866 if (ret_val)
3867 return ret_val;
3868 /* and again to get new status */
3869 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3870 if (ret_val)
3871 return ret_val;
3872
3873 /* check for PCS lock */
3874 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3875 return E1000_SUCCESS;
3876
3877 /* Issue PHY reset */
3878 e1000_phy_hw_reset(hw);
3879 msec_delay_irq(5);
3880 }
3881 /* Disable GigE link negotiation */
3882 reg = E1000_READ_REG(hw, PHY_CTRL);
3883 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3884 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3885
3886 /* unable to acquire PCS lock */
3887 return E1000_ERR_PHY;
3888 }
3889
3890 return E1000_SUCCESS;
3891 }
3892
3893 /******************************************************************************
3894 * Probes the expected PHY address for known PHY IDs
3895 *
3896 * hw - Struct containing variables accessed by shared code
3897 ******************************************************************************/
3898 int32_t
3899 e1000_detect_gig_phy(struct e1000_hw *hw)
3900 {
3901 int32_t phy_init_status, ret_val;
3902 uint16_t phy_id_high, phy_id_low;
3903 boolean_t match = FALSE;
3904
3905 DEBUGFUNC("e1000_detect_gig_phy");
3906
3907 /* The 82571 firmware may still be configuring the PHY. In this
3908 * case, we cannot access the PHY until the configuration is done. So
3909 * we explicitly set the PHY values. */
3910 if (hw->mac_type == e1000_82571 ||
3911 hw->mac_type == e1000_82572) {
3912 hw->phy_id = IGP01E1000_I_PHY_ID;
3913 hw->phy_type = e1000_phy_igp_2;
3914 return E1000_SUCCESS;
3915 }
3916
3917 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
3918 * around that forces PHY page 0 to be set or the reads fail. The rest of
3919 * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
3920 * So for ESB-2 we need to have this set so our reads won't fail. If the
3921 * attached PHY is not a e1000_phy_gg82563, the routines below will figure
3922 * this out as well. */
3923 if (hw->mac_type == e1000_80003es2lan)
3924 hw->phy_type = e1000_phy_gg82563;
3925
3926 /* Read the PHY ID Registers to identify which PHY is onboard. */
3927 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3928 if (ret_val)
3929 return ret_val;
3930
3931 hw->phy_id = (uint32_t) (phy_id_high << 16);
3932 udelay(20);
3933 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3934 if(ret_val)
3935 return ret_val;
3936
3937 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
3938 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
3939
3940 switch(hw->mac_type) {
3941 case e1000_82543:
3942 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
3943 break;
3944 case e1000_82544:
3945 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
3946 break;
3947 case e1000_82540:
3948 case e1000_82545:
3949 case e1000_82545_rev_3:
3950 case e1000_82546:
3951 case e1000_82546_rev_3:
3952 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
3953 break;
3954 case e1000_82541:
3955 case e1000_82541_rev_2:
3956 case e1000_82547:
3957 case e1000_82547_rev_2:
3958 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
3959 break;
3960 case e1000_82573:
3961 if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
3962 break;
3963 case e1000_80003es2lan:
3964 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
3965 break;
3966 case e1000_ich8lan:
3967 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
3968 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
3969 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
3970 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
3971 break;
3972 default:
3973 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
3974 return -E1000_ERR_CONFIG;
3975 }
3976 phy_init_status = e1000_set_phy_type(hw);
3977
3978 if ((match) && (phy_init_status == E1000_SUCCESS)) {
3979 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
3980 return E1000_SUCCESS;
3981 }
3982 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
3983 return -E1000_ERR_PHY;
3984 }
3985
3986 /******************************************************************************
3987 * Resets the PHY's DSP
3988 *
3989 * hw - Struct containing variables accessed by shared code
3990 ******************************************************************************/
3991 static int32_t
3992 e1000_phy_reset_dsp(struct e1000_hw *hw)
3993 {
3994 int32_t ret_val;
3995 DEBUGFUNC("e1000_phy_reset_dsp");
3996
3997 do {
3998 if (hw->phy_type != e1000_phy_gg82563) {
3999 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
4000 if(ret_val) break;
4001 }
4002 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
4003 if(ret_val) break;
4004 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
4005 if(ret_val) break;
4006 ret_val = E1000_SUCCESS;
4007 } while(0);
4008
4009 return ret_val;
4010 }
4011
4012 /******************************************************************************
4013 * Get PHY information from various PHY registers for igp PHY only.
4014 *
4015 * hw - Struct containing variables accessed by shared code
4016 * phy_info - PHY information structure
4017 ******************************************************************************/
4018 static int32_t
4019 e1000_phy_igp_get_info(struct e1000_hw *hw,
4020 struct e1000_phy_info *phy_info)
4021 {
4022 int32_t ret_val;
4023 uint16_t phy_data, polarity, min_length, max_length, average;
4024
4025 DEBUGFUNC("e1000_phy_igp_get_info");
4026
4027 /* The downshift status is checked only once, after link is established,
4028 * and it stored in the hw->speed_downgraded parameter. */
4029 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4030
4031 /* IGP01E1000 does not need to support it. */
4032 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4033
4034 /* IGP01E1000 always correct polarity reversal */
4035 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
4036
4037 /* Check polarity status */
4038 ret_val = e1000_check_polarity(hw, &polarity);
4039 if(ret_val)
4040 return ret_val;
4041
4042 phy_info->cable_polarity = polarity;
4043
4044 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
4045 if(ret_val)
4046 return ret_val;
4047
4048 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
4049 IGP01E1000_PSSR_MDIX_SHIFT;
4050
4051 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4052 IGP01E1000_PSSR_SPEED_1000MBPS) {
4053 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
4054 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4055 if(ret_val)
4056 return ret_val;
4057
4058 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4059 SR_1000T_LOCAL_RX_STATUS_SHIFT;
4060 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4061 SR_1000T_REMOTE_RX_STATUS_SHIFT;
4062
4063 /* Get cable length */
4064 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
4065 if(ret_val)
4066 return ret_val;
4067
4068 /* Translate to old method */
4069 average = (max_length + min_length) / 2;
4070
4071 if(average <= e1000_igp_cable_length_50)
4072 phy_info->cable_length = e1000_cable_length_50;
4073 else if(average <= e1000_igp_cable_length_80)
4074 phy_info->cable_length = e1000_cable_length_50_80;
4075 else if(average <= e1000_igp_cable_length_110)
4076 phy_info->cable_length = e1000_cable_length_80_110;
4077 else if(average <= e1000_igp_cable_length_140)
4078 phy_info->cable_length = e1000_cable_length_110_140;
4079 else
4080 phy_info->cable_length = e1000_cable_length_140;
4081 }
4082
4083 return E1000_SUCCESS;
4084 }
4085
4086 /******************************************************************************
4087 * Get PHY information from various PHY registers for ife PHY only.
4088 *
4089 * hw - Struct containing variables accessed by shared code
4090 * phy_info - PHY information structure
4091 ******************************************************************************/
4092 int32_t
4093 e1000_phy_ife_get_info(struct e1000_hw *hw,
4094 struct e1000_phy_info *phy_info)
4095 {
4096 int32_t ret_val;
4097 uint16_t phy_data, polarity;
4098
4099 DEBUGFUNC("e1000_phy_ife_get_info");
4100
4101 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4102 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4103
4104 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4105 if (ret_val)
4106 return ret_val;
4107 phy_info->polarity_correction =
4108 (phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4109 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT;
4110
4111 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4112 ret_val = e1000_check_polarity(hw, &polarity);
4113 if (ret_val)
4114 return ret_val;
4115 } else {
4116 /* Polarity is forced. */
4117 polarity = (phy_data & IFE_PSC_FORCE_POLARITY) >>
4118 IFE_PSC_FORCE_POLARITY_SHIFT;
4119 }
4120 phy_info->cable_polarity = polarity;
4121
4122 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4123 if (ret_val)
4124 return ret_val;
4125
4126 phy_info->mdix_mode =
4127 (phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4128 IFE_PMC_MDIX_MODE_SHIFT;
4129
4130 return E1000_SUCCESS;
4131 }
4132
4133 /******************************************************************************
4134 * Get PHY information from various PHY registers fot m88 PHY only.
4135 *
4136 * hw - Struct containing variables accessed by shared code
4137 * phy_info - PHY information structure
4138 ******************************************************************************/
4139 static int32_t
4140 e1000_phy_m88_get_info(struct e1000_hw *hw,
4141 struct e1000_phy_info *phy_info)
4142 {
4143 int32_t ret_val;
4144 uint16_t phy_data, polarity;
4145
4146 DEBUGFUNC("e1000_phy_m88_get_info");
4147
4148 /* The downshift status is checked only once, after link is established,
4149 * and it stored in the hw->speed_downgraded parameter. */
4150 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4151
4152 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
4153 if(ret_val)
4154 return ret_val;
4155
4156 phy_info->extended_10bt_distance =
4157 (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
4158 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
4159 phy_info->polarity_correction =
4160 (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
4161 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
4162
4163 /* Check polarity status */
4164 ret_val = e1000_check_polarity(hw, &polarity);
4165 if(ret_val)
4166 return ret_val;
4167 phy_info->cable_polarity = polarity;
4168
4169 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
4170 if(ret_val)
4171 return ret_val;
4172
4173 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
4174 M88E1000_PSSR_MDIX_SHIFT;
4175
4176 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
4177 /* Cable Length Estimation and Local/Remote Receiver Information
4178 * are only valid at 1000 Mbps.
4179 */
4180 if (hw->phy_type != e1000_phy_gg82563) {
4181 phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4182 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4183 } else {
4184 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
4185 &phy_data);
4186 if (ret_val)
4187 return ret_val;
4188
4189 phy_info->cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
4190 }
4191
4192 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4193 if(ret_val)
4194 return ret_val;
4195
4196 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4197 SR_1000T_LOCAL_RX_STATUS_SHIFT;
4198
4199 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4200 SR_1000T_REMOTE_RX_STATUS_SHIFT;
4201 }
4202
4203 return E1000_SUCCESS;
4204 }
4205
4206 /******************************************************************************
4207 * Get PHY information from various PHY registers
4208 *
4209 * hw - Struct containing variables accessed by shared code
4210 * phy_info - PHY information structure
4211 ******************************************************************************/
4212 int32_t
4213 e1000_phy_get_info(struct e1000_hw *hw,
4214 struct e1000_phy_info *phy_info)
4215 {
4216 int32_t ret_val;
4217 uint16_t phy_data;
4218
4219 DEBUGFUNC("e1000_phy_get_info");
4220
4221 phy_info->cable_length = e1000_cable_length_undefined;
4222 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
4223 phy_info->cable_polarity = e1000_rev_polarity_undefined;
4224 phy_info->downshift = e1000_downshift_undefined;
4225 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
4226 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
4227 phy_info->local_rx = e1000_1000t_rx_status_undefined;
4228 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
4229
4230 if(hw->media_type != e1000_media_type_copper) {
4231 DEBUGOUT("PHY info is only valid for copper media\n");
4232 return -E1000_ERR_CONFIG;
4233 }
4234
4235 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4236 if(ret_val)
4237 return ret_val;
4238
4239 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4240 if(ret_val)
4241 return ret_val;
4242
4243 if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
4244 DEBUGOUT("PHY info is only valid if link is up\n");
4245 return -E1000_ERR_CONFIG;
4246 }
4247
4248 if (hw->phy_type == e1000_phy_igp ||
4249 hw->phy_type == e1000_phy_igp_3 ||
4250 hw->phy_type == e1000_phy_igp_2)
4251 return e1000_phy_igp_get_info(hw, phy_info);
4252 else if (hw->phy_type == e1000_phy_ife)
4253 return e1000_phy_ife_get_info(hw, phy_info);
4254 else
4255 return e1000_phy_m88_get_info(hw, phy_info);
4256 }
4257
4258 int32_t
4259 e1000_validate_mdi_setting(struct e1000_hw *hw)
4260 {
4261 DEBUGFUNC("e1000_validate_mdi_settings");
4262
4263 if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
4264 DEBUGOUT("Invalid MDI setting detected\n");
4265 hw->mdix = 1;
4266 return -E1000_ERR_CONFIG;
4267 }
4268 return E1000_SUCCESS;
4269 }
4270
4271
4272 /******************************************************************************
4273 * Sets up eeprom variables in the hw struct. Must be called after mac_type
4274 * is configured. Additionally, if this is ICH8, the flash controller GbE
4275 * registers must be mapped, or this will crash.
4276 *
4277 * hw - Struct containing variables accessed by shared code
4278 *****************************************************************************/
4279 int32_t
4280 e1000_init_eeprom_params(struct e1000_hw *hw)
4281 {
4282 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4283 uint32_t eecd = E1000_READ_REG(hw, EECD);
4284 int32_t ret_val = E1000_SUCCESS;
4285 uint16_t eeprom_size;
4286
4287 DEBUGFUNC("e1000_init_eeprom_params");
4288
4289 switch (hw->mac_type) {
4290 case e1000_82542_rev2_0:
4291 case e1000_82542_rev2_1:
4292 case e1000_82543:
4293 case e1000_82544:
4294 eeprom->type = e1000_eeprom_microwire;
4295 eeprom->word_size = 64;
4296 eeprom->opcode_bits = 3;
4297 eeprom->address_bits = 6;
4298 eeprom->delay_usec = 50;
4299 eeprom->use_eerd = FALSE;
4300 eeprom->use_eewr = FALSE;
4301 break;
4302 case e1000_82540:
4303 case e1000_82545:
4304 case e1000_82545_rev_3:
4305 case e1000_82546:
4306 case e1000_82546_rev_3:
4307 eeprom->type = e1000_eeprom_microwire;
4308 eeprom->opcode_bits = 3;
4309 eeprom->delay_usec = 50;
4310 if(eecd & E1000_EECD_SIZE) {
4311 eeprom->word_size = 256;
4312 eeprom->address_bits = 8;
4313 } else {
4314 eeprom->word_size = 64;
4315 eeprom->address_bits = 6;
4316 }
4317 eeprom->use_eerd = FALSE;
4318 eeprom->use_eewr = FALSE;
4319 break;
4320 case e1000_82541:
4321 case e1000_82541_rev_2:
4322 case e1000_82547:
4323 case e1000_82547_rev_2:
4324 if (eecd & E1000_EECD_TYPE) {
4325 eeprom->type = e1000_eeprom_spi;
4326 eeprom->opcode_bits = 8;
4327 eeprom->delay_usec = 1;
4328 if (eecd & E1000_EECD_ADDR_BITS) {
4329 eeprom->page_size = 32;
4330 eeprom->address_bits = 16;
4331 } else {
4332 eeprom->page_size = 8;
4333 eeprom->address_bits = 8;
4334 }
4335 } else {
4336 eeprom->type = e1000_eeprom_microwire;
4337 eeprom->opcode_bits = 3;
4338 eeprom->delay_usec = 50;
4339 if (eecd & E1000_EECD_ADDR_BITS) {
4340 eeprom->word_size = 256;
4341 eeprom->address_bits = 8;
4342 } else {
4343 eeprom->word_size = 64;
4344 eeprom->address_bits = 6;
4345 }
4346 }
4347 eeprom->use_eerd = FALSE;
4348 eeprom->use_eewr = FALSE;
4349 break;
4350 case e1000_82571:
4351 case e1000_82572:
4352 eeprom->type = e1000_eeprom_spi;
4353 eeprom->opcode_bits = 8;
4354 eeprom->delay_usec = 1;
4355 if (eecd & E1000_EECD_ADDR_BITS) {
4356 eeprom->page_size = 32;
4357 eeprom->address_bits = 16;
4358 } else {
4359 eeprom->page_size = 8;
4360 eeprom->address_bits = 8;
4361 }
4362 eeprom->use_eerd = FALSE;
4363 eeprom->use_eewr = FALSE;
4364 break;
4365 case e1000_82573:
4366 eeprom->type = e1000_eeprom_spi;
4367 eeprom->opcode_bits = 8;
4368 eeprom->delay_usec = 1;
4369 if (eecd & E1000_EECD_ADDR_BITS) {
4370 eeprom->page_size = 32;
4371 eeprom->address_bits = 16;
4372 } else {
4373 eeprom->page_size = 8;
4374 eeprom->address_bits = 8;
4375 }
4376 eeprom->use_eerd = TRUE;
4377 eeprom->use_eewr = TRUE;
4378 if(e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
4379 eeprom->type = e1000_eeprom_flash;
4380 eeprom->word_size = 2048;
4381
4382 /* Ensure that the Autonomous FLASH update bit is cleared due to
4383 * Flash update issue on parts which use a FLASH for NVM. */
4384 eecd &= ~E1000_EECD_AUPDEN;
4385 E1000_WRITE_REG(hw, EECD, eecd);
4386 }
4387 break;
4388 case e1000_80003es2lan:
4389 eeprom->type = e1000_eeprom_spi;
4390 eeprom->opcode_bits = 8;
4391 eeprom->delay_usec = 1;
4392 if (eecd & E1000_EECD_ADDR_BITS) {
4393 eeprom->page_size = 32;
4394 eeprom->address_bits = 16;
4395 } else {
4396 eeprom->page_size = 8;
4397 eeprom->address_bits = 8;
4398 }
4399 eeprom->use_eerd = TRUE;
4400 eeprom->use_eewr = FALSE;
4401 break;
4402 case e1000_ich8lan:
4403 {
4404 int32_t i = 0;
4405 uint32_t flash_size = E1000_READ_ICH8_REG(hw, ICH8_FLASH_GFPREG);
4406
4407 eeprom->type = e1000_eeprom_ich8;
4408 eeprom->use_eerd = FALSE;
4409 eeprom->use_eewr = FALSE;
4410 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4411
4412 /* Zero the shadow RAM structure. But don't load it from NVM
4413 * so as to save time for driver init */
4414 if (hw->eeprom_shadow_ram != NULL) {
4415 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4416 hw->eeprom_shadow_ram[i].modified = FALSE;
4417 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4418 }
4419 }
4420
4421 hw->flash_base_addr = (flash_size & ICH8_GFPREG_BASE_MASK) *
4422 ICH8_FLASH_SECTOR_SIZE;
4423
4424 hw->flash_bank_size = ((flash_size >> 16) & ICH8_GFPREG_BASE_MASK) + 1;
4425 hw->flash_bank_size -= (flash_size & ICH8_GFPREG_BASE_MASK);
4426 hw->flash_bank_size *= ICH8_FLASH_SECTOR_SIZE;
4427 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4428
4429 break;
4430 }
4431 default:
4432 break;
4433 }
4434
4435 if (eeprom->type == e1000_eeprom_spi) {
4436 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4437 * 32KB (incremented by powers of 2).
4438 */
4439 if(hw->mac_type <= e1000_82547_rev_2) {
4440 /* Set to default value for initial eeprom read. */
4441 eeprom->word_size = 64;
4442 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4443 if(ret_val)
4444 return ret_val;
4445 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4446 /* 256B eeprom size was not supported in earlier hardware, so we
4447 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4448 * is never the result used in the shifting logic below. */
4449 if(eeprom_size)
4450 eeprom_size++;
4451 } else {
4452 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4453 E1000_EECD_SIZE_EX_SHIFT);
4454 }
4455
4456 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
4457 }
4458 return ret_val;
4459 }
4460
4461 /******************************************************************************
4462 * Raises the EEPROM's clock input.
4463 *
4464 * hw - Struct containing variables accessed by shared code
4465 * eecd - EECD's current value
4466 *****************************************************************************/
4467 static void
4468 e1000_raise_ee_clk(struct e1000_hw *hw,
4469 uint32_t *eecd)
4470 {
4471 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
4472 * wait <delay> microseconds.
4473 */
4474 *eecd = *eecd | E1000_EECD_SK;
4475 E1000_WRITE_REG(hw, EECD, *eecd);
4476 E1000_WRITE_FLUSH(hw);
4477 udelay(hw->eeprom.delay_usec);
4478 }
4479
4480 /******************************************************************************
4481 * Lowers the EEPROM's clock input.
4482 *
4483 * hw - Struct containing variables accessed by shared code
4484 * eecd - EECD's current value
4485 *****************************************************************************/
4486 static void
4487 e1000_lower_ee_clk(struct e1000_hw *hw,
4488 uint32_t *eecd)
4489 {
4490 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4491 * wait 50 microseconds.
4492 */
4493 *eecd = *eecd & ~E1000_EECD_SK;
4494 E1000_WRITE_REG(hw, EECD, *eecd);
4495 E1000_WRITE_FLUSH(hw);
4496 udelay(hw->eeprom.delay_usec);
4497 }
4498
4499 /******************************************************************************
4500 * Shift data bits out to the EEPROM.
4501 *
4502 * hw - Struct containing variables accessed by shared code
4503 * data - data to send to the EEPROM
4504 * count - number of bits to shift out
4505 *****************************************************************************/
4506 static void
4507 e1000_shift_out_ee_bits(struct e1000_hw *hw,
4508 uint16_t data,
4509 uint16_t count)
4510 {
4511 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4512 uint32_t eecd;
4513 uint32_t mask;
4514
4515 /* We need to shift "count" bits out to the EEPROM. So, value in the
4516 * "data" parameter will be shifted out to the EEPROM one bit at a time.
4517 * In order to do this, "data" must be broken down into bits.
4518 */
4519 mask = 0x01 << (count - 1);
4520 eecd = E1000_READ_REG(hw, EECD);
4521 if (eeprom->type == e1000_eeprom_microwire) {
4522 eecd &= ~E1000_EECD_DO;
4523 } else if (eeprom->type == e1000_eeprom_spi) {
4524 eecd |= E1000_EECD_DO;
4525 }
4526 do {
4527 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
4528 * and then raising and then lowering the clock (the SK bit controls
4529 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
4530 * by setting "DI" to "0" and then raising and then lowering the clock.
4531 */
4532 eecd &= ~E1000_EECD_DI;
4533
4534 if(data & mask)
4535 eecd |= E1000_EECD_DI;
4536
4537 E1000_WRITE_REG(hw, EECD, eecd);
4538 E1000_WRITE_FLUSH(hw);
4539
4540 udelay(eeprom->delay_usec);
4541
4542 e1000_raise_ee_clk(hw, &eecd);
4543 e1000_lower_ee_clk(hw, &eecd);
4544
4545 mask = mask >> 1;
4546
4547 } while(mask);
4548
4549 /* We leave the "DI" bit set to "0" when we leave this routine. */
4550 eecd &= ~E1000_EECD_DI;
4551 E1000_WRITE_REG(hw, EECD, eecd);
4552 }
4553
4554 /******************************************************************************
4555 * Shift data bits in from the EEPROM
4556 *
4557 * hw - Struct containing variables accessed by shared code
4558 *****************************************************************************/
4559 static uint16_t
4560 e1000_shift_in_ee_bits(struct e1000_hw *hw,
4561 uint16_t count)
4562 {
4563 uint32_t eecd;
4564 uint32_t i;
4565 uint16_t data;
4566
4567 /* In order to read a register from the EEPROM, we need to shift 'count'
4568 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
4569 * input to the EEPROM (setting the SK bit), and then reading the value of
4570 * the "DO" bit. During this "shifting in" process the "DI" bit should
4571 * always be clear.
4572 */
4573
4574 eecd = E1000_READ_REG(hw, EECD);
4575
4576 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4577 data = 0;
4578
4579 for(i = 0; i < count; i++) {
4580 data = data << 1;
4581 e1000_raise_ee_clk(hw, &eecd);
4582
4583 eecd = E1000_READ_REG(hw, EECD);
4584
4585 eecd &= ~(E1000_EECD_DI);
4586 if(eecd & E1000_EECD_DO)
4587 data |= 1;
4588
4589 e1000_lower_ee_clk(hw, &eecd);
4590 }
4591
4592 return data;
4593 }
4594
4595 /******************************************************************************
4596 * Prepares EEPROM for access
4597 *
4598 * hw - Struct containing variables accessed by shared code
4599 *
4600 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4601 * function should be called before issuing a command to the EEPROM.
4602 *****************************************************************************/
4603 static int32_t
4604 e1000_acquire_eeprom(struct e1000_hw *hw)
4605 {
4606 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4607 uint32_t eecd, i=0;
4608
4609 DEBUGFUNC("e1000_acquire_eeprom");
4610
4611 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4612 return -E1000_ERR_SWFW_SYNC;
4613 eecd = E1000_READ_REG(hw, EECD);
4614
4615 if (hw->mac_type != e1000_82573) {
4616 /* Request EEPROM Access */
4617 if(hw->mac_type > e1000_82544) {
4618 eecd |= E1000_EECD_REQ;
4619 E1000_WRITE_REG(hw, EECD, eecd);
4620 eecd = E1000_READ_REG(hw, EECD);
4621 while((!(eecd & E1000_EECD_GNT)) &&
4622 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4623 i++;
4624 udelay(5);
4625 eecd = E1000_READ_REG(hw, EECD);
4626 }
4627 if(!(eecd & E1000_EECD_GNT)) {
4628 eecd &= ~E1000_EECD_REQ;
4629 E1000_WRITE_REG(hw, EECD, eecd);
4630 DEBUGOUT("Could not acquire EEPROM grant\n");
4631 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4632 return -E1000_ERR_EEPROM;
4633 }
4634 }
4635 }
4636
4637 /* Setup EEPROM for Read/Write */
4638
4639 if (eeprom->type == e1000_eeprom_microwire) {
4640 /* Clear SK and DI */
4641 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
4642 E1000_WRITE_REG(hw, EECD, eecd);
4643
4644 /* Set CS */
4645 eecd |= E1000_EECD_CS;
4646 E1000_WRITE_REG(hw, EECD, eecd);
4647 } else if (eeprom->type == e1000_eeprom_spi) {
4648 /* Clear SK and CS */
4649 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4650 E1000_WRITE_REG(hw, EECD, eecd);
4651 udelay(1);
4652 }
4653
4654 return E1000_SUCCESS;
4655 }
4656
4657 /******************************************************************************
4658 * Returns EEPROM to a "standby" state
4659 *
4660 * hw - Struct containing variables accessed by shared code
4661 *****************************************************************************/
4662 static void
4663 e1000_standby_eeprom(struct e1000_hw *hw)
4664 {
4665 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4666 uint32_t eecd;
4667
4668 eecd = E1000_READ_REG(hw, EECD);
4669
4670 if(eeprom->type == e1000_eeprom_microwire) {
4671 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4672 E1000_WRITE_REG(hw, EECD, eecd);
4673 E1000_WRITE_FLUSH(hw);
4674 udelay(eeprom->delay_usec);
4675
4676 /* Clock high */
4677 eecd |= E1000_EECD_SK;
4678 E1000_WRITE_REG(hw, EECD, eecd);
4679 E1000_WRITE_FLUSH(hw);
4680 udelay(eeprom->delay_usec);
4681
4682 /* Select EEPROM */
4683 eecd |= E1000_EECD_CS;
4684 E1000_WRITE_REG(hw, EECD, eecd);
4685 E1000_WRITE_FLUSH(hw);
4686 udelay(eeprom->delay_usec);
4687
4688 /* Clock low */
4689 eecd &= ~E1000_EECD_SK;
4690 E1000_WRITE_REG(hw, EECD, eecd);
4691 E1000_WRITE_FLUSH(hw);
4692 udelay(eeprom->delay_usec);
4693 } else if(eeprom->type == e1000_eeprom_spi) {
4694 /* Toggle CS to flush commands */
4695 eecd |= E1000_EECD_CS;
4696 E1000_WRITE_REG(hw, EECD, eecd);
4697 E1000_WRITE_FLUSH(hw);
4698 udelay(eeprom->delay_usec);
4699 eecd &= ~E1000_EECD_CS;
4700 E1000_WRITE_REG(hw, EECD, eecd);
4701 E1000_WRITE_FLUSH(hw);
4702 udelay(eeprom->delay_usec);
4703 }
4704 }
4705
4706 /******************************************************************************
4707 * Terminates a command by inverting the EEPROM's chip select pin
4708 *
4709 * hw - Struct containing variables accessed by shared code
4710 *****************************************************************************/
4711 static void
4712 e1000_release_eeprom(struct e1000_hw *hw)
4713 {
4714 uint32_t eecd;
4715
4716 DEBUGFUNC("e1000_release_eeprom");
4717
4718 eecd = E1000_READ_REG(hw, EECD);
4719
4720 if (hw->eeprom.type == e1000_eeprom_spi) {
4721 eecd |= E1000_EECD_CS; /* Pull CS high */
4722 eecd &= ~E1000_EECD_SK; /* Lower SCK */
4723
4724 E1000_WRITE_REG(hw, EECD, eecd);
4725
4726 udelay(hw->eeprom.delay_usec);
4727 } else if(hw->eeprom.type == e1000_eeprom_microwire) {
4728 /* cleanup eeprom */
4729
4730 /* CS on Microwire is active-high */
4731 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4732
4733 E1000_WRITE_REG(hw, EECD, eecd);
4734
4735 /* Rising edge of clock */
4736 eecd |= E1000_EECD_SK;
4737 E1000_WRITE_REG(hw, EECD, eecd);
4738 E1000_WRITE_FLUSH(hw);
4739 udelay(hw->eeprom.delay_usec);
4740
4741 /* Falling edge of clock */
4742 eecd &= ~E1000_EECD_SK;
4743 E1000_WRITE_REG(hw, EECD, eecd);
4744 E1000_WRITE_FLUSH(hw);
4745 udelay(hw->eeprom.delay_usec);
4746 }
4747
4748 /* Stop requesting EEPROM access */
4749 if(hw->mac_type > e1000_82544) {
4750 eecd &= ~E1000_EECD_REQ;
4751 E1000_WRITE_REG(hw, EECD, eecd);
4752 }
4753
4754 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4755 }
4756
4757 /******************************************************************************
4758 * Reads a 16 bit word from the EEPROM.
4759 *
4760 * hw - Struct containing variables accessed by shared code
4761 *****************************************************************************/
4762 int32_t
4763 e1000_spi_eeprom_ready(struct e1000_hw *hw)
4764 {
4765 uint16_t retry_count = 0;
4766 uint8_t spi_stat_reg;
4767
4768 DEBUGFUNC("e1000_spi_eeprom_ready");
4769
4770 /* Read "Status Register" repeatedly until the LSB is cleared. The
4771 * EEPROM will signal that the command has been completed by clearing
4772 * bit 0 of the internal status register. If it's not cleared within
4773 * 5 milliseconds, then error out.
4774 */
4775 retry_count = 0;
4776 do {
4777 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4778 hw->eeprom.opcode_bits);
4779 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
4780 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
4781 break;
4782
4783 udelay(5);
4784 retry_count += 5;
4785
4786 e1000_standby_eeprom(hw);
4787 } while(retry_count < EEPROM_MAX_RETRY_SPI);
4788
4789 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
4790 * only 0-5mSec on 5V devices)
4791 */
4792 if(retry_count >= EEPROM_MAX_RETRY_SPI) {
4793 DEBUGOUT("SPI EEPROM Status error\n");
4794 return -E1000_ERR_EEPROM;
4795 }
4796
4797 return E1000_SUCCESS;
4798 }
4799
4800 /******************************************************************************
4801 * Reads a 16 bit word from the EEPROM.
4802 *
4803 * hw - Struct containing variables accessed by shared code
4804 * offset - offset of word in the EEPROM to read
4805 * data - word read from the EEPROM
4806 * words - number of words to read
4807 *****************************************************************************/
4808 int32_t
4809 e1000_read_eeprom(struct e1000_hw *hw,
4810 uint16_t offset,
4811 uint16_t words,
4812 uint16_t *data)
4813 {
4814 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4815 uint32_t i = 0;
4816 int32_t ret_val;
4817
4818 DEBUGFUNC("e1000_read_eeprom");
4819
4820 /* A check for invalid values: offset too large, too many words, and not
4821 * enough words.
4822 */
4823 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4824 (words == 0)) {
4825 DEBUGOUT("\"words\" parameter out of bounds\n");
4826 return -E1000_ERR_EEPROM;
4827 }
4828
4829 /* FLASH reads without acquiring the semaphore are safe */
4830 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
4831 hw->eeprom.use_eerd == FALSE) {
4832 switch (hw->mac_type) {
4833 case e1000_80003es2lan:
4834 break;
4835 default:
4836 /* Prepare the EEPROM for reading */
4837 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4838 return -E1000_ERR_EEPROM;
4839 break;
4840 }
4841 }
4842
4843 if (eeprom->use_eerd == TRUE) {
4844 ret_val = e1000_read_eeprom_eerd(hw, offset, words, data);
4845 if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) ||
4846 (hw->mac_type != e1000_82573))
4847 e1000_release_eeprom(hw);
4848 return ret_val;
4849 }
4850
4851 if (eeprom->type == e1000_eeprom_ich8)
4852 return e1000_read_eeprom_ich8(hw, offset, words, data);
4853
4854 if (eeprom->type == e1000_eeprom_spi) {
4855 uint16_t word_in;
4856 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
4857
4858 if(e1000_spi_eeprom_ready(hw)) {
4859 e1000_release_eeprom(hw);
4860 return -E1000_ERR_EEPROM;
4861 }
4862
4863 e1000_standby_eeprom(hw);
4864
4865 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4866 if((eeprom->address_bits == 8) && (offset >= 128))
4867 read_opcode |= EEPROM_A8_OPCODE_SPI;
4868
4869 /* Send the READ command (opcode + addr) */
4870 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
4871 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
4872
4873 /* Read the data. The address of the eeprom internally increments with
4874 * each byte (spi) being read, saving on the overhead of eeprom setup
4875 * and tear-down. The address counter will roll over if reading beyond
4876 * the size of the eeprom, thus allowing the entire memory to be read
4877 * starting from any offset. */
4878 for (i = 0; i < words; i++) {
4879 word_in = e1000_shift_in_ee_bits(hw, 16);
4880 data[i] = (word_in >> 8) | (word_in << 8);
4881 }
4882 } else if(eeprom->type == e1000_eeprom_microwire) {
4883 for (i = 0; i < words; i++) {
4884 /* Send the READ command (opcode + addr) */
4885 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
4886 eeprom->opcode_bits);
4887 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
4888 eeprom->address_bits);
4889
4890 /* Read the data. For microwire, each word requires the overhead
4891 * of eeprom setup and tear-down. */
4892 data[i] = e1000_shift_in_ee_bits(hw, 16);
4893 e1000_standby_eeprom(hw);
4894 }
4895 }
4896
4897 /* End this read operation */
4898 e1000_release_eeprom(hw);
4899
4900 return E1000_SUCCESS;
4901 }
4902
4903 /******************************************************************************
4904 * Reads a 16 bit word from the EEPROM using the EERD register.
4905 *
4906 * hw - Struct containing variables accessed by shared code
4907 * offset - offset of word in the EEPROM to read
4908 * data - word read from the EEPROM
4909 * words - number of words to read
4910 *****************************************************************************/
4911 static int32_t
4912 e1000_read_eeprom_eerd(struct e1000_hw *hw,
4913 uint16_t offset,
4914 uint16_t words,
4915 uint16_t *data)
4916 {
4917 uint32_t i, eerd = 0;
4918 int32_t error = 0;
4919
4920 for (i = 0; i < words; i++) {
4921 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
4922 E1000_EEPROM_RW_REG_START;
4923
4924 E1000_WRITE_REG(hw, EERD, eerd);
4925 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
4926
4927 if(error) {
4928 break;
4929 }
4930 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
4931
4932 }
4933
4934 return error;
4935 }
4936
4937 /******************************************************************************
4938 * Writes a 16 bit word from the EEPROM using the EEWR register.
4939 *
4940 * hw - Struct containing variables accessed by shared code
4941 * offset - offset of word in the EEPROM to read
4942 * data - word read from the EEPROM
4943 * words - number of words to read
4944 *****************************************************************************/
4945 static int32_t
4946 e1000_write_eeprom_eewr(struct e1000_hw *hw,
4947 uint16_t offset,
4948 uint16_t words,
4949 uint16_t *data)
4950 {
4951 uint32_t register_value = 0;
4952 uint32_t i = 0;
4953 int32_t error = 0;
4954
4955 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4956 return -E1000_ERR_SWFW_SYNC;
4957
4958 for (i = 0; i < words; i++) {
4959 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
4960 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
4961 E1000_EEPROM_RW_REG_START;
4962
4963 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
4964 if(error) {
4965 break;
4966 }
4967
4968 E1000_WRITE_REG(hw, EEWR, register_value);
4969
4970 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
4971
4972 if(error) {
4973 break;
4974 }
4975 }
4976
4977 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4978 return error;
4979 }
4980
4981 /******************************************************************************
4982 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
4983 *
4984 * hw - Struct containing variables accessed by shared code
4985 *****************************************************************************/
4986 static int32_t
4987 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
4988 {
4989 uint32_t attempts = 100000;
4990 uint32_t i, reg = 0;
4991 int32_t done = E1000_ERR_EEPROM;
4992
4993 for(i = 0; i < attempts; i++) {
4994 if(eerd == E1000_EEPROM_POLL_READ)
4995 reg = E1000_READ_REG(hw, EERD);
4996 else
4997 reg = E1000_READ_REG(hw, EEWR);
4998
4999 if(reg & E1000_EEPROM_RW_REG_DONE) {
5000 done = E1000_SUCCESS;
5001 break;
5002 }
5003 udelay(5);
5004 }
5005
5006 return done;
5007 }
5008
5009 /***************************************************************************
5010 * Description: Determines if the onboard NVM is FLASH or EEPROM.
5011 *
5012 * hw - Struct containing variables accessed by shared code
5013 ****************************************************************************/
5014 static boolean_t
5015 e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5016 {
5017 uint32_t eecd = 0;
5018
5019 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
5020
5021 if (hw->mac_type == e1000_ich8lan)
5022 return FALSE;
5023
5024 if (hw->mac_type == e1000_82573) {
5025 eecd = E1000_READ_REG(hw, EECD);
5026
5027 /* Isolate bits 15 & 16 */
5028 eecd = ((eecd >> 15) & 0x03);
5029
5030 /* If both bits are set, device is Flash type */
5031 if(eecd == 0x03) {
5032 return FALSE;
5033 }
5034 }
5035 return TRUE;
5036 }
5037
5038 /******************************************************************************
5039 * Verifies that the EEPROM has a valid checksum
5040 *
5041 * hw - Struct containing variables accessed by shared code
5042 *
5043 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
5044 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
5045 * valid.
5046 *****************************************************************************/
5047 int32_t
5048 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5049 {
5050 uint16_t checksum = 0;
5051 uint16_t i, eeprom_data;
5052
5053 DEBUGFUNC("e1000_validate_eeprom_checksum");
5054
5055 if ((hw->mac_type == e1000_82573) &&
5056 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
5057 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
5058 * 10h-12h. Checksum may need to be fixed. */
5059 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
5060 if ((eeprom_data & 0x10) == 0) {
5061 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
5062 * has already been fixed. If the checksum is still wrong and this
5063 * bit is a 1, we need to return bad checksum. Otherwise, we need
5064 * to set this bit to a 1 and update the checksum. */
5065 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
5066 if ((eeprom_data & 0x8000) == 0) {
5067 eeprom_data |= 0x8000;
5068 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
5069 e1000_update_eeprom_checksum(hw);
5070 }
5071 }
5072 }
5073
5074 if (hw->mac_type == e1000_ich8lan) {
5075 /* Drivers must allocate the shadow ram structure for the
5076 * EEPROM checksum to be updated. Otherwise, this bit as well
5077 * as the checksum must both be set correctly for this
5078 * validation to pass.
5079 */
5080 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5081 if ((eeprom_data & 0x40) == 0) {
5082 eeprom_data |= 0x40;
5083 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5084 e1000_update_eeprom_checksum(hw);
5085 }
5086 }
5087
5088 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5089 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5090 DEBUGOUT("EEPROM Read Error\n");
5091 return -E1000_ERR_EEPROM;
5092 }
5093 checksum += eeprom_data;
5094 }
5095
5096 if(checksum == (uint16_t) EEPROM_SUM)
5097 return E1000_SUCCESS;
5098 else {
5099 DEBUGOUT("EEPROM Checksum Invalid\n");
5100 return -E1000_ERR_EEPROM;
5101 }
5102 }
5103
5104 /******************************************************************************
5105 * Calculates the EEPROM checksum and writes it to the EEPROM
5106 *
5107 * hw - Struct containing variables accessed by shared code
5108 *
5109 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
5110 * Writes the difference to word offset 63 of the EEPROM.
5111 *****************************************************************************/
5112 int32_t
5113 e1000_update_eeprom_checksum(struct e1000_hw *hw)
5114 {
5115 uint32_t ctrl_ext;
5116 uint16_t checksum = 0;
5117 uint16_t i, eeprom_data;
5118
5119 DEBUGFUNC("e1000_update_eeprom_checksum");
5120
5121 for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5122 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5123 DEBUGOUT("EEPROM Read Error\n");
5124 return -E1000_ERR_EEPROM;
5125 }
5126 checksum += eeprom_data;
5127 }
5128 checksum = (uint16_t) EEPROM_SUM - checksum;
5129 if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5130 DEBUGOUT("EEPROM Write Error\n");
5131 return -E1000_ERR_EEPROM;
5132 } else if (hw->eeprom.type == e1000_eeprom_flash) {
5133 e1000_commit_shadow_ram(hw);
5134 } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5135 e1000_commit_shadow_ram(hw);
5136 /* Reload the EEPROM, or else modifications will not appear
5137 * until after next adapter reset. */
5138 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5139 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5140 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5141 msec_delay(10);
5142 }
5143 return E1000_SUCCESS;
5144 }
5145
5146 /******************************************************************************
5147 * Parent function for writing words to the different EEPROM types.
5148 *
5149 * hw - Struct containing variables accessed by shared code
5150 * offset - offset within the EEPROM to be written to
5151 * words - number of words to write
5152 * data - 16 bit word to be written to the EEPROM
5153 *
5154 * If e1000_update_eeprom_checksum is not called after this function, the
5155 * EEPROM will most likely contain an invalid checksum.
5156 *****************************************************************************/
5157 int32_t
5158 e1000_write_eeprom(struct e1000_hw *hw,
5159 uint16_t offset,
5160 uint16_t words,
5161 uint16_t *data)
5162 {
5163 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5164 int32_t status = 0;
5165
5166 DEBUGFUNC("e1000_write_eeprom");
5167
5168 /* A check for invalid values: offset too large, too many words, and not
5169 * enough words.
5170 */
5171 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
5172 (words == 0)) {
5173 DEBUGOUT("\"words\" parameter out of bounds\n");
5174 return -E1000_ERR_EEPROM;
5175 }
5176
5177 /* 82573 writes only through eewr */
5178 if(eeprom->use_eewr == TRUE)
5179 return e1000_write_eeprom_eewr(hw, offset, words, data);
5180
5181 if (eeprom->type == e1000_eeprom_ich8)
5182 return e1000_write_eeprom_ich8(hw, offset, words, data);
5183
5184 /* Prepare the EEPROM for writing */
5185 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5186 return -E1000_ERR_EEPROM;
5187
5188 if(eeprom->type == e1000_eeprom_microwire) {
5189 status = e1000_write_eeprom_microwire(hw, offset, words, data);
5190 } else {
5191 status = e1000_write_eeprom_spi(hw, offset, words, data);
5192 msec_delay(10);
5193 }
5194
5195 /* Done with writing */
5196 e1000_release_eeprom(hw);
5197
5198 return status;
5199 }
5200
5201 /******************************************************************************
5202 * Writes a 16 bit word to a given offset in an SPI EEPROM.
5203 *
5204 * hw - Struct containing variables accessed by shared code
5205 * offset - offset within the EEPROM to be written to
5206 * words - number of words to write
5207 * data - pointer to array of 8 bit words to be written to the EEPROM
5208 *
5209 *****************************************************************************/
5210 int32_t
5211 e1000_write_eeprom_spi(struct e1000_hw *hw,
5212 uint16_t offset,
5213 uint16_t words,
5214 uint16_t *data)
5215 {
5216 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5217 uint16_t widx = 0;
5218
5219 DEBUGFUNC("e1000_write_eeprom_spi");
5220
5221 while (widx < words) {
5222 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
5223
5224 if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
5225
5226 e1000_standby_eeprom(hw);
5227
5228 /* Send the WRITE ENABLE command (8 bit opcode ) */
5229 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
5230 eeprom->opcode_bits);
5231
5232 e1000_standby_eeprom(hw);
5233
5234 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
5235 if((eeprom->address_bits == 8) && (offset >= 128))
5236 write_opcode |= EEPROM_A8_OPCODE_SPI;
5237
5238 /* Send the Write command (8-bit opcode + addr) */
5239 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
5240
5241 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
5242 eeprom->address_bits);
5243
5244 /* Send the data */
5245
5246 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
5247 while (widx < words) {
5248 uint16_t word_out = data[widx];
5249 word_out = (word_out >> 8) | (word_out << 8);
5250 e1000_shift_out_ee_bits(hw, word_out, 16);
5251 widx++;
5252
5253 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
5254 * operation, while the smaller eeproms are capable of an 8-byte
5255 * PAGE WRITE operation. Break the inner loop to pass new address
5256 */
5257 if((((offset + widx)*2) % eeprom->page_size) == 0) {
5258 e1000_standby_eeprom(hw);
5259 break;
5260 }
5261 }
5262 }
5263
5264 return E1000_SUCCESS;
5265 }
5266
5267 /******************************************************************************
5268 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
5269 *
5270 * hw - Struct containing variables accessed by shared code
5271 * offset - offset within the EEPROM to be written to
5272 * words - number of words to write
5273 * data - pointer to array of 16 bit words to be written to the EEPROM
5274 *
5275 *****************************************************************************/
5276 int32_t
5277 e1000_write_eeprom_microwire(struct e1000_hw *hw,
5278 uint16_t offset,
5279 uint16_t words,
5280 uint16_t *data)
5281 {
5282 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5283 uint32_t eecd;
5284 uint16_t words_written = 0;
5285 uint16_t i = 0;
5286
5287 DEBUGFUNC("e1000_write_eeprom_microwire");
5288
5289 /* Send the write enable command to the EEPROM (3-bit opcode plus
5290 * 6/8-bit dummy address beginning with 11). It's less work to include
5291 * the 11 of the dummy address as part of the opcode than it is to shift
5292 * it over the correct number of bits for the address. This puts the
5293 * EEPROM into write/erase mode.
5294 */
5295 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
5296 (uint16_t)(eeprom->opcode_bits + 2));
5297
5298 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5299
5300 /* Prepare the EEPROM */
5301 e1000_standby_eeprom(hw);
5302
5303 while (words_written < words) {
5304 /* Send the Write command (3-bit opcode + addr) */
5305 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5306 eeprom->opcode_bits);
5307
5308 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
5309 eeprom->address_bits);
5310
5311 /* Send the data */
5312 e1000_shift_out_ee_bits(hw, data[words_written], 16);
5313
5314 /* Toggle the CS line. This in effect tells the EEPROM to execute
5315 * the previous command.
5316 */
5317 e1000_standby_eeprom(hw);
5318
5319 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
5320 * signal that the command has been completed by raising the DO signal.
5321 * If DO does not go high in 10 milliseconds, then error out.
5322 */
5323 for(i = 0; i < 200; i++) {
5324 eecd = E1000_READ_REG(hw, EECD);
5325 if(eecd & E1000_EECD_DO) break;
5326 udelay(50);
5327 }
5328 if(i == 200) {
5329 DEBUGOUT("EEPROM Write did not complete\n");
5330 return -E1000_ERR_EEPROM;
5331 }
5332
5333 /* Recover from write */
5334 e1000_standby_eeprom(hw);
5335
5336 words_written++;
5337 }
5338
5339 /* Send the write disable command to the EEPROM (3-bit opcode plus
5340 * 6/8-bit dummy address beginning with 10). It's less work to include
5341 * the 10 of the dummy address as part of the opcode than it is to shift
5342 * it over the correct number of bits for the address. This takes the
5343 * EEPROM out of write/erase mode.
5344 */
5345 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
5346 (uint16_t)(eeprom->opcode_bits + 2));
5347
5348 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5349
5350 return E1000_SUCCESS;
5351 }
5352
5353 /******************************************************************************
5354 * Flushes the cached eeprom to NVM. This is done by saving the modified values
5355 * in the eeprom cache and the non modified values in the currently active bank
5356 * to the new bank.
5357 *
5358 * hw - Struct containing variables accessed by shared code
5359 * offset - offset of word in the EEPROM to read
5360 * data - word read from the EEPROM
5361 * words - number of words to read
5362 *****************************************************************************/
5363 static int32_t
5364 e1000_commit_shadow_ram(struct e1000_hw *hw)
5365 {
5366 uint32_t attempts = 100000;
5367 uint32_t eecd = 0;
5368 uint32_t flop = 0;
5369 uint32_t i = 0;
5370 int32_t error = E1000_SUCCESS;
5371 uint32_t old_bank_offset = 0;
5372 uint32_t new_bank_offset = 0;
5373 uint32_t sector_retries = 0;
5374 uint8_t low_byte = 0;
5375 uint8_t high_byte = 0;
5376 uint8_t temp_byte = 0;
5377 boolean_t sector_write_failed = FALSE;
5378
5379 if (hw->mac_type == e1000_82573) {
5380 /* The flop register will be used to determine if flash type is STM */
5381 flop = E1000_READ_REG(hw, FLOP);
5382 for (i=0; i < attempts; i++) {
5383 eecd = E1000_READ_REG(hw, EECD);
5384 if ((eecd & E1000_EECD_FLUPD) == 0) {
5385 break;
5386 }
5387 udelay(5);
5388 }
5389
5390 if (i == attempts) {
5391 return -E1000_ERR_EEPROM;
5392 }
5393
5394 /* If STM opcode located in bits 15:8 of flop, reset firmware */
5395 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
5396 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
5397 }
5398
5399 /* Perform the flash update */
5400 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
5401
5402 for (i=0; i < attempts; i++) {
5403 eecd = E1000_READ_REG(hw, EECD);
5404 if ((eecd & E1000_EECD_FLUPD) == 0) {
5405 break;
5406 }
5407 udelay(5);
5408 }
5409
5410 if (i == attempts) {
5411 return -E1000_ERR_EEPROM;
5412 }
5413 }
5414
5415 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
5416 /* We're writing to the opposite bank so if we're on bank 1,
5417 * write to bank 0 etc. We also need to erase the segment that
5418 * is going to be written */
5419 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5420 new_bank_offset = hw->flash_bank_size * 2;
5421 old_bank_offset = 0;
5422 e1000_erase_ich8_4k_segment(hw, 1);
5423 } else {
5424 old_bank_offset = hw->flash_bank_size * 2;
5425 new_bank_offset = 0;
5426 e1000_erase_ich8_4k_segment(hw, 0);
5427 }
5428
5429 do {
5430 sector_write_failed = FALSE;
5431 /* Loop for every byte in the shadow RAM,
5432 * which is in units of words. */
5433 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5434 /* Determine whether to write the value stored
5435 * in the other NVM bank or a modified value stored
5436 * in the shadow RAM */
5437 if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5438 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5439 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5440 &temp_byte);
5441 udelay(100);
5442 error = e1000_verify_write_ich8_byte(hw,
5443 (i << 1) + new_bank_offset,
5444 low_byte);
5445 if (error != E1000_SUCCESS)
5446 sector_write_failed = TRUE;
5447 high_byte =
5448 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5449 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5450 &temp_byte);
5451 udelay(100);
5452 } else {
5453 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5454 &low_byte);
5455 udelay(100);
5456 error = e1000_verify_write_ich8_byte(hw,
5457 (i << 1) + new_bank_offset, low_byte);
5458 if (error != E1000_SUCCESS)
5459 sector_write_failed = TRUE;
5460 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5461 &high_byte);
5462 }
5463
5464 /* If the word is 0x13, then make sure the signature bits
5465 * (15:14) are 11b until the commit has completed.
5466 * This will allow us to write 10b which indicates the
5467 * signature is valid. We want to do this after the write
5468 * has completed so that we don't mark the segment valid
5469 * while the write is still in progress */
5470 if (i == E1000_ICH8_NVM_SIG_WORD)
5471 high_byte = E1000_ICH8_NVM_SIG_MASK | high_byte;
5472
5473 error = e1000_verify_write_ich8_byte(hw,
5474 (i << 1) + new_bank_offset + 1, high_byte);
5475 if (error != E1000_SUCCESS)
5476 sector_write_failed = TRUE;
5477
5478 if (sector_write_failed == FALSE) {
5479 /* Clear the now not used entry in the cache */
5480 hw->eeprom_shadow_ram[i].modified = FALSE;
5481 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5482 }
5483 }
5484
5485 /* Don't bother writing the segment valid bits if sector
5486 * programming failed. */
5487 if (sector_write_failed == FALSE) {
5488 /* Finally validate the new segment by setting bit 15:14
5489 * to 10b in word 0x13 , this can be done without an
5490 * erase as well since these bits are 11 to start with
5491 * and we need to change bit 14 to 0b */
5492 e1000_read_ich8_byte(hw,
5493 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5494 &high_byte);
5495 high_byte &= 0xBF;
5496 error = e1000_verify_write_ich8_byte(hw,
5497 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5498 high_byte);
5499 if (error != E1000_SUCCESS)
5500 sector_write_failed = TRUE;
5501
5502 /* And invalidate the previously valid segment by setting
5503 * its signature word (0x13) high_byte to 0b. This can be
5504 * done without an erase because flash erase sets all bits
5505 * to 1's. We can write 1's to 0's without an erase */
5506 error = e1000_verify_write_ich8_byte(hw,
5507 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + old_bank_offset,
5508 0);
5509 if (error != E1000_SUCCESS)
5510 sector_write_failed = TRUE;
5511 }
5512 } while (++sector_retries < 10 && sector_write_failed == TRUE);
5513 }
5514
5515 return error;
5516 }
5517
5518 /******************************************************************************
5519 * Reads the adapter's part number from the EEPROM
5520 *
5521 * hw - Struct containing variables accessed by shared code
5522 * part_num - Adapter's part number
5523 *****************************************************************************/
5524 int32_t
5525 e1000_read_part_num(struct e1000_hw *hw,
5526 uint32_t *part_num)
5527 {
5528 uint16_t offset = EEPROM_PBA_BYTE_1;
5529 uint16_t eeprom_data;
5530
5531 DEBUGFUNC("e1000_read_part_num");
5532
5533 /* Get word 0 from EEPROM */
5534 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5535 DEBUGOUT("EEPROM Read Error\n");
5536 return -E1000_ERR_EEPROM;
5537 }
5538 /* Save word 0 in upper half of part_num */
5539 *part_num = (uint32_t) (eeprom_data << 16);
5540
5541 /* Get word 1 from EEPROM */
5542 if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
5543 DEBUGOUT("EEPROM Read Error\n");
5544 return -E1000_ERR_EEPROM;
5545 }
5546 /* Save word 1 in lower half of part_num */
5547 *part_num |= eeprom_data;
5548
5549 return E1000_SUCCESS;
5550 }
5551
5552 /******************************************************************************
5553 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5554 * second function of dual function devices
5555 *
5556 * hw - Struct containing variables accessed by shared code
5557 *****************************************************************************/
5558 int32_t
5559 e1000_read_mac_addr(struct e1000_hw * hw)
5560 {
5561 uint16_t offset;
5562 uint16_t eeprom_data, i;
5563
5564 DEBUGFUNC("e1000_read_mac_addr");
5565
5566 for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
5567 offset = i >> 1;
5568 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5569 DEBUGOUT("EEPROM Read Error\n");
5570 return -E1000_ERR_EEPROM;
5571 }
5572 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
5573 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
5574 }
5575
5576 switch (hw->mac_type) {
5577 default:
5578 break;
5579 case e1000_82546:
5580 case e1000_82546_rev_3:
5581 case e1000_82571:
5582 case e1000_80003es2lan:
5583 if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
5584 hw->perm_mac_addr[5] ^= 0x01;
5585 break;
5586 }
5587
5588 for(i = 0; i < NODE_ADDRESS_SIZE; i++)
5589 hw->mac_addr[i] = hw->perm_mac_addr[i];
5590 return E1000_SUCCESS;
5591 }
5592
5593 /******************************************************************************
5594 * Initializes receive address filters.
5595 *
5596 * hw - Struct containing variables accessed by shared code
5597 *
5598 * Places the MAC address in receive address register 0 and clears the rest
5599 * of the receive addresss registers. Clears the multicast table. Assumes
5600 * the receiver is in reset when the routine is called.
5601 *****************************************************************************/
5602 static void
5603 e1000_init_rx_addrs(struct e1000_hw *hw)
5604 {
5605 uint32_t i;
5606 uint32_t rar_num;
5607
5608 DEBUGFUNC("e1000_init_rx_addrs");
5609
5610 /* Setup the receive address. */
5611 DEBUGOUT("Programming MAC Address into RAR[0]\n");
5612
5613 e1000_rar_set(hw, hw->mac_addr, 0);
5614
5615 rar_num = E1000_RAR_ENTRIES;
5616
5617 /* Reserve a spot for the Locally Administered Address to work around
5618 * an 82571 issue in which a reset on one port will reload the MAC on
5619 * the other port. */
5620 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5621 rar_num -= 1;
5622 if (hw->mac_type == e1000_ich8lan)
5623 rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5624
5625 /* Zero out the other 15 receive addresses. */
5626 DEBUGOUT("Clearing RAR[1-15]\n");
5627 for(i = 1; i < rar_num; i++) {
5628 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5629 E1000_WRITE_FLUSH(hw);
5630 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5631 E1000_WRITE_FLUSH(hw);
5632 }
5633 }
5634
5635 /******************************************************************************
5636 * Updates the MAC's list of multicast addresses.
5637 *
5638 * hw - Struct containing variables accessed by shared code
5639 * mc_addr_list - the list of new multicast addresses
5640 * mc_addr_count - number of addresses
5641 * pad - number of bytes between addresses in the list
5642 * rar_used_count - offset where to start adding mc addresses into the RAR's
5643 *
5644 * The given list replaces any existing list. Clears the last 15 receive
5645 * address registers and the multicast table. Uses receive address registers
5646 * for the first 15 multicast addresses, and hashes the rest into the
5647 * multicast table.
5648 *****************************************************************************/
5649 void
5650 e1000_mc_addr_list_update(struct e1000_hw *hw,
5651 uint8_t *mc_addr_list,
5652 uint32_t mc_addr_count,
5653 uint32_t pad,
5654 uint32_t rar_used_count)
5655 {
5656 uint32_t hash_value;
5657 uint32_t i;
5658 uint32_t num_rar_entry;
5659 uint32_t num_mta_entry;
5660
5661 DEBUGFUNC("e1000_mc_addr_list_update");
5662
5663 /* Set the new number of MC addresses that we are being requested to use. */
5664 hw->num_mc_addrs = mc_addr_count;
5665
5666 /* Clear RAR[1-15] */
5667 DEBUGOUT(" Clearing RAR[1-15]\n");
5668 num_rar_entry = E1000_RAR_ENTRIES;
5669 if (hw->mac_type == e1000_ich8lan)
5670 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN;
5671 /* Reserve a spot for the Locally Administered Address to work around
5672 * an 82571 issue in which a reset on one port will reload the MAC on
5673 * the other port. */
5674 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5675 num_rar_entry -= 1;
5676
5677 for(i = rar_used_count; i < num_rar_entry; i++) {
5678 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5679 E1000_WRITE_FLUSH(hw);
5680 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5681 E1000_WRITE_FLUSH(hw);
5682 }
5683
5684 /* Clear the MTA */
5685 DEBUGOUT(" Clearing MTA\n");
5686 num_mta_entry = E1000_NUM_MTA_REGISTERS;
5687 if (hw->mac_type == e1000_ich8lan)
5688 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN;
5689 for(i = 0; i < num_mta_entry; i++) {
5690 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
5691 E1000_WRITE_FLUSH(hw);
5692 }
5693
5694 /* Add the new addresses */
5695 for(i = 0; i < mc_addr_count; i++) {
5696 DEBUGOUT(" Adding the multicast addresses:\n");
5697 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
5698 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
5699 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
5700 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
5701 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
5702 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
5703 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
5704
5705 hash_value = e1000_hash_mc_addr(hw,
5706 mc_addr_list +
5707 (i * (ETH_LENGTH_OF_ADDRESS + pad)));
5708
5709 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
5710
5711 /* Place this multicast address in the RAR if there is room, *
5712 * else put it in the MTA
5713 */
5714 if (rar_used_count < num_rar_entry) {
5715 e1000_rar_set(hw,
5716 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
5717 rar_used_count);
5718 rar_used_count++;
5719 } else {
5720 e1000_mta_set(hw, hash_value);
5721 }
5722 }
5723 DEBUGOUT("MC Update Complete\n");
5724 }
5725
5726 /******************************************************************************
5727 * Hashes an address to determine its location in the multicast table
5728 *
5729 * hw - Struct containing variables accessed by shared code
5730 * mc_addr - the multicast address to hash
5731 *****************************************************************************/
5732 uint32_t
5733 e1000_hash_mc_addr(struct e1000_hw *hw,
5734 uint8_t *mc_addr)
5735 {
5736 uint32_t hash_value = 0;
5737
5738 /* The portion of the address that is used for the hash table is
5739 * determined by the mc_filter_type setting.
5740 */
5741 switch (hw->mc_filter_type) {
5742 /* [0] [1] [2] [3] [4] [5]
5743 * 01 AA 00 12 34 56
5744 * LSB MSB
5745 */
5746 case 0:
5747 if (hw->mac_type == e1000_ich8lan) {
5748 /* [47:38] i.e. 0x158 for above example address */
5749 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2));
5750 } else {
5751 /* [47:36] i.e. 0x563 for above example address */
5752 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5753 }
5754 break;
5755 case 1:
5756 if (hw->mac_type == e1000_ich8lan) {
5757 /* [46:37] i.e. 0x2B1 for above example address */
5758 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3));
5759 } else {
5760 /* [46:35] i.e. 0xAC6 for above example address */
5761 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5762 }
5763 break;
5764 case 2:
5765 if (hw->mac_type == e1000_ich8lan) {
5766 /*[45:36] i.e. 0x163 for above example address */
5767 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5768 } else {
5769 /* [45:34] i.e. 0x5D8 for above example address */
5770 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5771 }
5772 break;
5773 case 3:
5774 if (hw->mac_type == e1000_ich8lan) {
5775 /* [43:34] i.e. 0x18D for above example address */
5776 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5777 } else {
5778 /* [43:32] i.e. 0x634 for above example address */
5779 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5780 }
5781 break;
5782 }
5783
5784 hash_value &= 0xFFF;
5785 if (hw->mac_type == e1000_ich8lan)
5786 hash_value &= 0x3FF;
5787
5788 return hash_value;
5789 }
5790
5791 /******************************************************************************
5792 * Sets the bit in the multicast table corresponding to the hash value.
5793 *
5794 * hw - Struct containing variables accessed by shared code
5795 * hash_value - Multicast address hash value
5796 *****************************************************************************/
5797 void
5798 e1000_mta_set(struct e1000_hw *hw,
5799 uint32_t hash_value)
5800 {
5801 uint32_t hash_bit, hash_reg;
5802 uint32_t mta;
5803 uint32_t temp;
5804
5805 /* The MTA is a register array of 128 32-bit registers.
5806 * It is treated like an array of 4096 bits. We want to set
5807 * bit BitArray[hash_value]. So we figure out what register
5808 * the bit is in, read it, OR in the new bit, then write
5809 * back the new value. The register is determined by the
5810 * upper 7 bits of the hash value and the bit within that
5811 * register are determined by the lower 5 bits of the value.
5812 */
5813 hash_reg = (hash_value >> 5) & 0x7F;
5814 if (hw->mac_type == e1000_ich8lan)
5815 hash_reg &= 0x1F;
5816 hash_bit = hash_value & 0x1F;
5817
5818 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
5819
5820 mta |= (1 << hash_bit);
5821
5822 /* If we are on an 82544 and we are trying to write an odd offset
5823 * in the MTA, save off the previous entry before writing and
5824 * restore the old value after writing.
5825 */
5826 if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
5827 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5828 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5829 E1000_WRITE_FLUSH(hw);
5830 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
5831 E1000_WRITE_FLUSH(hw);
5832 } else {
5833 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5834 E1000_WRITE_FLUSH(hw);
5835 }
5836 }
5837
5838 /******************************************************************************
5839 * Puts an ethernet address into a receive address register.
5840 *
5841 * hw - Struct containing variables accessed by shared code
5842 * addr - Address to put into receive address register
5843 * index - Receive address register to write
5844 *****************************************************************************/
5845 void
5846 e1000_rar_set(struct e1000_hw *hw,
5847 uint8_t *addr,
5848 uint32_t index)
5849 {
5850 uint32_t rar_low, rar_high;
5851
5852 /* HW expects these in little endian so we reverse the byte order
5853 * from network order (big endian) to little endian
5854 */
5855 rar_low = ((uint32_t) addr[0] |
5856 ((uint32_t) addr[1] << 8) |
5857 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
5858 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
5859
5860 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
5861 * unit hang.
5862 *
5863 * Description:
5864 * If there are any Rx frames queued up or otherwise present in the HW
5865 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
5866 * hang. To work around this issue, we have to disable receives and
5867 * flush out all Rx frames before we enable RSS. To do so, we modify we
5868 * redirect all Rx traffic to manageability and then reset the HW.
5869 * This flushes away Rx frames, and (since the redirections to
5870 * manageability persists across resets) keeps new ones from coming in
5871 * while we work. Then, we clear the Address Valid AV bit for all MAC
5872 * addresses and undo the re-direction to manageability.
5873 * Now, frames are coming in again, but the MAC won't accept them, so
5874 * far so good. We now proceed to initialize RSS (if necessary) and
5875 * configure the Rx unit. Last, we re-enable the AV bits and continue
5876 * on our merry way.
5877 */
5878 switch (hw->mac_type) {
5879 case e1000_82571:
5880 case e1000_82572:
5881 case e1000_80003es2lan:
5882 if (hw->leave_av_bit_off == TRUE)
5883 break;
5884 default:
5885 /* Indicate to hardware the Address is Valid. */
5886 rar_high |= E1000_RAH_AV;
5887 break;
5888 }
5889
5890 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
5891 E1000_WRITE_FLUSH(hw);
5892 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
5893 E1000_WRITE_FLUSH(hw);
5894 }
5895
5896 /******************************************************************************
5897 * Writes a value to the specified offset in the VLAN filter table.
5898 *
5899 * hw - Struct containing variables accessed by shared code
5900 * offset - Offset in VLAN filer table to write
5901 * value - Value to write into VLAN filter table
5902 *****************************************************************************/
5903 void
5904 e1000_write_vfta(struct e1000_hw *hw,
5905 uint32_t offset,
5906 uint32_t value)
5907 {
5908 uint32_t temp;
5909
5910 if (hw->mac_type == e1000_ich8lan)
5911 return;
5912
5913 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
5914 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5915 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5916 E1000_WRITE_FLUSH(hw);
5917 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
5918 E1000_WRITE_FLUSH(hw);
5919 } else {
5920 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5921 E1000_WRITE_FLUSH(hw);
5922 }
5923 }
5924
5925 /******************************************************************************
5926 * Clears the VLAN filer table
5927 *
5928 * hw - Struct containing variables accessed by shared code
5929 *****************************************************************************/
5930 static void
5931 e1000_clear_vfta(struct e1000_hw *hw)
5932 {
5933 uint32_t offset;
5934 uint32_t vfta_value = 0;
5935 uint32_t vfta_offset = 0;
5936 uint32_t vfta_bit_in_reg = 0;
5937
5938 if (hw->mac_type == e1000_ich8lan)
5939 return;
5940
5941 if (hw->mac_type == e1000_82573) {
5942 if (hw->mng_cookie.vlan_id != 0) {
5943 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
5944 * ID. The following operations determine which 32b entry
5945 * (i.e. offset) into the array we want to set the VLAN ID
5946 * (i.e. bit) of the manageability unit. */
5947 vfta_offset = (hw->mng_cookie.vlan_id >>
5948 E1000_VFTA_ENTRY_SHIFT) &
5949 E1000_VFTA_ENTRY_MASK;
5950 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
5951 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
5952 }
5953 }
5954 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
5955 /* If the offset we want to clear is the same offset of the
5956 * manageability VLAN ID, then clear all bits except that of the
5957 * manageability unit */
5958 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
5959 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
5960 E1000_WRITE_FLUSH(hw);
5961 }
5962 }
5963
5964 static int32_t
5965 e1000_id_led_init(struct e1000_hw * hw)
5966 {
5967 uint32_t ledctl;
5968 const uint32_t ledctl_mask = 0x000000FF;
5969 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
5970 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
5971 uint16_t eeprom_data, i, temp;
5972 const uint16_t led_mask = 0x0F;
5973
5974 DEBUGFUNC("e1000_id_led_init");
5975
5976 if(hw->mac_type < e1000_82540) {
5977 /* Nothing to do */
5978 return E1000_SUCCESS;
5979 }
5980
5981 ledctl = E1000_READ_REG(hw, LEDCTL);
5982 hw->ledctl_default = ledctl;
5983 hw->ledctl_mode1 = hw->ledctl_default;
5984 hw->ledctl_mode2 = hw->ledctl_default;
5985
5986 if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
5987 DEBUGOUT("EEPROM Read Error\n");
5988 return -E1000_ERR_EEPROM;
5989 }
5990
5991 if ((hw->mac_type == e1000_82573) &&
5992 (eeprom_data == ID_LED_RESERVED_82573))
5993 eeprom_data = ID_LED_DEFAULT_82573;
5994 else if ((eeprom_data == ID_LED_RESERVED_0000) ||
5995 (eeprom_data == ID_LED_RESERVED_FFFF)) {
5996 if (hw->mac_type == e1000_ich8lan)
5997 eeprom_data = ID_LED_DEFAULT_ICH8LAN;
5998 else
5999 eeprom_data = ID_LED_DEFAULT;
6000 }
6001 for (i = 0; i < 4; i++) {
6002 temp = (eeprom_data >> (i << 2)) & led_mask;
6003 switch(temp) {
6004 case ID_LED_ON1_DEF2:
6005 case ID_LED_ON1_ON2:
6006 case ID_LED_ON1_OFF2:
6007 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6008 hw->ledctl_mode1 |= ledctl_on << (i << 3);
6009 break;
6010 case ID_LED_OFF1_DEF2:
6011 case ID_LED_OFF1_ON2:
6012 case ID_LED_OFF1_OFF2:
6013 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6014 hw->ledctl_mode1 |= ledctl_off << (i << 3);
6015 break;
6016 default:
6017 /* Do nothing */
6018 break;
6019 }
6020 switch(temp) {
6021 case ID_LED_DEF1_ON2:
6022 case ID_LED_ON1_ON2:
6023 case ID_LED_OFF1_ON2:
6024 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6025 hw->ledctl_mode2 |= ledctl_on << (i << 3);
6026 break;
6027 case ID_LED_DEF1_OFF2:
6028 case ID_LED_ON1_OFF2:
6029 case ID_LED_OFF1_OFF2:
6030 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6031 hw->ledctl_mode2 |= ledctl_off << (i << 3);
6032 break;
6033 default:
6034 /* Do nothing */
6035 break;
6036 }
6037 }
6038 return E1000_SUCCESS;
6039 }
6040
6041 /******************************************************************************
6042 * Prepares SW controlable LED for use and saves the current state of the LED.
6043 *
6044 * hw - Struct containing variables accessed by shared code
6045 *****************************************************************************/
6046 int32_t
6047 e1000_setup_led(struct e1000_hw *hw)
6048 {
6049 uint32_t ledctl;
6050 int32_t ret_val = E1000_SUCCESS;
6051
6052 DEBUGFUNC("e1000_setup_led");
6053
6054 switch(hw->mac_type) {
6055 case e1000_82542_rev2_0:
6056 case e1000_82542_rev2_1:
6057 case e1000_82543:
6058 case e1000_82544:
6059 /* No setup necessary */
6060 break;
6061 case e1000_82541:
6062 case e1000_82547:
6063 case e1000_82541_rev_2:
6064 case e1000_82547_rev_2:
6065 /* Turn off PHY Smart Power Down (if enabled) */
6066 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
6067 &hw->phy_spd_default);
6068 if(ret_val)
6069 return ret_val;
6070 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6071 (uint16_t)(hw->phy_spd_default &
6072 ~IGP01E1000_GMII_SPD));
6073 if(ret_val)
6074 return ret_val;
6075 /* Fall Through */
6076 default:
6077 if(hw->media_type == e1000_media_type_fiber) {
6078 ledctl = E1000_READ_REG(hw, LEDCTL);
6079 /* Save current LEDCTL settings */
6080 hw->ledctl_default = ledctl;
6081 /* Turn off LED0 */
6082 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
6083 E1000_LEDCTL_LED0_BLINK |
6084 E1000_LEDCTL_LED0_MODE_MASK);
6085 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6086 E1000_LEDCTL_LED0_MODE_SHIFT);
6087 E1000_WRITE_REG(hw, LEDCTL, ledctl);
6088 } else if(hw->media_type == e1000_media_type_copper)
6089 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6090 break;
6091 }
6092
6093 return E1000_SUCCESS;
6094 }
6095
6096 /******************************************************************************
6097 * Used on 82571 and later Si that has LED blink bits.
6098 * Callers must use their own timer and should have already called
6099 * e1000_id_led_init()
6100 * Call e1000_cleanup led() to stop blinking
6101 *
6102 * hw - Struct containing variables accessed by shared code
6103 *****************************************************************************/
6104 int32_t
6105 e1000_blink_led_start(struct e1000_hw *hw)
6106 {
6107 int16_t i;
6108 uint32_t ledctl_blink = 0;
6109
6110 DEBUGFUNC("e1000_id_led_blink_on");
6111
6112 if (hw->mac_type < e1000_82571) {
6113 /* Nothing to do */
6114 return E1000_SUCCESS;
6115 }
6116 if (hw->media_type == e1000_media_type_fiber) {
6117 /* always blink LED0 for PCI-E fiber */
6118 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
6119 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6120 } else {
6121 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
6122 ledctl_blink = hw->ledctl_mode2;
6123 for (i=0; i < 4; i++)
6124 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6125 E1000_LEDCTL_MODE_LED_ON)
6126 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6127 }
6128
6129 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink);
6130
6131 return E1000_SUCCESS;
6132 }
6133
6134 /******************************************************************************
6135 * Restores the saved state of the SW controlable LED.
6136 *
6137 * hw - Struct containing variables accessed by shared code
6138 *****************************************************************************/
6139 int32_t
6140 e1000_cleanup_led(struct e1000_hw *hw)
6141 {
6142 int32_t ret_val = E1000_SUCCESS;
6143
6144 DEBUGFUNC("e1000_cleanup_led");
6145
6146 switch(hw->mac_type) {
6147 case e1000_82542_rev2_0:
6148 case e1000_82542_rev2_1:
6149 case e1000_82543:
6150 case e1000_82544:
6151 /* No cleanup necessary */
6152 break;
6153 case e1000_82541:
6154 case e1000_82547:
6155 case e1000_82541_rev_2:
6156 case e1000_82547_rev_2:
6157 /* Turn on PHY Smart Power Down (if previously enabled) */
6158 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6159 hw->phy_spd_default);
6160 if(ret_val)
6161 return ret_val;
6162 /* Fall Through */
6163 default:
6164 if (hw->phy_type == e1000_phy_ife) {
6165 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6166 break;
6167 }
6168 /* Restore LEDCTL settings */
6169 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
6170 break;
6171 }
6172
6173 return E1000_SUCCESS;
6174 }
6175
6176 /******************************************************************************
6177 * Turns on the software controllable LED
6178 *
6179 * hw - Struct containing variables accessed by shared code
6180 *****************************************************************************/
6181 int32_t
6182 e1000_led_on(struct e1000_hw *hw)
6183 {
6184 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6185
6186 DEBUGFUNC("e1000_led_on");
6187
6188 switch(hw->mac_type) {
6189 case e1000_82542_rev2_0:
6190 case e1000_82542_rev2_1:
6191 case e1000_82543:
6192 /* Set SW Defineable Pin 0 to turn on the LED */
6193 ctrl |= E1000_CTRL_SWDPIN0;
6194 ctrl |= E1000_CTRL_SWDPIO0;
6195 break;
6196 case e1000_82544:
6197 if(hw->media_type == e1000_media_type_fiber) {
6198 /* Set SW Defineable Pin 0 to turn on the LED */
6199 ctrl |= E1000_CTRL_SWDPIN0;
6200 ctrl |= E1000_CTRL_SWDPIO0;
6201 } else {
6202 /* Clear SW Defineable Pin 0 to turn on the LED */
6203 ctrl &= ~E1000_CTRL_SWDPIN0;
6204 ctrl |= E1000_CTRL_SWDPIO0;
6205 }
6206 break;
6207 default:
6208 if(hw->media_type == e1000_media_type_fiber) {
6209 /* Clear SW Defineable Pin 0 to turn on the LED */
6210 ctrl &= ~E1000_CTRL_SWDPIN0;
6211 ctrl |= E1000_CTRL_SWDPIO0;
6212 } else if (hw->phy_type == e1000_phy_ife) {
6213 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6214 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6215 } else if (hw->media_type == e1000_media_type_copper) {
6216 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
6217 return E1000_SUCCESS;
6218 }
6219 break;
6220 }
6221
6222 E1000_WRITE_REG(hw, CTRL, ctrl);
6223
6224 return E1000_SUCCESS;
6225 }
6226
6227 /******************************************************************************
6228 * Turns off the software controllable LED
6229 *
6230 * hw - Struct containing variables accessed by shared code
6231 *****************************************************************************/
6232 int32_t
6233 e1000_led_off(struct e1000_hw *hw)
6234 {
6235 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6236
6237 DEBUGFUNC("e1000_led_off");
6238
6239 switch(hw->mac_type) {
6240 case e1000_82542_rev2_0:
6241 case e1000_82542_rev2_1:
6242 case e1000_82543:
6243 /* Clear SW Defineable Pin 0 to turn off the LED */
6244 ctrl &= ~E1000_CTRL_SWDPIN0;
6245 ctrl |= E1000_CTRL_SWDPIO0;
6246 break;
6247 case e1000_82544:
6248 if(hw->media_type == e1000_media_type_fiber) {
6249 /* Clear SW Defineable Pin 0 to turn off the LED */
6250 ctrl &= ~E1000_CTRL_SWDPIN0;
6251 ctrl |= E1000_CTRL_SWDPIO0;
6252 } else {
6253 /* Set SW Defineable Pin 0 to turn off the LED */
6254 ctrl |= E1000_CTRL_SWDPIN0;
6255 ctrl |= E1000_CTRL_SWDPIO0;
6256 }
6257 break;
6258 default:
6259 if(hw->media_type == e1000_media_type_fiber) {
6260 /* Set SW Defineable Pin 0 to turn off the LED */
6261 ctrl |= E1000_CTRL_SWDPIN0;
6262 ctrl |= E1000_CTRL_SWDPIO0;
6263 } else if (hw->phy_type == e1000_phy_ife) {
6264 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6265 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6266 } else if (hw->media_type == e1000_media_type_copper) {
6267 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6268 return E1000_SUCCESS;
6269 }
6270 break;
6271 }
6272
6273 E1000_WRITE_REG(hw, CTRL, ctrl);
6274
6275 return E1000_SUCCESS;
6276 }
6277
6278 /******************************************************************************
6279 * Clears all hardware statistics counters.
6280 *
6281 * hw - Struct containing variables accessed by shared code
6282 *****************************************************************************/
6283 static void
6284 e1000_clear_hw_cntrs(struct e1000_hw *hw)
6285 {
6286 volatile uint32_t temp;
6287
6288 temp = E1000_READ_REG(hw, CRCERRS);
6289 temp = E1000_READ_REG(hw, SYMERRS);
6290 temp = E1000_READ_REG(hw, MPC);
6291 temp = E1000_READ_REG(hw, SCC);
6292 temp = E1000_READ_REG(hw, ECOL);
6293 temp = E1000_READ_REG(hw, MCC);
6294 temp = E1000_READ_REG(hw, LATECOL);
6295 temp = E1000_READ_REG(hw, COLC);
6296 temp = E1000_READ_REG(hw, DC);
6297 temp = E1000_READ_REG(hw, SEC);
6298 temp = E1000_READ_REG(hw, RLEC);
6299 temp = E1000_READ_REG(hw, XONRXC);
6300 temp = E1000_READ_REG(hw, XONTXC);
6301 temp = E1000_READ_REG(hw, XOFFRXC);
6302 temp = E1000_READ_REG(hw, XOFFTXC);
6303 temp = E1000_READ_REG(hw, FCRUC);
6304
6305 if (hw->mac_type != e1000_ich8lan) {
6306 temp = E1000_READ_REG(hw, PRC64);
6307 temp = E1000_READ_REG(hw, PRC127);
6308 temp = E1000_READ_REG(hw, PRC255);
6309 temp = E1000_READ_REG(hw, PRC511);
6310 temp = E1000_READ_REG(hw, PRC1023);
6311 temp = E1000_READ_REG(hw, PRC1522);
6312 }
6313
6314 temp = E1000_READ_REG(hw, GPRC);
6315 temp = E1000_READ_REG(hw, BPRC);
6316 temp = E1000_READ_REG(hw, MPRC);
6317 temp = E1000_READ_REG(hw, GPTC);
6318 temp = E1000_READ_REG(hw, GORCL);
6319 temp = E1000_READ_REG(hw, GORCH);
6320 temp = E1000_READ_REG(hw, GOTCL);
6321 temp = E1000_READ_REG(hw, GOTCH);
6322 temp = E1000_READ_REG(hw, RNBC);
6323 temp = E1000_READ_REG(hw, RUC);
6324 temp = E1000_READ_REG(hw, RFC);
6325 temp = E1000_READ_REG(hw, ROC);
6326 temp = E1000_READ_REG(hw, RJC);
6327 temp = E1000_READ_REG(hw, TORL);
6328 temp = E1000_READ_REG(hw, TORH);
6329 temp = E1000_READ_REG(hw, TOTL);
6330 temp = E1000_READ_REG(hw, TOTH);
6331 temp = E1000_READ_REG(hw, TPR);
6332 temp = E1000_READ_REG(hw, TPT);
6333
6334 if (hw->mac_type != e1000_ich8lan) {
6335 temp = E1000_READ_REG(hw, PTC64);
6336 temp = E1000_READ_REG(hw, PTC127);
6337 temp = E1000_READ_REG(hw, PTC255);
6338 temp = E1000_READ_REG(hw, PTC511);
6339 temp = E1000_READ_REG(hw, PTC1023);
6340 temp = E1000_READ_REG(hw, PTC1522);
6341 }
6342
6343 temp = E1000_READ_REG(hw, MPTC);
6344 temp = E1000_READ_REG(hw, BPTC);
6345
6346 if(hw->mac_type < e1000_82543) return;
6347
6348 temp = E1000_READ_REG(hw, ALGNERRC);
6349 temp = E1000_READ_REG(hw, RXERRC);
6350 temp = E1000_READ_REG(hw, TNCRS);
6351 temp = E1000_READ_REG(hw, CEXTERR);
6352 temp = E1000_READ_REG(hw, TSCTC);
6353 temp = E1000_READ_REG(hw, TSCTFC);
6354
6355 if(hw->mac_type <= e1000_82544) return;
6356
6357 temp = E1000_READ_REG(hw, MGTPRC);
6358 temp = E1000_READ_REG(hw, MGTPDC);
6359 temp = E1000_READ_REG(hw, MGTPTC);
6360
6361 if(hw->mac_type <= e1000_82547_rev_2) return;
6362
6363 temp = E1000_READ_REG(hw, IAC);
6364 temp = E1000_READ_REG(hw, ICRXOC);
6365
6366 if (hw->mac_type == e1000_ich8lan) return;
6367
6368 temp = E1000_READ_REG(hw, ICRXPTC);
6369 temp = E1000_READ_REG(hw, ICRXATC);
6370 temp = E1000_READ_REG(hw, ICTXPTC);
6371 temp = E1000_READ_REG(hw, ICTXATC);
6372 temp = E1000_READ_REG(hw, ICTXQEC);
6373 temp = E1000_READ_REG(hw, ICTXQMTC);
6374 temp = E1000_READ_REG(hw, ICRXDMTC);
6375 }
6376
6377 /******************************************************************************
6378 * Resets Adaptive IFS to its default state.
6379 *
6380 * hw - Struct containing variables accessed by shared code
6381 *
6382 * Call this after e1000_init_hw. You may override the IFS defaults by setting
6383 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
6384 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
6385 * before calling this function.
6386 *****************************************************************************/
6387 void
6388 e1000_reset_adaptive(struct e1000_hw *hw)
6389 {
6390 DEBUGFUNC("e1000_reset_adaptive");
6391
6392 if(hw->adaptive_ifs) {
6393 if(!hw->ifs_params_forced) {
6394 hw->current_ifs_val = 0;
6395 hw->ifs_min_val = IFS_MIN;
6396 hw->ifs_max_val = IFS_MAX;
6397 hw->ifs_step_size = IFS_STEP;
6398 hw->ifs_ratio = IFS_RATIO;
6399 }
6400 hw->in_ifs_mode = FALSE;
6401 E1000_WRITE_REG(hw, AIT, 0);
6402 } else {
6403 DEBUGOUT("Not in Adaptive IFS mode!\n");
6404 }
6405 }
6406
6407 /******************************************************************************
6408 * Called during the callback/watchdog routine to update IFS value based on
6409 * the ratio of transmits to collisions.
6410 *
6411 * hw - Struct containing variables accessed by shared code
6412 * tx_packets - Number of transmits since last callback
6413 * total_collisions - Number of collisions since last callback
6414 *****************************************************************************/
6415 void
6416 e1000_update_adaptive(struct e1000_hw *hw)
6417 {
6418 DEBUGFUNC("e1000_update_adaptive");
6419
6420 if(hw->adaptive_ifs) {
6421 if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
6422 if(hw->tx_packet_delta > MIN_NUM_XMITS) {
6423 hw->in_ifs_mode = TRUE;
6424 if(hw->current_ifs_val < hw->ifs_max_val) {
6425 if(hw->current_ifs_val == 0)
6426 hw->current_ifs_val = hw->ifs_min_val;
6427 else
6428 hw->current_ifs_val += hw->ifs_step_size;
6429 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
6430 }
6431 }
6432 } else {
6433 if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
6434 hw->current_ifs_val = 0;
6435 hw->in_ifs_mode = FALSE;
6436 E1000_WRITE_REG(hw, AIT, 0);
6437 }
6438 }
6439 } else {
6440 DEBUGOUT("Not in Adaptive IFS mode!\n");
6441 }
6442 }
6443
6444 /******************************************************************************
6445 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
6446 *
6447 * hw - Struct containing variables accessed by shared code
6448 * frame_len - The length of the frame in question
6449 * mac_addr - The Ethernet destination address of the frame in question
6450 *****************************************************************************/
6451 void
6452 e1000_tbi_adjust_stats(struct e1000_hw *hw,
6453 struct e1000_hw_stats *stats,
6454 uint32_t frame_len,
6455 uint8_t *mac_addr)
6456 {
6457 uint64_t carry_bit;
6458
6459 /* First adjust the frame length. */
6460 frame_len--;
6461 /* We need to adjust the statistics counters, since the hardware
6462 * counters overcount this packet as a CRC error and undercount
6463 * the packet as a good packet
6464 */
6465 /* This packet should not be counted as a CRC error. */
6466 stats->crcerrs--;
6467 /* This packet does count as a Good Packet Received. */
6468 stats->gprc++;
6469
6470 /* Adjust the Good Octets received counters */
6471 carry_bit = 0x80000000 & stats->gorcl;
6472 stats->gorcl += frame_len;
6473 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
6474 * Received Count) was one before the addition,
6475 * AND it is zero after, then we lost the carry out,
6476 * need to add one to Gorch (Good Octets Received Count High).
6477 * This could be simplified if all environments supported
6478 * 64-bit integers.
6479 */
6480 if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
6481 stats->gorch++;
6482 /* Is this a broadcast or multicast? Check broadcast first,
6483 * since the test for a multicast frame will test positive on
6484 * a broadcast frame.
6485 */
6486 if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
6487 /* Broadcast packet */
6488 stats->bprc++;
6489 else if(*mac_addr & 0x01)
6490 /* Multicast packet */
6491 stats->mprc++;
6492
6493 if(frame_len == hw->max_frame_size) {
6494 /* In this case, the hardware has overcounted the number of
6495 * oversize frames.
6496 */
6497 if(stats->roc > 0)
6498 stats->roc--;
6499 }
6500
6501 /* Adjust the bin counters when the extra byte put the frame in the
6502 * wrong bin. Remember that the frame_len was adjusted above.
6503 */
6504 if(frame_len == 64) {
6505 stats->prc64++;
6506 stats->prc127--;
6507 } else if(frame_len == 127) {
6508 stats->prc127++;
6509 stats->prc255--;
6510 } else if(frame_len == 255) {
6511 stats->prc255++;
6512 stats->prc511--;
6513 } else if(frame_len == 511) {
6514 stats->prc511++;
6515 stats->prc1023--;
6516 } else if(frame_len == 1023) {
6517 stats->prc1023++;
6518 stats->prc1522--;
6519 } else if(frame_len == 1522) {
6520 stats->prc1522++;
6521 }
6522 }
6523
6524 /******************************************************************************
6525 * Gets the current PCI bus type, speed, and width of the hardware
6526 *
6527 * hw - Struct containing variables accessed by shared code
6528 *****************************************************************************/
6529 void
6530 e1000_get_bus_info(struct e1000_hw *hw)
6531 {
6532 uint32_t status;
6533
6534 switch (hw->mac_type) {
6535 case e1000_82542_rev2_0:
6536 case e1000_82542_rev2_1:
6537 hw->bus_type = e1000_bus_type_unknown;
6538 hw->bus_speed = e1000_bus_speed_unknown;
6539 hw->bus_width = e1000_bus_width_unknown;
6540 break;
6541 case e1000_82572:
6542 case e1000_82573:
6543 hw->bus_type = e1000_bus_type_pci_express;
6544 hw->bus_speed = e1000_bus_speed_2500;
6545 hw->bus_width = e1000_bus_width_pciex_1;
6546 break;
6547 case e1000_82571:
6548 case e1000_ich8lan:
6549 case e1000_80003es2lan:
6550 hw->bus_type = e1000_bus_type_pci_express;
6551 hw->bus_speed = e1000_bus_speed_2500;
6552 hw->bus_width = e1000_bus_width_pciex_4;
6553 break;
6554 default:
6555 status = E1000_READ_REG(hw, STATUS);
6556 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6557 e1000_bus_type_pcix : e1000_bus_type_pci;
6558
6559 if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
6560 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
6561 e1000_bus_speed_66 : e1000_bus_speed_120;
6562 } else if(hw->bus_type == e1000_bus_type_pci) {
6563 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6564 e1000_bus_speed_66 : e1000_bus_speed_33;
6565 } else {
6566 switch (status & E1000_STATUS_PCIX_SPEED) {
6567 case E1000_STATUS_PCIX_SPEED_66:
6568 hw->bus_speed = e1000_bus_speed_66;
6569 break;
6570 case E1000_STATUS_PCIX_SPEED_100:
6571 hw->bus_speed = e1000_bus_speed_100;
6572 break;
6573 case E1000_STATUS_PCIX_SPEED_133:
6574 hw->bus_speed = e1000_bus_speed_133;
6575 break;
6576 default:
6577 hw->bus_speed = e1000_bus_speed_reserved;
6578 break;
6579 }
6580 }
6581 hw->bus_width = (status & E1000_STATUS_BUS64) ?
6582 e1000_bus_width_64 : e1000_bus_width_32;
6583 break;
6584 }
6585 }
6586 /******************************************************************************
6587 * Reads a value from one of the devices registers using port I/O (as opposed
6588 * memory mapped I/O). Only 82544 and newer devices support port I/O.
6589 *
6590 * hw - Struct containing variables accessed by shared code
6591 * offset - offset to read from
6592 *****************************************************************************/
6593 uint32_t
6594 e1000_read_reg_io(struct e1000_hw *hw,
6595 uint32_t offset)
6596 {
6597 unsigned long io_addr = hw->io_base;
6598 unsigned long io_data = hw->io_base + 4;
6599
6600 e1000_io_write(hw, io_addr, offset);
6601 return e1000_io_read(hw, io_data);
6602 }
6603
6604 /******************************************************************************
6605 * Writes a value to one of the devices registers using port I/O (as opposed to
6606 * memory mapped I/O). Only 82544 and newer devices support port I/O.
6607 *
6608 * hw - Struct containing variables accessed by shared code
6609 * offset - offset to write to
6610 * value - value to write
6611 *****************************************************************************/
6612 static void
6613 e1000_write_reg_io(struct e1000_hw *hw,
6614 uint32_t offset,
6615 uint32_t value)
6616 {
6617 unsigned long io_addr = hw->io_base;
6618 unsigned long io_data = hw->io_base + 4;
6619
6620 e1000_io_write(hw, io_addr, offset);
6621 e1000_io_write(hw, io_data, value);
6622 }
6623
6624
6625 /******************************************************************************
6626 * Estimates the cable length.
6627 *
6628 * hw - Struct containing variables accessed by shared code
6629 * min_length - The estimated minimum length
6630 * max_length - The estimated maximum length
6631 *
6632 * returns: - E1000_ERR_XXX
6633 * E1000_SUCCESS
6634 *
6635 * This function always returns a ranged length (minimum & maximum).
6636 * So for M88 phy's, this function interprets the one value returned from the
6637 * register to the minimum and maximum range.
6638 * For IGP phy's, the function calculates the range by the AGC registers.
6639 *****************************************************************************/
6640 static int32_t
6641 e1000_get_cable_length(struct e1000_hw *hw,
6642 uint16_t *min_length,
6643 uint16_t *max_length)
6644 {
6645 int32_t ret_val;
6646 uint16_t agc_value = 0;
6647 uint16_t i, phy_data;
6648 uint16_t cable_length;
6649
6650 DEBUGFUNC("e1000_get_cable_length");
6651
6652 *min_length = *max_length = 0;
6653
6654 /* Use old method for Phy older than IGP */
6655 if(hw->phy_type == e1000_phy_m88) {
6656
6657 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6658 &phy_data);
6659 if(ret_val)
6660 return ret_val;
6661 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6662 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
6663
6664 /* Convert the enum value to ranged values */
6665 switch (cable_length) {
6666 case e1000_cable_length_50:
6667 *min_length = 0;
6668 *max_length = e1000_igp_cable_length_50;
6669 break;
6670 case e1000_cable_length_50_80:
6671 *min_length = e1000_igp_cable_length_50;
6672 *max_length = e1000_igp_cable_length_80;
6673 break;
6674 case e1000_cable_length_80_110:
6675 *min_length = e1000_igp_cable_length_80;
6676 *max_length = e1000_igp_cable_length_110;
6677 break;
6678 case e1000_cable_length_110_140:
6679 *min_length = e1000_igp_cable_length_110;
6680 *max_length = e1000_igp_cable_length_140;
6681 break;
6682 case e1000_cable_length_140:
6683 *min_length = e1000_igp_cable_length_140;
6684 *max_length = e1000_igp_cable_length_170;
6685 break;
6686 default:
6687 return -E1000_ERR_PHY;
6688 break;
6689 }
6690 } else if (hw->phy_type == e1000_phy_gg82563) {
6691 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
6692 &phy_data);
6693 if (ret_val)
6694 return ret_val;
6695 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
6696
6697 switch (cable_length) {
6698 case e1000_gg_cable_length_60:
6699 *min_length = 0;
6700 *max_length = e1000_igp_cable_length_60;
6701 break;
6702 case e1000_gg_cable_length_60_115:
6703 *min_length = e1000_igp_cable_length_60;
6704 *max_length = e1000_igp_cable_length_115;
6705 break;
6706 case e1000_gg_cable_length_115_150:
6707 *min_length = e1000_igp_cable_length_115;
6708 *max_length = e1000_igp_cable_length_150;
6709 break;
6710 case e1000_gg_cable_length_150:
6711 *min_length = e1000_igp_cable_length_150;
6712 *max_length = e1000_igp_cable_length_180;
6713 break;
6714 default:
6715 return -E1000_ERR_PHY;
6716 break;
6717 }
6718 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6719 uint16_t cur_agc_value;
6720 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6721 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6722 {IGP01E1000_PHY_AGC_A,
6723 IGP01E1000_PHY_AGC_B,
6724 IGP01E1000_PHY_AGC_C,
6725 IGP01E1000_PHY_AGC_D};
6726 /* Read the AGC registers for all channels */
6727 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6728
6729 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6730 if(ret_val)
6731 return ret_val;
6732
6733 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
6734
6735 /* Value bound check. */
6736 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6737 (cur_agc_value == 0))
6738 return -E1000_ERR_PHY;
6739
6740 agc_value += cur_agc_value;
6741
6742 /* Update minimal AGC value. */
6743 if (min_agc_value > cur_agc_value)
6744 min_agc_value = cur_agc_value;
6745 }
6746
6747 /* Remove the minimal AGC result for length < 50m */
6748 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6749 agc_value -= min_agc_value;
6750
6751 /* Get the average length of the remaining 3 channels */
6752 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
6753 } else {
6754 /* Get the average length of all the 4 channels. */
6755 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
6756 }
6757
6758 /* Set the range of the calculated length. */
6759 *min_length = ((e1000_igp_cable_length_table[agc_value] -
6760 IGP01E1000_AGC_RANGE) > 0) ?
6761 (e1000_igp_cable_length_table[agc_value] -
6762 IGP01E1000_AGC_RANGE) : 0;
6763 *max_length = e1000_igp_cable_length_table[agc_value] +
6764 IGP01E1000_AGC_RANGE;
6765 } else if (hw->phy_type == e1000_phy_igp_2 ||
6766 hw->phy_type == e1000_phy_igp_3) {
6767 uint16_t cur_agc_index, max_agc_index = 0;
6768 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6769 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6770 {IGP02E1000_PHY_AGC_A,
6771 IGP02E1000_PHY_AGC_B,
6772 IGP02E1000_PHY_AGC_C,
6773 IGP02E1000_PHY_AGC_D};
6774 /* Read the AGC registers for all channels */
6775 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
6776 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6777 if (ret_val)
6778 return ret_val;
6779
6780 /* Getting bits 15:9, which represent the combination of course and
6781 * fine gain values. The result is a number that can be put into
6782 * the lookup table to obtain the approximate cable length. */
6783 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6784 IGP02E1000_AGC_LENGTH_MASK;
6785
6786 /* Array index bound check. */
6787 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6788 (cur_agc_index == 0))
6789 return -E1000_ERR_PHY;
6790
6791 /* Remove min & max AGC values from calculation. */
6792 if (e1000_igp_2_cable_length_table[min_agc_index] >
6793 e1000_igp_2_cable_length_table[cur_agc_index])
6794 min_agc_index = cur_agc_index;
6795 if (e1000_igp_2_cable_length_table[max_agc_index] <
6796 e1000_igp_2_cable_length_table[cur_agc_index])
6797 max_agc_index = cur_agc_index;
6798
6799 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
6800 }
6801
6802 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6803 e1000_igp_2_cable_length_table[max_agc_index]);
6804 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6805
6806 /* Calculate cable length with the error range of +/- 10 meters. */
6807 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
6808 (agc_value - IGP02E1000_AGC_RANGE) : 0;
6809 *max_length = agc_value + IGP02E1000_AGC_RANGE;
6810 }
6811
6812 return E1000_SUCCESS;
6813 }
6814
6815 /******************************************************************************
6816 * Check the cable polarity
6817 *
6818 * hw - Struct containing variables accessed by shared code
6819 * polarity - output parameter : 0 - Polarity is not reversed
6820 * 1 - Polarity is reversed.
6821 *
6822 * returns: - E1000_ERR_XXX
6823 * E1000_SUCCESS
6824 *
6825 * For phy's older then IGP, this function simply reads the polarity bit in the
6826 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
6827 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
6828 * return 0. If the link speed is 1000 Mbps the polarity status is in the
6829 * IGP01E1000_PHY_PCS_INIT_REG.
6830 *****************************************************************************/
6831 static int32_t
6832 e1000_check_polarity(struct e1000_hw *hw,
6833 uint16_t *polarity)
6834 {
6835 int32_t ret_val;
6836 uint16_t phy_data;
6837
6838 DEBUGFUNC("e1000_check_polarity");
6839
6840 if ((hw->phy_type == e1000_phy_m88) ||
6841 (hw->phy_type == e1000_phy_gg82563)) {
6842 /* return the Polarity bit in the Status register. */
6843 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6844 &phy_data);
6845 if(ret_val)
6846 return ret_val;
6847 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
6848 M88E1000_PSSR_REV_POLARITY_SHIFT;
6849 } else if (hw->phy_type == e1000_phy_igp ||
6850 hw->phy_type == e1000_phy_igp_3 ||
6851 hw->phy_type == e1000_phy_igp_2) {
6852 /* Read the Status register to check the speed */
6853 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
6854 &phy_data);
6855 if(ret_val)
6856 return ret_val;
6857
6858 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
6859 * find the polarity status */
6860 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
6861 IGP01E1000_PSSR_SPEED_1000MBPS) {
6862
6863 /* Read the GIG initialization PCS register (0x00B4) */
6864 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
6865 &phy_data);
6866 if(ret_val)
6867 return ret_val;
6868
6869 /* Check the polarity bits */
6870 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0;
6871 } else {
6872 /* For 10 Mbps, read the polarity bit in the status register. (for
6873 * 100 Mbps this bit is always 0) */
6874 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
6875 }
6876 } else if (hw->phy_type == e1000_phy_ife) {
6877 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
6878 &phy_data);
6879 if (ret_val)
6880 return ret_val;
6881 *polarity = (phy_data & IFE_PESC_POLARITY_REVERSED) >>
6882 IFE_PESC_POLARITY_REVERSED_SHIFT;
6883 }
6884 return E1000_SUCCESS;
6885 }
6886
6887 /******************************************************************************
6888 * Check if Downshift occured
6889 *
6890 * hw - Struct containing variables accessed by shared code
6891 * downshift - output parameter : 0 - No Downshift ocured.
6892 * 1 - Downshift ocured.
6893 *
6894 * returns: - E1000_ERR_XXX
6895 * E1000_SUCCESS
6896 *
6897 * For phy's older then IGP, this function reads the Downshift bit in the Phy
6898 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
6899 * Link Health register. In IGP this bit is latched high, so the driver must
6900 * read it immediately after link is established.
6901 *****************************************************************************/
6902 static int32_t
6903 e1000_check_downshift(struct e1000_hw *hw)
6904 {
6905 int32_t ret_val;
6906 uint16_t phy_data;
6907
6908 DEBUGFUNC("e1000_check_downshift");
6909
6910 if (hw->phy_type == e1000_phy_igp ||
6911 hw->phy_type == e1000_phy_igp_3 ||
6912 hw->phy_type == e1000_phy_igp_2) {
6913 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6914 &phy_data);
6915 if(ret_val)
6916 return ret_val;
6917
6918 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
6919 } else if ((hw->phy_type == e1000_phy_m88) ||
6920 (hw->phy_type == e1000_phy_gg82563)) {
6921 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6922 &phy_data);
6923 if(ret_val)
6924 return ret_val;
6925
6926 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6927 M88E1000_PSSR_DOWNSHIFT_SHIFT;
6928 } else if (hw->phy_type == e1000_phy_ife) {
6929 /* e1000_phy_ife supports 10/100 speed only */
6930 hw->speed_downgraded = FALSE;
6931 }
6932
6933 return E1000_SUCCESS;
6934 }
6935
6936 /*****************************************************************************
6937 *
6938 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
6939 * gigabit link is achieved to improve link quality.
6940 *
6941 * hw: Struct containing variables accessed by shared code
6942 *
6943 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6944 * E1000_SUCCESS at any other case.
6945 *
6946 ****************************************************************************/
6947
6948 static int32_t
6949 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
6950 boolean_t link_up)
6951 {
6952 int32_t ret_val;
6953 uint16_t phy_data, phy_saved_data, speed, duplex, i;
6954 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6955 {IGP01E1000_PHY_AGC_PARAM_A,
6956 IGP01E1000_PHY_AGC_PARAM_B,
6957 IGP01E1000_PHY_AGC_PARAM_C,
6958 IGP01E1000_PHY_AGC_PARAM_D};
6959 uint16_t min_length, max_length;
6960
6961 DEBUGFUNC("e1000_config_dsp_after_link_change");
6962
6963 if(hw->phy_type != e1000_phy_igp)
6964 return E1000_SUCCESS;
6965
6966 if(link_up) {
6967 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
6968 if(ret_val) {
6969 DEBUGOUT("Error getting link speed and duplex\n");
6970 return ret_val;
6971 }
6972
6973 if(speed == SPEED_1000) {
6974
6975 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
6976 if (ret_val)
6977 return ret_val;
6978
6979 if((hw->dsp_config_state == e1000_dsp_config_enabled) &&
6980 min_length >= e1000_igp_cable_length_50) {
6981
6982 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6983 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
6984 &phy_data);
6985 if(ret_val)
6986 return ret_val;
6987
6988 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
6989
6990 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
6991 phy_data);
6992 if(ret_val)
6993 return ret_val;
6994 }
6995 hw->dsp_config_state = e1000_dsp_config_activated;
6996 }
6997
6998 if((hw->ffe_config_state == e1000_ffe_config_enabled) &&
6999 (min_length < e1000_igp_cable_length_50)) {
7000
7001 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
7002 uint32_t idle_errs = 0;
7003
7004 /* clear previous idle error counts */
7005 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7006 &phy_data);
7007 if(ret_val)
7008 return ret_val;
7009
7010 for(i = 0; i < ffe_idle_err_timeout; i++) {
7011 udelay(1000);
7012 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7013 &phy_data);
7014 if(ret_val)
7015 return ret_val;
7016
7017 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
7018 if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
7019 hw->ffe_config_state = e1000_ffe_config_active;
7020
7021 ret_val = e1000_write_phy_reg(hw,
7022 IGP01E1000_PHY_DSP_FFE,
7023 IGP01E1000_PHY_DSP_FFE_CM_CP);
7024 if(ret_val)
7025 return ret_val;
7026 break;
7027 }
7028
7029 if(idle_errs)
7030 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
7031 }
7032 }
7033 }
7034 } else {
7035 if(hw->dsp_config_state == e1000_dsp_config_activated) {
7036 /* Save off the current value of register 0x2F5B to be restored at
7037 * the end of the routines. */
7038 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7039
7040 if(ret_val)
7041 return ret_val;
7042
7043 /* Disable the PHY transmitter */
7044 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7045
7046 if(ret_val)
7047 return ret_val;
7048
7049 msec_delay_irq(20);
7050
7051 ret_val = e1000_write_phy_reg(hw, 0x0000,
7052 IGP01E1000_IEEE_FORCE_GIGA);
7053 if(ret_val)
7054 return ret_val;
7055 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7056 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
7057 if(ret_val)
7058 return ret_val;
7059
7060 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7061 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
7062
7063 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
7064 if(ret_val)
7065 return ret_val;
7066 }
7067
7068 ret_val = e1000_write_phy_reg(hw, 0x0000,
7069 IGP01E1000_IEEE_RESTART_AUTONEG);
7070 if(ret_val)
7071 return ret_val;
7072
7073 msec_delay_irq(20);
7074
7075 /* Now enable the transmitter */
7076 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7077
7078 if(ret_val)
7079 return ret_val;
7080
7081 hw->dsp_config_state = e1000_dsp_config_enabled;
7082 }
7083
7084 if(hw->ffe_config_state == e1000_ffe_config_active) {
7085 /* Save off the current value of register 0x2F5B to be restored at
7086 * the end of the routines. */
7087 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7088
7089 if(ret_val)
7090 return ret_val;
7091
7092 /* Disable the PHY transmitter */
7093 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7094
7095 if(ret_val)
7096 return ret_val;
7097
7098 msec_delay_irq(20);
7099
7100 ret_val = e1000_write_phy_reg(hw, 0x0000,
7101 IGP01E1000_IEEE_FORCE_GIGA);
7102 if(ret_val)
7103 return ret_val;
7104 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7105 IGP01E1000_PHY_DSP_FFE_DEFAULT);
7106 if(ret_val)
7107 return ret_val;
7108
7109 ret_val = e1000_write_phy_reg(hw, 0x0000,
7110 IGP01E1000_IEEE_RESTART_AUTONEG);
7111 if(ret_val)
7112 return ret_val;
7113
7114 msec_delay_irq(20);
7115
7116 /* Now enable the transmitter */
7117 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7118
7119 if(ret_val)
7120 return ret_val;
7121
7122 hw->ffe_config_state = e1000_ffe_config_enabled;
7123 }
7124 }
7125 return E1000_SUCCESS;
7126 }
7127
7128 /*****************************************************************************
7129 * Set PHY to class A mode
7130 * Assumes the following operations will follow to enable the new class mode.
7131 * 1. Do a PHY soft reset
7132 * 2. Restart auto-negotiation or force link.
7133 *
7134 * hw - Struct containing variables accessed by shared code
7135 ****************************************************************************/
7136 static int32_t
7137 e1000_set_phy_mode(struct e1000_hw *hw)
7138 {
7139 int32_t ret_val;
7140 uint16_t eeprom_data;
7141
7142 DEBUGFUNC("e1000_set_phy_mode");
7143
7144 if((hw->mac_type == e1000_82545_rev_3) &&
7145 (hw->media_type == e1000_media_type_copper)) {
7146 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
7147 if(ret_val) {
7148 return ret_val;
7149 }
7150
7151 if((eeprom_data != EEPROM_RESERVED_WORD) &&
7152 (eeprom_data & EEPROM_PHY_CLASS_A)) {
7153 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
7154 if(ret_val)
7155 return ret_val;
7156 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
7157 if(ret_val)
7158 return ret_val;
7159
7160 hw->phy_reset_disable = FALSE;
7161 }
7162 }
7163
7164 return E1000_SUCCESS;
7165 }
7166
7167 /*****************************************************************************
7168 *
7169 * This function sets the lplu state according to the active flag. When
7170 * activating lplu this function also disables smart speed and vise versa.
7171 * lplu will not be activated unless the device autonegotiation advertisment
7172 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7173 * hw: Struct containing variables accessed by shared code
7174 * active - true to enable lplu false to disable lplu.
7175 *
7176 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7177 * E1000_SUCCESS at any other case.
7178 *
7179 ****************************************************************************/
7180
7181 static int32_t
7182 e1000_set_d3_lplu_state(struct e1000_hw *hw,
7183 boolean_t active)
7184 {
7185 uint32_t phy_ctrl = 0;
7186 int32_t ret_val;
7187 uint16_t phy_data;
7188 DEBUGFUNC("e1000_set_d3_lplu_state");
7189
7190 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7191 && hw->phy_type != e1000_phy_igp_3)
7192 return E1000_SUCCESS;
7193
7194 /* During driver activity LPLU should not be used or it will attain link
7195 * from the lowest speeds starting from 10Mbps. The capability is used for
7196 * Dx transitions and states */
7197 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
7198 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
7199 if (ret_val)
7200 return ret_val;
7201 } else if (hw->mac_type == e1000_ich8lan) {
7202 /* MAC writes into PHY register based on the state transition
7203 * and start auto-negotiation. SW driver can overwrite the settings
7204 * in CSR PHY power control E1000_PHY_CTRL register. */
7205 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7206 } else {
7207 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7208 if(ret_val)
7209 return ret_val;
7210 }
7211
7212 if(!active) {
7213 if(hw->mac_type == e1000_82541_rev_2 ||
7214 hw->mac_type == e1000_82547_rev_2) {
7215 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7216 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7217 if(ret_val)
7218 return ret_val;
7219 } else {
7220 if (hw->mac_type == e1000_ich8lan) {
7221 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7222 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7223 } else {
7224 phy_data &= ~IGP02E1000_PM_D3_LPLU;
7225 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7226 phy_data);
7227 if (ret_val)
7228 return ret_val;
7229 }
7230 }
7231
7232 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7233 * Dx states where the power conservation is most important. During
7234 * driver activity we should enable SmartSpeed, so performance is
7235 * maintained. */
7236 if (hw->smart_speed == e1000_smart_speed_on) {
7237 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7238 &phy_data);
7239 if(ret_val)
7240 return ret_val;
7241
7242 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7243 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7244 phy_data);
7245 if(ret_val)
7246 return ret_val;
7247 } else if (hw->smart_speed == e1000_smart_speed_off) {
7248 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7249 &phy_data);
7250 if (ret_val)
7251 return ret_val;
7252
7253 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7254 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7255 phy_data);
7256 if(ret_val)
7257 return ret_val;
7258 }
7259
7260 } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
7261 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
7262 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
7263
7264 if(hw->mac_type == e1000_82541_rev_2 ||
7265 hw->mac_type == e1000_82547_rev_2) {
7266 phy_data |= IGP01E1000_GMII_FLEX_SPD;
7267 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7268 if(ret_val)
7269 return ret_val;
7270 } else {
7271 if (hw->mac_type == e1000_ich8lan) {
7272 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7273 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7274 } else {
7275 phy_data |= IGP02E1000_PM_D3_LPLU;
7276 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7277 phy_data);
7278 if (ret_val)
7279 return ret_val;
7280 }
7281 }
7282
7283 /* When LPLU is enabled we should disable SmartSpeed */
7284 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7285 if(ret_val)
7286 return ret_val;
7287
7288 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7289 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7290 if(ret_val)
7291 return ret_val;
7292
7293 }
7294 return E1000_SUCCESS;
7295 }
7296
7297 /*****************************************************************************
7298 *
7299 * This function sets the lplu d0 state according to the active flag. When
7300 * activating lplu this function also disables smart speed and vise versa.
7301 * lplu will not be activated unless the device autonegotiation advertisment
7302 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7303 * hw: Struct containing variables accessed by shared code
7304 * active - true to enable lplu false to disable lplu.
7305 *
7306 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7307 * E1000_SUCCESS at any other case.
7308 *
7309 ****************************************************************************/
7310
7311 static int32_t
7312 e1000_set_d0_lplu_state(struct e1000_hw *hw,
7313 boolean_t active)
7314 {
7315 uint32_t phy_ctrl = 0;
7316 int32_t ret_val;
7317 uint16_t phy_data;
7318 DEBUGFUNC("e1000_set_d0_lplu_state");
7319
7320 if(hw->mac_type <= e1000_82547_rev_2)
7321 return E1000_SUCCESS;
7322
7323 if (hw->mac_type == e1000_ich8lan) {
7324 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7325 } else {
7326 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7327 if(ret_val)
7328 return ret_val;
7329 }
7330
7331 if (!active) {
7332 if (hw->mac_type == e1000_ich8lan) {
7333 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7334 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7335 } else {
7336 phy_data &= ~IGP02E1000_PM_D0_LPLU;
7337 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7338 if (ret_val)
7339 return ret_val;
7340 }
7341
7342 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7343 * Dx states where the power conservation is most important. During
7344 * driver activity we should enable SmartSpeed, so performance is
7345 * maintained. */
7346 if (hw->smart_speed == e1000_smart_speed_on) {
7347 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7348 &phy_data);
7349 if(ret_val)
7350 return ret_val;
7351
7352 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7353 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7354 phy_data);
7355 if(ret_val)
7356 return ret_val;
7357 } else if (hw->smart_speed == e1000_smart_speed_off) {
7358 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7359 &phy_data);
7360 if (ret_val)
7361 return ret_val;
7362
7363 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7364 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7365 phy_data);
7366 if(ret_val)
7367 return ret_val;
7368 }
7369
7370
7371 } else {
7372
7373 if (hw->mac_type == e1000_ich8lan) {
7374 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7375 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7376 } else {
7377 phy_data |= IGP02E1000_PM_D0_LPLU;
7378 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7379 if (ret_val)
7380 return ret_val;
7381 }
7382
7383 /* When LPLU is enabled we should disable SmartSpeed */
7384 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7385 if(ret_val)
7386 return ret_val;
7387
7388 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7389 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7390 if(ret_val)
7391 return ret_val;
7392
7393 }
7394 return E1000_SUCCESS;
7395 }
7396
7397 /******************************************************************************
7398 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
7399 *
7400 * hw - Struct containing variables accessed by shared code
7401 *****************************************************************************/
7402 static int32_t
7403 e1000_set_vco_speed(struct e1000_hw *hw)
7404 {
7405 int32_t ret_val;
7406 uint16_t default_page = 0;
7407 uint16_t phy_data;
7408
7409 DEBUGFUNC("e1000_set_vco_speed");
7410
7411 switch(hw->mac_type) {
7412 case e1000_82545_rev_3:
7413 case e1000_82546_rev_3:
7414 break;
7415 default:
7416 return E1000_SUCCESS;
7417 }
7418
7419 /* Set PHY register 30, page 5, bit 8 to 0 */
7420
7421 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
7422 if(ret_val)
7423 return ret_val;
7424
7425 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
7426 if(ret_val)
7427 return ret_val;
7428
7429 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7430 if(ret_val)
7431 return ret_val;
7432
7433 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
7434 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7435 if(ret_val)
7436 return ret_val;
7437
7438 /* Set PHY register 30, page 4, bit 11 to 1 */
7439
7440 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
7441 if(ret_val)
7442 return ret_val;
7443
7444 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7445 if(ret_val)
7446 return ret_val;
7447
7448 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
7449 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7450 if(ret_val)
7451 return ret_val;
7452
7453 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
7454 if(ret_val)
7455 return ret_val;
7456
7457 return E1000_SUCCESS;
7458 }
7459
7460
7461 /*****************************************************************************
7462 * This function reads the cookie from ARC ram.
7463 *
7464 * returns: - E1000_SUCCESS .
7465 ****************************************************************************/
7466 int32_t
7467 e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
7468 {
7469 uint8_t i;
7470 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
7471 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
7472
7473 length = (length >> 2);
7474 offset = (offset >> 2);
7475
7476 for (i = 0; i < length; i++) {
7477 *((uint32_t *) buffer + i) =
7478 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7479 }
7480 return E1000_SUCCESS;
7481 }
7482
7483
7484 /*****************************************************************************
7485 * This function checks whether the HOST IF is enabled for command operaton
7486 * and also checks whether the previous command is completed.
7487 * It busy waits in case of previous command is not completed.
7488 *
7489 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
7490 * timeout
7491 * - E1000_SUCCESS for success.
7492 ****************************************************************************/
7493 static int32_t
7494 e1000_mng_enable_host_if(struct e1000_hw * hw)
7495 {
7496 uint32_t hicr;
7497 uint8_t i;
7498
7499 /* Check that the host interface is enabled. */
7500 hicr = E1000_READ_REG(hw, HICR);
7501 if ((hicr & E1000_HICR_EN) == 0) {
7502 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7503 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7504 }
7505 /* check the previous command is completed */
7506 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7507 hicr = E1000_READ_REG(hw, HICR);
7508 if (!(hicr & E1000_HICR_C))
7509 break;
7510 msec_delay_irq(1);
7511 }
7512
7513 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
7514 DEBUGOUT("Previous command timeout failed .\n");
7515 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7516 }
7517 return E1000_SUCCESS;
7518 }
7519
7520 /*****************************************************************************
7521 * This function writes the buffer content at the offset given on the host if.
7522 * It also does alignment considerations to do the writes in most efficient way.
7523 * Also fills up the sum of the buffer in *buffer parameter.
7524 *
7525 * returns - E1000_SUCCESS for success.
7526 ****************************************************************************/
7527 static int32_t
7528 e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7529 uint16_t length, uint16_t offset, uint8_t *sum)
7530 {
7531 uint8_t *tmp;
7532 uint8_t *bufptr = buffer;
7533 uint32_t data;
7534 uint16_t remaining, i, j, prev_bytes;
7535
7536 /* sum = only sum of the data and it is not checksum */
7537
7538 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
7539 return -E1000_ERR_PARAM;
7540 }
7541
7542 tmp = (uint8_t *)&data;
7543 prev_bytes = offset & 0x3;
7544 offset &= 0xFFFC;
7545 offset >>= 2;
7546
7547 if (prev_bytes) {
7548 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7549 for (j = prev_bytes; j < sizeof(uint32_t); j++) {
7550 *(tmp + j) = *bufptr++;
7551 *sum += *(tmp + j);
7552 }
7553 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
7554 length -= j - prev_bytes;
7555 offset++;
7556 }
7557
7558 remaining = length & 0x3;
7559 length -= remaining;
7560
7561 /* Calculate length in DWORDs */
7562 length >>= 2;
7563
7564 /* The device driver writes the relevant command block into the
7565 * ram area. */
7566 for (i = 0; i < length; i++) {
7567 for (j = 0; j < sizeof(uint32_t); j++) {
7568 *(tmp + j) = *bufptr++;
7569 *sum += *(tmp + j);
7570 }
7571
7572 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7573 }
7574 if (remaining) {
7575 for (j = 0; j < sizeof(uint32_t); j++) {
7576 if (j < remaining)
7577 *(tmp + j) = *bufptr++;
7578 else
7579 *(tmp + j) = 0;
7580
7581 *sum += *(tmp + j);
7582 }
7583 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7584 }
7585
7586 return E1000_SUCCESS;
7587 }
7588
7589
7590 /*****************************************************************************
7591 * This function writes the command header after does the checksum calculation.
7592 *
7593 * returns - E1000_SUCCESS for success.
7594 ****************************************************************************/
7595 static int32_t
7596 e1000_mng_write_cmd_header(struct e1000_hw * hw,
7597 struct e1000_host_mng_command_header * hdr)
7598 {
7599 uint16_t i;
7600 uint8_t sum;
7601 uint8_t *buffer;
7602
7603 /* Write the whole command header structure which includes sum of
7604 * the buffer */
7605
7606 uint16_t length = sizeof(struct e1000_host_mng_command_header);
7607
7608 sum = hdr->checksum;
7609 hdr->checksum = 0;
7610
7611 buffer = (uint8_t *) hdr;
7612 i = length;
7613 while(i--)
7614 sum += buffer[i];
7615
7616 hdr->checksum = 0 - sum;
7617
7618 length >>= 2;
7619 /* The device driver writes the relevant command block into the ram area. */
7620 for (i = 0; i < length; i++) {
7621 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
7622 E1000_WRITE_FLUSH(hw);
7623 }
7624
7625 return E1000_SUCCESS;
7626 }
7627
7628
7629 /*****************************************************************************
7630 * This function indicates to ARC that a new command is pending which completes
7631 * one write operation by the driver.
7632 *
7633 * returns - E1000_SUCCESS for success.
7634 ****************************************************************************/
7635 static int32_t
7636 e1000_mng_write_commit(
7637 struct e1000_hw * hw)
7638 {
7639 uint32_t hicr;
7640
7641 hicr = E1000_READ_REG(hw, HICR);
7642 /* Setting this bit tells the ARC that a new command is pending. */
7643 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
7644
7645 return E1000_SUCCESS;
7646 }
7647
7648
7649 /*****************************************************************************
7650 * This function checks the mode of the firmware.
7651 *
7652 * returns - TRUE when the mode is IAMT or FALSE.
7653 ****************************************************************************/
7654 boolean_t
7655 e1000_check_mng_mode(struct e1000_hw *hw)
7656 {
7657 uint32_t fwsm;
7658
7659 fwsm = E1000_READ_REG(hw, FWSM);
7660
7661 if (hw->mac_type == e1000_ich8lan) {
7662 if ((fwsm & E1000_FWSM_MODE_MASK) ==
7663 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7664 return TRUE;
7665 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7666 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7667 return TRUE;
7668
7669 return FALSE;
7670 }
7671
7672
7673 /*****************************************************************************
7674 * This function writes the dhcp info .
7675 ****************************************************************************/
7676 int32_t
7677 e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
7678 uint16_t length)
7679 {
7680 int32_t ret_val;
7681 struct e1000_host_mng_command_header hdr;
7682
7683 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
7684 hdr.command_length = length;
7685 hdr.reserved1 = 0;
7686 hdr.reserved2 = 0;
7687 hdr.checksum = 0;
7688
7689 ret_val = e1000_mng_enable_host_if(hw);
7690 if (ret_val == E1000_SUCCESS) {
7691 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7692 &(hdr.checksum));
7693 if (ret_val == E1000_SUCCESS) {
7694 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
7695 if (ret_val == E1000_SUCCESS)
7696 ret_val = e1000_mng_write_commit(hw);
7697 }
7698 }
7699 return ret_val;
7700 }
7701
7702
7703 /*****************************************************************************
7704 * This function calculates the checksum.
7705 *
7706 * returns - checksum of buffer contents.
7707 ****************************************************************************/
7708 uint8_t
7709 e1000_calculate_mng_checksum(char *buffer, uint32_t length)
7710 {
7711 uint8_t sum = 0;
7712 uint32_t i;
7713
7714 if (!buffer)
7715 return 0;
7716
7717 for (i=0; i < length; i++)
7718 sum += buffer[i];
7719
7720 return (uint8_t) (0 - sum);
7721 }
7722
7723 /*****************************************************************************
7724 * This function checks whether tx pkt filtering needs to be enabled or not.
7725 *
7726 * returns - TRUE for packet filtering or FALSE.
7727 ****************************************************************************/
7728 boolean_t
7729 e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7730 {
7731 /* called in init as well as watchdog timer functions */
7732
7733 int32_t ret_val, checksum;
7734 boolean_t tx_filter = FALSE;
7735 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7736 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
7737
7738 if (e1000_check_mng_mode(hw)) {
7739 ret_val = e1000_mng_enable_host_if(hw);
7740 if (ret_val == E1000_SUCCESS) {
7741 ret_val = e1000_host_if_read_cookie(hw, buffer);
7742 if (ret_val == E1000_SUCCESS) {
7743 checksum = hdr->checksum;
7744 hdr->checksum = 0;
7745 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7746 checksum == e1000_calculate_mng_checksum((char *)buffer,
7747 E1000_MNG_DHCP_COOKIE_LENGTH)) {
7748 if (hdr->status &
7749 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
7750 tx_filter = TRUE;
7751 } else
7752 tx_filter = TRUE;
7753 } else
7754 tx_filter = TRUE;
7755 }
7756 }
7757
7758 hw->tx_pkt_filtering = tx_filter;
7759 return tx_filter;
7760 }
7761
7762 /******************************************************************************
7763 * Verifies the hardware needs to allow ARPs to be processed by the host
7764 *
7765 * hw - Struct containing variables accessed by shared code
7766 *
7767 * returns: - TRUE/FALSE
7768 *
7769 *****************************************************************************/
7770 uint32_t
7771 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7772 {
7773 uint32_t manc;
7774 uint32_t fwsm, factps;
7775
7776 if (hw->asf_firmware_present) {
7777 manc = E1000_READ_REG(hw, MANC);
7778
7779 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7780 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7781 return FALSE;
7782 if (e1000_arc_subsystem_valid(hw) == TRUE) {
7783 fwsm = E1000_READ_REG(hw, FWSM);
7784 factps = E1000_READ_REG(hw, FACTPS);
7785
7786 if (((fwsm & E1000_FWSM_MODE_MASK) ==
7787 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) &&
7788 (factps & E1000_FACTPS_MNGCG))
7789 return TRUE;
7790 } else
7791 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7792 return TRUE;
7793 }
7794 return FALSE;
7795 }
7796
7797 static int32_t
7798 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7799 {
7800 int32_t ret_val;
7801 uint16_t mii_status_reg;
7802 uint16_t i;
7803
7804 /* Polarity reversal workaround for forced 10F/10H links. */
7805
7806 /* Disable the transmitter on the PHY */
7807
7808 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7809 if(ret_val)
7810 return ret_val;
7811 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
7812 if(ret_val)
7813 return ret_val;
7814
7815 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7816 if(ret_val)
7817 return ret_val;
7818
7819 /* This loop will early-out if the NO link condition has been met. */
7820 for(i = PHY_FORCE_TIME; i > 0; i--) {
7821 /* Read the MII Status Register and wait for Link Status bit
7822 * to be clear.
7823 */
7824
7825 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7826 if(ret_val)
7827 return ret_val;
7828
7829 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7830 if(ret_val)
7831 return ret_val;
7832
7833 if((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
7834 msec_delay_irq(100);
7835 }
7836
7837 /* Recommended delay time after link has been lost */
7838 msec_delay_irq(1000);
7839
7840 /* Now we will re-enable th transmitter on the PHY */
7841
7842 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7843 if(ret_val)
7844 return ret_val;
7845 msec_delay_irq(50);
7846 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
7847 if(ret_val)
7848 return ret_val;
7849 msec_delay_irq(50);
7850 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
7851 if(ret_val)
7852 return ret_val;
7853 msec_delay_irq(50);
7854 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
7855 if(ret_val)
7856 return ret_val;
7857
7858 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7859 if(ret_val)
7860 return ret_val;
7861
7862 /* This loop will early-out if the link condition has been met. */
7863 for(i = PHY_FORCE_TIME; i > 0; i--) {
7864 /* Read the MII Status Register and wait for Link Status bit
7865 * to be set.
7866 */
7867
7868 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7869 if(ret_val)
7870 return ret_val;
7871
7872 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7873 if(ret_val)
7874 return ret_val;
7875
7876 if(mii_status_reg & MII_SR_LINK_STATUS) break;
7877 msec_delay_irq(100);
7878 }
7879 return E1000_SUCCESS;
7880 }
7881
7882 /***************************************************************************
7883 *
7884 * Disables PCI-Express master access.
7885 *
7886 * hw: Struct containing variables accessed by shared code
7887 *
7888 * returns: - none.
7889 *
7890 ***************************************************************************/
7891 static void
7892 e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7893 {
7894 uint32_t ctrl;
7895
7896 DEBUGFUNC("e1000_set_pci_express_master_disable");
7897
7898 if (hw->bus_type != e1000_bus_type_pci_express)
7899 return;
7900
7901 ctrl = E1000_READ_REG(hw, CTRL);
7902 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
7903 E1000_WRITE_REG(hw, CTRL, ctrl);
7904 }
7905
7906 /***************************************************************************
7907 *
7908 * Enables PCI-Express master access.
7909 *
7910 * hw: Struct containing variables accessed by shared code
7911 *
7912 * returns: - none.
7913 *
7914 ***************************************************************************/
7915 void
7916 e1000_enable_pciex_master(struct e1000_hw *hw)
7917 {
7918 uint32_t ctrl;
7919
7920 DEBUGFUNC("e1000_enable_pciex_master");
7921
7922 if (hw->bus_type != e1000_bus_type_pci_express)
7923 return;
7924
7925 ctrl = E1000_READ_REG(hw, CTRL);
7926 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE;
7927 E1000_WRITE_REG(hw, CTRL, ctrl);
7928 }
7929
7930 /*******************************************************************************
7931 *
7932 * Disables PCI-Express master access and verifies there are no pending requests
7933 *
7934 * hw: Struct containing variables accessed by shared code
7935 *
7936 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
7937 * caused the master requests to be disabled.
7938 * E1000_SUCCESS master requests disabled.
7939 *
7940 ******************************************************************************/
7941 int32_t
7942 e1000_disable_pciex_master(struct e1000_hw *hw)
7943 {
7944 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
7945
7946 DEBUGFUNC("e1000_disable_pciex_master");
7947
7948 if (hw->bus_type != e1000_bus_type_pci_express)
7949 return E1000_SUCCESS;
7950
7951 e1000_set_pci_express_master_disable(hw);
7952
7953 while(timeout) {
7954 if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
7955 break;
7956 else
7957 udelay(100);
7958 timeout--;
7959 }
7960
7961 if(!timeout) {
7962 DEBUGOUT("Master requests are pending.\n");
7963 return -E1000_ERR_MASTER_REQUESTS_PENDING;
7964 }
7965
7966 return E1000_SUCCESS;
7967 }
7968
7969 /*******************************************************************************
7970 *
7971 * Check for EEPROM Auto Read bit done.
7972 *
7973 * hw: Struct containing variables accessed by shared code
7974 *
7975 * returns: - E1000_ERR_RESET if fail to reset MAC
7976 * E1000_SUCCESS at any other case.
7977 *
7978 ******************************************************************************/
7979 static int32_t
7980 e1000_get_auto_rd_done(struct e1000_hw *hw)
7981 {
7982 int32_t timeout = AUTO_READ_DONE_TIMEOUT;
7983
7984 DEBUGFUNC("e1000_get_auto_rd_done");
7985
7986 switch (hw->mac_type) {
7987 default:
7988 msec_delay(5);
7989 break;
7990 case e1000_82571:
7991 case e1000_82572:
7992 case e1000_82573:
7993 case e1000_80003es2lan:
7994 case e1000_ich8lan:
7995 while (timeout) {
7996 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
7997 break;
7998 else msec_delay(1);
7999 timeout--;
8000 }
8001
8002 if(!timeout) {
8003 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
8004 return -E1000_ERR_RESET;
8005 }
8006 break;
8007 }
8008
8009 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
8010 * Need to wait for PHY configuration completion before accessing NVM
8011 * and PHY. */
8012 if (hw->mac_type == e1000_82573)
8013 msec_delay(25);
8014
8015 return E1000_SUCCESS;
8016 }
8017
8018 /***************************************************************************
8019 * Checks if the PHY configuration is done
8020 *
8021 * hw: Struct containing variables accessed by shared code
8022 *
8023 * returns: - E1000_ERR_RESET if fail to reset MAC
8024 * E1000_SUCCESS at any other case.
8025 *
8026 ***************************************************************************/
8027 static int32_t
8028 e1000_get_phy_cfg_done(struct e1000_hw *hw)
8029 {
8030 int32_t timeout = PHY_CFG_TIMEOUT;
8031 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
8032
8033 DEBUGFUNC("e1000_get_phy_cfg_done");
8034
8035 switch (hw->mac_type) {
8036 default:
8037 msec_delay_irq(10);
8038 break;
8039 case e1000_80003es2lan:
8040 /* Separate *_CFG_DONE_* bit for each port */
8041 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
8042 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
8043 /* Fall Through */
8044 case e1000_82571:
8045 case e1000_82572:
8046 while (timeout) {
8047 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
8048 break;
8049 else
8050 msec_delay(1);
8051 timeout--;
8052 }
8053
8054 if (!timeout) {
8055 DEBUGOUT("MNG configuration cycle has not completed.\n");
8056 return -E1000_ERR_RESET;
8057 }
8058 break;
8059 }
8060
8061 return E1000_SUCCESS;
8062 }
8063
8064 /***************************************************************************
8065 *
8066 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
8067 * adapter or Eeprom access.
8068 *
8069 * hw: Struct containing variables accessed by shared code
8070 *
8071 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
8072 * E1000_SUCCESS at any other case.
8073 *
8074 ***************************************************************************/
8075 static int32_t
8076 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8077 {
8078 int32_t timeout;
8079 uint32_t swsm;
8080
8081 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
8082
8083 if(!hw->eeprom_semaphore_present)
8084 return E1000_SUCCESS;
8085
8086 if (hw->mac_type == e1000_80003es2lan) {
8087 /* Get the SW semaphore. */
8088 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
8089 return -E1000_ERR_EEPROM;
8090 }
8091
8092 /* Get the FW semaphore. */
8093 timeout = hw->eeprom.word_size + 1;
8094 while(timeout) {
8095 swsm = E1000_READ_REG(hw, SWSM);
8096 swsm |= E1000_SWSM_SWESMBI;
8097 E1000_WRITE_REG(hw, SWSM, swsm);
8098 /* if we managed to set the bit we got the semaphore. */
8099 swsm = E1000_READ_REG(hw, SWSM);
8100 if(swsm & E1000_SWSM_SWESMBI)
8101 break;
8102
8103 udelay(50);
8104 timeout--;
8105 }
8106
8107 if(!timeout) {
8108 /* Release semaphores */
8109 e1000_put_hw_eeprom_semaphore(hw);
8110 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
8111 return -E1000_ERR_EEPROM;
8112 }
8113
8114 return E1000_SUCCESS;
8115 }
8116
8117 /***************************************************************************
8118 * This function clears HW semaphore bits.
8119 *
8120 * hw: Struct containing variables accessed by shared code
8121 *
8122 * returns: - None.
8123 *
8124 ***************************************************************************/
8125 static void
8126 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8127 {
8128 uint32_t swsm;
8129
8130 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
8131
8132 if(!hw->eeprom_semaphore_present)
8133 return;
8134
8135 swsm = E1000_READ_REG(hw, SWSM);
8136 if (hw->mac_type == e1000_80003es2lan) {
8137 /* Release both semaphores. */
8138 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
8139 } else
8140 swsm &= ~(E1000_SWSM_SWESMBI);
8141 E1000_WRITE_REG(hw, SWSM, swsm);
8142 }
8143
8144 /***************************************************************************
8145 *
8146 * Obtaining software semaphore bit (SMBI) before resetting PHY.
8147 *
8148 * hw: Struct containing variables accessed by shared code
8149 *
8150 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
8151 * E1000_SUCCESS at any other case.
8152 *
8153 ***************************************************************************/
8154 int32_t
8155 e1000_get_software_semaphore(struct e1000_hw *hw)
8156 {
8157 int32_t timeout = hw->eeprom.word_size + 1;
8158 uint32_t swsm;
8159
8160 DEBUGFUNC("e1000_get_software_semaphore");
8161
8162 if (hw->mac_type != e1000_80003es2lan)
8163 return E1000_SUCCESS;
8164
8165 while(timeout) {
8166 swsm = E1000_READ_REG(hw, SWSM);
8167 /* If SMBI bit cleared, it is now set and we hold the semaphore */
8168 if(!(swsm & E1000_SWSM_SMBI))
8169 break;
8170 msec_delay_irq(1);
8171 timeout--;
8172 }
8173
8174 if(!timeout) {
8175 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
8176 return -E1000_ERR_RESET;
8177 }
8178
8179 return E1000_SUCCESS;
8180 }
8181
8182 /***************************************************************************
8183 *
8184 * Release semaphore bit (SMBI).
8185 *
8186 * hw: Struct containing variables accessed by shared code
8187 *
8188 ***************************************************************************/
8189 void
8190 e1000_release_software_semaphore(struct e1000_hw *hw)
8191 {
8192 uint32_t swsm;
8193
8194 DEBUGFUNC("e1000_release_software_semaphore");
8195
8196 if (hw->mac_type != e1000_80003es2lan)
8197 return;
8198
8199 swsm = E1000_READ_REG(hw, SWSM);
8200 /* Release the SW semaphores.*/
8201 swsm &= ~E1000_SWSM_SMBI;
8202 E1000_WRITE_REG(hw, SWSM, swsm);
8203 }
8204
8205 /******************************************************************************
8206 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
8207 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
8208 * the caller to figure out how to deal with it.
8209 *
8210 * hw - Struct containing variables accessed by shared code
8211 *
8212 * returns: - E1000_BLK_PHY_RESET
8213 * E1000_SUCCESS
8214 *
8215 *****************************************************************************/
8216 int32_t
8217 e1000_check_phy_reset_block(struct e1000_hw *hw)
8218 {
8219 uint32_t manc = 0;
8220 uint32_t fwsm = 0;
8221
8222 if (hw->mac_type == e1000_ich8lan) {
8223 fwsm = E1000_READ_REG(hw, FWSM);
8224 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8225 : E1000_BLK_PHY_RESET;
8226 }
8227
8228 if (hw->mac_type > e1000_82547_rev_2)
8229 manc = E1000_READ_REG(hw, MANC);
8230 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
8231 E1000_BLK_PHY_RESET : E1000_SUCCESS;
8232 }
8233
8234 static uint8_t
8235 e1000_arc_subsystem_valid(struct e1000_hw *hw)
8236 {
8237 uint32_t fwsm;
8238
8239 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
8240 * may not be provided a DMA clock when no manageability features are
8241 * enabled. We do not want to perform any reads/writes to these registers
8242 * if this is the case. We read FWSM to determine the manageability mode.
8243 */
8244 switch (hw->mac_type) {
8245 case e1000_82571:
8246 case e1000_82572:
8247 case e1000_82573:
8248 case e1000_80003es2lan:
8249 fwsm = E1000_READ_REG(hw, FWSM);
8250 if((fwsm & E1000_FWSM_MODE_MASK) != 0)
8251 return TRUE;
8252 break;
8253 case e1000_ich8lan:
8254 return TRUE;
8255 default:
8256 break;
8257 }
8258 return FALSE;
8259 }
8260
8261
8262 /******************************************************************************
8263 * Configure PCI-Ex no-snoop
8264 *
8265 * hw - Struct containing variables accessed by shared code.
8266 * no_snoop - Bitmap of no-snoop events.
8267 *
8268 * returns: E1000_SUCCESS
8269 *
8270 *****************************************************************************/
8271 int32_t
8272 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
8273 {
8274 uint32_t gcr_reg = 0;
8275
8276 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8277
8278 if (hw->bus_type == e1000_bus_type_unknown)
8279 e1000_get_bus_info(hw);
8280
8281 if (hw->bus_type != e1000_bus_type_pci_express)
8282 return E1000_SUCCESS;
8283
8284 if (no_snoop) {
8285 gcr_reg = E1000_READ_REG(hw, GCR);
8286 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8287 gcr_reg |= no_snoop;
8288 E1000_WRITE_REG(hw, GCR, gcr_reg);
8289 }
8290 if (hw->mac_type == e1000_ich8lan) {
8291 uint32_t ctrl_ext;
8292
8293 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8294
8295 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
8296 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8297 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
8298 }
8299
8300 return E1000_SUCCESS;
8301 }
8302
8303 /***************************************************************************
8304 *
8305 * Get software semaphore FLAG bit (SWFLAG).
8306 * SWFLAG is used to synchronize the access to all shared resource between
8307 * SW, FW and HW.
8308 *
8309 * hw: Struct containing variables accessed by shared code
8310 *
8311 ***************************************************************************/
8312 int32_t
8313 e1000_get_software_flag(struct e1000_hw *hw)
8314 {
8315 int32_t timeout = PHY_CFG_TIMEOUT;
8316 uint32_t extcnf_ctrl;
8317
8318 DEBUGFUNC("e1000_get_software_flag");
8319
8320 if (hw->mac_type == e1000_ich8lan) {
8321 while (timeout) {
8322 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8323 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8324 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8325
8326 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8327 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8328 break;
8329 msec_delay_irq(1);
8330 timeout--;
8331 }
8332
8333 if (!timeout) {
8334 DEBUGOUT("FW or HW locks the resource too long.\n");
8335 return -E1000_ERR_CONFIG;
8336 }
8337 }
8338
8339 return E1000_SUCCESS;
8340 }
8341
8342 /***************************************************************************
8343 *
8344 * Release software semaphore FLAG bit (SWFLAG).
8345 * SWFLAG is used to synchronize the access to all shared resource between
8346 * SW, FW and HW.
8347 *
8348 * hw: Struct containing variables accessed by shared code
8349 *
8350 ***************************************************************************/
8351 void
8352 e1000_release_software_flag(struct e1000_hw *hw)
8353 {
8354 uint32_t extcnf_ctrl;
8355
8356 DEBUGFUNC("e1000_release_software_flag");
8357
8358 if (hw->mac_type == e1000_ich8lan) {
8359 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
8360 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8361 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8362 }
8363
8364 return;
8365 }
8366
8367 /***************************************************************************
8368 *
8369 * Disable dynamic power down mode in ife PHY.
8370 * It can be used to workaround band-gap problem.
8371 *
8372 * hw: Struct containing variables accessed by shared code
8373 *
8374 ***************************************************************************/
8375 int32_t
8376 e1000_ife_disable_dynamic_power_down(struct e1000_hw *hw)
8377 {
8378 uint16_t phy_data;
8379 int32_t ret_val = E1000_SUCCESS;
8380
8381 DEBUGFUNC("e1000_ife_disable_dynamic_power_down");
8382
8383 if (hw->phy_type == e1000_phy_ife) {
8384 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
8385 if (ret_val)
8386 return ret_val;
8387
8388 phy_data |= IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN;
8389 ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data);
8390 }
8391
8392 return ret_val;
8393 }
8394
8395 /***************************************************************************
8396 *
8397 * Enable dynamic power down mode in ife PHY.
8398 * It can be used to workaround band-gap problem.
8399 *
8400 * hw: Struct containing variables accessed by shared code
8401 *
8402 ***************************************************************************/
8403 int32_t
8404 e1000_ife_enable_dynamic_power_down(struct e1000_hw *hw)
8405 {
8406 uint16_t phy_data;
8407 int32_t ret_val = E1000_SUCCESS;
8408
8409 DEBUGFUNC("e1000_ife_enable_dynamic_power_down");
8410
8411 if (hw->phy_type == e1000_phy_ife) {
8412 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
8413 if (ret_val)
8414 return ret_val;
8415
8416 phy_data &= ~IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN;
8417 ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data);
8418 }
8419
8420 return ret_val;
8421 }
8422
8423 /******************************************************************************
8424 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8425 * register.
8426 *
8427 * hw - Struct containing variables accessed by shared code
8428 * offset - offset of word in the EEPROM to read
8429 * data - word read from the EEPROM
8430 * words - number of words to read
8431 *****************************************************************************/
8432 int32_t
8433 e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8434 uint16_t *data)
8435 {
8436 int32_t error = E1000_SUCCESS;
8437 uint32_t flash_bank = 0;
8438 uint32_t act_offset = 0;
8439 uint32_t bank_offset = 0;
8440 uint16_t word = 0;
8441 uint16_t i = 0;
8442
8443 /* We need to know which is the valid flash bank. In the event
8444 * that we didn't allocate eeprom_shadow_ram, we may not be
8445 * managing flash_bank. So it cannot be trusted and needs
8446 * to be updated with each read.
8447 */
8448 /* Value of bit 22 corresponds to the flash bank we're on. */
8449 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8450
8451 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8452 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8453
8454 error = e1000_get_software_flag(hw);
8455 if (error != E1000_SUCCESS)
8456 return error;
8457
8458 for (i = 0; i < words; i++) {
8459 if (hw->eeprom_shadow_ram != NULL &&
8460 hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
8461 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8462 } else {
8463 /* The NVM part needs a byte offset, hence * 2 */
8464 act_offset = bank_offset + ((offset + i) * 2);
8465 error = e1000_read_ich8_word(hw, act_offset, &word);
8466 if (error != E1000_SUCCESS)
8467 break;
8468 data[i] = word;
8469 }
8470 }
8471
8472 e1000_release_software_flag(hw);
8473
8474 return error;
8475 }
8476
8477 /******************************************************************************
8478 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8479 * register. Actually, writes are written to the shadow ram cache in the hw
8480 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
8481 * the NVM, which occurs when the NVM checksum is updated.
8482 *
8483 * hw - Struct containing variables accessed by shared code
8484 * offset - offset of word in the EEPROM to write
8485 * words - number of words to write
8486 * data - words to write to the EEPROM
8487 *****************************************************************************/
8488 int32_t
8489 e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8490 uint16_t *data)
8491 {
8492 uint32_t i = 0;
8493 int32_t error = E1000_SUCCESS;
8494
8495 error = e1000_get_software_flag(hw);
8496 if (error != E1000_SUCCESS)
8497 return error;
8498
8499 /* A driver can write to the NVM only if it has eeprom_shadow_ram
8500 * allocated. Subsequent reads to the modified words are read from
8501 * this cached structure as well. Writes will only go into this
8502 * cached structure unless it's followed by a call to
8503 * e1000_update_eeprom_checksum() where it will commit the changes
8504 * and clear the "modified" field.
8505 */
8506 if (hw->eeprom_shadow_ram != NULL) {
8507 for (i = 0; i < words; i++) {
8508 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8509 hw->eeprom_shadow_ram[offset+i].modified = TRUE;
8510 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8511 } else {
8512 error = -E1000_ERR_EEPROM;
8513 break;
8514 }
8515 }
8516 } else {
8517 /* Drivers have the option to not allocate eeprom_shadow_ram as long
8518 * as they don't perform any NVM writes. An attempt in doing so
8519 * will result in this error.
8520 */
8521 error = -E1000_ERR_EEPROM;
8522 }
8523
8524 e1000_release_software_flag(hw);
8525
8526 return error;
8527 }
8528
8529 /******************************************************************************
8530 * This function does initial flash setup so that a new read/write/erase cycle
8531 * can be started.
8532 *
8533 * hw - The pointer to the hw structure
8534 ****************************************************************************/
8535 int32_t
8536 e1000_ich8_cycle_init(struct e1000_hw *hw)
8537 {
8538 union ich8_hws_flash_status hsfsts;
8539 int32_t error = E1000_ERR_EEPROM;
8540 int32_t i = 0;
8541
8542 DEBUGFUNC("e1000_ich8_cycle_init");
8543
8544 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8545
8546 /* May be check the Flash Des Valid bit in Hw status */
8547 if (hsfsts.hsf_status.fldesvalid == 0) {
8548 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8549 return error;
8550 }
8551
8552 /* Clear FCERR in Hw status by writing 1 */
8553 /* Clear DAEL in Hw status by writing a 1 */
8554 hsfsts.hsf_status.flcerr = 1;
8555 hsfsts.hsf_status.dael = 1;
8556
8557 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8558
8559 /* Either we should have a hardware SPI cycle in progress bit to check
8560 * against, in order to start a new cycle or FDONE bit should be changed
8561 * in the hardware so that it is 1 after harware reset, which can then be
8562 * used as an indication whether a cycle is in progress or has been
8563 * completed .. we should also have some software semaphore mechanism to
8564 * guard FDONE or the cycle in progress bit so that two threads access to
8565 * those bits can be sequentiallized or a way so that 2 threads dont
8566 * start the cycle at the same time */
8567
8568 if (hsfsts.hsf_status.flcinprog == 0) {
8569 /* There is no cycle running at present, so we can start a cycle */
8570 /* Begin by setting Flash Cycle Done. */
8571 hsfsts.hsf_status.flcdone = 1;
8572 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8573 error = E1000_SUCCESS;
8574 } else {
8575 /* otherwise poll for sometime so the current cycle has a chance
8576 * to end before giving up. */
8577 for (i = 0; i < ICH8_FLASH_COMMAND_TIMEOUT; i++) {
8578 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8579 if (hsfsts.hsf_status.flcinprog == 0) {
8580 error = E1000_SUCCESS;
8581 break;
8582 }
8583 udelay(1);
8584 }
8585 if (error == E1000_SUCCESS) {
8586 /* Successful in waiting for previous cycle to timeout,
8587 * now set the Flash Cycle Done. */
8588 hsfsts.hsf_status.flcdone = 1;
8589 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8590 } else {
8591 DEBUGOUT("Flash controller busy, cannot get access");
8592 }
8593 }
8594 return error;
8595 }
8596
8597 /******************************************************************************
8598 * This function starts a flash cycle and waits for its completion
8599 *
8600 * hw - The pointer to the hw structure
8601 ****************************************************************************/
8602 int32_t
8603 e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8604 {
8605 union ich8_hws_flash_ctrl hsflctl;
8606 union ich8_hws_flash_status hsfsts;
8607 int32_t error = E1000_ERR_EEPROM;
8608 uint32_t i = 0;
8609
8610 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8611 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8612 hsflctl.hsf_ctrl.flcgo = 1;
8613 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8614
8615 /* wait till FDONE bit is set to 1 */
8616 do {
8617 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8618 if (hsfsts.hsf_status.flcdone == 1)
8619 break;
8620 udelay(1);
8621 i++;
8622 } while (i < timeout);
8623 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8624 error = E1000_SUCCESS;
8625 }
8626 return error;
8627 }
8628
8629 /******************************************************************************
8630 * Reads a byte or word from the NVM using the ICH8 flash access registers.
8631 *
8632 * hw - The pointer to the hw structure
8633 * index - The index of the byte or word to read.
8634 * size - Size of data to read, 1=byte 2=word
8635 * data - Pointer to the word to store the value read.
8636 *****************************************************************************/
8637 int32_t
8638 e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8639 uint32_t size, uint16_t* data)
8640 {
8641 union ich8_hws_flash_status hsfsts;
8642 union ich8_hws_flash_ctrl hsflctl;
8643 uint32_t flash_linear_address;
8644 uint32_t flash_data = 0;
8645 int32_t error = -E1000_ERR_EEPROM;
8646 int32_t count = 0;
8647
8648 DEBUGFUNC("e1000_read_ich8_data");
8649
8650 if (size < 1 || size > 2 || data == 0x0 ||
8651 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8652 return error;
8653
8654 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8655 hw->flash_base_addr;
8656
8657 do {
8658 udelay(1);
8659 /* Steps */
8660 error = e1000_ich8_cycle_init(hw);
8661 if (error != E1000_SUCCESS)
8662 break;
8663
8664 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8665 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8666 hsflctl.hsf_ctrl.fldbcount = size - 1;
8667 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_READ;
8668 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8669
8670 /* Write the last 24 bits of index into Flash Linear address field in
8671 * Flash Address */
8672 /* TODO: TBD maybe check the index against the size of flash */
8673
8674 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8675
8676 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8677
8678 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8679 * sequence a few more times, else read in (shift in) the Flash Data0,
8680 * the order is least significant byte first msb to lsb */
8681 if (error == E1000_SUCCESS) {
8682 flash_data = E1000_READ_ICH8_REG(hw, ICH8_FLASH_FDATA0);
8683 if (size == 1) {
8684 *data = (uint8_t)(flash_data & 0x000000FF);
8685 } else if (size == 2) {
8686 *data = (uint16_t)(flash_data & 0x0000FFFF);
8687 }
8688 break;
8689 } else {
8690 /* If we've gotten here, then things are probably completely hosed,
8691 * but if the error condition is detected, it won't hurt to give
8692 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8693 */
8694 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8695 if (hsfsts.hsf_status.flcerr == 1) {
8696 /* Repeat for some time before giving up. */
8697 continue;
8698 } else if (hsfsts.hsf_status.flcdone == 0) {
8699 DEBUGOUT("Timeout error - flash cycle did not complete.");
8700 break;
8701 }
8702 }
8703 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8704
8705 return error;
8706 }
8707
8708 /******************************************************************************
8709 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
8710 *
8711 * hw - The pointer to the hw structure
8712 * index - The index of the byte/word to read.
8713 * size - Size of data to read, 1=byte 2=word
8714 * data - The byte(s) to write to the NVM.
8715 *****************************************************************************/
8716 int32_t
8717 e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8718 uint16_t data)
8719 {
8720 union ich8_hws_flash_status hsfsts;
8721 union ich8_hws_flash_ctrl hsflctl;
8722 uint32_t flash_linear_address;
8723 uint32_t flash_data = 0;
8724 int32_t error = -E1000_ERR_EEPROM;
8725 int32_t count = 0;
8726
8727 DEBUGFUNC("e1000_write_ich8_data");
8728
8729 if (size < 1 || size > 2 || data > size * 0xff ||
8730 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8731 return error;
8732
8733 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8734 hw->flash_base_addr;
8735
8736 do {
8737 udelay(1);
8738 /* Steps */
8739 error = e1000_ich8_cycle_init(hw);
8740 if (error != E1000_SUCCESS)
8741 break;
8742
8743 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8744 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8745 hsflctl.hsf_ctrl.fldbcount = size -1;
8746 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_WRITE;
8747 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8748
8749 /* Write the last 24 bits of index into Flash Linear address field in
8750 * Flash Address */
8751 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8752
8753 if (size == 1)
8754 flash_data = (uint32_t)data & 0x00FF;
8755 else
8756 flash_data = (uint32_t)data;
8757
8758 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FDATA0, flash_data);
8759
8760 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8761 * sequence a few more times else done */
8762 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8763 if (error == E1000_SUCCESS) {
8764 break;
8765 } else {
8766 /* If we're here, then things are most likely completely hosed,
8767 * but if the error condition is detected, it won't hurt to give
8768 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8769 */
8770 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8771 if (hsfsts.hsf_status.flcerr == 1) {
8772 /* Repeat for some time before giving up. */
8773 continue;
8774 } else if (hsfsts.hsf_status.flcdone == 0) {
8775 DEBUGOUT("Timeout error - flash cycle did not complete.");
8776 break;
8777 }
8778 }
8779 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8780
8781 return error;
8782 }
8783
8784 /******************************************************************************
8785 * Reads a single byte from the NVM using the ICH8 flash access registers.
8786 *
8787 * hw - pointer to e1000_hw structure
8788 * index - The index of the byte to read.
8789 * data - Pointer to a byte to store the value read.
8790 *****************************************************************************/
8791 int32_t
8792 e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
8793 {
8794 int32_t status = E1000_SUCCESS;
8795 uint16_t word = 0;
8796
8797 status = e1000_read_ich8_data(hw, index, 1, &word);
8798 if (status == E1000_SUCCESS) {
8799 *data = (uint8_t)word;
8800 }
8801
8802 return status;
8803 }
8804
8805 /******************************************************************************
8806 * Writes a single byte to the NVM using the ICH8 flash access registers.
8807 * Performs verification by reading back the value and then going through
8808 * a retry algorithm before giving up.
8809 *
8810 * hw - pointer to e1000_hw structure
8811 * index - The index of the byte to write.
8812 * byte - The byte to write to the NVM.
8813 *****************************************************************************/
8814 int32_t
8815 e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8816 {
8817 int32_t error = E1000_SUCCESS;
8818 int32_t program_retries;
8819 uint8_t temp_byte;
8820
8821 e1000_write_ich8_byte(hw, index, byte);
8822 udelay(100);
8823
8824 for (program_retries = 0; program_retries < 100; program_retries++) {
8825 e1000_read_ich8_byte(hw, index, &temp_byte);
8826 if (temp_byte == byte)
8827 break;
8828 udelay(10);
8829 e1000_write_ich8_byte(hw, index, byte);
8830 udelay(100);
8831 }
8832 if (program_retries == 100)
8833 error = E1000_ERR_EEPROM;
8834
8835 return error;
8836 }
8837
8838 /******************************************************************************
8839 * Writes a single byte to the NVM using the ICH8 flash access registers.
8840 *
8841 * hw - pointer to e1000_hw structure
8842 * index - The index of the byte to read.
8843 * data - The byte to write to the NVM.
8844 *****************************************************************************/
8845 int32_t
8846 e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
8847 {
8848 int32_t status = E1000_SUCCESS;
8849 uint16_t word = (uint16_t)data;
8850
8851 status = e1000_write_ich8_data(hw, index, 1, word);
8852
8853 return status;
8854 }
8855
8856 /******************************************************************************
8857 * Reads a word from the NVM using the ICH8 flash access registers.
8858 *
8859 * hw - pointer to e1000_hw structure
8860 * index - The starting byte index of the word to read.
8861 * data - Pointer to a word to store the value read.
8862 *****************************************************************************/
8863 int32_t
8864 e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
8865 {
8866 int32_t status = E1000_SUCCESS;
8867 status = e1000_read_ich8_data(hw, index, 2, data);
8868 return status;
8869 }
8870
8871 /******************************************************************************
8872 * Writes a word to the NVM using the ICH8 flash access registers.
8873 *
8874 * hw - pointer to e1000_hw structure
8875 * index - The starting byte index of the word to read.
8876 * data - The word to write to the NVM.
8877 *****************************************************************************/
8878 int32_t
8879 e1000_write_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t data)
8880 {
8881 int32_t status = E1000_SUCCESS;
8882 status = e1000_write_ich8_data(hw, index, 2, data);
8883 return status;
8884 }
8885
8886 /******************************************************************************
8887 * Erases the bank specified. Each bank is a 4k block. Segments are 0 based.
8888 * segment N is 4096 * N + flash_reg_addr.
8889 *
8890 * hw - pointer to e1000_hw structure
8891 * segment - 0 for first segment, 1 for second segment, etc.
8892 *****************************************************************************/
8893 int32_t
8894 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment)
8895 {
8896 union ich8_hws_flash_status hsfsts;
8897 union ich8_hws_flash_ctrl hsflctl;
8898 uint32_t flash_linear_address;
8899 int32_t count = 0;
8900 int32_t error = E1000_ERR_EEPROM;
8901 int32_t iteration, seg_size;
8902 int32_t sector_size;
8903 int32_t j = 0;
8904 int32_t error_flag = 0;
8905
8906 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8907
8908 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8909 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8910 * consecutive sectors. The start index for the nth Hw sector can be
8911 * calculated as = segment * 4096 + n * 256
8912 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8913 * The start index for the nth Hw sector can be calculated
8914 * as = segment * 4096
8915 * 10: Error condition
8916 * 11: The Hw sector size is much bigger than the size asked to
8917 * erase...error condition */
8918 if (hsfsts.hsf_status.berasesz == 0x0) {
8919 /* Hw sector size 256 */
8920 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_256;
8921 iteration = ICH8_FLASH_SECTOR_SIZE / ICH8_FLASH_SEG_SIZE_256;
8922 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8923 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_4K;
8924 iteration = 1;
8925 } else if (hsfsts.hsf_status.berasesz == 0x3) {
8926 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_64K;
8927 iteration = 1;
8928 } else {
8929 return error;
8930 }
8931
8932 for (j = 0; j < iteration ; j++) {
8933 do {
8934 count++;
8935 /* Steps */
8936 error = e1000_ich8_cycle_init(hw);
8937 if (error != E1000_SUCCESS) {
8938 error_flag = 1;
8939 break;
8940 }
8941
8942 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
8943 * Control */
8944 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8945 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_ERASE;
8946 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8947
8948 /* Write the last 24 bits of an index within the block into Flash
8949 * Linear address field in Flash Address. This probably needs to
8950 * be calculated here based off the on-chip segment size and the
8951 * software segment size assumed (4K) */
8952 /* TBD */
8953 flash_linear_address = segment * sector_size + j * seg_size;
8954 flash_linear_address &= ICH8_FLASH_LINEAR_ADDR_MASK;
8955 flash_linear_address += hw->flash_base_addr;
8956
8957 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8958
8959 error = e1000_ich8_flash_cycle(hw, 1000000);
8960 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8961 * sequence a few more times else Done */
8962 if (error == E1000_SUCCESS) {
8963 break;
8964 } else {
8965 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8966 if (hsfsts.hsf_status.flcerr == 1) {
8967 /* repeat for some time before giving up */
8968 continue;
8969 } else if (hsfsts.hsf_status.flcdone == 0) {
8970 error_flag = 1;
8971 break;
8972 }
8973 }
8974 } while ((count < ICH8_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
8975 if (error_flag == 1)
8976 break;
8977 }
8978 if (error_flag != 1)
8979 error = E1000_SUCCESS;
8980 return error;
8981 }
8982
8983 /******************************************************************************
8984 *
8985 * Reverse duplex setting without breaking the link.
8986 *
8987 * hw: Struct containing variables accessed by shared code
8988 *
8989 *****************************************************************************/
8990 int32_t
8991 e1000_duplex_reversal(struct e1000_hw *hw)
8992 {
8993 int32_t ret_val;
8994 uint16_t phy_data;
8995
8996 if (hw->phy_type != e1000_phy_igp_3)
8997 return E1000_SUCCESS;
8998
8999 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
9000 if (ret_val)
9001 return ret_val;
9002
9003 phy_data ^= MII_CR_FULL_DUPLEX;
9004
9005 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
9006 if (ret_val)
9007 return ret_val;
9008
9009 ret_val = e1000_read_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, &phy_data);
9010 if (ret_val)
9011 return ret_val;
9012
9013 phy_data |= IGP3_PHY_MISC_DUPLEX_MANUAL_SET;
9014 ret_val = e1000_write_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, phy_data);
9015
9016 return ret_val;
9017 }
9018
9019 int32_t
9020 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
9021 uint32_t cnf_base_addr, uint32_t cnf_size)
9022 {
9023 uint32_t ret_val = E1000_SUCCESS;
9024 uint16_t word_addr, reg_data, reg_addr;
9025 uint16_t i;
9026
9027 /* cnf_base_addr is in DWORD */
9028 word_addr = (uint16_t)(cnf_base_addr << 1);
9029
9030 /* cnf_size is returned in size of dwords */
9031 for (i = 0; i < cnf_size; i++) {
9032 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
9033 if (ret_val)
9034 return ret_val;
9035
9036 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
9037 if (ret_val)
9038 return ret_val;
9039
9040 ret_val = e1000_get_software_flag(hw);
9041 if (ret_val != E1000_SUCCESS)
9042 return ret_val;
9043
9044 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
9045
9046 e1000_release_software_flag(hw);
9047 }
9048
9049 return ret_val;
9050 }
9051
9052
9053 int32_t
9054 e1000_init_lcd_from_nvm(struct e1000_hw *hw)
9055 {
9056 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
9057
9058 if (hw->phy_type != e1000_phy_igp_3)
9059 return E1000_SUCCESS;
9060
9061 /* Check if SW needs configure the PHY */
9062 reg_data = E1000_READ_REG(hw, FEXTNVM);
9063 if (!(reg_data & FEXTNVM_SW_CONFIG))
9064 return E1000_SUCCESS;
9065
9066 /* Wait for basic configuration completes before proceeding*/
9067 loop = 0;
9068 do {
9069 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
9070 udelay(100);
9071 loop++;
9072 } while ((!reg_data) && (loop < 50));
9073
9074 /* Clear the Init Done bit for the next init event */
9075 reg_data = E1000_READ_REG(hw, STATUS);
9076 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
9077 E1000_WRITE_REG(hw, STATUS, reg_data);
9078
9079 /* Make sure HW does not configure LCD from PHY extended configuration
9080 before SW configuration */
9081 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9082 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
9083 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
9084 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
9085 cnf_size >>= 16;
9086 if (cnf_size) {
9087 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9088 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
9089 /* cnf_base_addr is in DWORD */
9090 cnf_base_addr >>= 16;
9091
9092 /* Configure LCD from extended configuration region. */
9093 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
9094 cnf_size);
9095 if (ret_val)
9096 return ret_val;
9097 }
9098 }
9099
9100 return E1000_SUCCESS;
9101 }
9102
9103
9104
x86 "subsystem" repository