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ahci: Add support for Promise PDC42819
[linux-2.6/x86.git] / drivers / ata / ahci.c
blob289719b2cb30392e49ab3c59707c8d967be621d6
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
51
52 static int ahci_skip_host_reset;
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56 static int ahci_enable_alpm(struct ata_port *ap,
57 enum link_pm policy);
58 static void ahci_disable_alpm(struct ata_port *ap);
59 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
60 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
61 size_t size);
62 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
63 ssize_t size);
64 #define MAX_SLOTS 8
65
66 enum {
67 AHCI_PCI_BAR = 5,
68 AHCI_MAX_PORTS = 32,
69 AHCI_MAX_SG = 168, /* hardware max is 64K */
70 AHCI_DMA_BOUNDARY = 0xffffffff,
71 AHCI_MAX_CMDS = 32,
72 AHCI_CMD_SZ = 32,
73 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
74 AHCI_RX_FIS_SZ = 256,
75 AHCI_CMD_TBL_CDB = 0x40,
76 AHCI_CMD_TBL_HDR_SZ = 0x80,
77 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
78 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
79 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
80 AHCI_RX_FIS_SZ,
81 AHCI_IRQ_ON_SG = (1 << 31),
82 AHCI_CMD_ATAPI = (1 << 5),
83 AHCI_CMD_WRITE = (1 << 6),
84 AHCI_CMD_PREFETCH = (1 << 7),
85 AHCI_CMD_RESET = (1 << 8),
86 AHCI_CMD_CLR_BUSY = (1 << 10),
87
88 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
89 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
90 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
91
92 board_ahci = 0,
93 board_ahci_vt8251 = 1,
94 board_ahci_ign_iferr = 2,
95 board_ahci_sb600 = 3,
96 board_ahci_mv = 4,
97 board_ahci_sb700 = 5,
98 board_ahci_mcp65 = 6,
99 board_ahci_nopmp = 7,
100
101 /* global controller registers */
102 HOST_CAP = 0x00, /* host capabilities */
103 HOST_CTL = 0x04, /* global host control */
104 HOST_IRQ_STAT = 0x08, /* interrupt status */
105 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
106 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
107 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
108 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
109
110 /* HOST_CTL bits */
111 HOST_RESET = (1 << 0), /* reset controller; self-clear */
112 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
113 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
114
115 /* HOST_CAP bits */
116 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
117 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
118 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
119 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
120 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
121 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
122 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
123 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
124 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
125
126 /* registers for each SATA port */
127 PORT_LST_ADDR = 0x00, /* command list DMA addr */
128 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
129 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
130 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
131 PORT_IRQ_STAT = 0x10, /* interrupt status */
132 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
133 PORT_CMD = 0x18, /* port command */
134 PORT_TFDATA = 0x20, /* taskfile data */
135 PORT_SIG = 0x24, /* device TF signature */
136 PORT_CMD_ISSUE = 0x38, /* command issue */
137 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
138 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
139 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
140 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
141 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
142
143 /* PORT_IRQ_{STAT,MASK} bits */
144 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
145 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
146 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
147 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
148 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
149 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
150 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
151 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
152
153 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
154 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
155 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
156 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
157 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
158 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
159 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
160 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
161 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
162
163 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
164 PORT_IRQ_IF_ERR |
165 PORT_IRQ_CONNECT |
166 PORT_IRQ_PHYRDY |
167 PORT_IRQ_UNK_FIS |
168 PORT_IRQ_BAD_PMP,
169 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
170 PORT_IRQ_TF_ERR |
171 PORT_IRQ_HBUS_DATA_ERR,
172 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
173 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
174 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
175
176 /* PORT_CMD bits */
177 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
178 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
179 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
180 PORT_CMD_PMP = (1 << 17), /* PMP attached */
181 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
182 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
183 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
184 PORT_CMD_CLO = (1 << 3), /* Command list override */
185 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
186 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
187 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
188
189 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
190 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
191 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
192 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
193
194 /* hpriv->flags bits */
195 AHCI_HFLAG_NO_NCQ = (1 << 0),
196 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
197 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
198 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
199 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
200 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
201 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
202 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
203 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
204 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
205
206 /* ap->flags bits */
207
208 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
209 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
210 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
211 ATA_FLAG_IPM,
212
213 ICH_MAP = 0x90, /* ICH MAP register */
214
215 /* em_ctl bits */
216 EM_CTL_RST = (1 << 9), /* Reset */
217 EM_CTL_TM = (1 << 8), /* Transmit Message */
218 EM_CTL_ALHD = (1 << 26), /* Activity LED */
219 };
220
221 struct ahci_cmd_hdr {
222 __le32 opts;
223 __le32 status;
224 __le32 tbl_addr;
225 __le32 tbl_addr_hi;
226 __le32 reserved[4];
227 };
228
229 struct ahci_sg {
230 __le32 addr;
231 __le32 addr_hi;
232 __le32 reserved;
233 __le32 flags_size;
234 };
235
236 struct ahci_em_priv {
237 enum sw_activity blink_policy;
238 struct timer_list timer;
239 unsigned long saved_activity;
240 unsigned long activity;
241 unsigned long led_state;
242 };
243
244 struct ahci_host_priv {
245 unsigned int flags; /* AHCI_HFLAG_* */
246 u32 cap; /* cap to use */
247 u32 port_map; /* port map to use */
248 u32 saved_cap; /* saved initial cap */
249 u32 saved_port_map; /* saved initial port_map */
250 u32 em_loc; /* enclosure management location */
251 };
252
253 struct ahci_port_priv {
254 struct ata_link *active_link;
255 struct ahci_cmd_hdr *cmd_slot;
256 dma_addr_t cmd_slot_dma;
257 void *cmd_tbl;
258 dma_addr_t cmd_tbl_dma;
259 void *rx_fis;
260 dma_addr_t rx_fis_dma;
261 /* for NCQ spurious interrupt analysis */
262 unsigned int ncq_saw_d2h:1;
263 unsigned int ncq_saw_dmas:1;
264 unsigned int ncq_saw_sdb:1;
265 u32 intr_mask; /* interrupts to enable */
266 struct ahci_em_priv em_priv[MAX_SLOTS];/* enclosure management info
267 * per PM slot */
268 };
269
270 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
271 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
272 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
273 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
274 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
275 static int ahci_port_start(struct ata_port *ap);
276 static void ahci_port_stop(struct ata_port *ap);
277 static void ahci_qc_prep(struct ata_queued_cmd *qc);
278 static void ahci_freeze(struct ata_port *ap);
279 static void ahci_thaw(struct ata_port *ap);
280 static void ahci_pmp_attach(struct ata_port *ap);
281 static void ahci_pmp_detach(struct ata_port *ap);
282 static int ahci_softreset(struct ata_link *link, unsigned int *class,
283 unsigned long deadline);
284 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
285 unsigned long deadline);
286 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
287 unsigned long deadline);
288 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
289 unsigned long deadline);
290 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
291 unsigned long deadline);
292 static void ahci_postreset(struct ata_link *link, unsigned int *class);
293 static void ahci_error_handler(struct ata_port *ap);
294 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
295 static int ahci_port_resume(struct ata_port *ap);
296 static void ahci_dev_config(struct ata_device *dev);
297 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
298 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
299 u32 opts);
300 #ifdef CONFIG_PM
301 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
302 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
303 static int ahci_pci_device_resume(struct pci_dev *pdev);
304 #endif
305 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
306 static ssize_t ahci_activity_store(struct ata_device *dev,
307 enum sw_activity val);
308 static void ahci_init_sw_activity(struct ata_link *link);
309
310 static struct device_attribute *ahci_shost_attrs[] = {
311 &dev_attr_link_power_management_policy,
312 &dev_attr_em_message_type,
313 &dev_attr_em_message,
314 NULL
315 };
316
317 static struct device_attribute *ahci_sdev_attrs[] = {
318 &dev_attr_sw_activity,
319 &dev_attr_unload_heads,
320 NULL
321 };
322
323 static struct scsi_host_template ahci_sht = {
324 ATA_NCQ_SHT(DRV_NAME),
325 .can_queue = AHCI_MAX_CMDS - 1,
326 .sg_tablesize = AHCI_MAX_SG,
327 .dma_boundary = AHCI_DMA_BOUNDARY,
328 .shost_attrs = ahci_shost_attrs,
329 .sdev_attrs = ahci_sdev_attrs,
330 };
331
332 static struct ata_port_operations ahci_ops = {
333 .inherits = &sata_pmp_port_ops,
334
335 .qc_defer = sata_pmp_qc_defer_cmd_switch,
336 .qc_prep = ahci_qc_prep,
337 .qc_issue = ahci_qc_issue,
338 .qc_fill_rtf = ahci_qc_fill_rtf,
339
340 .freeze = ahci_freeze,
341 .thaw = ahci_thaw,
342 .softreset = ahci_softreset,
343 .hardreset = ahci_hardreset,
344 .postreset = ahci_postreset,
345 .pmp_softreset = ahci_softreset,
346 .error_handler = ahci_error_handler,
347 .post_internal_cmd = ahci_post_internal_cmd,
348 .dev_config = ahci_dev_config,
349
350 .scr_read = ahci_scr_read,
351 .scr_write = ahci_scr_write,
352 .pmp_attach = ahci_pmp_attach,
353 .pmp_detach = ahci_pmp_detach,
354
355 .enable_pm = ahci_enable_alpm,
356 .disable_pm = ahci_disable_alpm,
357 .em_show = ahci_led_show,
358 .em_store = ahci_led_store,
359 .sw_activity_show = ahci_activity_show,
360 .sw_activity_store = ahci_activity_store,
361 #ifdef CONFIG_PM
362 .port_suspend = ahci_port_suspend,
363 .port_resume = ahci_port_resume,
364 #endif
365 .port_start = ahci_port_start,
366 .port_stop = ahci_port_stop,
367 };
368
369 static struct ata_port_operations ahci_vt8251_ops = {
370 .inherits = &ahci_ops,
371 .hardreset = ahci_vt8251_hardreset,
372 };
373
374 static struct ata_port_operations ahci_p5wdh_ops = {
375 .inherits = &ahci_ops,
376 .hardreset = ahci_p5wdh_hardreset,
377 };
378
379 static struct ata_port_operations ahci_sb600_ops = {
380 .inherits = &ahci_ops,
381 .softreset = ahci_sb600_softreset,
382 .pmp_softreset = ahci_sb600_softreset,
383 };
384
385 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
386
387 static const struct ata_port_info ahci_port_info[] = {
388 /* board_ahci */
389 {
390 .flags = AHCI_FLAG_COMMON,
391 .pio_mask = 0x1f, /* pio0-4 */
392 .udma_mask = ATA_UDMA6,
393 .port_ops = &ahci_ops,
394 },
395 /* board_ahci_vt8251 */
396 {
397 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
398 .flags = AHCI_FLAG_COMMON,
399 .pio_mask = 0x1f, /* pio0-4 */
400 .udma_mask = ATA_UDMA6,
401 .port_ops = &ahci_vt8251_ops,
402 },
403 /* board_ahci_ign_iferr */
404 {
405 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
406 .flags = AHCI_FLAG_COMMON,
407 .pio_mask = 0x1f, /* pio0-4 */
408 .udma_mask = ATA_UDMA6,
409 .port_ops = &ahci_ops,
410 },
411 /* board_ahci_sb600 */
412 {
413 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
414 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
415 AHCI_HFLAG_SECT255),
416 .flags = AHCI_FLAG_COMMON,
417 .pio_mask = 0x1f, /* pio0-4 */
418 .udma_mask = ATA_UDMA6,
419 .port_ops = &ahci_sb600_ops,
420 },
421 /* board_ahci_mv */
422 {
423 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
424 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
425 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
426 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
427 .pio_mask = 0x1f, /* pio0-4 */
428 .udma_mask = ATA_UDMA6,
429 .port_ops = &ahci_ops,
430 },
431 /* board_ahci_sb700 */
432 {
433 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
434 .flags = AHCI_FLAG_COMMON,
435 .pio_mask = 0x1f, /* pio0-4 */
436 .udma_mask = ATA_UDMA6,
437 .port_ops = &ahci_sb600_ops,
438 },
439 /* board_ahci_mcp65 */
440 {
441 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
442 .flags = AHCI_FLAG_COMMON,
443 .pio_mask = 0x1f, /* pio0-4 */
444 .udma_mask = ATA_UDMA6,
445 .port_ops = &ahci_ops,
446 },
447 /* board_ahci_nopmp */
448 {
449 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
450 .flags = AHCI_FLAG_COMMON,
451 .pio_mask = 0x1f, /* pio0-4 */
452 .udma_mask = ATA_UDMA6,
453 .port_ops = &ahci_ops,
454 },
455 };
456
457 static const struct pci_device_id ahci_pci_tbl[] = {
458 /* Intel */
459 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
460 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
461 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
462 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
463 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
464 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
465 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
466 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
467 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
468 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
469 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
470 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
471 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
472 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
473 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
474 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
475 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
476 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
477 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
478 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
479 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
480 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
481 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
482 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
483 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
484 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
485 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
486 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
487 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
488 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
489 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
490 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
491 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
492 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
493 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
494
495 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
496 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
497 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
498
499 /* ATI */
500 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
501 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
502 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
503 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
504 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
505 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
506 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
507
508 /* VIA */
509 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
510 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
511
512 /* NVIDIA */
513 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
514 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
515 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
516 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
517 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
518 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
519 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
520 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
521 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
522 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
523 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
524 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
525 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
526 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
527 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
528 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
529 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
530 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
531 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
532 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
533 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
534 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
535 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
536 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
537 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
538 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
539 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
540 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
541 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
542 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
543 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
544 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
545 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
546 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
547 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
548 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
549 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
550 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
551 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
552 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
553 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
554 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
555 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
556 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
557 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
558 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
559 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
560 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
561 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
562 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
563 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
564 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
565 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
566 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
567 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
568 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
569 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
570 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
571 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
572 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
573 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
574 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
575 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
576 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
577 { PCI_VDEVICE(NVIDIA, 0x0bc4), board_ahci }, /* MCP7B */
578 { PCI_VDEVICE(NVIDIA, 0x0bc5), board_ahci }, /* MCP7B */
579 { PCI_VDEVICE(NVIDIA, 0x0bc6), board_ahci }, /* MCP7B */
580 { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */
581
582 /* SiS */
583 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
584 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
585 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
586
587 /* Marvell */
588 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
589 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
590
591 /* Promise */
592 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
593
594 /* Generic, PCI class code for AHCI */
595 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
596 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
597
598 { } /* terminate list */
599 };
600
601
602 static struct pci_driver ahci_pci_driver = {
603 .name = DRV_NAME,
604 .id_table = ahci_pci_tbl,
605 .probe = ahci_init_one,
606 .remove = ata_pci_remove_one,
607 #ifdef CONFIG_PM
608 .suspend = ahci_pci_device_suspend,
609 .resume = ahci_pci_device_resume,
610 #endif
611 };
612
613 static int ahci_em_messages = 1;
614 module_param(ahci_em_messages, int, 0444);
615 /* add other LED protocol types when they become supported */
616 MODULE_PARM_DESC(ahci_em_messages,
617 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
618
619 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
620 static int marvell_enable;
621 #else
622 static int marvell_enable = 1;
623 #endif
624 module_param(marvell_enable, int, 0644);
625 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
626
627
628 static inline int ahci_nr_ports(u32 cap)
629 {
630 return (cap & 0x1f) + 1;
631 }
632
633 static inline void __iomem *__ahci_port_base(struct ata_host *host,
634 unsigned int port_no)
635 {
636 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
637
638 return mmio + 0x100 + (port_no * 0x80);
639 }
640
641 static inline void __iomem *ahci_port_base(struct ata_port *ap)
642 {
643 return __ahci_port_base(ap->host, ap->port_no);
644 }
645
646 static void ahci_enable_ahci(void __iomem *mmio)
647 {
648 int i;
649 u32 tmp;
650
651 /* turn on AHCI_EN */
652 tmp = readl(mmio + HOST_CTL);
653 if (tmp & HOST_AHCI_EN)
654 return;
655
656 /* Some controllers need AHCI_EN to be written multiple times.
657 * Try a few times before giving up.
658 */
659 for (i = 0; i < 5; i++) {
660 tmp |= HOST_AHCI_EN;
661 writel(tmp, mmio + HOST_CTL);
662 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
663 if (tmp & HOST_AHCI_EN)
664 return;
665 msleep(10);
666 }
667
668 WARN_ON(1);
669 }
670
671 /**
672 * ahci_save_initial_config - Save and fixup initial config values
673 * @pdev: target PCI device
674 * @hpriv: host private area to store config values
675 *
676 * Some registers containing configuration info might be setup by
677 * BIOS and might be cleared on reset. This function saves the
678 * initial values of those registers into @hpriv such that they
679 * can be restored after controller reset.
680 *
681 * If inconsistent, config values are fixed up by this function.
682 *
683 * LOCKING:
684 * None.
685 */
686 static void ahci_save_initial_config(struct pci_dev *pdev,
687 struct ahci_host_priv *hpriv)
688 {
689 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
690 u32 cap, port_map;
691 int i;
692 int mv;
693
694 /* make sure AHCI mode is enabled before accessing CAP */
695 ahci_enable_ahci(mmio);
696
697 /* Values prefixed with saved_ are written back to host after
698 * reset. Values without are used for driver operation.
699 */
700 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
701 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
702
703 /* some chips have errata preventing 64bit use */
704 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
705 dev_printk(KERN_INFO, &pdev->dev,
706 "controller can't do 64bit DMA, forcing 32bit\n");
707 cap &= ~HOST_CAP_64;
708 }
709
710 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
711 dev_printk(KERN_INFO, &pdev->dev,
712 "controller can't do NCQ, turning off CAP_NCQ\n");
713 cap &= ~HOST_CAP_NCQ;
714 }
715
716 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
717 dev_printk(KERN_INFO, &pdev->dev,
718 "controller can do NCQ, turning on CAP_NCQ\n");
719 cap |= HOST_CAP_NCQ;
720 }
721
722 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
723 dev_printk(KERN_INFO, &pdev->dev,
724 "controller can't do PMP, turning off CAP_PMP\n");
725 cap &= ~HOST_CAP_PMP;
726 }
727
728 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
729 port_map != 1) {
730 dev_printk(KERN_INFO, &pdev->dev,
731 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
732 port_map, 1);
733 port_map = 1;
734 }
735
736 /*
737 * Temporary Marvell 6145 hack: PATA port presence
738 * is asserted through the standard AHCI port
739 * presence register, as bit 4 (counting from 0)
740 */
741 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
742 if (pdev->device == 0x6121)
743 mv = 0x3;
744 else
745 mv = 0xf;
746 dev_printk(KERN_ERR, &pdev->dev,
747 "MV_AHCI HACK: port_map %x -> %x\n",
748 port_map,
749 port_map & mv);
750 dev_printk(KERN_ERR, &pdev->dev,
751 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
752
753 port_map &= mv;
754 }
755
756 /* cross check port_map and cap.n_ports */
757 if (port_map) {
758 int map_ports = 0;
759
760 for (i = 0; i < AHCI_MAX_PORTS; i++)
761 if (port_map & (1 << i))
762 map_ports++;
763
764 /* If PI has more ports than n_ports, whine, clear
765 * port_map and let it be generated from n_ports.
766 */
767 if (map_ports > ahci_nr_ports(cap)) {
768 dev_printk(KERN_WARNING, &pdev->dev,
769 "implemented port map (0x%x) contains more "
770 "ports than nr_ports (%u), using nr_ports\n",
771 port_map, ahci_nr_ports(cap));
772 port_map = 0;
773 }
774 }
775
776 /* fabricate port_map from cap.nr_ports */
777 if (!port_map) {
778 port_map = (1 << ahci_nr_ports(cap)) - 1;
779 dev_printk(KERN_WARNING, &pdev->dev,
780 "forcing PORTS_IMPL to 0x%x\n", port_map);
781
782 /* write the fixed up value to the PI register */
783 hpriv->saved_port_map = port_map;
784 }
785
786 /* record values to use during operation */
787 hpriv->cap = cap;
788 hpriv->port_map = port_map;
789 }
790
791 /**
792 * ahci_restore_initial_config - Restore initial config
793 * @host: target ATA host
794 *
795 * Restore initial config stored by ahci_save_initial_config().
796 *
797 * LOCKING:
798 * None.
799 */
800 static void ahci_restore_initial_config(struct ata_host *host)
801 {
802 struct ahci_host_priv *hpriv = host->private_data;
803 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
804
805 writel(hpriv->saved_cap, mmio + HOST_CAP);
806 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
807 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
808 }
809
810 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
811 {
812 static const int offset[] = {
813 [SCR_STATUS] = PORT_SCR_STAT,
814 [SCR_CONTROL] = PORT_SCR_CTL,
815 [SCR_ERROR] = PORT_SCR_ERR,
816 [SCR_ACTIVE] = PORT_SCR_ACT,
817 [SCR_NOTIFICATION] = PORT_SCR_NTF,
818 };
819 struct ahci_host_priv *hpriv = ap->host->private_data;
820
821 if (sc_reg < ARRAY_SIZE(offset) &&
822 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
823 return offset[sc_reg];
824 return 0;
825 }
826
827 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
828 {
829 void __iomem *port_mmio = ahci_port_base(link->ap);
830 int offset = ahci_scr_offset(link->ap, sc_reg);
831
832 if (offset) {
833 *val = readl(port_mmio + offset);
834 return 0;
835 }
836 return -EINVAL;
837 }
838
839 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
840 {
841 void __iomem *port_mmio = ahci_port_base(link->ap);
842 int offset = ahci_scr_offset(link->ap, sc_reg);
843
844 if (offset) {
845 writel(val, port_mmio + offset);
846 return 0;
847 }
848 return -EINVAL;
849 }
850
851 static void ahci_start_engine(struct ata_port *ap)
852 {
853 void __iomem *port_mmio = ahci_port_base(ap);
854 u32 tmp;
855
856 /* start DMA */
857 tmp = readl(port_mmio + PORT_CMD);
858 tmp |= PORT_CMD_START;
859 writel(tmp, port_mmio + PORT_CMD);
860 readl(port_mmio + PORT_CMD); /* flush */
861 }
862
863 static int ahci_stop_engine(struct ata_port *ap)
864 {
865 void __iomem *port_mmio = ahci_port_base(ap);
866 u32 tmp;
867
868 tmp = readl(port_mmio + PORT_CMD);
869
870 /* check if the HBA is idle */
871 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
872 return 0;
873
874 /* setting HBA to idle */
875 tmp &= ~PORT_CMD_START;
876 writel(tmp, port_mmio + PORT_CMD);
877
878 /* wait for engine to stop. This could be as long as 500 msec */
879 tmp = ata_wait_register(port_mmio + PORT_CMD,
880 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
881 if (tmp & PORT_CMD_LIST_ON)
882 return -EIO;
883
884 return 0;
885 }
886
887 static void ahci_start_fis_rx(struct ata_port *ap)
888 {
889 void __iomem *port_mmio = ahci_port_base(ap);
890 struct ahci_host_priv *hpriv = ap->host->private_data;
891 struct ahci_port_priv *pp = ap->private_data;
892 u32 tmp;
893
894 /* set FIS registers */
895 if (hpriv->cap & HOST_CAP_64)
896 writel((pp->cmd_slot_dma >> 16) >> 16,
897 port_mmio + PORT_LST_ADDR_HI);
898 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
899
900 if (hpriv->cap & HOST_CAP_64)
901 writel((pp->rx_fis_dma >> 16) >> 16,
902 port_mmio + PORT_FIS_ADDR_HI);
903 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
904
905 /* enable FIS reception */
906 tmp = readl(port_mmio + PORT_CMD);
907 tmp |= PORT_CMD_FIS_RX;
908 writel(tmp, port_mmio + PORT_CMD);
909
910 /* flush */
911 readl(port_mmio + PORT_CMD);
912 }
913
914 static int ahci_stop_fis_rx(struct ata_port *ap)
915 {
916 void __iomem *port_mmio = ahci_port_base(ap);
917 u32 tmp;
918
919 /* disable FIS reception */
920 tmp = readl(port_mmio + PORT_CMD);
921 tmp &= ~PORT_CMD_FIS_RX;
922 writel(tmp, port_mmio + PORT_CMD);
923
924 /* wait for completion, spec says 500ms, give it 1000 */
925 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
926 PORT_CMD_FIS_ON, 10, 1000);
927 if (tmp & PORT_CMD_FIS_ON)
928 return -EBUSY;
929
930 return 0;
931 }
932
933 static void ahci_power_up(struct ata_port *ap)
934 {
935 struct ahci_host_priv *hpriv = ap->host->private_data;
936 void __iomem *port_mmio = ahci_port_base(ap);
937 u32 cmd;
938
939 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
940
941 /* spin up device */
942 if (hpriv->cap & HOST_CAP_SSS) {
943 cmd |= PORT_CMD_SPIN_UP;
944 writel(cmd, port_mmio + PORT_CMD);
945 }
946
947 /* wake up link */
948 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
949 }
950
951 static void ahci_disable_alpm(struct ata_port *ap)
952 {
953 struct ahci_host_priv *hpriv = ap->host->private_data;
954 void __iomem *port_mmio = ahci_port_base(ap);
955 u32 cmd;
956 struct ahci_port_priv *pp = ap->private_data;
957
958 /* IPM bits should be disabled by libata-core */
959 /* get the existing command bits */
960 cmd = readl(port_mmio + PORT_CMD);
961
962 /* disable ALPM and ASP */
963 cmd &= ~PORT_CMD_ASP;
964 cmd &= ~PORT_CMD_ALPE;
965
966 /* force the interface back to active */
967 cmd |= PORT_CMD_ICC_ACTIVE;
968
969 /* write out new cmd value */
970 writel(cmd, port_mmio + PORT_CMD);
971 cmd = readl(port_mmio + PORT_CMD);
972
973 /* wait 10ms to be sure we've come out of any low power state */
974 msleep(10);
975
976 /* clear out any PhyRdy stuff from interrupt status */
977 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
978
979 /* go ahead and clean out PhyRdy Change from Serror too */
980 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
981
982 /*
983 * Clear flag to indicate that we should ignore all PhyRdy
984 * state changes
985 */
986 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
987
988 /*
989 * Enable interrupts on Phy Ready.
990 */
991 pp->intr_mask |= PORT_IRQ_PHYRDY;
992 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
993
994 /*
995 * don't change the link pm policy - we can be called
996 * just to turn of link pm temporarily
997 */
998 }
999
1000 static int ahci_enable_alpm(struct ata_port *ap,
1001 enum link_pm policy)
1002 {
1003 struct ahci_host_priv *hpriv = ap->host->private_data;
1004 void __iomem *port_mmio = ahci_port_base(ap);
1005 u32 cmd;
1006 struct ahci_port_priv *pp = ap->private_data;
1007 u32 asp;
1008
1009 /* Make sure the host is capable of link power management */
1010 if (!(hpriv->cap & HOST_CAP_ALPM))
1011 return -EINVAL;
1012
1013 switch (policy) {
1014 case MAX_PERFORMANCE:
1015 case NOT_AVAILABLE:
1016 /*
1017 * if we came here with NOT_AVAILABLE,
1018 * it just means this is the first time we
1019 * have tried to enable - default to max performance,
1020 * and let the user go to lower power modes on request.
1021 */
1022 ahci_disable_alpm(ap);
1023 return 0;
1024 case MIN_POWER:
1025 /* configure HBA to enter SLUMBER */
1026 asp = PORT_CMD_ASP;
1027 break;
1028 case MEDIUM_POWER:
1029 /* configure HBA to enter PARTIAL */
1030 asp = 0;
1031 break;
1032 default:
1033 return -EINVAL;
1034 }
1035
1036 /*
1037 * Disable interrupts on Phy Ready. This keeps us from
1038 * getting woken up due to spurious phy ready interrupts
1039 * TBD - Hot plug should be done via polling now, is
1040 * that even supported?
1041 */
1042 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1043 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1044
1045 /*
1046 * Set a flag to indicate that we should ignore all PhyRdy
1047 * state changes since these can happen now whenever we
1048 * change link state
1049 */
1050 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1051
1052 /* get the existing command bits */
1053 cmd = readl(port_mmio + PORT_CMD);
1054
1055 /*
1056 * Set ASP based on Policy
1057 */
1058 cmd |= asp;
1059
1060 /*
1061 * Setting this bit will instruct the HBA to aggressively
1062 * enter a lower power link state when it's appropriate and
1063 * based on the value set above for ASP
1064 */
1065 cmd |= PORT_CMD_ALPE;
1066
1067 /* write out new cmd value */
1068 writel(cmd, port_mmio + PORT_CMD);
1069 cmd = readl(port_mmio + PORT_CMD);
1070
1071 /* IPM bits should be set by libata-core */
1072 return 0;
1073 }
1074
1075 #ifdef CONFIG_PM
1076 static void ahci_power_down(struct ata_port *ap)
1077 {
1078 struct ahci_host_priv *hpriv = ap->host->private_data;
1079 void __iomem *port_mmio = ahci_port_base(ap);
1080 u32 cmd, scontrol;
1081
1082 if (!(hpriv->cap & HOST_CAP_SSS))
1083 return;
1084
1085 /* put device into listen mode, first set PxSCTL.DET to 0 */
1086 scontrol = readl(port_mmio + PORT_SCR_CTL);
1087 scontrol &= ~0xf;
1088 writel(scontrol, port_mmio + PORT_SCR_CTL);
1089
1090 /* then set PxCMD.SUD to 0 */
1091 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1092 cmd &= ~PORT_CMD_SPIN_UP;
1093 writel(cmd, port_mmio + PORT_CMD);
1094 }
1095 #endif
1096
1097 static void ahci_start_port(struct ata_port *ap)
1098 {
1099 struct ahci_port_priv *pp = ap->private_data;
1100 struct ata_link *link;
1101 struct ahci_em_priv *emp;
1102
1103 /* enable FIS reception */
1104 ahci_start_fis_rx(ap);
1105
1106 /* enable DMA */
1107 ahci_start_engine(ap);
1108
1109 /* turn on LEDs */
1110 if (ap->flags & ATA_FLAG_EM) {
1111 ata_port_for_each_link(link, ap) {
1112 emp = &pp->em_priv[link->pmp];
1113 ahci_transmit_led_message(ap, emp->led_state, 4);
1114 }
1115 }
1116
1117 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
1118 ata_port_for_each_link(link, ap)
1119 ahci_init_sw_activity(link);
1120
1121 }
1122
1123 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1124 {
1125 int rc;
1126
1127 /* disable DMA */
1128 rc = ahci_stop_engine(ap);
1129 if (rc) {
1130 *emsg = "failed to stop engine";
1131 return rc;
1132 }
1133
1134 /* disable FIS reception */
1135 rc = ahci_stop_fis_rx(ap);
1136 if (rc) {
1137 *emsg = "failed stop FIS RX";
1138 return rc;
1139 }
1140
1141 return 0;
1142 }
1143
1144 static int ahci_reset_controller(struct ata_host *host)
1145 {
1146 struct pci_dev *pdev = to_pci_dev(host->dev);
1147 struct ahci_host_priv *hpriv = host->private_data;
1148 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1149 u32 tmp;
1150
1151 /* we must be in AHCI mode, before using anything
1152 * AHCI-specific, such as HOST_RESET.
1153 */
1154 ahci_enable_ahci(mmio);
1155
1156 /* global controller reset */
1157 if (!ahci_skip_host_reset) {
1158 tmp = readl(mmio + HOST_CTL);
1159 if ((tmp & HOST_RESET) == 0) {
1160 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1161 readl(mmio + HOST_CTL); /* flush */
1162 }
1163
1164 /*
1165 * to perform host reset, OS should set HOST_RESET
1166 * and poll until this bit is read to be "0".
1167 * reset must complete within 1 second, or
1168 * the hardware should be considered fried.
1169 */
1170 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1171 HOST_RESET, 10, 1000);
1172
1173 if (tmp & HOST_RESET) {
1174 dev_printk(KERN_ERR, host->dev,
1175 "controller reset failed (0x%x)\n", tmp);
1176 return -EIO;
1177 }
1178
1179 /* turn on AHCI mode */
1180 ahci_enable_ahci(mmio);
1181
1182 /* Some registers might be cleared on reset. Restore
1183 * initial values.
1184 */
1185 ahci_restore_initial_config(host);
1186 } else
1187 dev_printk(KERN_INFO, host->dev,
1188 "skipping global host reset\n");
1189
1190 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1191 u16 tmp16;
1192
1193 /* configure PCS */
1194 pci_read_config_word(pdev, 0x92, &tmp16);
1195 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1196 tmp16 |= hpriv->port_map;
1197 pci_write_config_word(pdev, 0x92, tmp16);
1198 }
1199 }
1200
1201 return 0;
1202 }
1203
1204 static void ahci_sw_activity(struct ata_link *link)
1205 {
1206 struct ata_port *ap = link->ap;
1207 struct ahci_port_priv *pp = ap->private_data;
1208 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1209
1210 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1211 return;
1212
1213 emp->activity++;
1214 if (!timer_pending(&emp->timer))
1215 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1216 }
1217
1218 static void ahci_sw_activity_blink(unsigned long arg)
1219 {
1220 struct ata_link *link = (struct ata_link *)arg;
1221 struct ata_port *ap = link->ap;
1222 struct ahci_port_priv *pp = ap->private_data;
1223 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1224 unsigned long led_message = emp->led_state;
1225 u32 activity_led_state;
1226
1227 led_message &= 0xffff0000;
1228 led_message |= ap->port_no | (link->pmp << 8);
1229
1230 /* check to see if we've had activity. If so,
1231 * toggle state of LED and reset timer. If not,
1232 * turn LED to desired idle state.
1233 */
1234 if (emp->saved_activity != emp->activity) {
1235 emp->saved_activity = emp->activity;
1236 /* get the current LED state */
1237 activity_led_state = led_message & 0x00010000;
1238
1239 if (activity_led_state)
1240 activity_led_state = 0;
1241 else
1242 activity_led_state = 1;
1243
1244 /* clear old state */
1245 led_message &= 0xfff8ffff;
1246
1247 /* toggle state */
1248 led_message |= (activity_led_state << 16);
1249 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1250 } else {
1251 /* switch to idle */
1252 led_message &= 0xfff8ffff;
1253 if (emp->blink_policy == BLINK_OFF)
1254 led_message |= (1 << 16);
1255 }
1256 ahci_transmit_led_message(ap, led_message, 4);
1257 }
1258
1259 static void ahci_init_sw_activity(struct ata_link *link)
1260 {
1261 struct ata_port *ap = link->ap;
1262 struct ahci_port_priv *pp = ap->private_data;
1263 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1264
1265 /* init activity stats, setup timer */
1266 emp->saved_activity = emp->activity = 0;
1267 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1268
1269 /* check our blink policy and set flag for link if it's enabled */
1270 if (emp->blink_policy)
1271 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1272 }
1273
1274 static int ahci_reset_em(struct ata_host *host)
1275 {
1276 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1277 u32 em_ctl;
1278
1279 em_ctl = readl(mmio + HOST_EM_CTL);
1280 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1281 return -EINVAL;
1282
1283 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1284 return 0;
1285 }
1286
1287 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1288 ssize_t size)
1289 {
1290 struct ahci_host_priv *hpriv = ap->host->private_data;
1291 struct ahci_port_priv *pp = ap->private_data;
1292 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1293 u32 em_ctl;
1294 u32 message[] = {0, 0};
1295 unsigned long flags;
1296 int pmp;
1297 struct ahci_em_priv *emp;
1298
1299 /* get the slot number from the message */
1300 pmp = (state & 0x0000ff00) >> 8;
1301 if (pmp < MAX_SLOTS)
1302 emp = &pp->em_priv[pmp];
1303 else
1304 return -EINVAL;
1305
1306 spin_lock_irqsave(ap->lock, flags);
1307
1308 /*
1309 * if we are still busy transmitting a previous message,
1310 * do not allow
1311 */
1312 em_ctl = readl(mmio + HOST_EM_CTL);
1313 if (em_ctl & EM_CTL_TM) {
1314 spin_unlock_irqrestore(ap->lock, flags);
1315 return -EINVAL;
1316 }
1317
1318 /*
1319 * create message header - this is all zero except for
1320 * the message size, which is 4 bytes.
1321 */
1322 message[0] |= (4 << 8);
1323
1324 /* ignore 0:4 of byte zero, fill in port info yourself */
1325 message[1] = ((state & 0xfffffff0) | ap->port_no);
1326
1327 /* write message to EM_LOC */
1328 writel(message[0], mmio + hpriv->em_loc);
1329 writel(message[1], mmio + hpriv->em_loc+4);
1330
1331 /* save off new led state for port/slot */
1332 emp->led_state = message[1];
1333
1334 /*
1335 * tell hardware to transmit the message
1336 */
1337 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1338
1339 spin_unlock_irqrestore(ap->lock, flags);
1340 return size;
1341 }
1342
1343 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1344 {
1345 struct ahci_port_priv *pp = ap->private_data;
1346 struct ata_link *link;
1347 struct ahci_em_priv *emp;
1348 int rc = 0;
1349
1350 ata_port_for_each_link(link, ap) {
1351 emp = &pp->em_priv[link->pmp];
1352 rc += sprintf(buf, "%lx\n", emp->led_state);
1353 }
1354 return rc;
1355 }
1356
1357 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1358 size_t size)
1359 {
1360 int state;
1361 int pmp;
1362 struct ahci_port_priv *pp = ap->private_data;
1363 struct ahci_em_priv *emp;
1364
1365 state = simple_strtoul(buf, NULL, 0);
1366
1367 /* get the slot number from the message */
1368 pmp = (state & 0x0000ff00) >> 8;
1369 if (pmp < MAX_SLOTS)
1370 emp = &pp->em_priv[pmp];
1371 else
1372 return -EINVAL;
1373
1374 /* mask off the activity bits if we are in sw_activity
1375 * mode, user should turn off sw_activity before setting
1376 * activity led through em_message
1377 */
1378 if (emp->blink_policy)
1379 state &= 0xfff8ffff;
1380
1381 return ahci_transmit_led_message(ap, state, size);
1382 }
1383
1384 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1385 {
1386 struct ata_link *link = dev->link;
1387 struct ata_port *ap = link->ap;
1388 struct ahci_port_priv *pp = ap->private_data;
1389 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1390 u32 port_led_state = emp->led_state;
1391
1392 /* save the desired Activity LED behavior */
1393 if (val == OFF) {
1394 /* clear LFLAG */
1395 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1396
1397 /* set the LED to OFF */
1398 port_led_state &= 0xfff80000;
1399 port_led_state |= (ap->port_no | (link->pmp << 8));
1400 ahci_transmit_led_message(ap, port_led_state, 4);
1401 } else {
1402 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1403 if (val == BLINK_OFF) {
1404 /* set LED to ON for idle */
1405 port_led_state &= 0xfff80000;
1406 port_led_state |= (ap->port_no | (link->pmp << 8));
1407 port_led_state |= 0x00010000; /* check this */
1408 ahci_transmit_led_message(ap, port_led_state, 4);
1409 }
1410 }
1411 emp->blink_policy = val;
1412 return 0;
1413 }
1414
1415 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1416 {
1417 struct ata_link *link = dev->link;
1418 struct ata_port *ap = link->ap;
1419 struct ahci_port_priv *pp = ap->private_data;
1420 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1421
1422 /* display the saved value of activity behavior for this
1423 * disk.
1424 */
1425 return sprintf(buf, "%d\n", emp->blink_policy);
1426 }
1427
1428 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1429 int port_no, void __iomem *mmio,
1430 void __iomem *port_mmio)
1431 {
1432 const char *emsg = NULL;
1433 int rc;
1434 u32 tmp;
1435
1436 /* make sure port is not active */
1437 rc = ahci_deinit_port(ap, &emsg);
1438 if (rc)
1439 dev_printk(KERN_WARNING, &pdev->dev,
1440 "%s (%d)\n", emsg, rc);
1441
1442 /* clear SError */
1443 tmp = readl(port_mmio + PORT_SCR_ERR);
1444 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1445 writel(tmp, port_mmio + PORT_SCR_ERR);
1446
1447 /* clear port IRQ */
1448 tmp = readl(port_mmio + PORT_IRQ_STAT);
1449 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1450 if (tmp)
1451 writel(tmp, port_mmio + PORT_IRQ_STAT);
1452
1453 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1454 }
1455
1456 static void ahci_init_controller(struct ata_host *host)
1457 {
1458 struct ahci_host_priv *hpriv = host->private_data;
1459 struct pci_dev *pdev = to_pci_dev(host->dev);
1460 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1461 int i;
1462 void __iomem *port_mmio;
1463 u32 tmp;
1464 int mv;
1465
1466 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1467 if (pdev->device == 0x6121)
1468 mv = 2;
1469 else
1470 mv = 4;
1471 port_mmio = __ahci_port_base(host, mv);
1472
1473 writel(0, port_mmio + PORT_IRQ_MASK);
1474
1475 /* clear port IRQ */
1476 tmp = readl(port_mmio + PORT_IRQ_STAT);
1477 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1478 if (tmp)
1479 writel(tmp, port_mmio + PORT_IRQ_STAT);
1480 }
1481
1482 for (i = 0; i < host->n_ports; i++) {
1483 struct ata_port *ap = host->ports[i];
1484
1485 port_mmio = ahci_port_base(ap);
1486 if (ata_port_is_dummy(ap))
1487 continue;
1488
1489 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1490 }
1491
1492 tmp = readl(mmio + HOST_CTL);
1493 VPRINTK("HOST_CTL 0x%x\n", tmp);
1494 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1495 tmp = readl(mmio + HOST_CTL);
1496 VPRINTK("HOST_CTL 0x%x\n", tmp);
1497 }
1498
1499 static void ahci_dev_config(struct ata_device *dev)
1500 {
1501 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1502
1503 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1504 dev->max_sectors = 255;
1505 ata_dev_printk(dev, KERN_INFO,
1506 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1507 }
1508 }
1509
1510 static unsigned int ahci_dev_classify(struct ata_port *ap)
1511 {
1512 void __iomem *port_mmio = ahci_port_base(ap);
1513 struct ata_taskfile tf;
1514 u32 tmp;
1515
1516 tmp = readl(port_mmio + PORT_SIG);
1517 tf.lbah = (tmp >> 24) & 0xff;
1518 tf.lbam = (tmp >> 16) & 0xff;
1519 tf.lbal = (tmp >> 8) & 0xff;
1520 tf.nsect = (tmp) & 0xff;
1521
1522 return ata_dev_classify(&tf);
1523 }
1524
1525 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1526 u32 opts)
1527 {
1528 dma_addr_t cmd_tbl_dma;
1529
1530 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1531
1532 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1533 pp->cmd_slot[tag].status = 0;
1534 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1535 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1536 }
1537
1538 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1539 {
1540 void __iomem *port_mmio = ahci_port_base(ap);
1541 struct ahci_host_priv *hpriv = ap->host->private_data;
1542 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1543 u32 tmp;
1544 int busy, rc;
1545
1546 /* do we need to kick the port? */
1547 busy = status & (ATA_BUSY | ATA_DRQ);
1548 if (!busy && !force_restart)
1549 return 0;
1550
1551 /* stop engine */
1552 rc = ahci_stop_engine(ap);
1553 if (rc)
1554 goto out_restart;
1555
1556 /* need to do CLO? */
1557 if (!busy) {
1558 rc = 0;
1559 goto out_restart;
1560 }
1561
1562 if (!(hpriv->cap & HOST_CAP_CLO)) {
1563 rc = -EOPNOTSUPP;
1564 goto out_restart;
1565 }
1566
1567 /* perform CLO */
1568 tmp = readl(port_mmio + PORT_CMD);
1569 tmp |= PORT_CMD_CLO;
1570 writel(tmp, port_mmio + PORT_CMD);
1571
1572 rc = 0;
1573 tmp = ata_wait_register(port_mmio + PORT_CMD,
1574 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1575 if (tmp & PORT_CMD_CLO)
1576 rc = -EIO;
1577
1578 /* restart engine */
1579 out_restart:
1580 ahci_start_engine(ap);
1581 return rc;
1582 }
1583
1584 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1585 struct ata_taskfile *tf, int is_cmd, u16 flags,
1586 unsigned long timeout_msec)
1587 {
1588 const u32 cmd_fis_len = 5; /* five dwords */
1589 struct ahci_port_priv *pp = ap->private_data;
1590 void __iomem *port_mmio = ahci_port_base(ap);
1591 u8 *fis = pp->cmd_tbl;
1592 u32 tmp;
1593
1594 /* prep the command */
1595 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1596 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1597
1598 /* issue & wait */
1599 writel(1, port_mmio + PORT_CMD_ISSUE);
1600
1601 if (timeout_msec) {
1602 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1603 1, timeout_msec);
1604 if (tmp & 0x1) {
1605 ahci_kick_engine(ap, 1);
1606 return -EBUSY;
1607 }
1608 } else
1609 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1610
1611 return 0;
1612 }
1613
1614 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1615 int pmp, unsigned long deadline,
1616 int (*check_ready)(struct ata_link *link))
1617 {
1618 struct ata_port *ap = link->ap;
1619 const char *reason = NULL;
1620 unsigned long now, msecs;
1621 struct ata_taskfile tf;
1622 int rc;
1623
1624 DPRINTK("ENTER\n");
1625
1626 /* prepare for SRST (AHCI-1.1 10.4.1) */
1627 rc = ahci_kick_engine(ap, 1);
1628 if (rc && rc != -EOPNOTSUPP)
1629 ata_link_printk(link, KERN_WARNING,
1630 "failed to reset engine (errno=%d)\n", rc);
1631
1632 ata_tf_init(link->device, &tf);
1633
1634 /* issue the first D2H Register FIS */
1635 msecs = 0;
1636 now = jiffies;
1637 if (time_after(now, deadline))
1638 msecs = jiffies_to_msecs(deadline - now);
1639
1640 tf.ctl |= ATA_SRST;
1641 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1642 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1643 rc = -EIO;
1644 reason = "1st FIS failed";
1645 goto fail;
1646 }
1647
1648 /* spec says at least 5us, but be generous and sleep for 1ms */
1649 msleep(1);
1650
1651 /* issue the second D2H Register FIS */
1652 tf.ctl &= ~ATA_SRST;
1653 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1654
1655 /* wait for link to become ready */
1656 rc = ata_wait_after_reset(link, deadline, check_ready);
1657 /* link occupied, -ENODEV too is an error */
1658 if (rc) {
1659 reason = "device not ready";
1660 goto fail;
1661 }
1662 *class = ahci_dev_classify(ap);
1663
1664 DPRINTK("EXIT, class=%u\n", *class);
1665 return 0;
1666
1667 fail:
1668 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1669 return rc;
1670 }
1671
1672 static int ahci_check_ready(struct ata_link *link)
1673 {
1674 void __iomem *port_mmio = ahci_port_base(link->ap);
1675 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1676
1677 return ata_check_ready(status);
1678 }
1679
1680 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1681 unsigned long deadline)
1682 {
1683 int pmp = sata_srst_pmp(link);
1684
1685 DPRINTK("ENTER\n");
1686
1687 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1688 }
1689
1690 static int ahci_sb600_check_ready(struct ata_link *link)
1691 {
1692 void __iomem *port_mmio = ahci_port_base(link->ap);
1693 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1694 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1695
1696 /*
1697 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1698 * which can save timeout delay.
1699 */
1700 if (irq_status & PORT_IRQ_BAD_PMP)
1701 return -EIO;
1702
1703 return ata_check_ready(status);
1704 }
1705
1706 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1707 unsigned long deadline)
1708 {
1709 struct ata_port *ap = link->ap;
1710 void __iomem *port_mmio = ahci_port_base(ap);
1711 int pmp = sata_srst_pmp(link);
1712 int rc;
1713 u32 irq_sts;
1714
1715 DPRINTK("ENTER\n");
1716
1717 rc = ahci_do_softreset(link, class, pmp, deadline,
1718 ahci_sb600_check_ready);
1719
1720 /*
1721 * Soft reset fails on some ATI chips with IPMS set when PMP
1722 * is enabled but SATA HDD/ODD is connected to SATA port,
1723 * do soft reset again to port 0.
1724 */
1725 if (rc == -EIO) {
1726 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1727 if (irq_sts & PORT_IRQ_BAD_PMP) {
1728 ata_link_printk(link, KERN_WARNING,
1729 "failed due to HW bug, retry pmp=0\n");
1730 rc = ahci_do_softreset(link, class, 0, deadline,
1731 ahci_check_ready);
1732 }
1733 }
1734
1735 return rc;
1736 }
1737
1738 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1739 unsigned long deadline)
1740 {
1741 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1742 struct ata_port *ap = link->ap;
1743 struct ahci_port_priv *pp = ap->private_data;
1744 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1745 struct ata_taskfile tf;
1746 bool online;
1747 int rc;
1748
1749 DPRINTK("ENTER\n");
1750
1751 ahci_stop_engine(ap);
1752
1753 /* clear D2H reception area to properly wait for D2H FIS */
1754 ata_tf_init(link->device, &tf);
1755 tf.command = 0x80;
1756 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1757
1758 rc = sata_link_hardreset(link, timing, deadline, &online,
1759 ahci_check_ready);
1760
1761 ahci_start_engine(ap);
1762
1763 if (online)
1764 *class = ahci_dev_classify(ap);
1765
1766 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1767 return rc;
1768 }
1769
1770 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1771 unsigned long deadline)
1772 {
1773 struct ata_port *ap = link->ap;
1774 bool online;
1775 int rc;
1776
1777 DPRINTK("ENTER\n");
1778
1779 ahci_stop_engine(ap);
1780
1781 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1782 deadline, &online, NULL);
1783
1784 ahci_start_engine(ap);
1785
1786 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1787
1788 /* vt8251 doesn't clear BSY on signature FIS reception,
1789 * request follow-up softreset.
1790 */
1791 return online ? -EAGAIN : rc;
1792 }
1793
1794 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1795 unsigned long deadline)
1796 {
1797 struct ata_port *ap = link->ap;
1798 struct ahci_port_priv *pp = ap->private_data;
1799 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1800 struct ata_taskfile tf;
1801 bool online;
1802 int rc;
1803
1804 ahci_stop_engine(ap);
1805
1806 /* clear D2H reception area to properly wait for D2H FIS */
1807 ata_tf_init(link->device, &tf);
1808 tf.command = 0x80;
1809 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1810
1811 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1812 deadline, &online, NULL);
1813
1814 ahci_start_engine(ap);
1815
1816 /* The pseudo configuration device on SIMG4726 attached to
1817 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1818 * hardreset if no device is attached to the first downstream
1819 * port && the pseudo device locks up on SRST w/ PMP==0. To
1820 * work around this, wait for !BSY only briefly. If BSY isn't
1821 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1822 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1823 *
1824 * Wait for two seconds. Devices attached to downstream port
1825 * which can't process the following IDENTIFY after this will
1826 * have to be reset again. For most cases, this should
1827 * suffice while making probing snappish enough.
1828 */
1829 if (online) {
1830 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1831 ahci_check_ready);
1832 if (rc)
1833 ahci_kick_engine(ap, 0);
1834 }
1835 return rc;
1836 }
1837
1838 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1839 {
1840 struct ata_port *ap = link->ap;
1841 void __iomem *port_mmio = ahci_port_base(ap);
1842 u32 new_tmp, tmp;
1843
1844 ata_std_postreset(link, class);
1845
1846 /* Make sure port's ATAPI bit is set appropriately */
1847 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1848 if (*class == ATA_DEV_ATAPI)
1849 new_tmp |= PORT_CMD_ATAPI;
1850 else
1851 new_tmp &= ~PORT_CMD_ATAPI;
1852 if (new_tmp != tmp) {
1853 writel(new_tmp, port_mmio + PORT_CMD);
1854 readl(port_mmio + PORT_CMD); /* flush */
1855 }
1856 }
1857
1858 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1859 {
1860 struct scatterlist *sg;
1861 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1862 unsigned int si;
1863
1864 VPRINTK("ENTER\n");
1865
1866 /*
1867 * Next, the S/G list.
1868 */
1869 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1870 dma_addr_t addr = sg_dma_address(sg);
1871 u32 sg_len = sg_dma_len(sg);
1872
1873 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1874 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1875 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1876 }
1877
1878 return si;
1879 }
1880
1881 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1882 {
1883 struct ata_port *ap = qc->ap;
1884 struct ahci_port_priv *pp = ap->private_data;
1885 int is_atapi = ata_is_atapi(qc->tf.protocol);
1886 void *cmd_tbl;
1887 u32 opts;
1888 const u32 cmd_fis_len = 5; /* five dwords */
1889 unsigned int n_elem;
1890
1891 /*
1892 * Fill in command table information. First, the header,
1893 * a SATA Register - Host to Device command FIS.
1894 */
1895 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1896
1897 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1898 if (is_atapi) {
1899 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1900 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1901 }
1902
1903 n_elem = 0;
1904 if (qc->flags & ATA_QCFLAG_DMAMAP)
1905 n_elem = ahci_fill_sg(qc, cmd_tbl);
1906
1907 /*
1908 * Fill in command slot information.
1909 */
1910 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1911 if (qc->tf.flags & ATA_TFLAG_WRITE)
1912 opts |= AHCI_CMD_WRITE;
1913 if (is_atapi)
1914 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1915
1916 ahci_fill_cmd_slot(pp, qc->tag, opts);
1917 }
1918
1919 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1920 {
1921 struct ahci_host_priv *hpriv = ap->host->private_data;
1922 struct ahci_port_priv *pp = ap->private_data;
1923 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1924 struct ata_link *link = NULL;
1925 struct ata_queued_cmd *active_qc;
1926 struct ata_eh_info *active_ehi;
1927 u32 serror;
1928
1929 /* determine active link */
1930 ata_port_for_each_link(link, ap)
1931 if (ata_link_active(link))
1932 break;
1933 if (!link)
1934 link = &ap->link;
1935
1936 active_qc = ata_qc_from_tag(ap, link->active_tag);
1937 active_ehi = &link->eh_info;
1938
1939 /* record irq stat */
1940 ata_ehi_clear_desc(host_ehi);
1941 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1942
1943 /* AHCI needs SError cleared; otherwise, it might lock up */
1944 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1945 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1946 host_ehi->serror |= serror;
1947
1948 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1949 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1950 irq_stat &= ~PORT_IRQ_IF_ERR;
1951
1952 if (irq_stat & PORT_IRQ_TF_ERR) {
1953 /* If qc is active, charge it; otherwise, the active
1954 * link. There's no active qc on NCQ errors. It will
1955 * be determined by EH by reading log page 10h.
1956 */
1957 if (active_qc)
1958 active_qc->err_mask |= AC_ERR_DEV;
1959 else
1960 active_ehi->err_mask |= AC_ERR_DEV;
1961
1962 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1963 host_ehi->serror &= ~SERR_INTERNAL;
1964 }
1965
1966 if (irq_stat & PORT_IRQ_UNK_FIS) {
1967 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1968
1969 active_ehi->err_mask |= AC_ERR_HSM;
1970 active_ehi->action |= ATA_EH_RESET;
1971 ata_ehi_push_desc(active_ehi,
1972 "unknown FIS %08x %08x %08x %08x" ,
1973 unk[0], unk[1], unk[2], unk[3]);
1974 }
1975
1976 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1977 active_ehi->err_mask |= AC_ERR_HSM;
1978 active_ehi->action |= ATA_EH_RESET;
1979 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1980 }
1981
1982 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1983 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1984 host_ehi->action |= ATA_EH_RESET;
1985 ata_ehi_push_desc(host_ehi, "host bus error");
1986 }
1987
1988 if (irq_stat & PORT_IRQ_IF_ERR) {
1989 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1990 host_ehi->action |= ATA_EH_RESET;
1991 ata_ehi_push_desc(host_ehi, "interface fatal error");
1992 }
1993
1994 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1995 ata_ehi_hotplugged(host_ehi);
1996 ata_ehi_push_desc(host_ehi, "%s",
1997 irq_stat & PORT_IRQ_CONNECT ?
1998 "connection status changed" : "PHY RDY changed");
1999 }
2000
2001 /* okay, let's hand over to EH */
2002
2003 if (irq_stat & PORT_IRQ_FREEZE)
2004 ata_port_freeze(ap);
2005 else
2006 ata_port_abort(ap);
2007 }
2008
2009 static void ahci_port_intr(struct ata_port *ap)
2010 {
2011 void __iomem *port_mmio = ahci_port_base(ap);
2012 struct ata_eh_info *ehi = &ap->link.eh_info;
2013 struct ahci_port_priv *pp = ap->private_data;
2014 struct ahci_host_priv *hpriv = ap->host->private_data;
2015 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
2016 u32 status, qc_active;
2017 int rc;
2018
2019 status = readl(port_mmio + PORT_IRQ_STAT);
2020 writel(status, port_mmio + PORT_IRQ_STAT);
2021
2022 /* ignore BAD_PMP while resetting */
2023 if (unlikely(resetting))
2024 status &= ~PORT_IRQ_BAD_PMP;
2025
2026 /* If we are getting PhyRdy, this is
2027 * just a power state change, we should
2028 * clear out this, plus the PhyRdy/Comm
2029 * Wake bits from Serror
2030 */
2031 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2032 (status & PORT_IRQ_PHYRDY)) {
2033 status &= ~PORT_IRQ_PHYRDY;
2034 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
2035 }
2036
2037 if (unlikely(status & PORT_IRQ_ERROR)) {
2038 ahci_error_intr(ap, status);
2039 return;
2040 }
2041
2042 if (status & PORT_IRQ_SDB_FIS) {
2043 /* If SNotification is available, leave notification
2044 * handling to sata_async_notification(). If not,
2045 * emulate it by snooping SDB FIS RX area.
2046 *
2047 * Snooping FIS RX area is probably cheaper than
2048 * poking SNotification but some constrollers which
2049 * implement SNotification, ICH9 for example, don't
2050 * store AN SDB FIS into receive area.
2051 */
2052 if (hpriv->cap & HOST_CAP_SNTF)
2053 sata_async_notification(ap);
2054 else {
2055 /* If the 'N' bit in word 0 of the FIS is set,
2056 * we just received asynchronous notification.
2057 * Tell libata about it.
2058 */
2059 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2060 u32 f0 = le32_to_cpu(f[0]);
2061
2062 if (f0 & (1 << 15))
2063 sata_async_notification(ap);
2064 }
2065 }
2066
2067 /* pp->active_link is valid iff any command is in flight */
2068 if (ap->qc_active && pp->active_link->sactive)
2069 qc_active = readl(port_mmio + PORT_SCR_ACT);
2070 else
2071 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2072
2073 rc = ata_qc_complete_multiple(ap, qc_active);
2074
2075 /* while resetting, invalid completions are expected */
2076 if (unlikely(rc < 0 && !resetting)) {
2077 ehi->err_mask |= AC_ERR_HSM;
2078 ehi->action |= ATA_EH_RESET;
2079 ata_port_freeze(ap);
2080 }
2081 }
2082
2083 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
2084 {
2085 struct ata_host *host = dev_instance;
2086 struct ahci_host_priv *hpriv;
2087 unsigned int i, handled = 0;
2088 void __iomem *mmio;
2089 u32 irq_stat, irq_masked;
2090
2091 VPRINTK("ENTER\n");
2092
2093 hpriv = host->private_data;
2094 mmio = host->iomap[AHCI_PCI_BAR];
2095
2096 /* sigh. 0xffffffff is a valid return from h/w */
2097 irq_stat = readl(mmio + HOST_IRQ_STAT);
2098 if (!irq_stat)
2099 return IRQ_NONE;
2100
2101 irq_masked = irq_stat & hpriv->port_map;
2102
2103 spin_lock(&host->lock);
2104
2105 for (i = 0; i < host->n_ports; i++) {
2106 struct ata_port *ap;
2107
2108 if (!(irq_masked & (1 << i)))
2109 continue;
2110
2111 ap = host->ports[i];
2112 if (ap) {
2113 ahci_port_intr(ap);
2114 VPRINTK("port %u\n", i);
2115 } else {
2116 VPRINTK("port %u (no irq)\n", i);
2117 if (ata_ratelimit())
2118 dev_printk(KERN_WARNING, host->dev,
2119 "interrupt on disabled port %u\n", i);
2120 }
2121
2122 handled = 1;
2123 }
2124
2125 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2126 * it should be cleared after all the port events are cleared;
2127 * otherwise, it will raise a spurious interrupt after each
2128 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2129 * information.
2130 *
2131 * Also, use the unmasked value to clear interrupt as spurious
2132 * pending event on a dummy port might cause screaming IRQ.
2133 */
2134 writel(irq_stat, mmio + HOST_IRQ_STAT);
2135
2136 spin_unlock(&host->lock);
2137
2138 VPRINTK("EXIT\n");
2139
2140 return IRQ_RETVAL(handled);
2141 }
2142
2143 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
2144 {
2145 struct ata_port *ap = qc->ap;
2146 void __iomem *port_mmio = ahci_port_base(ap);
2147 struct ahci_port_priv *pp = ap->private_data;
2148
2149 /* Keep track of the currently active link. It will be used
2150 * in completion path to determine whether NCQ phase is in
2151 * progress.
2152 */
2153 pp->active_link = qc->dev->link;
2154
2155 if (qc->tf.protocol == ATA_PROT_NCQ)
2156 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2157 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
2158
2159 ahci_sw_activity(qc->dev->link);
2160
2161 return 0;
2162 }
2163
2164 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2165 {
2166 struct ahci_port_priv *pp = qc->ap->private_data;
2167 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2168
2169 ata_tf_from_fis(d2h_fis, &qc->result_tf);
2170 return true;
2171 }
2172
2173 static void ahci_freeze(struct ata_port *ap)
2174 {
2175 void __iomem *port_mmio = ahci_port_base(ap);
2176
2177 /* turn IRQ off */
2178 writel(0, port_mmio + PORT_IRQ_MASK);
2179 }
2180
2181 static void ahci_thaw(struct ata_port *ap)
2182 {
2183 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
2184 void __iomem *port_mmio = ahci_port_base(ap);
2185 u32 tmp;
2186 struct ahci_port_priv *pp = ap->private_data;
2187
2188 /* clear IRQ */
2189 tmp = readl(port_mmio + PORT_IRQ_STAT);
2190 writel(tmp, port_mmio + PORT_IRQ_STAT);
2191 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2192
2193 /* turn IRQ back on */
2194 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2195 }
2196
2197 static void ahci_error_handler(struct ata_port *ap)
2198 {
2199 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2200 /* restart engine */
2201 ahci_stop_engine(ap);
2202 ahci_start_engine(ap);
2203 }
2204
2205 sata_pmp_error_handler(ap);
2206 }
2207
2208 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2209 {
2210 struct ata_port *ap = qc->ap;
2211
2212 /* make DMA engine forget about the failed command */
2213 if (qc->flags & ATA_QCFLAG_FAILED)
2214 ahci_kick_engine(ap, 1);
2215 }
2216
2217 static void ahci_pmp_attach(struct ata_port *ap)
2218 {
2219 void __iomem *port_mmio = ahci_port_base(ap);
2220 struct ahci_port_priv *pp = ap->private_data;
2221 u32 cmd;
2222
2223 cmd = readl(port_mmio + PORT_CMD);
2224 cmd |= PORT_CMD_PMP;
2225 writel(cmd, port_mmio + PORT_CMD);
2226
2227 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2228 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2229 }
2230
2231 static void ahci_pmp_detach(struct ata_port *ap)
2232 {
2233 void __iomem *port_mmio = ahci_port_base(ap);
2234 struct ahci_port_priv *pp = ap->private_data;
2235 u32 cmd;
2236
2237 cmd = readl(port_mmio + PORT_CMD);
2238 cmd &= ~PORT_CMD_PMP;
2239 writel(cmd, port_mmio + PORT_CMD);
2240
2241 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2242 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2243 }
2244
2245 static int ahci_port_resume(struct ata_port *ap)
2246 {
2247 ahci_power_up(ap);
2248 ahci_start_port(ap);
2249
2250 if (sata_pmp_attached(ap))
2251 ahci_pmp_attach(ap);
2252 else
2253 ahci_pmp_detach(ap);
2254
2255 return 0;
2256 }
2257
2258 #ifdef CONFIG_PM
2259 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2260 {
2261 const char *emsg = NULL;
2262 int rc;
2263
2264 rc = ahci_deinit_port(ap, &emsg);
2265 if (rc == 0)
2266 ahci_power_down(ap);
2267 else {
2268 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
2269 ahci_start_port(ap);
2270 }
2271
2272 return rc;
2273 }
2274
2275 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2276 {
2277 struct ata_host *host = dev_get_drvdata(&pdev->dev);
2278 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2279 u32 ctl;
2280
2281 if (mesg.event & PM_EVENT_SLEEP) {
2282 /* AHCI spec rev1.1 section 8.3.3:
2283 * Software must disable interrupts prior to requesting a
2284 * transition of the HBA to D3 state.
2285 */
2286 ctl = readl(mmio + HOST_CTL);
2287 ctl &= ~HOST_IRQ_EN;
2288 writel(ctl, mmio + HOST_CTL);
2289 readl(mmio + HOST_CTL); /* flush */
2290 }
2291
2292 return ata_pci_device_suspend(pdev, mesg);
2293 }
2294
2295 static int ahci_pci_device_resume(struct pci_dev *pdev)
2296 {
2297 struct ata_host *host = dev_get_drvdata(&pdev->dev);
2298 int rc;
2299
2300 rc = ata_pci_device_do_resume(pdev);
2301 if (rc)
2302 return rc;
2303
2304 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
2305 rc = ahci_reset_controller(host);
2306 if (rc)
2307 return rc;
2308
2309 ahci_init_controller(host);
2310 }
2311
2312 ata_host_resume(host);
2313
2314 return 0;
2315 }
2316 #endif
2317
2318 static int ahci_port_start(struct ata_port *ap)
2319 {
2320 struct device *dev = ap->host->dev;
2321 struct ahci_port_priv *pp;
2322 void *mem;
2323 dma_addr_t mem_dma;
2324
2325 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2326 if (!pp)
2327 return -ENOMEM;
2328
2329 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2330 GFP_KERNEL);
2331 if (!mem)
2332 return -ENOMEM;
2333 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2334
2335 /*
2336 * First item in chunk of DMA memory: 32-slot command table,
2337 * 32 bytes each in size
2338 */
2339 pp->cmd_slot = mem;
2340 pp->cmd_slot_dma = mem_dma;
2341
2342 mem += AHCI_CMD_SLOT_SZ;
2343 mem_dma += AHCI_CMD_SLOT_SZ;
2344
2345 /*
2346 * Second item: Received-FIS area
2347 */
2348 pp->rx_fis = mem;
2349 pp->rx_fis_dma = mem_dma;
2350
2351 mem += AHCI_RX_FIS_SZ;
2352 mem_dma += AHCI_RX_FIS_SZ;
2353
2354 /*
2355 * Third item: data area for storing a single command
2356 * and its scatter-gather table
2357 */
2358 pp->cmd_tbl = mem;
2359 pp->cmd_tbl_dma = mem_dma;
2360
2361 /*
2362 * Save off initial list of interrupts to be enabled.
2363 * This could be changed later
2364 */
2365 pp->intr_mask = DEF_PORT_IRQ;
2366
2367 ap->private_data = pp;
2368
2369 /* engage engines, captain */
2370 return ahci_port_resume(ap);
2371 }
2372
2373 static void ahci_port_stop(struct ata_port *ap)
2374 {
2375 const char *emsg = NULL;
2376 int rc;
2377
2378 /* de-initialize port */
2379 rc = ahci_deinit_port(ap, &emsg);
2380 if (rc)
2381 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2382 }
2383
2384 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2385 {
2386 int rc;
2387
2388 if (using_dac &&
2389 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2390 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2391 if (rc) {
2392 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2393 if (rc) {
2394 dev_printk(KERN_ERR, &pdev->dev,
2395 "64-bit DMA enable failed\n");
2396 return rc;
2397 }
2398 }
2399 } else {
2400 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2401 if (rc) {
2402 dev_printk(KERN_ERR, &pdev->dev,
2403 "32-bit DMA enable failed\n");
2404 return rc;
2405 }
2406 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2407 if (rc) {
2408 dev_printk(KERN_ERR, &pdev->dev,
2409 "32-bit consistent DMA enable failed\n");
2410 return rc;
2411 }
2412 }
2413 return 0;
2414 }
2415
2416 static void ahci_print_info(struct ata_host *host)
2417 {
2418 struct ahci_host_priv *hpriv = host->private_data;
2419 struct pci_dev *pdev = to_pci_dev(host->dev);
2420 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2421 u32 vers, cap, impl, speed;
2422 const char *speed_s;
2423 u16 cc;
2424 const char *scc_s;
2425
2426 vers = readl(mmio + HOST_VERSION);
2427 cap = hpriv->cap;
2428 impl = hpriv->port_map;
2429
2430 speed = (cap >> 20) & 0xf;
2431 if (speed == 1)
2432 speed_s = "1.5";
2433 else if (speed == 2)
2434 speed_s = "3";
2435 else
2436 speed_s = "?";
2437
2438 pci_read_config_word(pdev, 0x0a, &cc);
2439 if (cc == PCI_CLASS_STORAGE_IDE)
2440 scc_s = "IDE";
2441 else if (cc == PCI_CLASS_STORAGE_SATA)
2442 scc_s = "SATA";
2443 else if (cc == PCI_CLASS_STORAGE_RAID)
2444 scc_s = "RAID";
2445 else
2446 scc_s = "unknown";
2447
2448 dev_printk(KERN_INFO, &pdev->dev,
2449 "AHCI %02x%02x.%02x%02x "
2450 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2451 ,
2452
2453 (vers >> 24) & 0xff,
2454 (vers >> 16) & 0xff,
2455 (vers >> 8) & 0xff,
2456 vers & 0xff,
2457
2458 ((cap >> 8) & 0x1f) + 1,
2459 (cap & 0x1f) + 1,
2460 speed_s,
2461 impl,
2462 scc_s);
2463
2464 dev_printk(KERN_INFO, &pdev->dev,
2465 "flags: "
2466 "%s%s%s%s%s%s%s"
2467 "%s%s%s%s%s%s%s"
2468 "%s\n"
2469 ,
2470
2471 cap & (1 << 31) ? "64bit " : "",
2472 cap & (1 << 30) ? "ncq " : "",
2473 cap & (1 << 29) ? "sntf " : "",
2474 cap & (1 << 28) ? "ilck " : "",
2475 cap & (1 << 27) ? "stag " : "",
2476 cap & (1 << 26) ? "pm " : "",
2477 cap & (1 << 25) ? "led " : "",
2478
2479 cap & (1 << 24) ? "clo " : "",
2480 cap & (1 << 19) ? "nz " : "",
2481 cap & (1 << 18) ? "only " : "",
2482 cap & (1 << 17) ? "pmp " : "",
2483 cap & (1 << 15) ? "pio " : "",
2484 cap & (1 << 14) ? "slum " : "",
2485 cap & (1 << 13) ? "part " : "",
2486 cap & (1 << 6) ? "ems ": ""
2487 );
2488 }
2489
2490 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2491 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2492 * support PMP and the 4726 either directly exports the device
2493 * attached to the first downstream port or acts as a hardware storage
2494 * controller and emulate a single ATA device (can be RAID 0/1 or some
2495 * other configuration).
2496 *
2497 * When there's no device attached to the first downstream port of the
2498 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2499 * configure the 4726. However, ATA emulation of the device is very
2500 * lame. It doesn't send signature D2H Reg FIS after the initial
2501 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2502 *
2503 * The following function works around the problem by always using
2504 * hardreset on the port and not depending on receiving signature FIS
2505 * afterward. If signature FIS isn't received soon, ATA class is
2506 * assumed without follow-up softreset.
2507 */
2508 static void ahci_p5wdh_workaround(struct ata_host *host)
2509 {
2510 static struct dmi_system_id sysids[] = {
2511 {
2512 .ident = "P5W DH Deluxe",
2513 .matches = {
2514 DMI_MATCH(DMI_SYS_VENDOR,
2515 "ASUSTEK COMPUTER INC"),
2516 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2517 },
2518 },
2519 { }
2520 };
2521 struct pci_dev *pdev = to_pci_dev(host->dev);
2522
2523 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2524 dmi_check_system(sysids)) {
2525 struct ata_port *ap = host->ports[1];
2526
2527 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2528 "Deluxe on-board SIMG4726 workaround\n");
2529
2530 ap->ops = &ahci_p5wdh_ops;
2531 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2532 }
2533 }
2534
2535 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2536 {
2537 static int printed_version;
2538 unsigned int board_id = ent->driver_data;
2539 struct ata_port_info pi = ahci_port_info[board_id];
2540 const struct ata_port_info *ppi[] = { &pi, NULL };
2541 struct device *dev = &pdev->dev;
2542 struct ahci_host_priv *hpriv;
2543 struct ata_host *host;
2544 int n_ports, i, rc;
2545
2546 VPRINTK("ENTER\n");
2547
2548 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2549
2550 if (!printed_version++)
2551 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2552
2553 /* The AHCI driver can only drive the SATA ports, the PATA driver
2554 can drive them all so if both drivers are selected make sure
2555 AHCI stays out of the way */
2556 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
2557 return -ENODEV;
2558
2559 /* acquire resources */
2560 rc = pcim_enable_device(pdev);
2561 if (rc)
2562 return rc;
2563
2564 /* AHCI controllers often implement SFF compatible interface.
2565 * Grab all PCI BARs just in case.
2566 */
2567 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2568 if (rc == -EBUSY)
2569 pcim_pin_device(pdev);
2570 if (rc)
2571 return rc;
2572
2573 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2574 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2575 u8 map;
2576
2577 /* ICH6s share the same PCI ID for both piix and ahci
2578 * modes. Enabling ahci mode while MAP indicates
2579 * combined mode is a bad idea. Yield to ata_piix.
2580 */
2581 pci_read_config_byte(pdev, ICH_MAP, &map);
2582 if (map & 0x3) {
2583 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2584 "combined mode, can't enable AHCI mode\n");
2585 return -ENODEV;
2586 }
2587 }
2588
2589 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2590 if (!hpriv)
2591 return -ENOMEM;
2592 hpriv->flags |= (unsigned long)pi.private_data;
2593
2594 /* MCP65 revision A1 and A2 can't do MSI */
2595 if (board_id == board_ahci_mcp65 &&
2596 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2597 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2598
2599 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2600 pci_intx(pdev, 1);
2601
2602 /* save initial config */
2603 ahci_save_initial_config(pdev, hpriv);
2604
2605 /* prepare host */
2606 if (hpriv->cap & HOST_CAP_NCQ)
2607 pi.flags |= ATA_FLAG_NCQ;
2608
2609 if (hpriv->cap & HOST_CAP_PMP)
2610 pi.flags |= ATA_FLAG_PMP;
2611
2612 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
2613 u8 messages;
2614 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
2615 u32 em_loc = readl(mmio + HOST_EM_LOC);
2616 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2617
2618 messages = (em_ctl & 0x000f0000) >> 16;
2619
2620 /* we only support LED message type right now */
2621 if ((messages & 0x01) && (ahci_em_messages == 1)) {
2622 /* store em_loc */
2623 hpriv->em_loc = ((em_loc >> 16) * 4);
2624 pi.flags |= ATA_FLAG_EM;
2625 if (!(em_ctl & EM_CTL_ALHD))
2626 pi.flags |= ATA_FLAG_SW_ACTIVITY;
2627 }
2628 }
2629
2630 /* CAP.NP sometimes indicate the index of the last enabled
2631 * port, at other times, that of the last possible port, so
2632 * determining the maximum port number requires looking at
2633 * both CAP.NP and port_map.
2634 */
2635 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2636
2637 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2638 if (!host)
2639 return -ENOMEM;
2640 host->iomap = pcim_iomap_table(pdev);
2641 host->private_data = hpriv;
2642
2643 if (pi.flags & ATA_FLAG_EM)
2644 ahci_reset_em(host);
2645
2646 for (i = 0; i < host->n_ports; i++) {
2647 struct ata_port *ap = host->ports[i];
2648
2649 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2650 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2651 0x100 + ap->port_no * 0x80, "port");
2652
2653 /* set initial link pm policy */
2654 ap->pm_policy = NOT_AVAILABLE;
2655
2656 /* set enclosure management message type */
2657 if (ap->flags & ATA_FLAG_EM)
2658 ap->em_message_type = ahci_em_messages;
2659
2660
2661 /* disabled/not-implemented port */
2662 if (!(hpriv->port_map & (1 << i)))
2663 ap->ops = &ata_dummy_port_ops;
2664 }
2665
2666 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2667 ahci_p5wdh_workaround(host);
2668
2669 /* initialize adapter */
2670 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2671 if (rc)
2672 return rc;
2673
2674 rc = ahci_reset_controller(host);
2675 if (rc)
2676 return rc;
2677
2678 ahci_init_controller(host);
2679 ahci_print_info(host);
2680
2681 pci_set_master(pdev);
2682 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2683 &ahci_sht);
2684 }
2685
2686 static int __init ahci_init(void)
2687 {
2688 return pci_register_driver(&ahci_pci_driver);
2689 }
2690
2691 static void __exit ahci_exit(void)
2692 {
2693 pci_unregister_driver(&ahci_pci_driver);
2694 }
2695
2696
2697 MODULE_AUTHOR("Jeff Garzik");
2698 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2699 MODULE_LICENSE("GPL");
2700 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2701 MODULE_VERSION(DRV_VERSION);
2702
2703 module_init(ahci_init);
2704 module_exit(ahci_exit);
x86 "subsystem" repository