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[IA64] clean up asm/intel_intrin.h
[linux-2.6/x86.git] / drivers / pci / hotplug / shpchp_hpc.c
blobb4226ff3a8544bd2740786f99d15698bc49435e4
1 /*
2 * Standard PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/interrupt.h>
35
36 #include "shpchp.h"
37
38 #ifdef DEBUG
39 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
40 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
41 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
42 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
43 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
44 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
45 /* Redefine this flagword to set debug level */
46 #define DEBUG_LEVEL DBG_K_STANDARD
47
48 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
49
50 #define DBG_PRINT( dbg_flags, args... ) \
51 do { \
52 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
53 { \
54 int len; \
55 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
56 __FILE__, __LINE__, __FUNCTION__ ); \
57 sprintf( __dbg_str_buf + len, args ); \
58 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
59 } \
60 } while (0)
61
62 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
63 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
64 #else
65 #define DEFINE_DBG_BUFFER
66 #define DBG_ENTER_ROUTINE
67 #define DBG_LEAVE_ROUTINE
68 #endif /* DEBUG */
69
70 /* Slot Available Register I field definition */
71 #define SLOT_33MHZ 0x0000001f
72 #define SLOT_66MHZ_PCIX 0x00001f00
73 #define SLOT_100MHZ_PCIX 0x001f0000
74 #define SLOT_133MHZ_PCIX 0x1f000000
75
76 /* Slot Available Register II field definition */
77 #define SLOT_66MHZ 0x0000001f
78 #define SLOT_66MHZ_PCIX_266 0x00000f00
79 #define SLOT_100MHZ_PCIX_266 0x0000f000
80 #define SLOT_133MHZ_PCIX_266 0x000f0000
81 #define SLOT_66MHZ_PCIX_533 0x00f00000
82 #define SLOT_100MHZ_PCIX_533 0x0f000000
83 #define SLOT_133MHZ_PCIX_533 0xf0000000
84
85
86 /* Secondary Bus Configuration Register */
87 /* For PI = 1, Bits 0 to 2 have been encoded as follows to show current bus speed/mode */
88 #define PCI_33MHZ 0x0
89 #define PCI_66MHZ 0x1
90 #define PCIX_66MHZ 0x2
91 #define PCIX_100MHZ 0x3
92 #define PCIX_133MHZ 0x4
93
94 /* For PI = 2, Bits 0 to 3 have been encoded as follows to show current bus speed/mode */
95 #define PCI_33MHZ 0x0
96 #define PCI_66MHZ 0x1
97 #define PCIX_66MHZ 0x2
98 #define PCIX_100MHZ 0x3
99 #define PCIX_133MHZ 0x4
100 #define PCIX_66MHZ_ECC 0x5
101 #define PCIX_100MHZ_ECC 0x6
102 #define PCIX_133MHZ_ECC 0x7
103 #define PCIX_66MHZ_266 0x9
104 #define PCIX_100MHZ_266 0xa
105 #define PCIX_133MHZ_266 0xb
106 #define PCIX_66MHZ_533 0x11
107 #define PCIX_100MHZ_533 0x12
108 #define PCIX_133MHZ_533 0x13
109
110 /* Slot Configuration */
111 #define SLOT_NUM 0x0000001F
112 #define FIRST_DEV_NUM 0x00001F00
113 #define PSN 0x07FF0000
114 #define UPDOWN 0x20000000
115 #define MRLSENSOR 0x40000000
116 #define ATTN_BUTTON 0x80000000
117
118 /* Slot Status Field Definitions */
119 /* Slot State */
120 #define PWR_ONLY 0x0001
121 #define ENABLED 0x0002
122 #define DISABLED 0x0003
123
124 /* Power Indicator State */
125 #define PWR_LED_ON 0x0004
126 #define PWR_LED_BLINK 0x0008
127 #define PWR_LED_OFF 0x000c
128
129 /* Attention Indicator State */
130 #define ATTEN_LED_ON 0x0010
131 #define ATTEN_LED_BLINK 0x0020
132 #define ATTEN_LED_OFF 0x0030
133
134 /* Power Fault */
135 #define pwr_fault 0x0040
136
137 /* Attention Button */
138 #define ATTEN_BUTTON 0x0080
139
140 /* MRL Sensor */
141 #define MRL_SENSOR 0x0100
142
143 /* 66 MHz Capable */
144 #define IS_66MHZ_CAP 0x0200
145
146 /* PRSNT1#/PRSNT2# */
147 #define SLOT_EMP 0x0c00
148
149 /* PCI-X Capability */
150 #define NON_PCIX 0x0000
151 #define PCIX_66 0x1000
152 #define PCIX_133 0x3000
153 #define PCIX_266 0x4000 /* For PI = 2 only */
154 #define PCIX_533 0x5000 /* For PI = 2 only */
155
156 /* SHPC 'write' operations/commands */
157
158 /* Slot operation - 0x00h to 0x3Fh */
159
160 #define NO_CHANGE 0x00
161
162 /* Slot state - Bits 0 & 1 of controller command register */
163 #define SET_SLOT_PWR 0x01
164 #define SET_SLOT_ENABLE 0x02
165 #define SET_SLOT_DISABLE 0x03
166
167 /* Power indicator state - Bits 2 & 3 of controller command register*/
168 #define SET_PWR_ON 0x04
169 #define SET_PWR_BLINK 0x08
170 #define SET_PWR_OFF 0x0C
171
172 /* Attention indicator state - Bits 4 & 5 of controller command register*/
173 #define SET_ATTN_ON 0x010
174 #define SET_ATTN_BLINK 0x020
175 #define SET_ATTN_OFF 0x030
176
177 /* Set bus speed/mode A - 0x40h to 0x47h */
178 #define SETA_PCI_33MHZ 0x40
179 #define SETA_PCI_66MHZ 0x41
180 #define SETA_PCIX_66MHZ 0x42
181 #define SETA_PCIX_100MHZ 0x43
182 #define SETA_PCIX_133MHZ 0x44
183 #define RESERV_1 0x45
184 #define RESERV_2 0x46
185 #define RESERV_3 0x47
186
187 /* Set bus speed/mode B - 0x50h to 0x5fh */
188 #define SETB_PCI_33MHZ 0x50
189 #define SETB_PCI_66MHZ 0x51
190 #define SETB_PCIX_66MHZ_PM 0x52
191 #define SETB_PCIX_100MHZ_PM 0x53
192 #define SETB_PCIX_133MHZ_PM 0x54
193 #define SETB_PCIX_66MHZ_EM 0x55
194 #define SETB_PCIX_100MHZ_EM 0x56
195 #define SETB_PCIX_133MHZ_EM 0x57
196 #define SETB_PCIX_66MHZ_266 0x58
197 #define SETB_PCIX_100MHZ_266 0x59
198 #define SETB_PCIX_133MHZ_266 0x5a
199 #define SETB_PCIX_66MHZ_533 0x5b
200 #define SETB_PCIX_100MHZ_533 0x5c
201 #define SETB_PCIX_133MHZ_533 0x5d
202
203
204 /* Power-on all slots - 0x48h */
205 #define SET_PWR_ON_ALL 0x48
206
207 /* Enable all slots - 0x49h */
208 #define SET_ENABLE_ALL 0x49
209
210 /* SHPC controller command error code */
211 #define SWITCH_OPEN 0x1
212 #define INVALID_CMD 0x2
213 #define INVALID_SPEED_MODE 0x4
214
215 /* For accessing SHPC Working Register Set */
216 #define DWORD_SELECT 0x2
217 #define DWORD_DATA 0x4
218 #define BASE_OFFSET 0x0
219
220 /* Field Offset in Logical Slot Register - byte boundary */
221 #define SLOT_EVENT_LATCH 0x2
222 #define SLOT_SERR_INT_MASK 0x3
223
224 static spinlock_t hpc_event_lock;
225
226 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
227 static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */
228 static int ctlr_seq_num = 0; /* Controller sequenc # */
229 static spinlock_t list_lock;
230
231 static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs);
232
233 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds);
234
235 /* This is the interrupt polling timeout function. */
236 static void int_poll_timeout(unsigned long lphp_ctlr)
237 {
238 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr;
239
240 DBG_ENTER_ROUTINE
241
242 if ( !php_ctlr ) {
243 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
244 return;
245 }
246
247 /* Poll for interrupt events. regs == NULL => polling */
248 shpc_isr( 0, (void *)php_ctlr, NULL );
249
250 init_timer(&php_ctlr->int_poll_timer);
251 if (!shpchp_poll_time)
252 shpchp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
253
254 start_int_poll_timer(php_ctlr, shpchp_poll_time);
255
256 return;
257 }
258
259 /* This function starts the interrupt polling timer. */
260 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds)
261 {
262 if (!php_ctlr) {
263 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
264 return;
265 }
266
267 if ( ( seconds <= 0 ) || ( seconds > 60 ) )
268 seconds = 2; /* Clamp to sane value */
269
270 php_ctlr->int_poll_timer.function = &int_poll_timeout;
271 php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */
272 php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ;
273 add_timer(&php_ctlr->int_poll_timer);
274
275 return;
276 }
277
278 static inline int shpc_wait_cmd(struct controller *ctrl)
279 {
280 int retval = 0;
281 unsigned int timeout_msec = shpchp_poll_mode ? 2000 : 1000;
282 unsigned long timeout = msecs_to_jiffies(timeout_msec);
283 int rc = wait_event_interruptible_timeout(ctrl->queue,
284 !ctrl->cmd_busy, timeout);
285 if (!rc) {
286 retval = -EIO;
287 err("Command not completed in %d msec\n", timeout_msec);
288 } else if (rc < 0) {
289 retval = -EINTR;
290 info("Command was interrupted by a signal\n");
291 }
292 ctrl->cmd_busy = 0;
293
294 return retval;
295 }
296
297 static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
298 {
299 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
300 u16 cmd_status;
301 int retval = 0;
302 u16 temp_word;
303 int i;
304
305 DBG_ENTER_ROUTINE
306
307 if (!php_ctlr) {
308 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
309 return -1;
310 }
311
312 for (i = 0; i < 10; i++) {
313 cmd_status = readw(php_ctlr->creg + CMD_STATUS);
314
315 if (!(cmd_status & 0x1))
316 break;
317 /* Check every 0.1 sec for a total of 1 sec*/
318 msleep(100);
319 }
320
321 cmd_status = readw(php_ctlr->creg + CMD_STATUS);
322
323 if (cmd_status & 0x1) {
324 /* After 1 sec and and the controller is still busy */
325 err("%s : Controller is still busy after 1 sec.\n", __FUNCTION__);
326 return -1;
327 }
328
329 ++t_slot;
330 temp_word = (t_slot << 8) | (cmd & 0xFF);
331 dbg("%s: t_slot %x cmd %x\n", __FUNCTION__, t_slot, cmd);
332
333 /* To make sure the Controller Busy bit is 0 before we send out the
334 * command.
335 */
336 slot->ctrl->cmd_busy = 1;
337 writew(temp_word, php_ctlr->creg + CMD);
338
339 /*
340 * Wait for command completion.
341 */
342 retval = shpc_wait_cmd(slot->ctrl);
343
344 DBG_LEAVE_ROUTINE
345 return retval;
346 }
347
348 static int hpc_check_cmd_status(struct controller *ctrl)
349 {
350 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
351 u16 cmd_status;
352 int retval = 0;
353
354 DBG_ENTER_ROUTINE
355
356 if (!ctrl->hpc_ctlr_handle) {
357 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
358 return -1;
359 }
360
361 cmd_status = readw(php_ctlr->creg + CMD_STATUS) & 0x000F;
362
363 switch (cmd_status >> 1) {
364 case 0:
365 retval = 0;
366 break;
367 case 1:
368 retval = SWITCH_OPEN;
369 err("%s: Switch opened!\n", __FUNCTION__);
370 break;
371 case 2:
372 retval = INVALID_CMD;
373 err("%s: Invalid HPC command!\n", __FUNCTION__);
374 break;
375 case 4:
376 retval = INVALID_SPEED_MODE;
377 err("%s: Invalid bus speed/mode!\n", __FUNCTION__);
378 break;
379 default:
380 retval = cmd_status;
381 }
382
383 DBG_LEAVE_ROUTINE
384 return retval;
385 }
386
387
388 static int hpc_get_attention_status(struct slot *slot, u8 *status)
389 {
390 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
391 u32 slot_reg;
392 u16 slot_status;
393 u8 atten_led_state;
394
395 DBG_ENTER_ROUTINE
396
397 if (!slot->ctrl->hpc_ctlr_handle) {
398 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
399 return -1;
400 }
401
402 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
403 slot_status = (u16) slot_reg;
404 atten_led_state = (slot_status & 0x0030) >> 4;
405
406 switch (atten_led_state) {
407 case 0:
408 *status = 0xFF; /* Reserved */
409 break;
410 case 1:
411 *status = 1; /* On */
412 break;
413 case 2:
414 *status = 2; /* Blink */
415 break;
416 case 3:
417 *status = 0; /* Off */
418 break;
419 default:
420 *status = 0xFF;
421 break;
422 }
423
424 DBG_LEAVE_ROUTINE
425 return 0;
426 }
427
428 static int hpc_get_power_status(struct slot * slot, u8 *status)
429 {
430 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
431 u32 slot_reg;
432 u16 slot_status;
433 u8 slot_state;
434 int retval = 0;
435
436 DBG_ENTER_ROUTINE
437
438 if (!slot->ctrl->hpc_ctlr_handle) {
439 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
440 return -1;
441 }
442
443 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
444 slot_status = (u16) slot_reg;
445 slot_state = (slot_status & 0x0003);
446
447 switch (slot_state) {
448 case 0:
449 *status = 0xFF;
450 break;
451 case 1:
452 *status = 2; /* Powered only */
453 break;
454 case 2:
455 *status = 1; /* Enabled */
456 break;
457 case 3:
458 *status = 0; /* Disabled */
459 break;
460 default:
461 *status = 0xFF;
462 break;
463 }
464
465 DBG_LEAVE_ROUTINE
466 return retval;
467 }
468
469
470 static int hpc_get_latch_status(struct slot *slot, u8 *status)
471 {
472 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
473 u32 slot_reg;
474 u16 slot_status;
475
476 DBG_ENTER_ROUTINE
477
478 if (!slot->ctrl->hpc_ctlr_handle) {
479 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
480 return -1;
481 }
482
483 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
484 slot_status = (u16)slot_reg;
485
486 *status = ((slot_status & 0x0100) == 0) ? 0 : 1; /* 0 -> close; 1 -> open */
487
488
489 DBG_LEAVE_ROUTINE
490 return 0;
491 }
492
493 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
494 {
495 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
496 u32 slot_reg;
497 u16 slot_status;
498 u8 card_state;
499
500 DBG_ENTER_ROUTINE
501
502 if (!slot->ctrl->hpc_ctlr_handle) {
503 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
504 return -1;
505 }
506
507 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
508 slot_status = (u16)slot_reg;
509 card_state = (u8)((slot_status & 0x0C00) >> 10);
510 *status = (card_state != 0x3) ? 1 : 0;
511
512 DBG_LEAVE_ROUTINE
513 return 0;
514 }
515
516 static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
517 {
518 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
519
520 DBG_ENTER_ROUTINE
521
522 if (!slot->ctrl->hpc_ctlr_handle) {
523 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
524 return -1;
525 }
526
527 *prog_int = readb(php_ctlr->creg + PROG_INTERFACE);
528
529 DBG_LEAVE_ROUTINE
530 return 0;
531 }
532
533 static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
534 {
535 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
536 u32 slot_reg;
537 u16 slot_status, sec_bus_status;
538 u8 m66_cap, pcix_cap, pi;
539 int retval = 0;
540
541 DBG_ENTER_ROUTINE
542
543 if (!slot->ctrl->hpc_ctlr_handle) {
544 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
545 return -1;
546 }
547
548 if (slot->hp_slot >= php_ctlr->num_slots) {
549 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
550 return -1;
551 }
552
553 pi = readb(php_ctlr->creg + PROG_INTERFACE);
554 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
555 dbg("%s: pi = %d, slot_reg = %x\n", __FUNCTION__, pi, slot_reg);
556 slot_status = (u16) slot_reg;
557 dbg("%s: slot_status = %x\n", __FUNCTION__, slot_status);
558 sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG);
559
560 pcix_cap = (u8) ((slot_status & 0x3000) >> 12);
561 dbg("%s: pcix_cap = %x\n", __FUNCTION__, pcix_cap);
562 m66_cap = (u8) ((slot_status & 0x0200) >> 9);
563 dbg("%s: m66_cap = %x\n", __FUNCTION__, m66_cap);
564
565
566 if (pi == 2) {
567 switch (pcix_cap) {
568 case 0:
569 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
570 break;
571 case 1:
572 *value = PCI_SPEED_66MHz_PCIX;
573 break;
574 case 3:
575 *value = PCI_SPEED_133MHz_PCIX;
576 break;
577 case 4:
578 *value = PCI_SPEED_133MHz_PCIX_266;
579 break;
580 case 5:
581 *value = PCI_SPEED_133MHz_PCIX_533;
582 break;
583 case 2: /* Reserved */
584 default:
585 *value = PCI_SPEED_UNKNOWN;
586 retval = -ENODEV;
587 break;
588 }
589 } else {
590 switch (pcix_cap) {
591 case 0:
592 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
593 break;
594 case 1:
595 *value = PCI_SPEED_66MHz_PCIX;
596 break;
597 case 3:
598 *value = PCI_SPEED_133MHz_PCIX;
599 break;
600 case 2: /* Reserved */
601 default:
602 *value = PCI_SPEED_UNKNOWN;
603 retval = -ENODEV;
604 break;
605 }
606 }
607
608 dbg("Adapter speed = %d\n", *value);
609
610 DBG_LEAVE_ROUTINE
611 return retval;
612 }
613
614 static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
615 {
616 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
617 u16 sec_bus_status;
618 u8 pi;
619 int retval = 0;
620
621 DBG_ENTER_ROUTINE
622
623 if (!slot->ctrl->hpc_ctlr_handle) {
624 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
625 return -1;
626 }
627
628 pi = readb(php_ctlr->creg + PROG_INTERFACE);
629 sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG);
630
631 if (pi == 2) {
632 *mode = (sec_bus_status & 0x0100) >> 8;
633 } else {
634 retval = -1;
635 }
636
637 dbg("Mode 1 ECC cap = %d\n", *mode);
638
639 DBG_LEAVE_ROUTINE
640 return retval;
641 }
642
643 static int hpc_query_power_fault(struct slot * slot)
644 {
645 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
646 u32 slot_reg;
647 u16 slot_status;
648 u8 pwr_fault_state, status;
649
650 DBG_ENTER_ROUTINE
651
652 if (!slot->ctrl->hpc_ctlr_handle) {
653 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
654 return -1;
655 }
656
657 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
658 slot_status = (u16) slot_reg;
659 pwr_fault_state = (slot_status & 0x0040) >> 7;
660 status = (pwr_fault_state == 1) ? 0 : 1;
661
662 DBG_LEAVE_ROUTINE
663 /* Note: Logic 0 => fault */
664 return status;
665 }
666
667 static int hpc_set_attention_status(struct slot *slot, u8 value)
668 {
669 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
670 u8 slot_cmd = 0;
671 int rc = 0;
672
673 if (!slot->ctrl->hpc_ctlr_handle) {
674 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
675 return -1;
676 }
677
678 if (slot->hp_slot >= php_ctlr->num_slots) {
679 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
680 return -1;
681 }
682
683 switch (value) {
684 case 0 :
685 slot_cmd = 0x30; /* OFF */
686 break;
687 case 1:
688 slot_cmd = 0x10; /* ON */
689 break;
690 case 2:
691 slot_cmd = 0x20; /* BLINK */
692 break;
693 default:
694 return -1;
695 }
696
697 shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
698
699 return rc;
700 }
701
702
703 static void hpc_set_green_led_on(struct slot *slot)
704 {
705 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
706 u8 slot_cmd;
707
708 if (!slot->ctrl->hpc_ctlr_handle) {
709 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
710 return ;
711 }
712
713 if (slot->hp_slot >= php_ctlr->num_slots) {
714 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
715 return ;
716 }
717
718 slot_cmd = 0x04;
719
720 shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
721
722 return;
723 }
724
725 static void hpc_set_green_led_off(struct slot *slot)
726 {
727 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
728 u8 slot_cmd;
729
730 if (!slot->ctrl->hpc_ctlr_handle) {
731 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
732 return ;
733 }
734
735 if (slot->hp_slot >= php_ctlr->num_slots) {
736 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
737 return ;
738 }
739
740 slot_cmd = 0x0C;
741
742 shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
743
744 return;
745 }
746
747 static void hpc_set_green_led_blink(struct slot *slot)
748 {
749 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
750 u8 slot_cmd;
751
752 if (!slot->ctrl->hpc_ctlr_handle) {
753 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
754 return ;
755 }
756
757 if (slot->hp_slot >= php_ctlr->num_slots) {
758 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
759 return ;
760 }
761
762 slot_cmd = 0x08;
763
764 shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
765
766 return;
767 }
768
769 int shpc_get_ctlr_slot_config(struct controller *ctrl,
770 int *num_ctlr_slots, /* number of slots in this HPC */
771 int *first_device_num, /* PCI dev num of the first slot in this SHPC */
772 int *physical_slot_num, /* phy slot num of the first slot in this SHPC */
773 int *updown, /* physical_slot_num increament: 1 or -1 */
774 int *flags)
775 {
776 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
777
778 DBG_ENTER_ROUTINE
779
780 if (!ctrl->hpc_ctlr_handle) {
781 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
782 return -1;
783 }
784
785 *first_device_num = php_ctlr->slot_device_offset; /* Obtained in shpc_init() */
786 *num_ctlr_slots = php_ctlr->num_slots; /* Obtained in shpc_init() */
787
788 *physical_slot_num = (readl(php_ctlr->creg + SLOT_CONFIG) & PSN) >> 16;
789 dbg("%s: physical_slot_num = %x\n", __FUNCTION__, *physical_slot_num);
790 *updown = ((readl(php_ctlr->creg + SLOT_CONFIG) & UPDOWN ) >> 29) ? 1 : -1;
791
792 DBG_LEAVE_ROUTINE
793 return 0;
794 }
795
796 static void hpc_release_ctlr(struct controller *ctrl)
797 {
798 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
799 struct php_ctlr_state_s *p, *p_prev;
800
801 DBG_ENTER_ROUTINE
802
803 if (!ctrl->hpc_ctlr_handle) {
804 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
805 return ;
806 }
807
808 if (shpchp_poll_mode) {
809 del_timer(&php_ctlr->int_poll_timer);
810 } else {
811 if (php_ctlr->irq) {
812 free_irq(php_ctlr->irq, ctrl);
813 php_ctlr->irq = 0;
814 pci_disable_msi(php_ctlr->pci_dev);
815 }
816 }
817 if (php_ctlr->pci_dev) {
818 iounmap(php_ctlr->creg);
819 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
820 php_ctlr->pci_dev = NULL;
821 }
822
823 spin_lock(&list_lock);
824 p = php_ctlr_list_head;
825 p_prev = NULL;
826 while (p) {
827 if (p == php_ctlr) {
828 if (p_prev)
829 p_prev->pnext = p->pnext;
830 else
831 php_ctlr_list_head = p->pnext;
832 break;
833 } else {
834 p_prev = p;
835 p = p->pnext;
836 }
837 }
838 spin_unlock(&list_lock);
839
840 kfree(php_ctlr);
841
842 DBG_LEAVE_ROUTINE
843
844 }
845
846 static int hpc_power_on_slot(struct slot * slot)
847 {
848 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
849 u8 slot_cmd;
850 int retval = 0;
851
852 DBG_ENTER_ROUTINE
853
854 if (!slot->ctrl->hpc_ctlr_handle) {
855 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
856 return -1;
857 }
858
859 if (slot->hp_slot >= php_ctlr->num_slots) {
860 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
861 return -1;
862 }
863 slot_cmd = 0x01;
864
865 retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
866
867 if (retval) {
868 err("%s: Write command failed!\n", __FUNCTION__);
869 return -1;
870 }
871
872 DBG_LEAVE_ROUTINE
873
874 return retval;
875 }
876
877 static int hpc_slot_enable(struct slot * slot)
878 {
879 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
880 u8 slot_cmd;
881 int retval = 0;
882
883 DBG_ENTER_ROUTINE
884
885 if (!slot->ctrl->hpc_ctlr_handle) {
886 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
887 return -1;
888 }
889
890 if (slot->hp_slot >= php_ctlr->num_slots) {
891 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
892 return -1;
893 }
894 /* 3A => Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
895 slot_cmd = 0x3A;
896
897 retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
898
899 if (retval) {
900 err("%s: Write command failed!\n", __FUNCTION__);
901 return -1;
902 }
903
904 DBG_LEAVE_ROUTINE
905 return retval;
906 }
907
908 static int hpc_slot_disable(struct slot * slot)
909 {
910 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
911 u8 slot_cmd;
912 int retval = 0;
913
914 DBG_ENTER_ROUTINE
915
916 if (!slot->ctrl->hpc_ctlr_handle) {
917 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
918 return -1;
919 }
920
921 if (slot->hp_slot >= php_ctlr->num_slots) {
922 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
923 return -1;
924 }
925
926 /* 1F => Slot - Disable, Power Indicator - Off, Attention Indicator - On */
927 slot_cmd = 0x1F;
928
929 retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
930
931 if (retval) {
932 err("%s: Write command failed!\n", __FUNCTION__);
933 return -1;
934 }
935
936 DBG_LEAVE_ROUTINE
937 return retval;
938 }
939
940 static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
941 {
942 u8 slot_cmd;
943 u8 pi;
944 int retval = 0;
945 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
946
947 DBG_ENTER_ROUTINE
948
949 if (!slot->ctrl->hpc_ctlr_handle) {
950 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
951 return -1;
952 }
953
954 pi = readb(php_ctlr->creg + PROG_INTERFACE);
955
956 if (pi == 1) {
957 switch (value) {
958 case 0:
959 slot_cmd = SETA_PCI_33MHZ;
960 break;
961 case 1:
962 slot_cmd = SETA_PCI_66MHZ;
963 break;
964 case 2:
965 slot_cmd = SETA_PCIX_66MHZ;
966 break;
967 case 3:
968 slot_cmd = SETA_PCIX_100MHZ;
969 break;
970 case 4:
971 slot_cmd = SETA_PCIX_133MHZ;
972 break;
973 default:
974 slot_cmd = PCI_SPEED_UNKNOWN;
975 retval = -ENODEV;
976 return retval;
977 }
978 } else {
979 switch (value) {
980 case 0:
981 slot_cmd = SETB_PCI_33MHZ;
982 break;
983 case 1:
984 slot_cmd = SETB_PCI_66MHZ;
985 break;
986 case 2:
987 slot_cmd = SETB_PCIX_66MHZ_PM;
988 break;
989 case 3:
990 slot_cmd = SETB_PCIX_100MHZ_PM;
991 break;
992 case 4:
993 slot_cmd = SETB_PCIX_133MHZ_PM;
994 break;
995 case 5:
996 slot_cmd = SETB_PCIX_66MHZ_EM;
997 break;
998 case 6:
999 slot_cmd = SETB_PCIX_100MHZ_EM;
1000 break;
1001 case 7:
1002 slot_cmd = SETB_PCIX_133MHZ_EM;
1003 break;
1004 case 8:
1005 slot_cmd = SETB_PCIX_66MHZ_266;
1006 break;
1007 case 0x9:
1008 slot_cmd = SETB_PCIX_100MHZ_266;
1009 break;
1010 case 0xa:
1011 slot_cmd = SETB_PCIX_133MHZ_266;
1012 break;
1013 case 0xb:
1014 slot_cmd = SETB_PCIX_66MHZ_533;
1015 break;
1016 case 0xc:
1017 slot_cmd = SETB_PCIX_100MHZ_533;
1018 break;
1019 case 0xd:
1020 slot_cmd = SETB_PCIX_133MHZ_533;
1021 break;
1022 default:
1023 slot_cmd = PCI_SPEED_UNKNOWN;
1024 retval = -ENODEV;
1025 return retval;
1026 }
1027
1028 }
1029 retval = shpc_write_cmd(slot, 0, slot_cmd);
1030 if (retval) {
1031 err("%s: Write command failed!\n", __FUNCTION__);
1032 return -1;
1033 }
1034
1035 DBG_LEAVE_ROUTINE
1036 return retval;
1037 }
1038
1039 static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
1040 {
1041 struct controller *ctrl = NULL;
1042 struct php_ctlr_state_s *php_ctlr;
1043 u8 schedule_flag = 0;
1044 u8 temp_byte;
1045 u32 temp_dword, intr_loc, intr_loc2;
1046 int hp_slot;
1047
1048 if (!dev_id)
1049 return IRQ_NONE;
1050
1051 if (!shpchp_poll_mode) {
1052 ctrl = (struct controller *)dev_id;
1053 php_ctlr = ctrl->hpc_ctlr_handle;
1054 } else {
1055 php_ctlr = (struct php_ctlr_state_s *) dev_id;
1056 ctrl = (struct controller *)php_ctlr->callback_instance_id;
1057 }
1058
1059 if (!ctrl)
1060 return IRQ_NONE;
1061
1062 if (!php_ctlr || !php_ctlr->creg)
1063 return IRQ_NONE;
1064
1065 /* Check to see if it was our interrupt */
1066 intr_loc = readl(php_ctlr->creg + INTR_LOC);
1067
1068 if (!intr_loc)
1069 return IRQ_NONE;
1070 dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc);
1071
1072 if(!shpchp_poll_mode) {
1073 /* Mask Global Interrupt Mask - see implementation note on p. 139 */
1074 /* of SHPC spec rev 1.0*/
1075 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1076 temp_dword |= 0x00000001;
1077 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
1078
1079 intr_loc2 = readl(php_ctlr->creg + INTR_LOC);
1080 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
1081 }
1082
1083 if (intr_loc & 0x0001) {
1084 /*
1085 * Command Complete Interrupt Pending
1086 * RO only - clear by writing 1 to the Command Completion
1087 * Detect bit in Controller SERR-INT register
1088 */
1089 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1090 temp_dword &= 0xfffdffff;
1091 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
1092 ctrl->cmd_busy = 0;
1093 wake_up_interruptible(&ctrl->queue);
1094 }
1095
1096 if ((intr_loc = (intr_loc >> 1)) == 0) {
1097 /* Unmask Global Interrupt Mask */
1098 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1099 temp_dword &= 0xfffffffe;
1100 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
1101
1102 return IRQ_NONE;
1103 }
1104
1105 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1106 /* To find out which slot has interrupt pending */
1107 if ((intr_loc >> hp_slot) & 0x01) {
1108 temp_dword = readl(php_ctlr->creg + SLOT1 + (4*hp_slot));
1109 dbg("%s: Slot %x with intr, slot register = %x\n",
1110 __FUNCTION__, hp_slot, temp_dword);
1111 temp_byte = (temp_dword >> 16) & 0xFF;
1112 if ((php_ctlr->switch_change_callback) && (temp_byte & 0x08))
1113 schedule_flag += php_ctlr->switch_change_callback(
1114 hp_slot, php_ctlr->callback_instance_id);
1115 if ((php_ctlr->attention_button_callback) && (temp_byte & 0x04))
1116 schedule_flag += php_ctlr->attention_button_callback(
1117 hp_slot, php_ctlr->callback_instance_id);
1118 if ((php_ctlr->presence_change_callback) && (temp_byte & 0x01))
1119 schedule_flag += php_ctlr->presence_change_callback(
1120 hp_slot , php_ctlr->callback_instance_id);
1121 if ((php_ctlr->power_fault_callback) && (temp_byte & 0x12))
1122 schedule_flag += php_ctlr->power_fault_callback(
1123 hp_slot, php_ctlr->callback_instance_id);
1124
1125 /* Clear all slot events */
1126 temp_dword = 0xe01f3fff;
1127 writel(temp_dword, php_ctlr->creg + SLOT1 + (4*hp_slot));
1128
1129 intr_loc2 = readl(php_ctlr->creg + INTR_LOC);
1130 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
1131 }
1132 }
1133 if (!shpchp_poll_mode) {
1134 /* Unmask Global Interrupt Mask */
1135 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1136 temp_dword &= 0xfffffffe;
1137 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
1138 }
1139
1140 return IRQ_HANDLED;
1141 }
1142
1143 static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1144 {
1145 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1146 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
1147 int retval = 0;
1148 u8 pi;
1149 u32 slot_avail1, slot_avail2;
1150
1151 DBG_ENTER_ROUTINE
1152
1153 if (!slot->ctrl->hpc_ctlr_handle) {
1154 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1155 return -1;
1156 }
1157
1158 if (slot->hp_slot >= php_ctlr->num_slots) {
1159 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1160 return -1;
1161 }
1162
1163 pi = readb(php_ctlr->creg + PROG_INTERFACE);
1164 slot_avail1 = readl(php_ctlr->creg + SLOT_AVAIL1);
1165 slot_avail2 = readl(php_ctlr->creg + SLOT_AVAIL2);
1166
1167 if (pi == 2) {
1168 if (slot_avail2 & SLOT_133MHZ_PCIX_533)
1169 bus_speed = PCIX_133MHZ_533;
1170 else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
1171 bus_speed = PCIX_100MHZ_533;
1172 else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
1173 bus_speed = PCIX_66MHZ_533;
1174 else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
1175 bus_speed = PCIX_133MHZ_266;
1176 else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
1177 bus_speed = PCIX_100MHZ_266;
1178 else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
1179 bus_speed = PCIX_66MHZ_266;
1180 else if (slot_avail1 & SLOT_133MHZ_PCIX)
1181 bus_speed = PCIX_133MHZ;
1182 else if (slot_avail1 & SLOT_100MHZ_PCIX)
1183 bus_speed = PCIX_100MHZ;
1184 else if (slot_avail1 & SLOT_66MHZ_PCIX)
1185 bus_speed = PCIX_66MHZ;
1186 else if (slot_avail2 & SLOT_66MHZ)
1187 bus_speed = PCI_66MHZ;
1188 else if (slot_avail1 & SLOT_33MHZ)
1189 bus_speed = PCI_33MHZ;
1190 else bus_speed = PCI_SPEED_UNKNOWN;
1191 } else {
1192 if (slot_avail1 & SLOT_133MHZ_PCIX)
1193 bus_speed = PCIX_133MHZ;
1194 else if (slot_avail1 & SLOT_100MHZ_PCIX)
1195 bus_speed = PCIX_100MHZ;
1196 else if (slot_avail1 & SLOT_66MHZ_PCIX)
1197 bus_speed = PCIX_66MHZ;
1198 else if (slot_avail2 & SLOT_66MHZ)
1199 bus_speed = PCI_66MHZ;
1200 else if (slot_avail1 & SLOT_33MHZ)
1201 bus_speed = PCI_33MHZ;
1202 else bus_speed = PCI_SPEED_UNKNOWN;
1203 }
1204
1205 *value = bus_speed;
1206 dbg("Max bus speed = %d\n", bus_speed);
1207 DBG_LEAVE_ROUTINE
1208 return retval;
1209 }
1210
1211 static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1212 {
1213 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1214 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
1215 u16 sec_bus_status;
1216 int retval = 0;
1217 u8 pi;
1218
1219 DBG_ENTER_ROUTINE
1220
1221 if (!slot->ctrl->hpc_ctlr_handle) {
1222 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1223 return -1;
1224 }
1225
1226 if (slot->hp_slot >= php_ctlr->num_slots) {
1227 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1228 return -1;
1229 }
1230
1231 pi = readb(php_ctlr->creg + PROG_INTERFACE);
1232 sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG);
1233
1234 if (pi == 2) {
1235 switch (sec_bus_status & 0x000f) {
1236 case 0:
1237 bus_speed = PCI_SPEED_33MHz;
1238 break;
1239 case 1:
1240 bus_speed = PCI_SPEED_66MHz;
1241 break;
1242 case 2:
1243 bus_speed = PCI_SPEED_66MHz_PCIX;
1244 break;
1245 case 3:
1246 bus_speed = PCI_SPEED_100MHz_PCIX;
1247 break;
1248 case 4:
1249 bus_speed = PCI_SPEED_133MHz_PCIX;
1250 break;
1251 case 5:
1252 bus_speed = PCI_SPEED_66MHz_PCIX_ECC;
1253 break;
1254 case 6:
1255 bus_speed = PCI_SPEED_100MHz_PCIX_ECC;
1256 break;
1257 case 7:
1258 bus_speed = PCI_SPEED_133MHz_PCIX_ECC;
1259 break;
1260 case 8:
1261 bus_speed = PCI_SPEED_66MHz_PCIX_266;
1262 break;
1263 case 9:
1264 bus_speed = PCI_SPEED_100MHz_PCIX_266;
1265 break;
1266 case 0xa:
1267 bus_speed = PCI_SPEED_133MHz_PCIX_266;
1268 break;
1269 case 0xb:
1270 bus_speed = PCI_SPEED_66MHz_PCIX_533;
1271 break;
1272 case 0xc:
1273 bus_speed = PCI_SPEED_100MHz_PCIX_533;
1274 break;
1275 case 0xd:
1276 bus_speed = PCI_SPEED_133MHz_PCIX_533;
1277 break;
1278 case 0xe:
1279 case 0xf:
1280 default:
1281 bus_speed = PCI_SPEED_UNKNOWN;
1282 break;
1283 }
1284 } else {
1285 /* In the case where pi is undefined, default it to 1 */
1286 switch (sec_bus_status & 0x0007) {
1287 case 0:
1288 bus_speed = PCI_SPEED_33MHz;
1289 break;
1290 case 1:
1291 bus_speed = PCI_SPEED_66MHz;
1292 break;
1293 case 2:
1294 bus_speed = PCI_SPEED_66MHz_PCIX;
1295 break;
1296 case 3:
1297 bus_speed = PCI_SPEED_100MHz_PCIX;
1298 break;
1299 case 4:
1300 bus_speed = PCI_SPEED_133MHz_PCIX;
1301 break;
1302 case 5:
1303 bus_speed = PCI_SPEED_UNKNOWN; /* Reserved */
1304 break;
1305 case 6:
1306 bus_speed = PCI_SPEED_UNKNOWN; /* Reserved */
1307 break;
1308 case 7:
1309 bus_speed = PCI_SPEED_UNKNOWN; /* Reserved */
1310 break;
1311 default:
1312 bus_speed = PCI_SPEED_UNKNOWN;
1313 break;
1314 }
1315 }
1316
1317 *value = bus_speed;
1318 dbg("Current bus speed = %d\n", bus_speed);
1319 DBG_LEAVE_ROUTINE
1320 return retval;
1321 }
1322
1323 static struct hpc_ops shpchp_hpc_ops = {
1324 .power_on_slot = hpc_power_on_slot,
1325 .slot_enable = hpc_slot_enable,
1326 .slot_disable = hpc_slot_disable,
1327 .set_bus_speed_mode = hpc_set_bus_speed_mode,
1328 .set_attention_status = hpc_set_attention_status,
1329 .get_power_status = hpc_get_power_status,
1330 .get_attention_status = hpc_get_attention_status,
1331 .get_latch_status = hpc_get_latch_status,
1332 .get_adapter_status = hpc_get_adapter_status,
1333
1334 .get_max_bus_speed = hpc_get_max_bus_speed,
1335 .get_cur_bus_speed = hpc_get_cur_bus_speed,
1336 .get_adapter_speed = hpc_get_adapter_speed,
1337 .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap,
1338 .get_prog_int = hpc_get_prog_int,
1339
1340 .query_power_fault = hpc_query_power_fault,
1341 .green_led_on = hpc_set_green_led_on,
1342 .green_led_off = hpc_set_green_led_off,
1343 .green_led_blink = hpc_set_green_led_blink,
1344
1345 .release_ctlr = hpc_release_ctlr,
1346 .check_cmd_status = hpc_check_cmd_status,
1347 };
1348
1349 inline static int shpc_indirect_creg_read(struct controller *ctrl, int index,
1350 u32 *value)
1351 {
1352 int rc;
1353 u32 cap_offset = ctrl->cap_offset;
1354 struct pci_dev *pdev = ctrl->pci_dev;
1355
1356 rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index);
1357 if (rc)
1358 return rc;
1359 return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
1360 }
1361
1362 int shpc_init(struct controller * ctrl, struct pci_dev * pdev)
1363 {
1364 struct php_ctlr_state_s *php_ctlr, *p;
1365 void *instance_id = ctrl;
1366 int rc, num_slots = 0;
1367 u8 hp_slot;
1368 static int first = 1;
1369 u32 shpc_base_offset;
1370 u32 tempdword, slot_reg;
1371 u8 i;
1372
1373 DBG_ENTER_ROUTINE
1374
1375 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
1376
1377 spin_lock_init(&list_lock);
1378 php_ctlr = (struct php_ctlr_state_s *) kmalloc(sizeof(struct php_ctlr_state_s), GFP_KERNEL);
1379
1380 if (!php_ctlr) { /* allocate controller state data */
1381 err("%s: HPC controller memory allocation error!\n", __FUNCTION__);
1382 goto abort;
1383 }
1384
1385 memset(php_ctlr, 0, sizeof(struct php_ctlr_state_s));
1386
1387 php_ctlr->pci_dev = pdev; /* save pci_dev in context */
1388
1389 if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device ==
1390 PCI_DEVICE_ID_AMD_GOLAM_7450)) {
1391 /* amd shpc driver doesn't use Base Offset; assume 0 */
1392 ctrl->mmio_base = pci_resource_start(pdev, 0);
1393 ctrl->mmio_size = pci_resource_len(pdev, 0);
1394 } else {
1395 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
1396 if (!ctrl->cap_offset) {
1397 err("%s : cap_offset == 0\n", __FUNCTION__);
1398 goto abort_free_ctlr;
1399 }
1400 dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset);
1401
1402 rc = shpc_indirect_creg_read(ctrl, 0, &shpc_base_offset);
1403 if (rc) {
1404 err("%s: cannot read base_offset\n", __FUNCTION__);
1405 goto abort_free_ctlr;
1406 }
1407
1408 rc = shpc_indirect_creg_read(ctrl, 3, &tempdword);
1409 if (rc) {
1410 err("%s: cannot read slot config\n", __FUNCTION__);
1411 goto abort_free_ctlr;
1412 }
1413 num_slots = tempdword & SLOT_NUM;
1414 dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots);
1415
1416 for (i = 0; i < 9 + num_slots; i++) {
1417 rc = shpc_indirect_creg_read(ctrl, i, &tempdword);
1418 if (rc) {
1419 err("%s: cannot read creg (index = %d)\n",
1420 __FUNCTION__, i);
1421 goto abort_free_ctlr;
1422 }
1423 dbg("%s: offset %d: value %x\n", __FUNCTION__,i,
1424 tempdword);
1425 }
1426
1427 ctrl->mmio_base =
1428 pci_resource_start(pdev, 0) + shpc_base_offset;
1429 ctrl->mmio_size = 0x24 + 0x4 * num_slots;
1430 }
1431
1432 if (first) {
1433 spin_lock_init(&hpc_event_lock);
1434 first = 0;
1435 }
1436
1437 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor,
1438 pdev->subsystem_device);
1439
1440 if (pci_enable_device(pdev))
1441 goto abort_free_ctlr;
1442
1443 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
1444 err("%s: cannot reserve MMIO region\n", __FUNCTION__);
1445 goto abort_free_ctlr;
1446 }
1447
1448 php_ctlr->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
1449 if (!php_ctlr->creg) {
1450 err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__,
1451 ctrl->mmio_size, ctrl->mmio_base);
1452 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
1453 goto abort_free_ctlr;
1454 }
1455 dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg);
1456
1457 init_MUTEX(&ctrl->crit_sect);
1458 /* Setup wait queue */
1459 init_waitqueue_head(&ctrl->queue);
1460
1461 /* Find the IRQ */
1462 php_ctlr->irq = pdev->irq;
1463 php_ctlr->attention_button_callback = shpchp_handle_attention_button,
1464 php_ctlr->switch_change_callback = shpchp_handle_switch_change;
1465 php_ctlr->presence_change_callback = shpchp_handle_presence_change;
1466 php_ctlr->power_fault_callback = shpchp_handle_power_fault;
1467 php_ctlr->callback_instance_id = instance_id;
1468
1469 /* Return PCI Controller Info */
1470 php_ctlr->slot_device_offset = (readl(php_ctlr->creg + SLOT_CONFIG) & FIRST_DEV_NUM ) >> 8;
1471 php_ctlr->num_slots = readl(php_ctlr->creg + SLOT_CONFIG) & SLOT_NUM;
1472 dbg("%s: slot_device_offset %x\n", __FUNCTION__, php_ctlr->slot_device_offset);
1473 dbg("%s: num_slots %x\n", __FUNCTION__, php_ctlr->num_slots);
1474
1475 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
1476 tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1477 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1478 tempdword = 0x0003000f;
1479 writel(tempdword, php_ctlr->creg + SERR_INTR_ENABLE);
1480 tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1481 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1482
1483 /* Mask the MRL sensor SERR Mask of individual slot in
1484 * Slot SERR-INT Mask & clear all the existing event if any
1485 */
1486 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
1487 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*hp_slot );
1488 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1489 hp_slot, slot_reg);
1490 tempdword = 0xffff3fff;
1491 writel(tempdword, php_ctlr->creg + SLOT1 + (4*hp_slot));
1492 }
1493
1494 if (shpchp_poll_mode) {/* Install interrupt polling code */
1495 /* Install and start the interrupt polling timer */
1496 init_timer(&php_ctlr->int_poll_timer);
1497 start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */
1498 } else {
1499 /* Installs the interrupt handler */
1500 rc = pci_enable_msi(pdev);
1501 if (rc) {
1502 info("Can't get msi for the hotplug controller\n");
1503 info("Use INTx for the hotplug controller\n");
1504 } else
1505 php_ctlr->irq = pdev->irq;
1506
1507 rc = request_irq(php_ctlr->irq, shpc_isr, SA_SHIRQ, MY_NAME, (void *) ctrl);
1508 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
1509 if (rc) {
1510 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
1511 goto abort_free_ctlr;
1512 }
1513 }
1514 dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__,
1515 pdev->bus->number, PCI_SLOT(pdev->devfn),
1516 PCI_FUNC(pdev->devfn), pdev->irq);
1517 get_hp_hw_control_from_firmware(pdev);
1518
1519 /* Add this HPC instance into the HPC list */
1520 spin_lock(&list_lock);
1521 if (php_ctlr_list_head == 0) {
1522 php_ctlr_list_head = php_ctlr;
1523 p = php_ctlr_list_head;
1524 p->pnext = NULL;
1525 } else {
1526 p = php_ctlr_list_head;
1527
1528 while (p->pnext)
1529 p = p->pnext;
1530
1531 p->pnext = php_ctlr;
1532 }
1533 spin_unlock(&list_lock);
1534
1535
1536 ctlr_seq_num++;
1537 ctrl->hpc_ctlr_handle = php_ctlr;
1538 ctrl->hpc_ops = &shpchp_hpc_ops;
1539
1540 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
1541 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*hp_slot );
1542 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1543 hp_slot, slot_reg);
1544 tempdword = 0xe01f3fff;
1545 writel(tempdword, php_ctlr->creg + SLOT1 + (4*hp_slot));
1546 }
1547 if (!shpchp_poll_mode) {
1548 /* Unmask all general input interrupts and SERR */
1549 tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1550 tempdword = 0x0000000a;
1551 writel(tempdword, php_ctlr->creg + SERR_INTR_ENABLE);
1552 tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1553 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1554 }
1555
1556 DBG_LEAVE_ROUTINE
1557 return 0;
1558
1559 /* We end up here for the many possible ways to fail this API. */
1560 abort_free_ctlr:
1561 kfree(php_ctlr);
1562 abort:
1563 DBG_LEAVE_ROUTINE
1564 return -1;
1565 }
x86 "subsystem" repository