drivers/pci/msi.c

   1 /*
   2  * File:        msi.c
   3  * Purpose:     PCI Message Signaled Interrupt (MSI)
   4  *
   5  * Copyright (C) 2003-2004 Intel
   6  * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
   7  */
   8
   9 #include <linux/err.h>
  10 #include <linux/mm.h>
  11 #include <linux/irq.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/init.h>
  14 #include <linux/ioport.h>
  15 #include <linux/smp_lock.h>
  16 #include <linux/pci.h>
  17 #include <linux/proc_fs.h>
  18 #include <linux/msi.h>
  19
  20 #include <asm/errno.h>
  21 #include <asm/io.h>
  22 #include <asm/smp.h>
  23
  24 #include "pci.h"
  25 #include "msi.h"
  26
  27 static DEFINE_SPINLOCK(msi_lock);
  28 static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL };
  29 static struct kmem_cache* msi_cachep;
  30
  31 static int pci_msi_enable = 1;
  32
  33 static int msi_cache_init(void)
  34 {
  35         msi_cachep = kmem_cache_create("msi_cache", sizeof(struct msi_desc),
  36                                         0, SLAB_HWCACHE_ALIGN, NULL, NULL);
  37         if (!msi_cachep)
  38                 return -ENOMEM;
  39
  40         return 0;
  41 }
  42
  43 static void msi_set_mask_bit(unsigned int irq, int flag)
  44 {
  45         struct msi_desc *entry;
  46
  47         entry = msi_desc[irq];
  48         BUG_ON(!entry || !entry->dev);
  49         switch (entry->msi_attrib.type) {
  50         case PCI_CAP_ID_MSI:
  51                 if (entry->msi_attrib.maskbit) {
  52                         int pos;
  53                         u32 mask_bits;
  54
  55                         pos = (long)entry->mask_base;
  56                         pci_read_config_dword(entry->dev, pos, &mask_bits);
  57                         mask_bits &= ~(1);
  58                         mask_bits |= flag;
  59                         pci_write_config_dword(entry->dev, pos, mask_bits);
  60                 }
  61                 break;
  62         case PCI_CAP_ID_MSIX:
  63         {
  64                 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
  65                         PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
  66                 writel(flag, entry->mask_base + offset);
  67                 break;
  68         }
  69         default:
  70                 BUG();
  71                 break;
  72         }
  73 }
  74
  75 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
  76 {
  77         struct msi_desc *entry = get_irq_data(irq);
  78         switch(entry->msi_attrib.type) {
  79         case PCI_CAP_ID_MSI:
  80         {
  81                 struct pci_dev *dev = entry->dev;
  82                 int pos = entry->msi_attrib.pos;
  83                 u16 data;
  84
  85                 pci_read_config_dword(dev, msi_lower_address_reg(pos),
  86                                         &msg->address_lo);
  87                 if (entry->msi_attrib.is_64) {
  88                         pci_read_config_dword(dev, msi_upper_address_reg(pos),
  89                                                 &msg->address_hi);
  90                         pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
  91                 } else {
  92                         msg->address_hi = 0;
  93                         pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
  94                 }
  95                 msg->data = data;
  96                 break;
  97         }
  98         case PCI_CAP_ID_MSIX:
  99         {
 100                 void __iomem *base;
 101                 base = entry->mask_base +
 102                         entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
 103
 104                 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
 105                 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
 106                 msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET);
 107                 break;
 108         }
 109         default:
 110                 BUG();
 111         }
 112 }
 113
 114 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
 115 {
 116         struct msi_desc *entry = get_irq_data(irq);
 117         switch (entry->msi_attrib.type) {
 118         case PCI_CAP_ID_MSI:
 119         {
 120                 struct pci_dev *dev = entry->dev;
 121                 int pos = entry->msi_attrib.pos;
 122
 123                 pci_write_config_dword(dev, msi_lower_address_reg(pos),
 124                                         msg->address_lo);
 125                 if (entry->msi_attrib.is_64) {
 126                         pci_write_config_dword(dev, msi_upper_address_reg(pos),
 127                                                 msg->address_hi);
 128                         pci_write_config_word(dev, msi_data_reg(pos, 1),
 129                                                 msg->data);
 130                 } else {
 131                         pci_write_config_word(dev, msi_data_reg(pos, 0),
 132                                                 msg->data);
 133                 }
 134                 break;
 135         }
 136         case PCI_CAP_ID_MSIX:
 137         {
 138                 void __iomem *base;
 139                 base = entry->mask_base +
 140                         entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
 141
 142                 writel(msg->address_lo,
 143                         base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
 144                 writel(msg->address_hi,
 145                         base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
 146                 writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET);
 147                 break;
 148         }
 149         default:
 150                 BUG();
 151         }
 152 }
 153
 154 void mask_msi_irq(unsigned int irq)
 155 {
 156         msi_set_mask_bit(irq, 1);
 157 }
 158
 159 void unmask_msi_irq(unsigned int irq)
 160 {
 161         msi_set_mask_bit(irq, 0);
 162 }
 163
 164 static int msi_free_irq(struct pci_dev* dev, int irq);
 165
 166 static int msi_init(void)
 167 {
 168         static int status = -ENOMEM;
 169
 170         if (!status)
 171                 return status;
 172
 173         if (pci_msi_quirk) {
 174                 pci_msi_enable = 0;
 175                 printk(KERN_WARNING "PCI: MSI quirk detected. MSI disabled.\n");
 176                 status = -EINVAL;
 177                 return status;
 178         }
 179
 180         status = msi_cache_init();
 181         if (status < 0) {
 182                 pci_msi_enable = 0;
 183                 printk(KERN_WARNING "PCI: MSI cache init failed\n");
 184                 return status;
 185         }
 186
 187         return status;
 188 }
 189
 190 static struct msi_desc* alloc_msi_entry(void)
 191 {
 192         struct msi_desc *entry;
 193
 194         entry = kmem_cache_zalloc(msi_cachep, GFP_KERNEL);
 195         if (!entry)
 196                 return NULL;
 197
 198         entry->link.tail = entry->link.head = 0;        /* single message */
 199         entry->dev = NULL;
 200
 201         return entry;
 202 }
 203
 204 static void attach_msi_entry(struct msi_desc *entry, int irq)
 205 {
 206         unsigned long flags;
 207
 208         spin_lock_irqsave(&msi_lock, flags);
 209         msi_desc[irq] = entry;
 210         spin_unlock_irqrestore(&msi_lock, flags);
 211 }
 212
 213 static int create_msi_irq(void)
 214 {
 215         struct msi_desc *entry;
 216         int irq;
 217
 218         entry = alloc_msi_entry();
 219         if (!entry)
 220                 return -ENOMEM;
 221
 222         irq = create_irq();
 223         if (irq < 0) {
 224                 kmem_cache_free(msi_cachep, entry);
 225                 return -EBUSY;
 226         }
 227
 228         set_irq_data(irq, entry);
 229
 230         return irq;
 231 }
 232
 233 static void destroy_msi_irq(unsigned int irq)
 234 {
 235         struct msi_desc *entry;
 236
 237         entry = get_irq_data(irq);
 238         set_irq_chip(irq, NULL);
 239         set_irq_data(irq, NULL);
 240         destroy_irq(irq);
 241         kmem_cache_free(msi_cachep, entry);
 242 }
 243
 244 static void enable_msi_mode(struct pci_dev *dev, int pos, int type)
 245 {
 246         u16 control;
 247
 248         pci_read_config_word(dev, msi_control_reg(pos), &control);
 249         if (type == PCI_CAP_ID_MSI) {
 250                 /* Set enabled bits to single MSI & enable MSI_enable bit */
 251                 msi_enable(control, 1);
 252                 pci_write_config_word(dev, msi_control_reg(pos), control);
 253                 dev->msi_enabled = 1;
 254         } else {
 255                 msix_enable(control);
 256                 pci_write_config_word(dev, msi_control_reg(pos), control);
 257                 dev->msix_enabled = 1;
 258         }
 259
 260         pci_intx(dev, 0);  /* disable intx */
 261 }
 262
 263 void disable_msi_mode(struct pci_dev *dev, int pos, int type)
 264 {
 265         u16 control;
 266
 267         pci_read_config_word(dev, msi_control_reg(pos), &control);
 268         if (type == PCI_CAP_ID_MSI) {
 269                 /* Set enabled bits to single MSI & enable MSI_enable bit */
 270                 msi_disable(control);
 271                 pci_write_config_word(dev, msi_control_reg(pos), control);
 272                 dev->msi_enabled = 0;
 273         } else {
 274                 msix_disable(control);
 275                 pci_write_config_word(dev, msi_control_reg(pos), control);
 276                 dev->msix_enabled = 0;
 277         }
 278
 279         pci_intx(dev, 1);  /* enable intx */
 280 }
 281
 282 static int msi_lookup_irq(struct pci_dev *dev, int type)
 283 {
 284         int irq;
 285         unsigned long flags;
 286
 287         spin_lock_irqsave(&msi_lock, flags);
 288         for (irq = 0; irq < NR_IRQS; irq++) {
 289                 if (!msi_desc[irq] || msi_desc[irq]->dev != dev ||
 290                         msi_desc[irq]->msi_attrib.type != type ||
 291                         msi_desc[irq]->msi_attrib.default_irq != dev->irq)
 292                         continue;
 293                 spin_unlock_irqrestore(&msi_lock, flags);
 294                 /* This pre-assigned MSI irq for this device
 295                    already exists. Override dev->irq with this irq */
 296                 dev->irq = irq;
 297                 return 0;
 298         }
 299         spin_unlock_irqrestore(&msi_lock, flags);
 300
 301         return -EACCES;
 302 }
 303
 304 void pci_scan_msi_device(struct pci_dev *dev)
 305 {
 306         if (!dev)
 307                 return;
 308 }
 309
 310 #ifdef CONFIG_PM
 311 int pci_save_msi_state(struct pci_dev *dev)
 312 {
 313         int pos, i = 0;
 314         u16 control;
 315         struct pci_cap_saved_state *save_state;
 316         u32 *cap;
 317
 318         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 319         if (pos <= 0 || dev->no_msi)
 320                 return 0;
 321
 322         pci_read_config_word(dev, msi_control_reg(pos), &control);
 323         if (!(control & PCI_MSI_FLAGS_ENABLE))
 324                 return 0;
 325
 326         save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5,
 327                 GFP_KERNEL);
 328         if (!save_state) {
 329                 printk(KERN_ERR "Out of memory in pci_save_msi_state\n");
 330                 return -ENOMEM;
 331         }
 332         cap = &save_state->data[0];
 333
 334         pci_read_config_dword(dev, pos, &cap[i++]);
 335         control = cap[0] >> 16;
 336         pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]);
 337         if (control & PCI_MSI_FLAGS_64BIT) {
 338                 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]);
 339                 pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]);
 340         } else
 341                 pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]);
 342         if (control & PCI_MSI_FLAGS_MASKBIT)
 343                 pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]);
 344         save_state->cap_nr = PCI_CAP_ID_MSI;
 345         pci_add_saved_cap(dev, save_state);
 346         return 0;
 347 }
 348
 349 void pci_restore_msi_state(struct pci_dev *dev)
 350 {
 351         int i = 0, pos;
 352         u16 control;
 353         struct pci_cap_saved_state *save_state;
 354         u32 *cap;
 355
 356         save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI);
 357         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 358         if (!save_state || pos <= 0)
 359                 return;
 360         cap = &save_state->data[0];
 361
 362         control = cap[i++] >> 16;
 363         pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]);
 364         if (control & PCI_MSI_FLAGS_64BIT) {
 365                 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]);
 366                 pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]);
 367         } else
 368                 pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]);
 369         if (control & PCI_MSI_FLAGS_MASKBIT)
 370                 pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]);
 371         pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
 372         enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
 373         pci_remove_saved_cap(save_state);
 374         kfree(save_state);
 375 }
 376
 377 int pci_save_msix_state(struct pci_dev *dev)
 378 {
 379         int pos;
 380         int temp;
 381         int irq, head, tail = 0;
 382         u16 control;
 383         struct pci_cap_saved_state *save_state;
 384
 385         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 386         if (pos <= 0 || dev->no_msi)
 387                 return 0;
 388
 389         /* save the capability */
 390         pci_read_config_word(dev, msi_control_reg(pos), &control);
 391         if (!(control & PCI_MSIX_FLAGS_ENABLE))
 392                 return 0;
 393         save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16),
 394                 GFP_KERNEL);
 395         if (!save_state) {
 396                 printk(KERN_ERR "Out of memory in pci_save_msix_state\n");
 397                 return -ENOMEM;
 398         }
 399         *((u16 *)&save_state->data[0]) = control;
 400
 401         /* save the table */
 402         temp = dev->irq;
 403         if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
 404                 kfree(save_state);
 405                 return -EINVAL;
 406         }
 407
 408         irq = head = dev->irq;
 409         while (head != tail) {
 410                 struct msi_desc *entry;
 411
 412                 entry = msi_desc[irq];
 413                 read_msi_msg(irq, &entry->msg_save);
 414
 415                 tail = msi_desc[irq]->link.tail;
 416                 irq = tail;
 417         }
 418         dev->irq = temp;
 419
 420         save_state->cap_nr = PCI_CAP_ID_MSIX;
 421         pci_add_saved_cap(dev, save_state);
 422         return 0;
 423 }
 424
 425 void pci_restore_msix_state(struct pci_dev *dev)
 426 {
 427         u16 save;
 428         int pos;
 429         int irq, head, tail = 0;
 430         struct msi_desc *entry;
 431         int temp;
 432         struct pci_cap_saved_state *save_state;
 433
 434         save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX);
 435         if (!save_state)
 436                 return;
 437         save = *((u16 *)&save_state->data[0]);
 438         pci_remove_saved_cap(save_state);
 439         kfree(save_state);
 440
 441         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 442         if (pos <= 0)
 443                 return;
 444
 445         /* route the table */
 446         temp = dev->irq;
 447         if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX))
 448                 return;
 449         irq = head = dev->irq;
 450         while (head != tail) {
 451                 entry = msi_desc[irq];
 452                 write_msi_msg(irq, &entry->msg_save);
 453
 454                 tail = msi_desc[irq]->link.tail;
 455                 irq = tail;
 456         }
 457         dev->irq = temp;
 458
 459         pci_write_config_word(dev, msi_control_reg(pos), save);
 460         enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
 461 }
 462 #endif  /* CONFIG_PM */
 463
 464 /**
 465  * msi_capability_init - configure device's MSI capability structure
 466  * @dev: pointer to the pci_dev data structure of MSI device function
 467  *
 468  * Setup the MSI capability structure of device function with a single
 469  * MSI irq, regardless of device function is capable of handling
 470  * multiple messages. A return of zero indicates the successful setup
 471  * of an entry zero with the new MSI irq or non-zero for otherwise.
 472  **/
 473 static int msi_capability_init(struct pci_dev *dev)
 474 {
 475         int status;
 476         struct msi_desc *entry;
 477         int pos, irq;
 478         u16 control;
 479
 480         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 481         pci_read_config_word(dev, msi_control_reg(pos), &control);
 482         /* MSI Entry Initialization */
 483         irq = create_msi_irq();
 484         if (irq < 0)
 485                 return irq;
 486
 487         entry = get_irq_data(irq);
 488         entry->link.head = irq;
 489         entry->link.tail = irq;
 490         entry->msi_attrib.type = PCI_CAP_ID_MSI;
 491         entry->msi_attrib.is_64 = is_64bit_address(control);
 492         entry->msi_attrib.entry_nr = 0;
 493         entry->msi_attrib.maskbit = is_mask_bit_support(control);
 494         entry->msi_attrib.default_irq = dev->irq;       /* Save IOAPIC IRQ */
 495         entry->msi_attrib.pos = pos;
 496         if (is_mask_bit_support(control)) {
 497                 entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos,
 498                                 is_64bit_address(control));
 499         }
 500         entry->dev = dev;
 501         if (entry->msi_attrib.maskbit) {
 502                 unsigned int maskbits, temp;
 503                 /* All MSIs are unmasked by default, Mask them all */
 504                 pci_read_config_dword(dev,
 505                         msi_mask_bits_reg(pos, is_64bit_address(control)),
 506                         &maskbits);
 507                 temp = (1 << multi_msi_capable(control));
 508                 temp = ((temp - 1) & ~temp);
 509                 maskbits |= temp;
 510                 pci_write_config_dword(dev,
 511                         msi_mask_bits_reg(pos, is_64bit_address(control)),
 512                         maskbits);
 513         }
 514         /* Configure MSI capability structure */
 515         status = arch_setup_msi_irq(irq, dev);
 516         if (status < 0) {
 517                 destroy_msi_irq(irq);
 518                 return status;
 519         }
 520
 521         attach_msi_entry(entry, irq);
 522         /* Set MSI enabled bits  */
 523         enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
 524
 525         dev->irq = irq;
 526         return 0;
 527 }
 528
 529 /**
 530  * msix_capability_init - configure device's MSI-X capability
 531  * @dev: pointer to the pci_dev data structure of MSI-X device function
 532  * @entries: pointer to an array of struct msix_entry entries
 533  * @nvec: number of @entries
 534  *
 535  * Setup the MSI-X capability structure of device function with a
 536  * single MSI-X irq. A return of zero indicates the successful setup of
 537  * requested MSI-X entries with allocated irqs or non-zero for otherwise.
 538  **/
 539 static int msix_capability_init(struct pci_dev *dev,
 540                                 struct msix_entry *entries, int nvec)
 541 {
 542         struct msi_desc *head = NULL, *tail = NULL, *entry = NULL;
 543         int status;
 544         int irq, pos, i, j, nr_entries, temp = 0;
 545         unsigned long phys_addr;
 546         u32 table_offset;
 547         u16 control;
 548         u8 bir;
 549         void __iomem *base;
 550
 551         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 552         /* Request & Map MSI-X table region */
 553         pci_read_config_word(dev, msi_control_reg(pos), &control);
 554         nr_entries = multi_msix_capable(control);
 555
 556         pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
 557         bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
 558         table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
 559         phys_addr = pci_resource_start (dev, bir) + table_offset;
 560         base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
 561         if (base == NULL)
 562                 return -ENOMEM;
 563
 564         /* MSI-X Table Initialization */
 565         for (i = 0; i < nvec; i++) {
 566                 irq = create_msi_irq();
 567                 if (irq < 0)
 568                         break;
 569
 570                 entry = get_irq_data(irq);
 571                 j = entries[i].entry;
 572                 entries[i].vector = irq;
 573                 entry->msi_attrib.type = PCI_CAP_ID_MSIX;
 574                 entry->msi_attrib.is_64 = 1;
 575                 entry->msi_attrib.entry_nr = j;
 576                 entry->msi_attrib.maskbit = 1;
 577                 entry->msi_attrib.default_irq = dev->irq;
 578                 entry->msi_attrib.pos = pos;
 579                 entry->dev = dev;
 580                 entry->mask_base = base;
 581                 if (!head) {
 582                         entry->link.head = irq;
 583                         entry->link.tail = irq;
 584                         head = entry;
 585                 } else {
 586                         entry->link.head = temp;
 587                         entry->link.tail = tail->link.tail;
 588                         tail->link.tail = irq;
 589                         head->link.head = irq;
 590                 }
 591                 temp = irq;
 592                 tail = entry;
 593                 /* Configure MSI-X capability structure */
 594                 status = arch_setup_msi_irq(irq, dev);
 595                 if (status < 0) {
 596                         destroy_msi_irq(irq);
 597                         break;
 598                 }
 599
 600                 attach_msi_entry(entry, irq);
 601         }
 602         if (i != nvec) {
 603                 int avail = i - 1;
 604                 i--;
 605                 for (; i >= 0; i--) {
 606                         irq = (entries + i)->vector;
 607                         msi_free_irq(dev, irq);
 608                         (entries + i)->vector = 0;
 609                 }
 610                 /* If we had some success report the number of irqs
 611                  * we succeeded in setting up.
 612                  */
 613                 if (avail <= 0)
 614                         avail = -EBUSY;
 615                 return avail;
 616         }
 617         /* Set MSI-X enabled bits */
 618         enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
 619
 620         return 0;
 621 }
 622
 623 /**
 624  * pci_msi_supported - check whether MSI may be enabled on device
 625  * @dev: pointer to the pci_dev data structure of MSI device function
 626  *
 627  * Look at global flags, the device itself, and its parent busses
 628  * to return 0 if MSI are supported for the device.
 629  **/
 630 static
 631 int pci_msi_supported(struct pci_dev * dev)
 632 {
 633         struct pci_bus *bus;
 634
 635         /* MSI must be globally enabled and supported by the device */
 636         if (!pci_msi_enable || !dev || dev->no_msi)
 637                 return -EINVAL;
 638
 639         /* Any bridge which does NOT route MSI transactions from it's
 640          * secondary bus to it's primary bus must set NO_MSI flag on
 641          * the secondary pci_bus.
 642          * We expect only arch-specific PCI host bus controller driver
 643          * or quirks for specific PCI bridges to be setting NO_MSI.
 644          */
 645         for (bus = dev->bus; bus; bus = bus->parent)
 646                 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
 647                         return -EINVAL;
 648
 649         return 0;
 650 }
 651
 652 /**
 653  * pci_enable_msi - configure device's MSI capability structure
 654  * @dev: pointer to the pci_dev data structure of MSI device function
 655  *
 656  * Setup the MSI capability structure of device function with
 657  * a single MSI irq upon its software driver call to request for
 658  * MSI mode enabled on its hardware device function. A return of zero
 659  * indicates the successful setup of an entry zero with the new MSI
 660  * irq or non-zero for otherwise.
 661  **/
 662 int pci_enable_msi(struct pci_dev* dev)
 663 {
 664         int pos, temp, status;
 665
 666         if (pci_msi_supported(dev) < 0)
 667                 return -EINVAL;
 668
 669         temp = dev->irq;
 670
 671         status = msi_init();
 672         if (status < 0)
 673                 return status;
 674
 675         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 676         if (!pos)
 677                 return -EINVAL;
 678
 679         WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSI));
 680
 681         /* Check whether driver already requested for MSI-X irqs */
 682         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 683         if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
 684                         printk(KERN_INFO "PCI: %s: Can't enable MSI.  "
 685                                "Device already has MSI-X irq assigned\n",
 686                                pci_name(dev));
 687                         dev->irq = temp;
 688                         return -EINVAL;
 689         }
 690         status = msi_capability_init(dev);
 691         return status;
 692 }
 693
 694 void pci_disable_msi(struct pci_dev* dev)
 695 {
 696         struct msi_desc *entry;
 697         int pos, default_irq;
 698         u16 control;
 699         unsigned long flags;
 700
 701         if (!pci_msi_enable)
 702                 return;
 703         if (!dev)
 704                 return;
 705
 706         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 707         if (!pos)
 708                 return;
 709
 710         pci_read_config_word(dev, msi_control_reg(pos), &control);
 711         if (!(control & PCI_MSI_FLAGS_ENABLE))
 712                 return;
 713
 714         disable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
 715
 716         spin_lock_irqsave(&msi_lock, flags);
 717         entry = msi_desc[dev->irq];
 718         if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) {
 719                 spin_unlock_irqrestore(&msi_lock, flags);
 720                 return;
 721         }
 722         if (irq_has_action(dev->irq)) {
 723                 spin_unlock_irqrestore(&msi_lock, flags);
 724                 printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without "
 725                        "free_irq() on MSI irq %d\n",
 726                        pci_name(dev), dev->irq);
 727                 BUG_ON(irq_has_action(dev->irq));
 728         } else {
 729                 default_irq = entry->msi_attrib.default_irq;
 730                 spin_unlock_irqrestore(&msi_lock, flags);
 731                 msi_free_irq(dev, dev->irq);
 732
 733                 /* Restore dev->irq to its default pin-assertion irq */
 734                 dev->irq = default_irq;
 735         }
 736 }
 737
 738 static int msi_free_irq(struct pci_dev* dev, int irq)
 739 {
 740         struct msi_desc *entry;
 741         int head, entry_nr, type;
 742         void __iomem *base;
 743         unsigned long flags;
 744
 745         arch_teardown_msi_irq(irq);
 746
 747         spin_lock_irqsave(&msi_lock, flags);
 748         entry = msi_desc[irq];
 749         if (!entry || entry->dev != dev) {
 750                 spin_unlock_irqrestore(&msi_lock, flags);
 751                 return -EINVAL;
 752         }
 753         type = entry->msi_attrib.type;
 754         entry_nr = entry->msi_attrib.entry_nr;
 755         head = entry->link.head;
 756         base = entry->mask_base;
 757         msi_desc[entry->link.head]->link.tail = entry->link.tail;
 758         msi_desc[entry->link.tail]->link.head = entry->link.head;
 759         entry->dev = NULL;
 760         msi_desc[irq] = NULL;
 761         spin_unlock_irqrestore(&msi_lock, flags);
 762
 763         destroy_msi_irq(irq);
 764
 765         if (type == PCI_CAP_ID_MSIX) {
 766                 writel(1, base + entry_nr * PCI_MSIX_ENTRY_SIZE +
 767                         PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
 768
 769                 if (head == irq)
 770                         iounmap(base);
 771         }
 772
 773         return 0;
 774 }
 775
 776 /**
 777  * pci_enable_msix - configure device's MSI-X capability structure
 778  * @dev: pointer to the pci_dev data structure of MSI-X device function
 779  * @entries: pointer to an array of MSI-X entries
 780  * @nvec: number of MSI-X irqs requested for allocation by device driver
 781  *
 782  * Setup the MSI-X capability structure of device function with the number
 783  * of requested irqs upon its software driver call to request for
 784  * MSI-X mode enabled on its hardware device function. A return of zero
 785  * indicates the successful configuration of MSI-X capability structure
 786  * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
 787  * Or a return of > 0 indicates that driver request is exceeding the number
 788  * of irqs available. Driver should use the returned value to re-send
 789  * its request.
 790  **/
 791 int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
 792 {
 793         int status, pos, nr_entries;
 794         int i, j, temp;
 795         u16 control;
 796
 797         if (!entries || pci_msi_supported(dev) < 0)
 798                 return -EINVAL;
 799
 800         status = msi_init();
 801         if (status < 0)
 802                 return status;
 803
 804         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 805         if (!pos)
 806                 return -EINVAL;
 807
 808         pci_read_config_word(dev, msi_control_reg(pos), &control);
 809         nr_entries = multi_msix_capable(control);
 810         if (nvec > nr_entries)
 811                 return -EINVAL;
 812
 813         /* Check for any invalid entries */
 814         for (i = 0; i < nvec; i++) {
 815                 if (entries[i].entry >= nr_entries)
 816                         return -EINVAL;         /* invalid entry */
 817                 for (j = i + 1; j < nvec; j++) {
 818                         if (entries[i].entry == entries[j].entry)
 819                                 return -EINVAL; /* duplicate entry */
 820                 }
 821         }
 822         temp = dev->irq;
 823         WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSIX));
 824
 825         /* Check whether driver already requested for MSI irq */
 826         if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 &&
 827                 !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) {
 828                 printk(KERN_INFO "PCI: %s: Can't enable MSI-X.  "
 829                        "Device already has an MSI irq assigned\n",
 830                        pci_name(dev));
 831                 dev->irq = temp;
 832                 return -EINVAL;
 833         }
 834         status = msix_capability_init(dev, entries, nvec);
 835         return status;
 836 }
 837
 838 void pci_disable_msix(struct pci_dev* dev)
 839 {
 840         int pos, temp;
 841         u16 control;
 842
 843         if (!pci_msi_enable)
 844                 return;
 845         if (!dev)
 846                 return;
 847
 848         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 849         if (!pos)
 850                 return;
 851
 852         pci_read_config_word(dev, msi_control_reg(pos), &control);
 853         if (!(control & PCI_MSIX_FLAGS_ENABLE))
 854                 return;
 855
 856         disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
 857
 858         temp = dev->irq;
 859         if (!msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
 860                 int irq, head, tail = 0, warning = 0;
 861                 unsigned long flags;
 862
 863                 irq = head = dev->irq;
 864                 dev->irq = temp;                        /* Restore pin IRQ */
 865                 while (head != tail) {
 866                         spin_lock_irqsave(&msi_lock, flags);
 867                         tail = msi_desc[irq]->link.tail;
 868                         spin_unlock_irqrestore(&msi_lock, flags);
 869                         if (irq_has_action(irq))
 870                                 warning = 1;
 871                         else if (irq != head)   /* Release MSI-X irq */
 872                                 msi_free_irq(dev, irq);
 873                         irq = tail;
 874                 }
 875                 msi_free_irq(dev, irq);
 876                 if (warning) {
 877                         printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without "
 878                                "free_irq() on all MSI-X irqs\n",
 879                                pci_name(dev));
 880                         BUG_ON(warning > 0);
 881                 }
 882         }
 883 }
 884
 885 /**
 886  * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
 887  * @dev: pointer to the pci_dev data structure of MSI(X) device function
 888  *
 889  * Being called during hotplug remove, from which the device function
 890  * is hot-removed. All previous assigned MSI/MSI-X irqs, if
 891  * allocated for this device function, are reclaimed to unused state,
 892  * which may be used later on.
 893  **/
 894 void msi_remove_pci_irq_vectors(struct pci_dev* dev)
 895 {
 896         int pos, temp;
 897         unsigned long flags;
 898
 899         if (!pci_msi_enable || !dev)
 900                 return;
 901
 902         temp = dev->irq;                /* Save IOAPIC IRQ */
 903         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 904         if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) {
 905                 if (irq_has_action(dev->irq)) {
 906                         printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
 907                                "called without free_irq() on MSI irq %d\n",
 908                                pci_name(dev), dev->irq);
 909                         BUG_ON(irq_has_action(dev->irq));
 910                 } else /* Release MSI irq assigned to this device */
 911                         msi_free_irq(dev, dev->irq);
 912                 dev->irq = temp;                /* Restore IOAPIC IRQ */
 913         }
 914         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 915         if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
 916                 int irq, head, tail = 0, warning = 0;
 917                 void __iomem *base = NULL;
 918
 919                 irq = head = dev->irq;
 920                 while (head != tail) {
 921                         spin_lock_irqsave(&msi_lock, flags);
 922                         tail = msi_desc[irq]->link.tail;
 923                         base = msi_desc[irq]->mask_base;
 924                         spin_unlock_irqrestore(&msi_lock, flags);
 925                         if (irq_has_action(irq))
 926                                 warning = 1;
 927                         else if (irq != head) /* Release MSI-X irq */
 928                                 msi_free_irq(dev, irq);
 929                         irq = tail;
 930                 }
 931                 msi_free_irq(dev, irq);
 932                 if (warning) {
 933                         iounmap(base);
 934                         printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
 935                                "called without free_irq() on all MSI-X irqs\n",
 936                                pci_name(dev));
 937                         BUG_ON(warning > 0);
 938                 }
 939                 dev->irq = temp;                /* Restore IOAPIC IRQ */
 940         }
 941 }
 942
 943 void pci_no_msi(void)
 944 {
 945         pci_msi_enable = 0;
 946 }
 947
 948 EXPORT_SYMBOL(pci_enable_msi);
 949 EXPORT_SYMBOL(pci_disable_msi);
 950 EXPORT_SYMBOL(pci_enable_msix);
 951 EXPORT_SYMBOL(pci_disable_msix);