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i2c: davinci: misc. cleanups: remove MOD_REG_BIT and IO_ADDRESS usage
[linux-2.6/x86.git] / drivers / i2c / busses / i2c-davinci.c
blob4e33909dd3f07a2b33b0b51df677c4046198bca0
1 /*
2 * TI DAVINCI I2C adapter driver.
3 *
4 * Copyright (C) 2006 Texas Instruments.
5 * Copyright (C) 2007 MontaVista Software Inc.
6 *
7 * Updated by Vinod & Sudhakar Feb 2005
8 *
9 * ----------------------------------------------------------------------------
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * ----------------------------------------------------------------------------
25 *
26 */
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/delay.h>
30 #include <linux/i2c.h>
31 #include <linux/clk.h>
32 #include <linux/errno.h>
33 #include <linux/sched.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/platform_device.h>
37 #include <linux/io.h>
38 #include <linux/slab.h>
39
40 #include <mach/hardware.h>
41 #include <mach/i2c.h>
42
43 /* ----- global defines ----------------------------------------------- */
44
45 #define DAVINCI_I2C_TIMEOUT (1*HZ)
46 #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_AAS | \
47 DAVINCI_I2C_IMR_SCD | \
48 DAVINCI_I2C_IMR_ARDY | \
49 DAVINCI_I2C_IMR_NACK | \
50 DAVINCI_I2C_IMR_AL)
51
52 #define DAVINCI_I2C_OAR_REG 0x00
53 #define DAVINCI_I2C_IMR_REG 0x04
54 #define DAVINCI_I2C_STR_REG 0x08
55 #define DAVINCI_I2C_CLKL_REG 0x0c
56 #define DAVINCI_I2C_CLKH_REG 0x10
57 #define DAVINCI_I2C_CNT_REG 0x14
58 #define DAVINCI_I2C_DRR_REG 0x18
59 #define DAVINCI_I2C_SAR_REG 0x1c
60 #define DAVINCI_I2C_DXR_REG 0x20
61 #define DAVINCI_I2C_MDR_REG 0x24
62 #define DAVINCI_I2C_IVR_REG 0x28
63 #define DAVINCI_I2C_EMDR_REG 0x2c
64 #define DAVINCI_I2C_PSC_REG 0x30
65
66 #define DAVINCI_I2C_IVR_AAS 0x07
67 #define DAVINCI_I2C_IVR_SCD 0x06
68 #define DAVINCI_I2C_IVR_XRDY 0x05
69 #define DAVINCI_I2C_IVR_RDR 0x04
70 #define DAVINCI_I2C_IVR_ARDY 0x03
71 #define DAVINCI_I2C_IVR_NACK 0x02
72 #define DAVINCI_I2C_IVR_AL 0x01
73
74 #define DAVINCI_I2C_STR_BB BIT(12)
75 #define DAVINCI_I2C_STR_RSFULL BIT(11)
76 #define DAVINCI_I2C_STR_SCD BIT(5)
77 #define DAVINCI_I2C_STR_ARDY BIT(2)
78 #define DAVINCI_I2C_STR_NACK BIT(1)
79 #define DAVINCI_I2C_STR_AL BIT(0)
80
81 #define DAVINCI_I2C_MDR_NACK BIT(15)
82 #define DAVINCI_I2C_MDR_STT BIT(13)
83 #define DAVINCI_I2C_MDR_STP BIT(11)
84 #define DAVINCI_I2C_MDR_MST BIT(10)
85 #define DAVINCI_I2C_MDR_TRX BIT(9)
86 #define DAVINCI_I2C_MDR_XA BIT(8)
87 #define DAVINCI_I2C_MDR_RM BIT(7)
88 #define DAVINCI_I2C_MDR_IRS BIT(5)
89
90 #define DAVINCI_I2C_IMR_AAS BIT(6)
91 #define DAVINCI_I2C_IMR_SCD BIT(5)
92 #define DAVINCI_I2C_IMR_XRDY BIT(4)
93 #define DAVINCI_I2C_IMR_RRDY BIT(3)
94 #define DAVINCI_I2C_IMR_ARDY BIT(2)
95 #define DAVINCI_I2C_IMR_NACK BIT(1)
96 #define DAVINCI_I2C_IMR_AL BIT(0)
97
98 struct davinci_i2c_dev {
99 struct device *dev;
100 void __iomem *base;
101 struct completion cmd_complete;
102 struct clk *clk;
103 int cmd_err;
104 u8 *buf;
105 size_t buf_len;
106 int irq;
107 int stop;
108 u8 terminate;
109 struct i2c_adapter adapter;
110 };
111
112 /* default platform data to use if not supplied in the platform_device */
113 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
114 .bus_freq = 100,
115 .bus_delay = 0,
116 };
117
118 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
119 int reg, u16 val)
120 {
121 __raw_writew(val, i2c_dev->base + reg);
122 }
123
124 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
125 {
126 return __raw_readw(i2c_dev->base + reg);
127 }
128
129 /*
130 * This functions configures I2C and brings I2C out of reset.
131 * This function is called during I2C init function. This function
132 * also gets called if I2C encounters any errors.
133 */
134 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
135 {
136 struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
137 u16 psc;
138 u32 clk;
139 u32 d;
140 u32 clkh;
141 u32 clkl;
142 u32 input_clock = clk_get_rate(dev->clk);
143 u16 w;
144
145 if (!pdata)
146 pdata = &davinci_i2c_platform_data_default;
147
148 /* put I2C into reset */
149 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
150 w &= ~DAVINCI_I2C_MDR_IRS;
151 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
152
153 /* NOTE: I2C Clock divider programming info
154 * As per I2C specs the following formulas provide prescaler
155 * and low/high divider values
156 * input clk --> PSC Div -----------> ICCL/H Div --> output clock
157 * module clk
158 *
159 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
160 *
161 * Thus,
162 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
163 *
164 * where if PSC == 0, d = 7,
165 * if PSC == 1, d = 6
166 * if PSC > 1 , d = 5
167 */
168
169 /* get minimum of 7 MHz clock, but max of 12 MHz */
170 psc = (input_clock / 7000000) - 1;
171 if ((input_clock / (psc + 1)) > 12000000)
172 psc++; /* better to run under spec than over */
173 d = (psc >= 2) ? 5 : 7 - psc;
174
175 clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1);
176 clkh = clk >> 1;
177 clkl = clk - clkh;
178
179 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
180 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
181 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
182
183 /* Respond at reserved "SMBus Host" slave address" (and zero);
184 * we seem to have no option to not respond...
185 */
186 davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08);
187
188 dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
189 dev_dbg(dev->dev, "PSC = %d\n",
190 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
191 dev_dbg(dev->dev, "CLKL = %d\n",
192 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
193 dev_dbg(dev->dev, "CLKH = %d\n",
194 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
195 dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
196 pdata->bus_freq, pdata->bus_delay);
197
198 /* Take the I2C module out of reset: */
199 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
200 w |= DAVINCI_I2C_MDR_IRS;
201 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
202
203 /* Enable interrupts */
204 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
205
206 return 0;
207 }
208
209 /*
210 * Waiting for bus not busy
211 */
212 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
213 char allow_sleep)
214 {
215 unsigned long timeout;
216
217 timeout = jiffies + dev->adapter.timeout;
218 while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
219 & DAVINCI_I2C_STR_BB) {
220 if (time_after(jiffies, timeout)) {
221 dev_warn(dev->dev,
222 "timeout waiting for bus ready\n");
223 return -ETIMEDOUT;
224 }
225 if (allow_sleep)
226 schedule_timeout(1);
227 }
228
229 return 0;
230 }
231
232 /*
233 * Low level master read/write transaction. This function is called
234 * from i2c_davinci_xfer.
235 */
236 static int
237 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
238 {
239 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
240 struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
241 u32 flag;
242 u16 w;
243 int r;
244
245 if (!pdata)
246 pdata = &davinci_i2c_platform_data_default;
247 /* Introduce a delay, required for some boards (e.g Davinci EVM) */
248 if (pdata->bus_delay)
249 udelay(pdata->bus_delay);
250
251 /* set the slave address */
252 davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
253
254 dev->buf = msg->buf;
255 dev->buf_len = msg->len;
256 dev->stop = stop;
257
258 davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
259
260 INIT_COMPLETION(dev->cmd_complete);
261 dev->cmd_err = 0;
262
263 /* Take I2C out of reset, configure it as master and set the
264 * start bit */
265 flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST | DAVINCI_I2C_MDR_STT;
266
267 /* if the slave address is ten bit address, enable XA bit */
268 if (msg->flags & I2C_M_TEN)
269 flag |= DAVINCI_I2C_MDR_XA;
270 if (!(msg->flags & I2C_M_RD))
271 flag |= DAVINCI_I2C_MDR_TRX;
272 if (stop)
273 flag |= DAVINCI_I2C_MDR_STP;
274 if (msg->len == 0) {
275 flag |= DAVINCI_I2C_MDR_RM;
276 flag &= ~DAVINCI_I2C_MDR_STP;
277 }
278
279 /* Enable receive or transmit interrupts */
280 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
281 if (msg->flags & I2C_M_RD)
282 w |= DAVINCI_I2C_IMR_RRDY;
283 else
284 w |= DAVINCI_I2C_IMR_XRDY;
285 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
286
287 dev->terminate = 0;
288
289 /* write the data into mode register */
290 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
291
292 /*
293 * First byte should be set here, not after interrupt,
294 * because transmit-data-ready interrupt can come before
295 * NACK-interrupt during sending of previous message and
296 * ICDXR may have wrong data
297 */
298 if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
299 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
300 dev->buf_len--;
301 }
302
303 r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
304 dev->adapter.timeout);
305 if (r == 0) {
306 dev_err(dev->dev, "controller timed out\n");
307 i2c_davinci_init(dev);
308 dev->buf_len = 0;
309 return -ETIMEDOUT;
310 }
311 if (dev->buf_len) {
312 /* This should be 0 if all bytes were transferred
313 * or dev->cmd_err denotes an error.
314 * A signal may have aborted the transfer.
315 */
316 if (r >= 0) {
317 dev_err(dev->dev, "abnormal termination buf_len=%i\n",
318 dev->buf_len);
319 r = -EREMOTEIO;
320 }
321 dev->terminate = 1;
322 wmb();
323 dev->buf_len = 0;
324 }
325 if (r < 0)
326 return r;
327
328 /* no error */
329 if (likely(!dev->cmd_err))
330 return msg->len;
331
332 /* We have an error */
333 if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
334 i2c_davinci_init(dev);
335 return -EIO;
336 }
337
338 if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
339 if (msg->flags & I2C_M_IGNORE_NAK)
340 return msg->len;
341 if (stop) {
342 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
343 w |= DAVINCI_I2C_MDR_STP;
344 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
345 }
346 return -EREMOTEIO;
347 }
348 return -EIO;
349 }
350
351 /*
352 * Prepare controller for a transaction and call i2c_davinci_xfer_msg
353 */
354 static int
355 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
356 {
357 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
358 int i;
359 int ret;
360
361 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
362
363 ret = i2c_davinci_wait_bus_not_busy(dev, 1);
364 if (ret < 0) {
365 dev_warn(dev->dev, "timeout waiting for bus ready\n");
366 return ret;
367 }
368
369 for (i = 0; i < num; i++) {
370 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
371 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
372 ret);
373 if (ret < 0)
374 return ret;
375 }
376 return num;
377 }
378
379 static u32 i2c_davinci_func(struct i2c_adapter *adap)
380 {
381 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
382 }
383
384 static void terminate_read(struct davinci_i2c_dev *dev)
385 {
386 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
387 w |= DAVINCI_I2C_MDR_NACK;
388 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
389
390 /* Throw away data */
391 davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
392 if (!dev->terminate)
393 dev_err(dev->dev, "RDR IRQ while no data requested\n");
394 }
395 static void terminate_write(struct davinci_i2c_dev *dev)
396 {
397 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
398 w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
399 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
400
401 if (!dev->terminate)
402 dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
403 }
404
405 /*
406 * Interrupt service routine. This gets called whenever an I2C interrupt
407 * occurs.
408 */
409 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
410 {
411 struct davinci_i2c_dev *dev = dev_id;
412 u32 stat;
413 int count = 0;
414 u16 w;
415
416 while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
417 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
418 if (count++ == 100) {
419 dev_warn(dev->dev, "Too much work in one IRQ\n");
420 break;
421 }
422
423 switch (stat) {
424 case DAVINCI_I2C_IVR_AL:
425 /* Arbitration lost, must retry */
426 dev->cmd_err |= DAVINCI_I2C_STR_AL;
427 dev->buf_len = 0;
428 complete(&dev->cmd_complete);
429 break;
430
431 case DAVINCI_I2C_IVR_NACK:
432 dev->cmd_err |= DAVINCI_I2C_STR_NACK;
433 dev->buf_len = 0;
434 complete(&dev->cmd_complete);
435 break;
436
437 case DAVINCI_I2C_IVR_ARDY:
438 davinci_i2c_write_reg(dev,
439 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
440 if (((dev->buf_len == 0) && (dev->stop != 0)) ||
441 (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
442 w = davinci_i2c_read_reg(dev,
443 DAVINCI_I2C_MDR_REG);
444 w |= DAVINCI_I2C_MDR_STP;
445 davinci_i2c_write_reg(dev,
446 DAVINCI_I2C_MDR_REG, w);
447 }
448 complete(&dev->cmd_complete);
449 break;
450
451 case DAVINCI_I2C_IVR_RDR:
452 if (dev->buf_len) {
453 *dev->buf++ =
454 davinci_i2c_read_reg(dev,
455 DAVINCI_I2C_DRR_REG);
456 dev->buf_len--;
457 if (dev->buf_len)
458 continue;
459
460 davinci_i2c_write_reg(dev,
461 DAVINCI_I2C_STR_REG,
462 DAVINCI_I2C_IMR_RRDY);
463 } else {
464 /* signal can terminate transfer */
465 terminate_read(dev);
466 }
467 break;
468
469 case DAVINCI_I2C_IVR_XRDY:
470 if (dev->buf_len) {
471 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
472 *dev->buf++);
473 dev->buf_len--;
474 if (dev->buf_len)
475 continue;
476
477 w = davinci_i2c_read_reg(dev,
478 DAVINCI_I2C_IMR_REG);
479 w &= ~DAVINCI_I2C_IMR_XRDY;
480 davinci_i2c_write_reg(dev,
481 DAVINCI_I2C_IMR_REG,
482 w);
483 } else {
484 /* signal can terminate transfer */
485 terminate_write(dev);
486 }
487 break;
488
489 case DAVINCI_I2C_IVR_SCD:
490 davinci_i2c_write_reg(dev,
491 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
492 complete(&dev->cmd_complete);
493 break;
494
495 case DAVINCI_I2C_IVR_AAS:
496 dev_dbg(dev->dev, "Address as slave interrupt\n");
497 break;
498
499 default:
500 dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
501 break;
502 }
503 }
504
505 return count ? IRQ_HANDLED : IRQ_NONE;
506 }
507
508 static struct i2c_algorithm i2c_davinci_algo = {
509 .master_xfer = i2c_davinci_xfer,
510 .functionality = i2c_davinci_func,
511 };
512
513 static int davinci_i2c_probe(struct platform_device *pdev)
514 {
515 struct davinci_i2c_dev *dev;
516 struct i2c_adapter *adap;
517 struct resource *mem, *irq, *ioarea;
518 int r;
519
520 /* NOTE: driver uses the static register mapping */
521 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
522 if (!mem) {
523 dev_err(&pdev->dev, "no mem resource?\n");
524 return -ENODEV;
525 }
526
527 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
528 if (!irq) {
529 dev_err(&pdev->dev, "no irq resource?\n");
530 return -ENODEV;
531 }
532
533 ioarea = request_mem_region(mem->start, resource_size(mem),
534 pdev->name);
535 if (!ioarea) {
536 dev_err(&pdev->dev, "I2C region already claimed\n");
537 return -EBUSY;
538 }
539
540 dev = kzalloc(sizeof(struct davinci_i2c_dev), GFP_KERNEL);
541 if (!dev) {
542 r = -ENOMEM;
543 goto err_release_region;
544 }
545
546 init_completion(&dev->cmd_complete);
547 dev->dev = get_device(&pdev->dev);
548 dev->irq = irq->start;
549 platform_set_drvdata(pdev, dev);
550
551 dev->clk = clk_get(&pdev->dev, NULL);
552 if (IS_ERR(dev->clk)) {
553 r = -ENODEV;
554 goto err_free_mem;
555 }
556 clk_enable(dev->clk);
557
558 dev->base = ioremap(mem->start, resource_size(mem));
559 if (!dev->base) {
560 r = -EBUSY;
561 goto err_mem_ioremap;
562 }
563
564 i2c_davinci_init(dev);
565
566 r = request_irq(dev->irq, i2c_davinci_isr, 0, pdev->name, dev);
567 if (r) {
568 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
569 goto err_unuse_clocks;
570 }
571
572 adap = &dev->adapter;
573 i2c_set_adapdata(adap, dev);
574 adap->owner = THIS_MODULE;
575 adap->class = I2C_CLASS_HWMON;
576 strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
577 adap->algo = &i2c_davinci_algo;
578 adap->dev.parent = &pdev->dev;
579 adap->timeout = DAVINCI_I2C_TIMEOUT;
580
581 adap->nr = pdev->id;
582 r = i2c_add_numbered_adapter(adap);
583 if (r) {
584 dev_err(&pdev->dev, "failure adding adapter\n");
585 goto err_free_irq;
586 }
587
588 return 0;
589
590 err_free_irq:
591 free_irq(dev->irq, dev);
592 err_unuse_clocks:
593 iounmap(dev->base);
594 err_mem_ioremap:
595 clk_disable(dev->clk);
596 clk_put(dev->clk);
597 dev->clk = NULL;
598 err_free_mem:
599 platform_set_drvdata(pdev, NULL);
600 put_device(&pdev->dev);
601 kfree(dev);
602 err_release_region:
603 release_mem_region(mem->start, resource_size(mem));
604
605 return r;
606 }
607
608 static int davinci_i2c_remove(struct platform_device *pdev)
609 {
610 struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
611 struct resource *mem;
612
613 platform_set_drvdata(pdev, NULL);
614 i2c_del_adapter(&dev->adapter);
615 put_device(&pdev->dev);
616
617 clk_disable(dev->clk);
618 clk_put(dev->clk);
619 dev->clk = NULL;
620
621 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
622 free_irq(IRQ_I2C, dev);
623 iounmap(dev->base);
624 kfree(dev);
625
626 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
627 release_mem_region(mem->start, resource_size(mem));
628 return 0;
629 }
630
631 /* work with hotplug and coldplug */
632 MODULE_ALIAS("platform:i2c_davinci");
633
634 static struct platform_driver davinci_i2c_driver = {
635 .probe = davinci_i2c_probe,
636 .remove = davinci_i2c_remove,
637 .driver = {
638 .name = "i2c_davinci",
639 .owner = THIS_MODULE,
640 },
641 };
642
643 /* I2C may be needed to bring up other drivers */
644 static int __init davinci_i2c_init_driver(void)
645 {
646 return platform_driver_register(&davinci_i2c_driver);
647 }
648 subsys_initcall(davinci_i2c_init_driver);
649
650 static void __exit davinci_i2c_exit_driver(void)
651 {
652 platform_driver_unregister(&davinci_i2c_driver);
653 }
654 module_exit(davinci_i2c_exit_driver);
655
656 MODULE_AUTHOR("Texas Instruments India");
657 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
658 MODULE_LICENSE("GPL");
x86 "subsystem" repository