2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
9 * written by Manish Lachwani
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 * Copyright (C) 2004-2005 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
33 #include <linux/init.h>
34 #include <linux/dma-mapping.h>
37 #include <linux/tcp.h>
38 #include <linux/udp.h>
39 #include <linux/etherdevice.h>
43 #include <linux/bitops.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
49 #include <asm/types.h>
50 #include <asm/pgtable.h>
51 #include <asm/system.h>
52 #include <asm/delay.h>
53 #include "mv643xx_eth.h"
56 * The first part is the high level driver of the gigE ethernet ports.
62 #define DMA_ALIGN 8 /* hw requires 8-byte alignment */
63 #define HW_IP_ALIGN 2 /* hw aligns IP header */
64 #define WRAP HW_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN
65 #define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7)
67 #define INT_UNMASK_ALL 0x0007ffff
68 #define INT_UNMASK_ALL_EXT 0x0011ffff
69 #define INT_MASK_ALL 0x00000000
70 #define INT_MASK_ALL_EXT 0x00000000
71 #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
72 #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
74 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
75 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
77 #define MAX_DESCS_PER_SKB 1
80 #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
81 #define PHY_WAIT_MICRO_SECONDS 10
83 /* Static function declarations */
84 static int eth_port_link_is_up(unsigned int eth_port_num
);
85 static void eth_port_uc_addr_get(struct net_device
*dev
,
86 unsigned char *MacAddr
);
87 static void eth_port_set_multicast_list(struct net_device
*);
88 static int mv643xx_eth_open(struct net_device
*);
89 static int mv643xx_eth_stop(struct net_device
*);
90 static int mv643xx_eth_change_mtu(struct net_device
*, int);
91 static struct net_device_stats
*mv643xx_eth_get_stats(struct net_device
*);
92 static void eth_port_init_mac_tables(unsigned int eth_port_num
);
94 static int mv643xx_poll(struct net_device
*dev
, int *budget
);
96 static void ethernet_phy_set(unsigned int eth_port_num
, int phy_addr
);
97 static int ethernet_phy_detect(unsigned int eth_port_num
);
98 static struct ethtool_ops mv643xx_ethtool_ops
;
100 static char mv643xx_driver_name
[] = "mv643xx_eth";
101 static char mv643xx_driver_version
[] = "1.0";
103 static void __iomem
*mv643xx_eth_shared_base
;
105 /* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
106 static DEFINE_SPINLOCK(mv643xx_eth_phy_lock
);
108 static inline u32
mv_read(int offset
)
110 void __iomem
*reg_base
;
112 reg_base
= mv643xx_eth_shared_base
- MV643XX_ETH_SHARED_REGS
;
114 return readl(reg_base
+ offset
);
117 static inline void mv_write(int offset
, u32 data
)
119 void __iomem
*reg_base
;
121 reg_base
= mv643xx_eth_shared_base
- MV643XX_ETH_SHARED_REGS
;
122 writel(data
, reg_base
+ offset
);
126 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
128 * Input : pointer to ethernet interface network device structure
130 * Output : 0 upon success, -EINVAL upon failure
132 static int mv643xx_eth_change_mtu(struct net_device
*dev
, int new_mtu
)
134 if ((new_mtu
> 9500) || (new_mtu
< 64))
139 * Stop then re-open the interface. This will allocate RX skb's with
141 * There is a possible danger that the open will not successed, due
142 * to memory is full, which might fail the open function.
144 if (netif_running(dev
)) {
145 mv643xx_eth_stop(dev
);
146 if (mv643xx_eth_open(dev
))
148 "%s: Fatal error on opening device\n",
156 * mv643xx_eth_rx_task
158 * Fills / refills RX queue on a certain gigabit ethernet port
160 * Input : pointer to ethernet interface network device structure
163 static void mv643xx_eth_rx_task(void *data
)
165 struct net_device
*dev
= (struct net_device
*)data
;
166 struct mv643xx_private
*mp
= netdev_priv(dev
);
167 struct pkt_info pkt_info
;
171 if (test_and_set_bit(0, &mp
->rx_task_busy
))
172 panic("%s: Error in test_set_bit / clear_bit", dev
->name
);
174 while (mp
->rx_ring_skbs
< (mp
->rx_ring_size
- 5)) {
175 skb
= dev_alloc_skb(RX_SKB_SIZE
+ DMA_ALIGN
);
179 unaligned
= (u32
)skb
->data
& (DMA_ALIGN
- 1);
181 skb_reserve(skb
, DMA_ALIGN
- unaligned
);
182 pkt_info
.cmd_sts
= ETH_RX_ENABLE_INTERRUPT
;
183 pkt_info
.byte_cnt
= RX_SKB_SIZE
;
184 pkt_info
.buf_ptr
= dma_map_single(NULL
, skb
->data
, RX_SKB_SIZE
,
186 pkt_info
.return_info
= skb
;
187 if (eth_rx_return_buff(mp
, &pkt_info
) != ETH_OK
) {
189 "%s: Error allocating RX Ring\n", dev
->name
);
192 skb_reserve(skb
, HW_IP_ALIGN
);
194 clear_bit(0, &mp
->rx_task_busy
);
196 * If RX ring is empty of SKB, set a timer to try allocating
197 * again in a later time .
199 if ((mp
->rx_ring_skbs
== 0) && (mp
->rx_timer_flag
== 0)) {
200 printk(KERN_INFO
"%s: Rx ring is empty\n", dev
->name
);
202 mp
->timeout
.expires
= jiffies
+ (HZ
/ 10);
203 add_timer(&mp
->timeout
);
204 mp
->rx_timer_flag
= 1;
206 #ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
208 /* Return interrupts */
209 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp
->port_num
),
216 * mv643xx_eth_rx_task_timer_wrapper
218 * Timer routine to wake up RX queue filling task. This function is
219 * used only in case the RX queue is empty, and all alloc_skb has
220 * failed (due to out of memory event).
222 * Input : pointer to ethernet interface network device structure
225 static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data
)
227 struct net_device
*dev
= (struct net_device
*)data
;
228 struct mv643xx_private
*mp
= netdev_priv(dev
);
230 mp
->rx_timer_flag
= 0;
231 mv643xx_eth_rx_task((void *)data
);
235 * mv643xx_eth_update_mac_address
237 * Update the MAC address of the port in the address table
239 * Input : pointer to ethernet interface network device structure
242 static void mv643xx_eth_update_mac_address(struct net_device
*dev
)
244 struct mv643xx_private
*mp
= netdev_priv(dev
);
245 unsigned int port_num
= mp
->port_num
;
247 eth_port_init_mac_tables(port_num
);
248 memcpy(mp
->port_mac_addr
, dev
->dev_addr
, 6);
249 eth_port_uc_addr_set(port_num
, mp
->port_mac_addr
);
253 * mv643xx_eth_set_rx_mode
255 * Change from promiscuos to regular rx mode
257 * Input : pointer to ethernet interface network device structure
260 static void mv643xx_eth_set_rx_mode(struct net_device
*dev
)
262 struct mv643xx_private
*mp
= netdev_priv(dev
);
264 if (dev
->flags
& IFF_PROMISC
)
265 mp
->port_config
|= (u32
) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE
;
267 mp
->port_config
&= ~(u32
) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE
;
269 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp
->port_num
), mp
->port_config
);
271 eth_port_set_multicast_list(dev
);
275 * mv643xx_eth_set_mac_address
277 * Change the interface's mac address.
278 * No special hardware thing should be done because interface is always
279 * put in promiscuous mode.
281 * Input : pointer to ethernet interface network device structure and
282 * a pointer to the designated entry to be added to the cache.
283 * Output : zero upon success, negative upon failure
285 static int mv643xx_eth_set_mac_address(struct net_device
*dev
, void *addr
)
289 for (i
= 0; i
< 6; i
++)
290 /* +2 is for the offset of the HW addr type */
291 dev
->dev_addr
[i
] = ((unsigned char *)addr
)[i
+ 2];
292 mv643xx_eth_update_mac_address(dev
);
297 * mv643xx_eth_tx_timeout
299 * Called upon a timeout on transmitting a packet
301 * Input : pointer to ethernet interface network device structure.
304 static void mv643xx_eth_tx_timeout(struct net_device
*dev
)
306 struct mv643xx_private
*mp
= netdev_priv(dev
);
308 printk(KERN_INFO
"%s: TX timeout ", dev
->name
);
310 /* Do the reset outside of interrupt context */
311 schedule_work(&mp
->tx_timeout_task
);
315 * mv643xx_eth_tx_timeout_task
317 * Actual routine to reset the adapter when a timeout on Tx has occurred
319 static void mv643xx_eth_tx_timeout_task(struct net_device
*dev
)
321 struct mv643xx_private
*mp
= netdev_priv(dev
);
323 netif_device_detach(dev
);
324 eth_port_reset(mp
->port_num
);
326 netif_device_attach(dev
);
330 * mv643xx_eth_free_tx_queue
332 * Input : dev - a pointer to the required interface
334 * Output : 0 if was able to release skb , nonzero otherwise
336 static int mv643xx_eth_free_tx_queue(struct net_device
*dev
,
337 unsigned int eth_int_cause_ext
)
339 struct mv643xx_private
*mp
= netdev_priv(dev
);
340 struct net_device_stats
*stats
= &mp
->stats
;
341 struct pkt_info pkt_info
;
344 if (!(eth_int_cause_ext
& (BIT0
| BIT8
)))
347 /* Check only queue 0 */
348 while (eth_tx_return_desc(mp
, &pkt_info
) == ETH_OK
) {
349 if (pkt_info
.cmd_sts
& BIT0
) {
350 printk("%s: Error in TX\n", dev
->name
);
354 if (pkt_info
.cmd_sts
& ETH_TX_FIRST_DESC
)
355 dma_unmap_single(NULL
, pkt_info
.buf_ptr
,
359 dma_unmap_page(NULL
, pkt_info
.buf_ptr
,
363 if (pkt_info
.return_info
) {
364 dev_kfree_skb_irq(pkt_info
.return_info
);
373 * mv643xx_eth_receive
375 * This function is forward packets that are received from the port's
376 * queues toward kernel core or FastRoute them to another interface.
378 * Input : dev - a pointer to the required interface
379 * max - maximum number to receive (0 means unlimted)
381 * Output : number of served packets
384 static int mv643xx_eth_receive_queue(struct net_device
*dev
, int budget
)
386 static int mv643xx_eth_receive_queue(struct net_device
*dev
)
389 struct mv643xx_private
*mp
= netdev_priv(dev
);
390 struct net_device_stats
*stats
= &mp
->stats
;
391 unsigned int received_packets
= 0;
393 struct pkt_info pkt_info
;
396 while (budget
-- > 0 && eth_port_receive(mp
, &pkt_info
) == ETH_OK
) {
398 while (eth_port_receive(mp
, &pkt_info
) == ETH_OK
) {
403 /* Update statistics. Note byte count includes 4 byte CRC count */
405 stats
->rx_bytes
+= pkt_info
.byte_cnt
;
406 skb
= pkt_info
.return_info
;
408 * In case received a packet without first / last bits on OR
409 * the error summary bit is on, the packets needs to be dropeed.
411 if (((pkt_info
.cmd_sts
412 & (ETH_RX_FIRST_DESC
| ETH_RX_LAST_DESC
)) !=
413 (ETH_RX_FIRST_DESC
| ETH_RX_LAST_DESC
))
414 || (pkt_info
.cmd_sts
& ETH_ERROR_SUMMARY
)) {
416 if ((pkt_info
.cmd_sts
& (ETH_RX_FIRST_DESC
|
417 ETH_RX_LAST_DESC
)) !=
418 (ETH_RX_FIRST_DESC
| ETH_RX_LAST_DESC
)) {
421 "%s: Received packet spread "
422 "on multiple descriptors\n",
425 if (pkt_info
.cmd_sts
& ETH_ERROR_SUMMARY
)
428 dev_kfree_skb_irq(skb
);
431 * The -4 is for the CRC in the trailer of the
434 skb_put(skb
, pkt_info
.byte_cnt
- 4);
437 if (pkt_info
.cmd_sts
& ETH_LAYER_4_CHECKSUM_OK
) {
438 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
440 (pkt_info
.cmd_sts
& 0x0007fff8) >> 3);
442 skb
->protocol
= eth_type_trans(skb
, dev
);
444 netif_receive_skb(skb
);
449 dev
->last_rx
= jiffies
;
452 return received_packets
;
456 * mv643xx_eth_int_handler
458 * Main interrupt handler for the gigbit ethernet ports
460 * Input : irq - irq number (not used)
461 * dev_id - a pointer to the required interface's data structure
466 static irqreturn_t
mv643xx_eth_int_handler(int irq
, void *dev_id
,
467 struct pt_regs
*regs
)
469 struct net_device
*dev
= (struct net_device
*)dev_id
;
470 struct mv643xx_private
*mp
= netdev_priv(dev
);
471 u32 eth_int_cause
, eth_int_cause_ext
= 0;
472 unsigned int port_num
= mp
->port_num
;
474 /* Read interrupt cause registers */
475 eth_int_cause
= mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num
)) &
478 if (eth_int_cause
& BIT1
)
479 eth_int_cause_ext
= mv_read(
480 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num
)) &
484 if (!(eth_int_cause
& 0x0007fffd)) {
485 /* Dont ack the Rx interrupt */
488 * Clear specific ethernet port intrerrupt registers by
489 * acknowleding relevant bits.
491 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num
),
493 if (eth_int_cause_ext
!= 0x0)
494 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG
495 (port_num
), ~eth_int_cause_ext
);
497 /* UDP change : We may need this */
498 if ((eth_int_cause_ext
& 0x0000ffff) &&
499 (mv643xx_eth_free_tx_queue(dev
, eth_int_cause_ext
) == 0) &&
500 (mp
->tx_ring_size
> mp
->tx_ring_skbs
+ MAX_DESCS_PER_SKB
))
501 netif_wake_queue(dev
);
504 if (netif_rx_schedule_prep(dev
)) {
505 /* Mask all the interrupts */
506 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
),
508 /* wait for previous write to complete */
509 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
));
510 __netif_rx_schedule(dev
);
513 if (eth_int_cause
& (BIT2
| BIT11
))
514 mv643xx_eth_receive_queue(dev
, 0);
517 * After forwarded received packets to upper layer, add a task
518 * in an interrupts enabled context that refills the RX ring
521 #ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
522 /* Mask all interrupts on ethernet port */
523 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
),
525 /* wait for previous write to take effect */
526 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
));
528 queue_task(&mp
->rx_task
, &tq_immediate
);
529 mark_bh(IMMEDIATE_BH
);
531 mp
->rx_task
.func(dev
);
535 /* PHY status changed */
536 if (eth_int_cause_ext
& (BIT16
| BIT20
)) {
537 if (eth_port_link_is_up(port_num
)) {
538 netif_carrier_on(dev
);
539 netif_wake_queue(dev
);
541 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG
544 netif_carrier_off(dev
);
545 netif_stop_queue(dev
);
550 * If no real interrupt occured, exit.
551 * This can happen when using gigE interrupt coalescing mechanism.
553 if ((eth_int_cause
== 0x0) && (eth_int_cause_ext
== 0x0))
562 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
565 * This routine sets the RX coalescing interrupt mechanism parameter.
566 * This parameter is a timeout counter, that counts in 64 t_clk
567 * chunks ; that when timeout event occurs a maskable interrupt
569 * The parameter is calculated using the tClk of the MV-643xx chip
570 * , and the required delay of the interrupt in usec.
573 * unsigned int eth_port_num Ethernet port number
574 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
575 * unsigned int delay Delay in usec
578 * Interrupt coalescing mechanism value is set in MV-643xx chip.
581 * The interrupt coalescing value set in the gigE port.
584 static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num
,
585 unsigned int t_clk
, unsigned int delay
)
587 unsigned int coal
= ((t_clk
/ 1000000) * delay
) / 64;
589 /* Set RX Coalescing mechanism */
590 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num
),
591 ((coal
& 0x3fff) << 8) |
592 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num
))
600 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
603 * This routine sets the TX coalescing interrupt mechanism parameter.
604 * This parameter is a timeout counter, that counts in 64 t_clk
605 * chunks ; that when timeout event occurs a maskable interrupt
607 * The parameter is calculated using the t_cLK frequency of the
608 * MV-643xx chip and the required delay in the interrupt in uSec
611 * unsigned int eth_port_num Ethernet port number
612 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
613 * unsigned int delay Delay in uSeconds
616 * Interrupt coalescing mechanism value is set in MV-643xx chip.
619 * The interrupt coalescing value set in the gigE port.
622 static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num
,
623 unsigned int t_clk
, unsigned int delay
)
626 coal
= ((t_clk
/ 1000000) * delay
) / 64;
627 /* Set TX Coalescing mechanism */
628 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num
),
634 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
637 * This function prepares a Rx chained list of descriptors and packet
638 * buffers in a form of a ring. The routine must be called after port
639 * initialization routine and before port start routine.
640 * The Ethernet SDMA engine uses CPU bus addresses to access the various
641 * devices in the system (i.e. DRAM). This function uses the ethernet
642 * struct 'virtual to physical' routine (set by the user) to set the ring
643 * with physical addresses.
646 * struct mv643xx_private *mp Ethernet Port Control srtuct.
649 * The routine updates the Ethernet port control struct with information
650 * regarding the Rx descriptors and buffers.
655 static void ether_init_rx_desc_ring(struct mv643xx_private
*mp
)
657 volatile struct eth_rx_desc
*p_rx_desc
;
658 int rx_desc_num
= mp
->rx_ring_size
;
661 /* initialize the next_desc_ptr links in the Rx descriptors ring */
662 p_rx_desc
= (struct eth_rx_desc
*)mp
->p_rx_desc_area
;
663 for (i
= 0; i
< rx_desc_num
; i
++) {
664 p_rx_desc
[i
].next_desc_ptr
= mp
->rx_desc_dma
+
665 ((i
+ 1) % rx_desc_num
) * sizeof(struct eth_rx_desc
);
668 /* Save Rx desc pointer to driver struct. */
669 mp
->rx_curr_desc_q
= 0;
670 mp
->rx_used_desc_q
= 0;
672 mp
->rx_desc_area_size
= rx_desc_num
* sizeof(struct eth_rx_desc
);
674 /* Add the queue to the list of RX queues of this port */
675 mp
->port_rx_queue_command
|= 1;
679 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
682 * This function prepares a Tx chained list of descriptors and packet
683 * buffers in a form of a ring. The routine must be called after port
684 * initialization routine and before port start routine.
685 * The Ethernet SDMA engine uses CPU bus addresses to access the various
686 * devices in the system (i.e. DRAM). This function uses the ethernet
687 * struct 'virtual to physical' routine (set by the user) to set the ring
688 * with physical addresses.
691 * struct mv643xx_private *mp Ethernet Port Control srtuct.
694 * The routine updates the Ethernet port control struct with information
695 * regarding the Tx descriptors and buffers.
700 static void ether_init_tx_desc_ring(struct mv643xx_private
*mp
)
702 int tx_desc_num
= mp
->tx_ring_size
;
703 struct eth_tx_desc
*p_tx_desc
;
706 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
707 p_tx_desc
= (struct eth_tx_desc
*)mp
->p_tx_desc_area
;
708 for (i
= 0; i
< tx_desc_num
; i
++) {
709 p_tx_desc
[i
].next_desc_ptr
= mp
->tx_desc_dma
+
710 ((i
+ 1) % tx_desc_num
) * sizeof(struct eth_tx_desc
);
713 mp
->tx_curr_desc_q
= 0;
714 mp
->tx_used_desc_q
= 0;
715 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
716 mp
->tx_first_desc_q
= 0;
719 mp
->tx_desc_area_size
= tx_desc_num
* sizeof(struct eth_tx_desc
);
721 /* Add the queue to the list of Tx queues of this port */
722 mp
->port_tx_queue_command
|= 1;
728 * This function is called when openning the network device. The function
729 * should initialize all the hardware, initialize cyclic Rx/Tx
730 * descriptors chain and buffers and allocate an IRQ to the network
733 * Input : a pointer to the network device structure
735 * Output : zero of success , nonzero if fails.
738 static int mv643xx_eth_open(struct net_device
*dev
)
740 struct mv643xx_private
*mp
= netdev_priv(dev
);
741 unsigned int port_num
= mp
->port_num
;
745 err
= request_irq(dev
->irq
, mv643xx_eth_int_handler
,
746 SA_SHIRQ
| SA_SAMPLE_RANDOM
, dev
->name
, dev
);
748 printk(KERN_ERR
"Can not assign IRQ number to MV643XX_eth%d\n",
754 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num
), 0x0000ff00);
756 /* Set the MAC Address */
757 memcpy(mp
->port_mac_addr
, dev
->dev_addr
, 6);
761 INIT_WORK(&mp
->rx_task
, (void (*)(void *))mv643xx_eth_rx_task
, dev
);
763 memset(&mp
->timeout
, 0, sizeof(struct timer_list
));
764 mp
->timeout
.function
= mv643xx_eth_rx_task_timer_wrapper
;
765 mp
->timeout
.data
= (unsigned long)dev
;
767 mp
->rx_task_busy
= 0;
768 mp
->rx_timer_flag
= 0;
770 /* Allocate RX and TX skb rings */
771 mp
->rx_skb
= kmalloc(sizeof(*mp
->rx_skb
) * mp
->rx_ring_size
,
774 printk(KERN_ERR
"%s: Cannot allocate Rx skb ring\n", dev
->name
);
778 mp
->tx_skb
= kmalloc(sizeof(*mp
->tx_skb
) * mp
->tx_ring_size
,
781 printk(KERN_ERR
"%s: Cannot allocate Tx skb ring\n", dev
->name
);
783 goto out_free_rx_skb
;
786 /* Allocate TX ring */
787 mp
->tx_ring_skbs
= 0;
788 size
= mp
->tx_ring_size
* sizeof(struct eth_tx_desc
);
789 mp
->tx_desc_area_size
= size
;
791 if (mp
->tx_sram_size
) {
792 mp
->p_tx_desc_area
= ioremap(mp
->tx_sram_addr
,
794 mp
->tx_desc_dma
= mp
->tx_sram_addr
;
796 mp
->p_tx_desc_area
= dma_alloc_coherent(NULL
, size
,
800 if (!mp
->p_tx_desc_area
) {
801 printk(KERN_ERR
"%s: Cannot allocate Tx Ring (size %d bytes)\n",
804 goto out_free_tx_skb
;
806 BUG_ON((u32
) mp
->p_tx_desc_area
& 0xf); /* check 16-byte alignment */
807 memset((void *)mp
->p_tx_desc_area
, 0, mp
->tx_desc_area_size
);
809 ether_init_tx_desc_ring(mp
);
811 /* Allocate RX ring */
812 mp
->rx_ring_skbs
= 0;
813 size
= mp
->rx_ring_size
* sizeof(struct eth_rx_desc
);
814 mp
->rx_desc_area_size
= size
;
816 if (mp
->rx_sram_size
) {
817 mp
->p_rx_desc_area
= ioremap(mp
->rx_sram_addr
,
819 mp
->rx_desc_dma
= mp
->rx_sram_addr
;
821 mp
->p_rx_desc_area
= dma_alloc_coherent(NULL
, size
,
825 if (!mp
->p_rx_desc_area
) {
826 printk(KERN_ERR
"%s: Cannot allocate Rx ring (size %d bytes)\n",
828 printk(KERN_ERR
"%s: Freeing previously allocated TX queues...",
830 if (mp
->rx_sram_size
)
831 iounmap(mp
->p_tx_desc_area
);
833 dma_free_coherent(NULL
, mp
->tx_desc_area_size
,
834 mp
->p_tx_desc_area
, mp
->tx_desc_dma
);
836 goto out_free_tx_skb
;
838 memset((void *)mp
->p_rx_desc_area
, 0, size
);
840 ether_init_rx_desc_ring(mp
);
842 mv643xx_eth_rx_task(dev
); /* Fill RX ring with skb's */
846 /* Interrupt Coalescing */
850 eth_port_set_rx_coal(port_num
, 133000000, MV643XX_RX_COAL
);
854 eth_port_set_tx_coal(port_num
, 133000000, MV643XX_TX_COAL
);
856 /* Clear any pending ethernet port interrupts */
857 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num
), 0);
858 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num
), 0);
860 /* Unmask phy and link status changes interrupts */
861 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num
),
864 /* Unmask RX buffer and TX end interrupt */
865 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
), INT_UNMASK_ALL
);
873 free_irq(dev
->irq
, dev
);
878 static void mv643xx_eth_free_tx_rings(struct net_device
*dev
)
880 struct mv643xx_private
*mp
= netdev_priv(dev
);
881 unsigned int port_num
= mp
->port_num
;
886 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num
), 0x0000ff00);
888 /* Free outstanding skb's on TX rings */
889 for (curr
= 0; mp
->tx_ring_skbs
&& curr
< mp
->tx_ring_size
; curr
++) {
890 skb
= mp
->tx_skb
[curr
];
892 mp
->tx_ring_skbs
-= skb_shinfo(skb
)->nr_frags
;
897 if (mp
->tx_ring_skbs
)
898 printk("%s: Error on Tx descriptor free - could not free %d"
899 " descriptors\n", dev
->name
, mp
->tx_ring_skbs
);
902 if (mp
->tx_sram_size
)
903 iounmap(mp
->p_tx_desc_area
);
905 dma_free_coherent(NULL
, mp
->tx_desc_area_size
,
906 mp
->p_tx_desc_area
, mp
->tx_desc_dma
);
909 static void mv643xx_eth_free_rx_rings(struct net_device
*dev
)
911 struct mv643xx_private
*mp
= netdev_priv(dev
);
912 unsigned int port_num
= mp
->port_num
;
916 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num
), 0x0000ff00);
918 /* Free preallocated skb's on RX rings */
919 for (curr
= 0; mp
->rx_ring_skbs
&& curr
< mp
->rx_ring_size
; curr
++) {
920 if (mp
->rx_skb
[curr
]) {
921 dev_kfree_skb(mp
->rx_skb
[curr
]);
926 if (mp
->rx_ring_skbs
)
928 "%s: Error in freeing Rx Ring. %d skb's still"
929 " stuck in RX Ring - ignoring them\n", dev
->name
,
932 if (mp
->rx_sram_size
)
933 iounmap(mp
->p_rx_desc_area
);
935 dma_free_coherent(NULL
, mp
->rx_desc_area_size
,
936 mp
->p_rx_desc_area
, mp
->rx_desc_dma
);
942 * This function is used when closing the network device.
943 * It updates the hardware,
944 * release all memory that holds buffers and descriptors and release the IRQ.
945 * Input : a pointer to the device structure
946 * Output : zero if success , nonzero if fails
949 static int mv643xx_eth_stop(struct net_device
*dev
)
951 struct mv643xx_private
*mp
= netdev_priv(dev
);
952 unsigned int port_num
= mp
->port_num
;
954 /* Mask all interrupts on ethernet port */
955 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
), INT_MASK_ALL
);
956 /* wait for previous write to complete */
957 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
));
960 netif_poll_disable(dev
);
962 netif_carrier_off(dev
);
963 netif_stop_queue(dev
);
965 eth_port_reset(mp
->port_num
);
967 mv643xx_eth_free_tx_rings(dev
);
968 mv643xx_eth_free_rx_rings(dev
);
971 netif_poll_enable(dev
);
974 free_irq(dev
->irq
, dev
);
980 static void mv643xx_tx(struct net_device
*dev
)
982 struct mv643xx_private
*mp
= netdev_priv(dev
);
983 struct pkt_info pkt_info
;
985 while (eth_tx_return_desc(mp
, &pkt_info
) == ETH_OK
) {
986 if (pkt_info
.cmd_sts
& ETH_TX_FIRST_DESC
)
987 dma_unmap_single(NULL
, pkt_info
.buf_ptr
,
991 dma_unmap_page(NULL
, pkt_info
.buf_ptr
,
995 if (pkt_info
.return_info
)
996 dev_kfree_skb_irq(pkt_info
.return_info
);
999 if (netif_queue_stopped(dev
) &&
1000 mp
->tx_ring_size
> mp
->tx_ring_skbs
+ MAX_DESCS_PER_SKB
)
1001 netif_wake_queue(dev
);
1007 * This function is used in case of NAPI
1009 static int mv643xx_poll(struct net_device
*dev
, int *budget
)
1011 struct mv643xx_private
*mp
= netdev_priv(dev
);
1012 int done
= 1, orig_budget
, work_done
;
1013 unsigned int port_num
= mp
->port_num
;
1015 #ifdef MV643XX_TX_FAST_REFILL
1016 if (++mp
->tx_clean_threshold
> 5) {
1018 mp
->tx_clean_threshold
= 0;
1022 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num
)))
1023 != (u32
) mp
->rx_used_desc_q
) {
1024 orig_budget
= *budget
;
1025 if (orig_budget
> dev
->quota
)
1026 orig_budget
= dev
->quota
;
1027 work_done
= mv643xx_eth_receive_queue(dev
, orig_budget
);
1028 mp
->rx_task
.func(dev
);
1029 *budget
-= work_done
;
1030 dev
->quota
-= work_done
;
1031 if (work_done
>= orig_budget
)
1036 netif_rx_complete(dev
);
1037 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num
), 0);
1038 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num
), 0);
1039 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
),
1043 return done
? 0 : 1;
1047 /* Hardware can't handle unaligned fragments smaller than 9 bytes.
1048 * This helper function detects that case.
1051 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff
*skb
)
1056 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
1057 fragp
= &skb_shinfo(skb
)->frags
[frag
];
1058 if (fragp
->size
<= 8 && fragp
->page_offset
& 0x7)
1066 * mv643xx_eth_start_xmit
1068 * This function is queues a packet in the Tx descriptor for
1071 * Input : skb - a pointer to socket buffer
1072 * dev - a pointer to the required port
1074 * Output : zero upon success
1076 static int mv643xx_eth_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1078 struct mv643xx_private
*mp
= netdev_priv(dev
);
1079 struct net_device_stats
*stats
= &mp
->stats
;
1080 ETH_FUNC_RET_STATUS status
;
1081 unsigned long flags
;
1082 struct pkt_info pkt_info
;
1084 if (netif_queue_stopped(dev
)) {
1086 "%s: Tried sending packet when interface is stopped\n",
1091 /* This is a hard error, log it. */
1092 if ((mp
->tx_ring_size
- mp
->tx_ring_skbs
) <=
1093 (skb_shinfo(skb
)->nr_frags
+ 1)) {
1094 netif_stop_queue(dev
);
1096 "%s: Bug in mv643xx_eth - Trying to transmit when"
1097 " queue full !\n", dev
->name
);
1101 /* Paranoid check - this shouldn't happen */
1103 stats
->tx_dropped
++;
1104 printk(KERN_ERR
"mv64320_eth paranoid check failed\n");
1108 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1109 if (has_tiny_unaligned_frags(skb
)) {
1110 if ((skb_linearize(skb
, GFP_ATOMIC
) != 0)) {
1111 stats
->tx_dropped
++;
1112 printk(KERN_DEBUG
"%s: failed to linearize tiny "
1113 "unaligned fragment\n", dev
->name
);
1118 spin_lock_irqsave(&mp
->lock
, flags
);
1120 if (!skb_shinfo(skb
)->nr_frags
) {
1121 if (skb
->ip_summed
!= CHECKSUM_HW
) {
1122 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1123 pkt_info
.cmd_sts
= ETH_TX_ENABLE_INTERRUPT
|
1126 5 << ETH_TX_IHL_SHIFT
;
1127 pkt_info
.l4i_chk
= 0;
1129 pkt_info
.cmd_sts
= ETH_TX_ENABLE_INTERRUPT
|
1132 ETH_GEN_TCP_UDP_CHECKSUM
|
1133 ETH_GEN_IP_V_4_CHECKSUM
|
1134 skb
->nh
.iph
->ihl
<< ETH_TX_IHL_SHIFT
;
1135 /* CPU already calculated pseudo header checksum. */
1136 if ((skb
->protocol
== ETH_P_IP
) &&
1137 (skb
->nh
.iph
->protocol
== IPPROTO_UDP
) ) {
1138 pkt_info
.cmd_sts
|= ETH_UDP_FRAME
;
1139 pkt_info
.l4i_chk
= skb
->h
.uh
->check
;
1140 } else if ((skb
->protocol
== ETH_P_IP
) &&
1141 (skb
->nh
.iph
->protocol
== IPPROTO_TCP
))
1142 pkt_info
.l4i_chk
= skb
->h
.th
->check
;
1145 "%s: chksum proto != IPv4 TCP or UDP\n",
1147 spin_unlock_irqrestore(&mp
->lock
, flags
);
1151 pkt_info
.byte_cnt
= skb
->len
;
1152 pkt_info
.buf_ptr
= dma_map_single(NULL
, skb
->data
, skb
->len
,
1154 pkt_info
.return_info
= skb
;
1155 status
= eth_port_send(mp
, &pkt_info
);
1156 if ((status
== ETH_ERROR
) || (status
== ETH_QUEUE_FULL
))
1157 printk(KERN_ERR
"%s: Error on transmitting packet\n",
1159 stats
->tx_bytes
+= pkt_info
.byte_cnt
;
1163 /* first frag which is skb header */
1164 pkt_info
.byte_cnt
= skb_headlen(skb
);
1165 pkt_info
.buf_ptr
= dma_map_single(NULL
, skb
->data
,
1168 pkt_info
.l4i_chk
= 0;
1169 pkt_info
.return_info
= 0;
1171 if (skb
->ip_summed
!= CHECKSUM_HW
)
1172 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1173 pkt_info
.cmd_sts
= ETH_TX_FIRST_DESC
|
1174 5 << ETH_TX_IHL_SHIFT
;
1176 pkt_info
.cmd_sts
= ETH_TX_FIRST_DESC
|
1177 ETH_GEN_TCP_UDP_CHECKSUM
|
1178 ETH_GEN_IP_V_4_CHECKSUM
|
1179 skb
->nh
.iph
->ihl
<< ETH_TX_IHL_SHIFT
;
1180 /* CPU already calculated pseudo header checksum. */
1181 if ((skb
->protocol
== ETH_P_IP
) &&
1182 (skb
->nh
.iph
->protocol
== IPPROTO_UDP
)) {
1183 pkt_info
.cmd_sts
|= ETH_UDP_FRAME
;
1184 pkt_info
.l4i_chk
= skb
->h
.uh
->check
;
1185 } else if ((skb
->protocol
== ETH_P_IP
) &&
1186 (skb
->nh
.iph
->protocol
== IPPROTO_TCP
))
1187 pkt_info
.l4i_chk
= skb
->h
.th
->check
;
1190 "%s: chksum proto != IPv4 TCP or UDP\n",
1192 spin_unlock_irqrestore(&mp
->lock
, flags
);
1197 status
= eth_port_send(mp
, &pkt_info
);
1198 if (status
!= ETH_OK
) {
1199 if ((status
== ETH_ERROR
))
1201 "%s: Error on transmitting packet\n",
1203 if (status
== ETH_QUEUE_FULL
)
1204 printk("Error on Queue Full \n");
1205 if (status
== ETH_QUEUE_LAST_RESOURCE
)
1206 printk("Tx resource error \n");
1208 stats
->tx_bytes
+= pkt_info
.byte_cnt
;
1210 /* Check for the remaining frags */
1211 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
1212 skb_frag_t
*this_frag
= &skb_shinfo(skb
)->frags
[frag
];
1213 pkt_info
.l4i_chk
= 0x0000;
1214 pkt_info
.cmd_sts
= 0x00000000;
1216 /* Last Frag enables interrupt and frees the skb */
1217 if (frag
== (skb_shinfo(skb
)->nr_frags
- 1)) {
1218 pkt_info
.cmd_sts
|= ETH_TX_ENABLE_INTERRUPT
|
1220 pkt_info
.return_info
= skb
;
1222 pkt_info
.return_info
= 0;
1224 pkt_info
.l4i_chk
= 0;
1225 pkt_info
.byte_cnt
= this_frag
->size
;
1227 pkt_info
.buf_ptr
= dma_map_page(NULL
, this_frag
->page
,
1228 this_frag
->page_offset
,
1232 status
= eth_port_send(mp
, &pkt_info
);
1234 if (status
!= ETH_OK
) {
1235 if ((status
== ETH_ERROR
))
1236 printk(KERN_ERR
"%s: Error on "
1237 "transmitting packet\n",
1240 if (status
== ETH_QUEUE_LAST_RESOURCE
)
1241 printk("Tx resource error \n");
1243 if (status
== ETH_QUEUE_FULL
)
1244 printk("Queue is full \n");
1246 stats
->tx_bytes
+= pkt_info
.byte_cnt
;
1250 spin_lock_irqsave(&mp
->lock
, flags
);
1252 pkt_info
.cmd_sts
= ETH_TX_ENABLE_INTERRUPT
| ETH_TX_FIRST_DESC
|
1254 pkt_info
.l4i_chk
= 0;
1255 pkt_info
.byte_cnt
= skb
->len
;
1256 pkt_info
.buf_ptr
= dma_map_single(NULL
, skb
->data
, skb
->len
,
1258 pkt_info
.return_info
= skb
;
1259 status
= eth_port_send(mp
, &pkt_info
);
1260 if ((status
== ETH_ERROR
) || (status
== ETH_QUEUE_FULL
))
1261 printk(KERN_ERR
"%s: Error on transmitting packet\n",
1263 stats
->tx_bytes
+= pkt_info
.byte_cnt
;
1266 /* Check if TX queue can handle another skb. If not, then
1267 * signal higher layers to stop requesting TX
1269 if (mp
->tx_ring_size
<= (mp
->tx_ring_skbs
+ MAX_DESCS_PER_SKB
))
1271 * Stop getting skb's from upper layers.
1272 * Getting skb's from upper layers will be enabled again after
1273 * packets are released.
1275 netif_stop_queue(dev
);
1277 /* Update statistics and start of transmittion time */
1278 stats
->tx_packets
++;
1279 dev
->trans_start
= jiffies
;
1281 spin_unlock_irqrestore(&mp
->lock
, flags
);
1283 return 0; /* success */
1287 * mv643xx_eth_get_stats
1289 * Returns a pointer to the interface statistics.
1291 * Input : dev - a pointer to the required interface
1293 * Output : a pointer to the interface's statistics
1296 static struct net_device_stats
*mv643xx_eth_get_stats(struct net_device
*dev
)
1298 struct mv643xx_private
*mp
= netdev_priv(dev
);
1303 #ifdef CONFIG_NET_POLL_CONTROLLER
1304 static void mv643xx_netpoll(struct net_device
*netdev
)
1306 struct mv643xx_private
*mp
= netdev_priv(netdev
);
1307 int port_num
= mp
->port_num
;
1309 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
), INT_MASK_ALL
);
1310 /* wait for previous write to complete */
1311 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
));
1313 mv643xx_eth_int_handler(netdev
->irq
, netdev
, NULL
);
1315 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
), INT_UNMASK_ALL
);
1322 * First function called after registering the network device.
1323 * It's purpose is to initialize the device as an ethernet device,
1324 * fill the ethernet device structure with pointers * to functions,
1325 * and set the MAC address of the interface
1327 * Input : struct device *
1328 * Output : -ENOMEM if failed , 0 if success
1330 static int mv643xx_eth_probe(struct platform_device
*pdev
)
1332 struct mv643xx_eth_platform_data
*pd
;
1333 int port_num
= pdev
->id
;
1334 struct mv643xx_private
*mp
;
1335 struct net_device
*dev
;
1337 struct resource
*res
;
1340 dev
= alloc_etherdev(sizeof(struct mv643xx_private
));
1344 platform_set_drvdata(pdev
, dev
);
1346 mp
= netdev_priv(dev
);
1348 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1350 dev
->irq
= res
->start
;
1352 mp
->port_num
= port_num
;
1354 dev
->open
= mv643xx_eth_open
;
1355 dev
->stop
= mv643xx_eth_stop
;
1356 dev
->hard_start_xmit
= mv643xx_eth_start_xmit
;
1357 dev
->get_stats
= mv643xx_eth_get_stats
;
1358 dev
->set_mac_address
= mv643xx_eth_set_mac_address
;
1359 dev
->set_multicast_list
= mv643xx_eth_set_rx_mode
;
1361 /* No need to Tx Timeout */
1362 dev
->tx_timeout
= mv643xx_eth_tx_timeout
;
1364 dev
->poll
= mv643xx_poll
;
1368 #ifdef CONFIG_NET_POLL_CONTROLLER
1369 dev
->poll_controller
= mv643xx_netpoll
;
1372 dev
->watchdog_timeo
= 2 * HZ
;
1373 dev
->tx_queue_len
= mp
->tx_ring_size
;
1375 dev
->change_mtu
= mv643xx_eth_change_mtu
;
1376 SET_ETHTOOL_OPS(dev
, &mv643xx_ethtool_ops
);
1378 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1379 #ifdef MAX_SKB_FRAGS
1381 * Zero copy can only work if we use Discovery II memory. Else, we will
1382 * have to map the buffers to ISA memory which is only 16 MB
1384 dev
->features
= NETIF_F_SG
| NETIF_F_IP_CSUM
;
1388 /* Configure the timeout task */
1389 INIT_WORK(&mp
->tx_timeout_task
,
1390 (void (*)(void *))mv643xx_eth_tx_timeout_task
, dev
);
1392 spin_lock_init(&mp
->lock
);
1394 /* set default config values */
1395 eth_port_uc_addr_get(dev
, dev
->dev_addr
);
1396 mp
->port_config
= MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE
;
1397 mp
->port_config_extend
= MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE
;
1398 mp
->port_sdma_config
= MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE
;
1399 mp
->port_serial_control
= MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE
;
1400 mp
->rx_ring_size
= MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE
;
1401 mp
->tx_ring_size
= MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE
;
1403 pd
= pdev
->dev
.platform_data
;
1405 if (pd
->mac_addr
!= NULL
)
1406 memcpy(dev
->dev_addr
, pd
->mac_addr
, 6);
1408 if (pd
->phy_addr
|| pd
->force_phy_addr
)
1409 ethernet_phy_set(port_num
, pd
->phy_addr
);
1411 if (pd
->port_config
|| pd
->force_port_config
)
1412 mp
->port_config
= pd
->port_config
;
1414 if (pd
->port_config_extend
|| pd
->force_port_config_extend
)
1415 mp
->port_config_extend
= pd
->port_config_extend
;
1417 if (pd
->port_sdma_config
|| pd
->force_port_sdma_config
)
1418 mp
->port_sdma_config
= pd
->port_sdma_config
;
1420 if (pd
->port_serial_control
|| pd
->force_port_serial_control
)
1421 mp
->port_serial_control
= pd
->port_serial_control
;
1423 if (pd
->rx_queue_size
)
1424 mp
->rx_ring_size
= pd
->rx_queue_size
;
1426 if (pd
->tx_queue_size
)
1427 mp
->tx_ring_size
= pd
->tx_queue_size
;
1429 if (pd
->tx_sram_size
) {
1430 mp
->tx_sram_size
= pd
->tx_sram_size
;
1431 mp
->tx_sram_addr
= pd
->tx_sram_addr
;
1434 if (pd
->rx_sram_size
) {
1435 mp
->rx_sram_size
= pd
->rx_sram_size
;
1436 mp
->rx_sram_addr
= pd
->rx_sram_addr
;
1440 err
= ethernet_phy_detect(port_num
);
1442 pr_debug("MV643xx ethernet port %d: "
1443 "No PHY detected at addr %d\n",
1444 port_num
, ethernet_phy_get(port_num
));
1448 err
= register_netdev(dev
);
1454 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1455 dev
->name
, port_num
, p
[0], p
[1], p
[2], p
[3], p
[4], p
[5]);
1457 if (dev
->features
& NETIF_F_SG
)
1458 printk(KERN_NOTICE
"%s: Scatter Gather Enabled\n", dev
->name
);
1460 if (dev
->features
& NETIF_F_IP_CSUM
)
1461 printk(KERN_NOTICE
"%s: TX TCP/IP Checksumming Supported\n",
1464 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1465 printk(KERN_NOTICE
"%s: RX TCP/UDP Checksum Offload ON \n", dev
->name
);
1469 printk(KERN_NOTICE
"%s: TX and RX Interrupt Coalescing ON \n",
1474 printk(KERN_NOTICE
"%s: RX NAPI Enabled \n", dev
->name
);
1477 if (mp
->tx_sram_size
> 0)
1478 printk(KERN_NOTICE
"%s: Using SRAM\n", dev
->name
);
1488 static int mv643xx_eth_remove(struct platform_device
*pdev
)
1490 struct net_device
*dev
= platform_get_drvdata(pdev
);
1492 unregister_netdev(dev
);
1493 flush_scheduled_work();
1496 platform_set_drvdata(pdev
, NULL
);
1500 static int mv643xx_eth_shared_probe(struct platform_device
*pdev
)
1502 struct resource
*res
;
1504 printk(KERN_NOTICE
"MV-643xx 10/100/1000 Ethernet Driver\n");
1506 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1510 mv643xx_eth_shared_base
= ioremap(res
->start
,
1511 MV643XX_ETH_SHARED_REGS_SIZE
);
1512 if (mv643xx_eth_shared_base
== NULL
)
1519 static int mv643xx_eth_shared_remove(struct platform_device
*pdev
)
1521 iounmap(mv643xx_eth_shared_base
);
1522 mv643xx_eth_shared_base
= NULL
;
1527 static struct platform_driver mv643xx_eth_driver
= {
1528 .probe
= mv643xx_eth_probe
,
1529 .remove
= mv643xx_eth_remove
,
1531 .name
= MV643XX_ETH_NAME
,
1535 static struct platform_driver mv643xx_eth_shared_driver
= {
1536 .probe
= mv643xx_eth_shared_probe
,
1537 .remove
= mv643xx_eth_shared_remove
,
1539 .name
= MV643XX_ETH_SHARED_NAME
,
1544 * mv643xx_init_module
1546 * Registers the network drivers into the Linux kernel
1552 static int __init
mv643xx_init_module(void)
1556 rc
= platform_driver_register(&mv643xx_eth_shared_driver
);
1558 rc
= platform_driver_register(&mv643xx_eth_driver
);
1560 platform_driver_unregister(&mv643xx_eth_shared_driver
);
1566 * mv643xx_cleanup_module
1568 * Registers the network drivers into the Linux kernel
1574 static void __exit
mv643xx_cleanup_module(void)
1576 platform_driver_unregister(&mv643xx_eth_driver
);
1577 platform_driver_unregister(&mv643xx_eth_shared_driver
);
1580 module_init(mv643xx_init_module
);
1581 module_exit(mv643xx_cleanup_module
);
1583 MODULE_LICENSE("GPL");
1584 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1585 " and Dale Farnsworth");
1586 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1589 * The second part is the low level driver of the gigE ethernet ports.
1593 * Marvell's Gigabit Ethernet controller low level driver
1596 * This file introduce low level API to Marvell's Gigabit Ethernet
1597 * controller. This Gigabit Ethernet Controller driver API controls
1598 * 1) Operations (i.e. port init, start, reset etc').
1599 * 2) Data flow (i.e. port send, receive etc').
1600 * Each Gigabit Ethernet port is controlled via
1601 * struct mv643xx_private.
1602 * This struct includes user configuration information as well as
1603 * driver internal data needed for its operations.
1605 * Supported Features:
1606 * - This low level driver is OS independent. Allocating memory for
1607 * the descriptor rings and buffers are not within the scope of
1609 * - The user is free from Rx/Tx queue managing.
1610 * - This low level driver introduce functionality API that enable
1611 * the to operate Marvell's Gigabit Ethernet Controller in a
1613 * - Simple Gigabit Ethernet port operation API.
1614 * - Simple Gigabit Ethernet port data flow API.
1615 * - Data flow and operation API support per queue functionality.
1616 * - Support cached descriptors for better performance.
1617 * - Enable access to all four DRAM banks and internal SRAM memory
1619 * - PHY access and control API.
1620 * - Port control register configuration API.
1621 * - Full control over Unicast and Multicast MAC configurations.
1625 * Initialization phase
1626 * This phase complete the initialization of the the
1627 * mv643xx_private struct.
1628 * User information regarding port configuration has to be set
1629 * prior to calling the port initialization routine.
1631 * In this phase any port Tx/Rx activity is halted, MIB counters
1632 * are cleared, PHY address is set according to user parameter and
1633 * access to DRAM and internal SRAM memory spaces.
1635 * Driver ring initialization
1636 * Allocating memory for the descriptor rings and buffers is not
1637 * within the scope of this driver. Thus, the user is required to
1638 * allocate memory for the descriptors ring and buffers. Those
1639 * memory parameters are used by the Rx and Tx ring initialization
1640 * routines in order to curve the descriptor linked list in a form
1642 * Note: Pay special attention to alignment issues when using
1643 * cached descriptors/buffers. In this phase the driver store
1644 * information in the mv643xx_private struct regarding each queue
1648 * This phase prepares the Ethernet port for Rx and Tx activity.
1649 * It uses the information stored in the mv643xx_private struct to
1650 * initialize the various port registers.
1653 * All packet references to/from the driver are done using
1655 * This struct is a unified struct used with Rx and Tx operations.
1656 * This way the user is not required to be familiar with neither
1657 * Tx nor Rx descriptors structures.
1658 * The driver's descriptors rings are management by indexes.
1659 * Those indexes controls the ring resources and used to indicate
1660 * a SW resource error:
1662 * This index points to the current available resource for use. For
1663 * example in Rx process this index will point to the descriptor
1664 * that will be passed to the user upon calling the receive
1665 * routine. In Tx process, this index will point to the descriptor
1666 * that will be assigned with the user packet info and transmitted.
1668 * This index points to the descriptor that need to restore its
1669 * resources. For example in Rx process, using the Rx buffer return
1670 * API will attach the buffer returned in packet info to the
1671 * descriptor pointed by 'used'. In Tx process, using the Tx
1672 * descriptor return will merely return the user packet info with
1673 * the command status of the transmitted buffer pointed by the
1674 * 'used' index. Nevertheless, it is essential to use this routine
1675 * to update the 'used' index.
1677 * This index supports Tx Scatter-Gather. It points to the first
1678 * descriptor of a packet assembled of multiple buffers. For
1679 * example when in middle of Such packet we have a Tx resource
1680 * error the 'curr' index get the value of 'first' to indicate
1681 * that the ring returned to its state before trying to transmit
1684 * Receive operation:
1685 * The eth_port_receive API set the packet information struct,
1686 * passed by the caller, with received information from the
1687 * 'current' SDMA descriptor.
1688 * It is the user responsibility to return this resource back
1689 * to the Rx descriptor ring to enable the reuse of this source.
1690 * Return Rx resource is done using the eth_rx_return_buff API.
1692 * Transmit operation:
1693 * The eth_port_send API supports Scatter-Gather which enables to
1694 * send a packet spanned over multiple buffers. This means that
1695 * for each packet info structure given by the user and put into
1696 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1697 * bit will be set in the packet info command status field. This
1698 * API also consider restriction regarding buffer alignments and
1700 * The user must return a Tx resource after ensuring the buffer
1701 * has been transmitted to enable the Tx ring indexes to update.
1704 * This device is on-board. No jumper diagram is necessary.
1706 * EXTERNAL INTERFACE
1708 * Prior to calling the initialization routine eth_port_init() the user
1709 * must set the following fields under mv643xx_private struct:
1710 * port_num User Ethernet port number.
1711 * port_mac_addr[6] User defined port MAC address.
1712 * port_config User port configuration value.
1713 * port_config_extend User port config extend value.
1714 * port_sdma_config User port SDMA config value.
1715 * port_serial_control User port serial control value.
1717 * This driver data flow is done using the struct pkt_info which
1718 * is a unified struct for Rx and Tx operations:
1720 * byte_cnt Tx/Rx descriptor buffer byte count.
1721 * l4i_chk CPU provided TCP Checksum. For Tx operation
1723 * cmd_sts Tx/Rx descriptor command status.
1724 * buf_ptr Tx/Rx descriptor buffer pointer.
1725 * return_info Tx/Rx user resource return information.
1729 /* SDMA command macros */
1730 #define ETH_ENABLE_TX_QUEUE(eth_port) \
1731 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), 1)
1736 static int ethernet_phy_get(unsigned int eth_port_num
);
1737 static void ethernet_phy_set(unsigned int eth_port_num
, int phy_addr
);
1739 /* Ethernet Port routines */
1740 static int eth_port_uc_addr(unsigned int eth_port_num
, unsigned char uc_nibble
,
1744 * eth_port_init - Initialize the Ethernet port driver
1747 * This function prepares the ethernet port to start its activity:
1748 * 1) Completes the ethernet port driver struct initialization toward port
1750 * 2) Resets the device to a quiescent state in case of warm reboot.
1751 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1752 * 4) Clean MAC tables. The reset status of those tables is unknown.
1753 * 5) Set PHY address.
1754 * Note: Call this routine prior to eth_port_start routine and after
1755 * setting user values in the user fields of Ethernet port control
1759 * struct mv643xx_private *mp Ethernet port control struct
1767 static void eth_port_init(struct mv643xx_private
*mp
)
1769 mp
->port_rx_queue_command
= 0;
1770 mp
->port_tx_queue_command
= 0;
1772 mp
->rx_resource_err
= 0;
1773 mp
->tx_resource_err
= 0;
1775 eth_port_reset(mp
->port_num
);
1777 eth_port_init_mac_tables(mp
->port_num
);
1779 ethernet_phy_reset(mp
->port_num
);
1783 * eth_port_start - Start the Ethernet port activity.
1786 * This routine prepares the Ethernet port for Rx and Tx activity:
1787 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1788 * has been initialized a descriptor's ring (using
1789 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1790 * 2. Initialize and enable the Ethernet configuration port by writing to
1791 * the port's configuration and command registers.
1792 * 3. Initialize and enable the SDMA by writing to the SDMA's
1793 * configuration and command registers. After completing these steps,
1794 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1796 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1797 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1798 * and ether_init_rx_desc_ring for Rx queues).
1801 * struct mv643xx_private *mp Ethernet port control struct
1804 * Ethernet port is ready to receive and transmit.
1809 static void eth_port_start(struct mv643xx_private
*mp
)
1811 unsigned int port_num
= mp
->port_num
;
1812 int tx_curr_desc
, rx_curr_desc
;
1814 /* Assignment of Tx CTRP of given queue */
1815 tx_curr_desc
= mp
->tx_curr_desc_q
;
1816 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num
),
1817 (u32
)((struct eth_tx_desc
*)mp
->tx_desc_dma
+ tx_curr_desc
));
1819 /* Assignment of Rx CRDP of given queue */
1820 rx_curr_desc
= mp
->rx_curr_desc_q
;
1821 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num
),
1822 (u32
)((struct eth_rx_desc
*)mp
->rx_desc_dma
+ rx_curr_desc
));
1824 /* Add the assigned Ethernet address to the port's address table */
1825 eth_port_uc_addr_set(port_num
, mp
->port_mac_addr
);
1827 /* Assign port configuration and command. */
1828 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num
), mp
->port_config
);
1830 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num
),
1831 mp
->port_config_extend
);
1834 /* Increase the Rx side buffer size if supporting GigE */
1835 if (mp
->port_serial_control
& MV643XX_ETH_SET_GMII_SPEED_TO_1000
)
1836 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
),
1837 (mp
->port_serial_control
& 0xfff1ffff) | (0x5 << 17));
1839 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
),
1840 mp
->port_serial_control
);
1842 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
),
1843 mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
)) |
1844 MV643XX_ETH_SERIAL_PORT_ENABLE
);
1846 /* Assign port SDMA configuration */
1847 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num
),
1848 mp
->port_sdma_config
);
1850 /* Enable port Rx. */
1851 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num
),
1852 mp
->port_rx_queue_command
);
1854 /* Disable port bandwidth limits by clearing MTU register */
1855 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num
), 0);
1859 * eth_port_uc_addr_set - This function Set the port Unicast address.
1862 * This function Set the port Ethernet MAC address.
1865 * unsigned int eth_port_num Port number.
1866 * char * p_addr Address to be set
1869 * Set MAC address low and high registers. also calls eth_port_uc_addr()
1870 * To set the unicast table with the proper information.
1876 static void eth_port_uc_addr_set(unsigned int eth_port_num
,
1877 unsigned char *p_addr
)
1882 mac_l
= (p_addr
[4] << 8) | (p_addr
[5]);
1883 mac_h
= (p_addr
[0] << 24) | (p_addr
[1] << 16) | (p_addr
[2] << 8) |
1886 mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num
), mac_l
);
1887 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num
), mac_h
);
1889 /* Accept frames of this address */
1890 eth_port_uc_addr(eth_port_num
, p_addr
[5], ACCEPT_MAC_ADDR
);
1896 * eth_port_uc_addr_get - This function retrieves the port Unicast address
1897 * (MAC address) from the ethernet hw registers.
1900 * This function retrieves the port Ethernet MAC address.
1903 * unsigned int eth_port_num Port number.
1904 * char *MacAddr pointer where the MAC address is stored
1907 * Copy the MAC address to the location pointed to by MacAddr
1913 static void eth_port_uc_addr_get(struct net_device
*dev
, unsigned char *p_addr
)
1915 struct mv643xx_private
*mp
= netdev_priv(dev
);
1919 mac_h
= mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp
->port_num
));
1920 mac_l
= mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp
->port_num
));
1922 p_addr
[0] = (mac_h
>> 24) & 0xff;
1923 p_addr
[1] = (mac_h
>> 16) & 0xff;
1924 p_addr
[2] = (mac_h
>> 8) & 0xff;
1925 p_addr
[3] = mac_h
& 0xff;
1926 p_addr
[4] = (mac_l
>> 8) & 0xff;
1927 p_addr
[5] = mac_l
& 0xff;
1931 * eth_port_uc_addr - This function Set the port unicast address table
1934 * This function locates the proper entry in the Unicast table for the
1935 * specified MAC nibble and sets its properties according to function
1939 * unsigned int eth_port_num Port number.
1940 * unsigned char uc_nibble Unicast MAC Address last nibble.
1941 * int option 0 = Add, 1 = remove address.
1944 * This function add/removes MAC addresses from the port unicast address
1948 * true is output succeeded.
1949 * false if option parameter is invalid.
1952 static int eth_port_uc_addr(unsigned int eth_port_num
, unsigned char uc_nibble
,
1955 unsigned int unicast_reg
;
1956 unsigned int tbl_offset
;
1957 unsigned int reg_offset
;
1959 /* Locate the Unicast table entry */
1960 uc_nibble
= (0xf & uc_nibble
);
1961 tbl_offset
= (uc_nibble
/ 4) * 4; /* Register offset from unicast table base */
1962 reg_offset
= uc_nibble
% 4; /* Entry offset within the above register */
1965 case REJECT_MAC_ADDR
:
1966 /* Clear accepts frame bit at given unicast DA table entry */
1967 unicast_reg
= mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
1968 (eth_port_num
) + tbl_offset
));
1970 unicast_reg
&= (0x0E << (8 * reg_offset
));
1972 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
1973 (eth_port_num
) + tbl_offset
), unicast_reg
);
1976 case ACCEPT_MAC_ADDR
:
1977 /* Set accepts frame bit at unicast DA filter table entry */
1979 mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
1980 (eth_port_num
) + tbl_offset
));
1982 unicast_reg
|= (0x01 << (8 * reg_offset
));
1984 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
1985 (eth_port_num
) + tbl_offset
), unicast_reg
);
1997 * The entries in each table are indexed by a hash of a packet's MAC
1998 * address. One bit in each entry determines whether the packet is
1999 * accepted. There are 4 entries (each 8 bits wide) in each register
2000 * of the table. The bits in each entry are defined as follows:
2001 * 0 Accept=1, Drop=0
2002 * 3-1 Queue (ETH_Q0=0)
2005 static void eth_port_set_filter_table_entry(int table
, unsigned char entry
)
2007 unsigned int table_reg
;
2008 unsigned int tbl_offset
;
2009 unsigned int reg_offset
;
2011 tbl_offset
= (entry
/ 4) * 4; /* Register offset of DA table entry */
2012 reg_offset
= entry
% 4; /* Entry offset within the register */
2014 /* Set "accepts frame bit" at specified table entry */
2015 table_reg
= mv_read(table
+ tbl_offset
);
2016 table_reg
|= 0x01 << (8 * reg_offset
);
2017 mv_write(table
+ tbl_offset
, table_reg
);
2021 * eth_port_mc_addr - Multicast address settings.
2023 * The MV device supports multicast using two tables:
2024 * 1) Special Multicast Table for MAC addresses of the form
2025 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
2026 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2027 * Table entries in the DA-Filter table.
2028 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
2029 * is used as an index to the Other Multicast Table entries in the
2030 * DA-Filter table. This function calculates the CRC-8bit value.
2031 * In either case, eth_port_set_filter_table_entry() is then called
2032 * to set to set the actual table entry.
2034 static void eth_port_mc_addr(unsigned int eth_port_num
, unsigned char *p_addr
)
2038 unsigned char crc_result
= 0;
2044 if ((p_addr
[0] == 0x01) && (p_addr
[1] == 0x00) &&
2045 (p_addr
[2] == 0x5E) && (p_addr
[3] == 0x00) && (p_addr
[4] == 0x00)) {
2046 table
= MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2048 eth_port_set_filter_table_entry(table
, p_addr
[5]);
2052 /* Calculate CRC-8 out of the given address */
2053 mac_h
= (p_addr
[0] << 8) | (p_addr
[1]);
2054 mac_l
= (p_addr
[2] << 24) | (p_addr
[3] << 16) |
2055 (p_addr
[4] << 8) | (p_addr
[5] << 0);
2057 for (i
= 0; i
< 32; i
++)
2058 mac_array
[i
] = (mac_l
>> i
) & 0x1;
2059 for (i
= 32; i
< 48; i
++)
2060 mac_array
[i
] = (mac_h
>> (i
- 32)) & 0x1;
2062 crc
[0] = mac_array
[45] ^ mac_array
[43] ^ mac_array
[40] ^ mac_array
[39] ^
2063 mac_array
[35] ^ mac_array
[34] ^ mac_array
[31] ^ mac_array
[30] ^
2064 mac_array
[28] ^ mac_array
[23] ^ mac_array
[21] ^ mac_array
[19] ^
2065 mac_array
[18] ^ mac_array
[16] ^ mac_array
[14] ^ mac_array
[12] ^
2066 mac_array
[8] ^ mac_array
[7] ^ mac_array
[6] ^ mac_array
[0];
2068 crc
[1] = mac_array
[46] ^ mac_array
[45] ^ mac_array
[44] ^ mac_array
[43] ^
2069 mac_array
[41] ^ mac_array
[39] ^ mac_array
[36] ^ mac_array
[34] ^
2070 mac_array
[32] ^ mac_array
[30] ^ mac_array
[29] ^ mac_array
[28] ^
2071 mac_array
[24] ^ mac_array
[23] ^ mac_array
[22] ^ mac_array
[21] ^
2072 mac_array
[20] ^ mac_array
[18] ^ mac_array
[17] ^ mac_array
[16] ^
2073 mac_array
[15] ^ mac_array
[14] ^ mac_array
[13] ^ mac_array
[12] ^
2074 mac_array
[9] ^ mac_array
[6] ^ mac_array
[1] ^ mac_array
[0];
2076 crc
[2] = mac_array
[47] ^ mac_array
[46] ^ mac_array
[44] ^ mac_array
[43] ^
2077 mac_array
[42] ^ mac_array
[39] ^ mac_array
[37] ^ mac_array
[34] ^
2078 mac_array
[33] ^ mac_array
[29] ^ mac_array
[28] ^ mac_array
[25] ^
2079 mac_array
[24] ^ mac_array
[22] ^ mac_array
[17] ^ mac_array
[15] ^
2080 mac_array
[13] ^ mac_array
[12] ^ mac_array
[10] ^ mac_array
[8] ^
2081 mac_array
[6] ^ mac_array
[2] ^ mac_array
[1] ^ mac_array
[0];
2083 crc
[3] = mac_array
[47] ^ mac_array
[45] ^ mac_array
[44] ^ mac_array
[43] ^
2084 mac_array
[40] ^ mac_array
[38] ^ mac_array
[35] ^ mac_array
[34] ^
2085 mac_array
[30] ^ mac_array
[29] ^ mac_array
[26] ^ mac_array
[25] ^
2086 mac_array
[23] ^ mac_array
[18] ^ mac_array
[16] ^ mac_array
[14] ^
2087 mac_array
[13] ^ mac_array
[11] ^ mac_array
[9] ^ mac_array
[7] ^
2088 mac_array
[3] ^ mac_array
[2] ^ mac_array
[1];
2090 crc
[4] = mac_array
[46] ^ mac_array
[45] ^ mac_array
[44] ^ mac_array
[41] ^
2091 mac_array
[39] ^ mac_array
[36] ^ mac_array
[35] ^ mac_array
[31] ^
2092 mac_array
[30] ^ mac_array
[27] ^ mac_array
[26] ^ mac_array
[24] ^
2093 mac_array
[19] ^ mac_array
[17] ^ mac_array
[15] ^ mac_array
[14] ^
2094 mac_array
[12] ^ mac_array
[10] ^ mac_array
[8] ^ mac_array
[4] ^
2095 mac_array
[3] ^ mac_array
[2];
2097 crc
[5] = mac_array
[47] ^ mac_array
[46] ^ mac_array
[45] ^ mac_array
[42] ^
2098 mac_array
[40] ^ mac_array
[37] ^ mac_array
[36] ^ mac_array
[32] ^
2099 mac_array
[31] ^ mac_array
[28] ^ mac_array
[27] ^ mac_array
[25] ^
2100 mac_array
[20] ^ mac_array
[18] ^ mac_array
[16] ^ mac_array
[15] ^
2101 mac_array
[13] ^ mac_array
[11] ^ mac_array
[9] ^ mac_array
[5] ^
2102 mac_array
[4] ^ mac_array
[3];
2104 crc
[6] = mac_array
[47] ^ mac_array
[46] ^ mac_array
[43] ^ mac_array
[41] ^
2105 mac_array
[38] ^ mac_array
[37] ^ mac_array
[33] ^ mac_array
[32] ^
2106 mac_array
[29] ^ mac_array
[28] ^ mac_array
[26] ^ mac_array
[21] ^
2107 mac_array
[19] ^ mac_array
[17] ^ mac_array
[16] ^ mac_array
[14] ^
2108 mac_array
[12] ^ mac_array
[10] ^ mac_array
[6] ^ mac_array
[5] ^
2111 crc
[7] = mac_array
[47] ^ mac_array
[44] ^ mac_array
[42] ^ mac_array
[39] ^
2112 mac_array
[38] ^ mac_array
[34] ^ mac_array
[33] ^ mac_array
[30] ^
2113 mac_array
[29] ^ mac_array
[27] ^ mac_array
[22] ^ mac_array
[20] ^
2114 mac_array
[18] ^ mac_array
[17] ^ mac_array
[15] ^ mac_array
[13] ^
2115 mac_array
[11] ^ mac_array
[7] ^ mac_array
[6] ^ mac_array
[5];
2117 for (i
= 0; i
< 8; i
++)
2118 crc_result
= crc_result
| (crc
[i
] << i
);
2120 table
= MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num
);
2121 eth_port_set_filter_table_entry(table
, crc_result
);
2125 * Set the entire multicast list based on dev->mc_list.
2127 static void eth_port_set_multicast_list(struct net_device
*dev
)
2130 struct dev_mc_list
*mc_list
;
2133 struct mv643xx_private
*mp
= netdev_priv(dev
);
2134 unsigned int eth_port_num
= mp
->port_num
;
2136 /* If the device is in promiscuous mode or in all multicast mode,
2137 * we will fully populate both multicast tables with accept.
2138 * This is guaranteed to yield a match on all multicast addresses...
2140 if ((dev
->flags
& IFF_PROMISC
) || (dev
->flags
& IFF_ALLMULTI
)) {
2141 for (table_index
= 0; table_index
<= 0xFC; table_index
+= 4) {
2142 /* Set all entries in DA filter special multicast
2144 * Set for ETH_Q0 for now
2146 * 0 Accept=1, Drop=0
2147 * 3-1 Queue ETH_Q0=0
2150 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num
) + table_index
, 0x01010101);
2152 /* Set all entries in DA filter other multicast
2154 * Set for ETH_Q0 for now
2156 * 0 Accept=1, Drop=0
2157 * 3-1 Queue ETH_Q0=0
2160 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num
) + table_index
, 0x01010101);
2165 /* We will clear out multicast tables every time we get the list.
2166 * Then add the entire new list...
2168 for (table_index
= 0; table_index
<= 0xFC; table_index
+= 4) {
2169 /* Clear DA filter special multicast table (Ex_dFSMT) */
2170 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2171 (eth_port_num
) + table_index
, 0);
2173 /* Clear DA filter other multicast table (Ex_dFOMT) */
2174 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2175 (eth_port_num
) + table_index
, 0);
2178 /* Get pointer to net_device multicast list and add each one... */
2179 for (i
= 0, mc_list
= dev
->mc_list
;
2180 (i
< 256) && (mc_list
!= NULL
) && (i
< dev
->mc_count
);
2181 i
++, mc_list
= mc_list
->next
)
2182 if (mc_list
->dmi_addrlen
== 6)
2183 eth_port_mc_addr(eth_port_num
, mc_list
->dmi_addr
);
2187 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2190 * Go through all the DA filter tables (Unicast, Special Multicast &
2191 * Other Multicast) and set each entry to 0.
2194 * unsigned int eth_port_num Ethernet Port number.
2197 * Multicast and Unicast packets are rejected.
2202 static void eth_port_init_mac_tables(unsigned int eth_port_num
)
2206 /* Clear DA filter unicast table (Ex_dFUT) */
2207 for (table_index
= 0; table_index
<= 0xC; table_index
+= 4)
2208 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2209 (eth_port_num
) + table_index
), 0);
2211 for (table_index
= 0; table_index
<= 0xFC; table_index
+= 4) {
2212 /* Clear DA filter special multicast table (Ex_dFSMT) */
2213 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2214 (eth_port_num
) + table_index
, 0);
2215 /* Clear DA filter other multicast table (Ex_dFOMT) */
2216 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2217 (eth_port_num
) + table_index
, 0);
2222 * eth_clear_mib_counters - Clear all MIB counters
2225 * This function clears all MIB counters of a specific ethernet port.
2226 * A read from the MIB counter will reset the counter.
2229 * unsigned int eth_port_num Ethernet Port number.
2232 * After reading all MIB counters, the counters resets.
2235 * MIB counter value.
2238 static void eth_clear_mib_counters(unsigned int eth_port_num
)
2242 /* Perform dummy reads from MIB counters */
2243 for (i
= ETH_MIB_GOOD_OCTETS_RECEIVED_LOW
; i
< ETH_MIB_LATE_COLLISION
;
2245 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num
) + i
);
2248 static inline u32
read_mib(struct mv643xx_private
*mp
, int offset
)
2250 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp
->port_num
) + offset
);
2253 static void eth_update_mib_counters(struct mv643xx_private
*mp
)
2255 struct mv643xx_mib_counters
*p
= &mp
->mib_counters
;
2258 p
->good_octets_received
+=
2259 read_mib(mp
, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW
);
2260 p
->good_octets_received
+=
2261 (u64
)read_mib(mp
, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
) << 32;
2263 for (offset
= ETH_MIB_BAD_OCTETS_RECEIVED
;
2264 offset
<= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS
;
2266 *(u32
*)((char *)p
+ offset
) = read_mib(mp
, offset
);
2268 p
->good_octets_sent
+= read_mib(mp
, ETH_MIB_GOOD_OCTETS_SENT_LOW
);
2269 p
->good_octets_sent
+=
2270 (u64
)read_mib(mp
, ETH_MIB_GOOD_OCTETS_SENT_HIGH
) << 32;
2272 for (offset
= ETH_MIB_GOOD_FRAMES_SENT
;
2273 offset
<= ETH_MIB_LATE_COLLISION
;
2275 *(u32
*)((char *)p
+ offset
) = read_mib(mp
, offset
);
2279 * ethernet_phy_detect - Detect whether a phy is present
2282 * This function tests whether there is a PHY present on
2283 * the specified port.
2286 * unsigned int eth_port_num Ethernet Port number.
2293 * -ENODEV on failure
2296 static int ethernet_phy_detect(unsigned int port_num
)
2298 unsigned int phy_reg_data0
;
2301 eth_port_read_smi_reg(port_num
, 0, &phy_reg_data0
);
2302 auto_neg
= phy_reg_data0
& 0x1000;
2303 phy_reg_data0
^= 0x1000; /* invert auto_neg */
2304 eth_port_write_smi_reg(port_num
, 0, phy_reg_data0
);
2306 eth_port_read_smi_reg(port_num
, 0, &phy_reg_data0
);
2307 if ((phy_reg_data0
& 0x1000) == auto_neg
)
2308 return -ENODEV
; /* change didn't take */
2310 phy_reg_data0
^= 0x1000;
2311 eth_port_write_smi_reg(port_num
, 0, phy_reg_data0
);
2316 * ethernet_phy_get - Get the ethernet port PHY address.
2319 * This routine returns the given ethernet port PHY address.
2322 * unsigned int eth_port_num Ethernet Port number.
2331 static int ethernet_phy_get(unsigned int eth_port_num
)
2333 unsigned int reg_data
;
2335 reg_data
= mv_read(MV643XX_ETH_PHY_ADDR_REG
);
2337 return ((reg_data
>> (5 * eth_port_num
)) & 0x1f);
2341 * ethernet_phy_set - Set the ethernet port PHY address.
2344 * This routine sets the given ethernet port PHY address.
2347 * unsigned int eth_port_num Ethernet Port number.
2348 * int phy_addr PHY address.
2357 static void ethernet_phy_set(unsigned int eth_port_num
, int phy_addr
)
2360 int addr_shift
= 5 * eth_port_num
;
2362 reg_data
= mv_read(MV643XX_ETH_PHY_ADDR_REG
);
2363 reg_data
&= ~(0x1f << addr_shift
);
2364 reg_data
|= (phy_addr
& 0x1f) << addr_shift
;
2365 mv_write(MV643XX_ETH_PHY_ADDR_REG
, reg_data
);
2369 * ethernet_phy_reset - Reset Ethernet port PHY.
2372 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2375 * unsigned int eth_port_num Ethernet Port number.
2384 static void ethernet_phy_reset(unsigned int eth_port_num
)
2386 unsigned int phy_reg_data
;
2389 eth_port_read_smi_reg(eth_port_num
, 0, &phy_reg_data
);
2390 phy_reg_data
|= 0x8000; /* Set bit 15 to reset the PHY */
2391 eth_port_write_smi_reg(eth_port_num
, 0, phy_reg_data
);
2395 * eth_port_reset - Reset Ethernet port
2398 * This routine resets the chip by aborting any SDMA engine activity and
2399 * clearing the MIB counters. The Receiver and the Transmit unit are in
2400 * idle state after this command is performed and the port is disabled.
2403 * unsigned int eth_port_num Ethernet Port number.
2406 * Channel activity is halted.
2412 static void eth_port_reset(unsigned int port_num
)
2414 unsigned int reg_data
;
2416 /* Stop Tx port activity. Check port Tx activity. */
2417 reg_data
= mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num
));
2419 if (reg_data
& 0xFF) {
2420 /* Issue stop command for active channels only */
2421 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num
),
2424 /* Wait for all Tx activity to terminate. */
2425 /* Check port cause register that all Tx queues are stopped */
2426 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num
))
2431 /* Stop Rx port activity. Check port Rx activity. */
2432 reg_data
= mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num
));
2434 if (reg_data
& 0xFF) {
2435 /* Issue stop command for active channels only */
2436 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num
),
2439 /* Wait for all Rx activity to terminate. */
2440 /* Check port cause register that all Rx queues are stopped */
2441 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num
))
2446 /* Clear all MIB counters */
2447 eth_clear_mib_counters(port_num
);
2449 /* Reset the Enable bit in the Configuration Register */
2450 reg_data
= mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
));
2451 reg_data
&= ~MV643XX_ETH_SERIAL_PORT_ENABLE
;
2452 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
), reg_data
);
2456 static int eth_port_autoneg_supported(unsigned int eth_port_num
)
2458 unsigned int phy_reg_data0
;
2460 eth_port_read_smi_reg(eth_port_num
, 0, &phy_reg_data0
);
2462 return phy_reg_data0
& 0x1000;
2465 static int eth_port_link_is_up(unsigned int eth_port_num
)
2467 unsigned int phy_reg_data1
;
2469 eth_port_read_smi_reg(eth_port_num
, 1, &phy_reg_data1
);
2471 if (eth_port_autoneg_supported(eth_port_num
)) {
2472 if (phy_reg_data1
& 0x20) /* auto-neg complete */
2474 } else if (phy_reg_data1
& 0x4) /* link up */
2481 * eth_port_read_smi_reg - Read PHY registers
2484 * This routine utilize the SMI interface to interact with the PHY in
2485 * order to perform PHY register read.
2488 * unsigned int port_num Ethernet Port number.
2489 * unsigned int phy_reg PHY register address offset.
2490 * unsigned int *value Register value buffer.
2493 * Write the value of a specified PHY register into given buffer.
2496 * false if the PHY is busy or read data is not in valid state.
2500 static void eth_port_read_smi_reg(unsigned int port_num
,
2501 unsigned int phy_reg
, unsigned int *value
)
2503 int phy_addr
= ethernet_phy_get(port_num
);
2504 unsigned long flags
;
2507 /* the SMI register is a shared resource */
2508 spin_lock_irqsave(&mv643xx_eth_phy_lock
, flags
);
2510 /* wait for the SMI register to become available */
2511 for (i
= 0; mv_read(MV643XX_ETH_SMI_REG
) & ETH_SMI_BUSY
; i
++) {
2512 if (i
== PHY_WAIT_ITERATIONS
) {
2513 printk("mv643xx PHY busy timeout, port %d\n", port_num
);
2516 udelay(PHY_WAIT_MICRO_SECONDS
);
2519 mv_write(MV643XX_ETH_SMI_REG
,
2520 (phy_addr
<< 16) | (phy_reg
<< 21) | ETH_SMI_OPCODE_READ
);
2522 /* now wait for the data to be valid */
2523 for (i
= 0; !(mv_read(MV643XX_ETH_SMI_REG
) & ETH_SMI_READ_VALID
); i
++) {
2524 if (i
== PHY_WAIT_ITERATIONS
) {
2525 printk("mv643xx PHY read timeout, port %d\n", port_num
);
2528 udelay(PHY_WAIT_MICRO_SECONDS
);
2531 *value
= mv_read(MV643XX_ETH_SMI_REG
) & 0xffff;
2533 spin_unlock_irqrestore(&mv643xx_eth_phy_lock
, flags
);
2537 * eth_port_write_smi_reg - Write to PHY registers
2540 * This routine utilize the SMI interface to interact with the PHY in
2541 * order to perform writes to PHY registers.
2544 * unsigned int eth_port_num Ethernet Port number.
2545 * unsigned int phy_reg PHY register address offset.
2546 * unsigned int value Register value.
2549 * Write the given value to the specified PHY register.
2552 * false if the PHY is busy.
2556 static void eth_port_write_smi_reg(unsigned int eth_port_num
,
2557 unsigned int phy_reg
, unsigned int value
)
2561 unsigned long flags
;
2563 phy_addr
= ethernet_phy_get(eth_port_num
);
2565 /* the SMI register is a shared resource */
2566 spin_lock_irqsave(&mv643xx_eth_phy_lock
, flags
);
2568 /* wait for the SMI register to become available */
2569 for (i
= 0; mv_read(MV643XX_ETH_SMI_REG
) & ETH_SMI_BUSY
; i
++) {
2570 if (i
== PHY_WAIT_ITERATIONS
) {
2571 printk("mv643xx PHY busy timeout, port %d\n",
2575 udelay(PHY_WAIT_MICRO_SECONDS
);
2578 mv_write(MV643XX_ETH_SMI_REG
, (phy_addr
<< 16) | (phy_reg
<< 21) |
2579 ETH_SMI_OPCODE_WRITE
| (value
& 0xffff));
2581 spin_unlock_irqrestore(&mv643xx_eth_phy_lock
, flags
);
2585 * eth_port_send - Send an Ethernet packet
2588 * This routine send a given packet described by p_pktinfo parameter. It
2589 * supports transmitting of a packet spaned over multiple buffers. The
2590 * routine updates 'curr' and 'first' indexes according to the packet
2591 * segment passed to the routine. In case the packet segment is first,
2592 * the 'first' index is update. In any case, the 'curr' index is updated.
2593 * If the routine get into Tx resource error it assigns 'curr' index as
2594 * 'first'. This way the function can abort Tx process of multiple
2595 * descriptors per packet.
2598 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2599 * struct pkt_info *p_pkt_info User packet buffer.
2602 * Tx ring 'curr' and 'first' indexes are updated.
2605 * ETH_QUEUE_FULL in case of Tx resource error.
2606 * ETH_ERROR in case the routine can not access Tx desc ring.
2607 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2611 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2613 * Modified to include the first descriptor pointer in case of SG
2615 static ETH_FUNC_RET_STATUS
eth_port_send(struct mv643xx_private
*mp
,
2616 struct pkt_info
*p_pkt_info
)
2618 int tx_desc_curr
, tx_desc_used
, tx_first_desc
, tx_next_desc
;
2619 struct eth_tx_desc
*current_descriptor
;
2620 struct eth_tx_desc
*first_descriptor
;
2623 /* Do not process Tx ring in case of Tx ring resource error */
2624 if (mp
->tx_resource_err
)
2625 return ETH_QUEUE_FULL
;
2628 * The hardware requires that each buffer that is <= 8 bytes
2629 * in length must be aligned on an 8 byte boundary.
2631 if (p_pkt_info
->byte_cnt
<= 8 && p_pkt_info
->buf_ptr
& 0x7) {
2633 "mv643xx_eth port %d: packet size <= 8 problem\n",
2639 BUG_ON(mp
->tx_ring_skbs
> mp
->tx_ring_size
);
2641 /* Get the Tx Desc ring indexes */
2642 tx_desc_curr
= mp
->tx_curr_desc_q
;
2643 tx_desc_used
= mp
->tx_used_desc_q
;
2645 current_descriptor
= &mp
->p_tx_desc_area
[tx_desc_curr
];
2647 tx_next_desc
= (tx_desc_curr
+ 1) % mp
->tx_ring_size
;
2649 current_descriptor
->buf_ptr
= p_pkt_info
->buf_ptr
;
2650 current_descriptor
->byte_cnt
= p_pkt_info
->byte_cnt
;
2651 current_descriptor
->l4i_chk
= p_pkt_info
->l4i_chk
;
2652 mp
->tx_skb
[tx_desc_curr
] = p_pkt_info
->return_info
;
2654 command
= p_pkt_info
->cmd_sts
| ETH_ZERO_PADDING
| ETH_GEN_CRC
|
2655 ETH_BUFFER_OWNED_BY_DMA
;
2656 if (command
& ETH_TX_FIRST_DESC
) {
2657 tx_first_desc
= tx_desc_curr
;
2658 mp
->tx_first_desc_q
= tx_first_desc
;
2659 first_descriptor
= current_descriptor
;
2660 mp
->tx_first_command
= command
;
2662 tx_first_desc
= mp
->tx_first_desc_q
;
2663 first_descriptor
= &mp
->p_tx_desc_area
[tx_first_desc
];
2664 BUG_ON(first_descriptor
== NULL
);
2665 current_descriptor
->cmd_sts
= command
;
2668 if (command
& ETH_TX_LAST_DESC
) {
2670 first_descriptor
->cmd_sts
= mp
->tx_first_command
;
2673 ETH_ENABLE_TX_QUEUE(mp
->port_num
);
2676 * Finish Tx packet. Update first desc in case of Tx resource
2678 tx_first_desc
= tx_next_desc
;
2679 mp
->tx_first_desc_q
= tx_first_desc
;
2682 /* Check for ring index overlap in the Tx desc ring */
2683 if (tx_next_desc
== tx_desc_used
) {
2684 mp
->tx_resource_err
= 1;
2685 mp
->tx_curr_desc_q
= tx_first_desc
;
2687 return ETH_QUEUE_LAST_RESOURCE
;
2690 mp
->tx_curr_desc_q
= tx_next_desc
;
2695 static ETH_FUNC_RET_STATUS
eth_port_send(struct mv643xx_private
*mp
,
2696 struct pkt_info
*p_pkt_info
)
2700 struct eth_tx_desc
*current_descriptor
;
2701 unsigned int command_status
;
2703 /* Do not process Tx ring in case of Tx ring resource error */
2704 if (mp
->tx_resource_err
)
2705 return ETH_QUEUE_FULL
;
2708 BUG_ON(mp
->tx_ring_skbs
> mp
->tx_ring_size
);
2710 /* Get the Tx Desc ring indexes */
2711 tx_desc_curr
= mp
->tx_curr_desc_q
;
2712 tx_desc_used
= mp
->tx_used_desc_q
;
2713 current_descriptor
= &mp
->p_tx_desc_area
[tx_desc_curr
];
2715 command_status
= p_pkt_info
->cmd_sts
| ETH_ZERO_PADDING
| ETH_GEN_CRC
;
2716 current_descriptor
->buf_ptr
= p_pkt_info
->buf_ptr
;
2717 current_descriptor
->byte_cnt
= p_pkt_info
->byte_cnt
;
2718 mp
->tx_skb
[tx_desc_curr
] = p_pkt_info
->return_info
;
2720 /* Set last desc with DMA ownership and interrupt enable. */
2722 current_descriptor
->cmd_sts
= command_status
|
2723 ETH_BUFFER_OWNED_BY_DMA
| ETH_TX_ENABLE_INTERRUPT
;
2726 ETH_ENABLE_TX_QUEUE(mp
->port_num
);
2728 /* Finish Tx packet. Update first desc in case of Tx resource error */
2729 tx_desc_curr
= (tx_desc_curr
+ 1) % mp
->tx_ring_size
;
2731 /* Update the current descriptor */
2732 mp
->tx_curr_desc_q
= tx_desc_curr
;
2734 /* Check for ring index overlap in the Tx desc ring */
2735 if (tx_desc_curr
== tx_desc_used
) {
2736 mp
->tx_resource_err
= 1;
2737 return ETH_QUEUE_LAST_RESOURCE
;
2745 * eth_tx_return_desc - Free all used Tx descriptors
2748 * This routine returns the transmitted packet information to the caller.
2749 * It uses the 'first' index to support Tx desc return in case a transmit
2750 * of a packet spanned over multiple buffer still in process.
2751 * In case the Tx queue was in "resource error" condition, where there are
2752 * no available Tx resources, the function resets the resource error flag.
2755 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2756 * struct pkt_info *p_pkt_info User packet buffer.
2759 * Tx ring 'first' and 'used' indexes are updated.
2763 * ETH_ERROR otherwise.
2766 static ETH_FUNC_RET_STATUS
eth_tx_return_desc(struct mv643xx_private
*mp
,
2767 struct pkt_info
*p_pkt_info
)
2771 struct eth_tx_desc
*p_tx_desc_used
;
2772 unsigned int command_status
;
2773 unsigned long flags
;
2776 spin_lock_irqsave(&mp
->lock
, flags
);
2778 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2779 tx_busy_desc
= mp
->tx_first_desc_q
;
2781 tx_busy_desc
= mp
->tx_curr_desc_q
;
2784 /* Get the Tx Desc ring indexes */
2785 tx_desc_used
= mp
->tx_used_desc_q
;
2787 p_tx_desc_used
= &mp
->p_tx_desc_area
[tx_desc_used
];
2790 if (p_tx_desc_used
== NULL
) {
2795 /* Stop release. About to overlap the current available Tx descriptor */
2796 if (tx_desc_used
== tx_busy_desc
&& !mp
->tx_resource_err
) {
2801 command_status
= p_tx_desc_used
->cmd_sts
;
2803 /* Still transmitting... */
2804 if (command_status
& (ETH_BUFFER_OWNED_BY_DMA
)) {
2809 /* Pass the packet information to the caller */
2810 p_pkt_info
->cmd_sts
= command_status
;
2811 p_pkt_info
->return_info
= mp
->tx_skb
[tx_desc_used
];
2812 p_pkt_info
->buf_ptr
= p_tx_desc_used
->buf_ptr
;
2813 p_pkt_info
->byte_cnt
= p_tx_desc_used
->byte_cnt
;
2814 mp
->tx_skb
[tx_desc_used
] = NULL
;
2816 /* Update the next descriptor to release. */
2817 mp
->tx_used_desc_q
= (tx_desc_used
+ 1) % mp
->tx_ring_size
;
2819 /* Any Tx return cancels the Tx resource error status */
2820 mp
->tx_resource_err
= 0;
2822 BUG_ON(mp
->tx_ring_skbs
== 0);
2826 spin_unlock_irqrestore(&mp
->lock
, flags
);
2832 * eth_port_receive - Get received information from Rx ring.
2835 * This routine returns the received data to the caller. There is no
2836 * data copying during routine operation. All information is returned
2837 * using pointer to packet information struct passed from the caller.
2838 * If the routine exhausts Rx ring resources then the resource error flag
2842 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2843 * struct pkt_info *p_pkt_info User packet buffer.
2846 * Rx ring current and used indexes are updated.
2849 * ETH_ERROR in case the routine can not access Rx desc ring.
2850 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2851 * ETH_END_OF_JOB if there is no received data.
2854 static ETH_FUNC_RET_STATUS
eth_port_receive(struct mv643xx_private
*mp
,
2855 struct pkt_info
*p_pkt_info
)
2857 int rx_next_curr_desc
, rx_curr_desc
, rx_used_desc
;
2858 volatile struct eth_rx_desc
*p_rx_desc
;
2859 unsigned int command_status
;
2860 unsigned long flags
;
2862 /* Do not process Rx ring in case of Rx ring resource error */
2863 if (mp
->rx_resource_err
)
2864 return ETH_QUEUE_FULL
;
2866 spin_lock_irqsave(&mp
->lock
, flags
);
2868 /* Get the Rx Desc ring 'curr and 'used' indexes */
2869 rx_curr_desc
= mp
->rx_curr_desc_q
;
2870 rx_used_desc
= mp
->rx_used_desc_q
;
2872 p_rx_desc
= &mp
->p_rx_desc_area
[rx_curr_desc
];
2874 /* The following parameters are used to save readings from memory */
2875 command_status
= p_rx_desc
->cmd_sts
;
2878 /* Nothing to receive... */
2879 if (command_status
& (ETH_BUFFER_OWNED_BY_DMA
)) {
2880 spin_unlock_irqrestore(&mp
->lock
, flags
);
2881 return ETH_END_OF_JOB
;
2884 p_pkt_info
->byte_cnt
= (p_rx_desc
->byte_cnt
) - RX_BUF_OFFSET
;
2885 p_pkt_info
->cmd_sts
= command_status
;
2886 p_pkt_info
->buf_ptr
= (p_rx_desc
->buf_ptr
) + RX_BUF_OFFSET
;
2887 p_pkt_info
->return_info
= mp
->rx_skb
[rx_curr_desc
];
2888 p_pkt_info
->l4i_chk
= p_rx_desc
->buf_size
;
2891 * Clean the return info field to indicate that the
2892 * packet has been moved to the upper layers
2894 mp
->rx_skb
[rx_curr_desc
] = NULL
;
2896 /* Update current index in data structure */
2897 rx_next_curr_desc
= (rx_curr_desc
+ 1) % mp
->rx_ring_size
;
2898 mp
->rx_curr_desc_q
= rx_next_curr_desc
;
2900 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2901 if (rx_next_curr_desc
== rx_used_desc
)
2902 mp
->rx_resource_err
= 1;
2904 spin_unlock_irqrestore(&mp
->lock
, flags
);
2910 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2913 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2914 * next 'used' descriptor and attached the returned buffer to it.
2915 * In case the Rx ring was in "resource error" condition, where there are
2916 * no available Rx resources, the function resets the resource error flag.
2919 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2920 * struct pkt_info *p_pkt_info Information on returned buffer.
2923 * New available Rx resource in Rx descriptor ring.
2926 * ETH_ERROR in case the routine can not access Rx desc ring.
2929 static ETH_FUNC_RET_STATUS
eth_rx_return_buff(struct mv643xx_private
*mp
,
2930 struct pkt_info
*p_pkt_info
)
2932 int used_rx_desc
; /* Where to return Rx resource */
2933 volatile struct eth_rx_desc
*p_used_rx_desc
;
2934 unsigned long flags
;
2936 spin_lock_irqsave(&mp
->lock
, flags
);
2938 /* Get 'used' Rx descriptor */
2939 used_rx_desc
= mp
->rx_used_desc_q
;
2940 p_used_rx_desc
= &mp
->p_rx_desc_area
[used_rx_desc
];
2942 p_used_rx_desc
->buf_ptr
= p_pkt_info
->buf_ptr
;
2943 p_used_rx_desc
->buf_size
= p_pkt_info
->byte_cnt
;
2944 mp
->rx_skb
[used_rx_desc
] = p_pkt_info
->return_info
;
2946 /* Flush the write pipe */
2948 /* Return the descriptor to DMA ownership */
2950 p_used_rx_desc
->cmd_sts
=
2951 ETH_BUFFER_OWNED_BY_DMA
| ETH_RX_ENABLE_INTERRUPT
;
2954 /* Move the used descriptor pointer to the next descriptor */
2955 mp
->rx_used_desc_q
= (used_rx_desc
+ 1) % mp
->rx_ring_size
;
2957 /* Any Rx return cancels the Rx resource error status */
2958 mp
->rx_resource_err
= 0;
2960 spin_unlock_irqrestore(&mp
->lock
, flags
);
2965 /************* Begin ethtool support *************************/
2967 struct mv643xx_stats
{
2968 char stat_string
[ETH_GSTRING_LEN
];
2973 #define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
2974 offsetof(struct mv643xx_private, m)
2976 static const struct mv643xx_stats mv643xx_gstrings_stats
[] = {
2977 { "rx_packets", MV643XX_STAT(stats
.rx_packets
) },
2978 { "tx_packets", MV643XX_STAT(stats
.tx_packets
) },
2979 { "rx_bytes", MV643XX_STAT(stats
.rx_bytes
) },
2980 { "tx_bytes", MV643XX_STAT(stats
.tx_bytes
) },
2981 { "rx_errors", MV643XX_STAT(stats
.rx_errors
) },
2982 { "tx_errors", MV643XX_STAT(stats
.tx_errors
) },
2983 { "rx_dropped", MV643XX_STAT(stats
.rx_dropped
) },
2984 { "tx_dropped", MV643XX_STAT(stats
.tx_dropped
) },
2985 { "good_octets_received", MV643XX_STAT(mib_counters
.good_octets_received
) },
2986 { "bad_octets_received", MV643XX_STAT(mib_counters
.bad_octets_received
) },
2987 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters
.internal_mac_transmit_err
) },
2988 { "good_frames_received", MV643XX_STAT(mib_counters
.good_frames_received
) },
2989 { "bad_frames_received", MV643XX_STAT(mib_counters
.bad_frames_received
) },
2990 { "broadcast_frames_received", MV643XX_STAT(mib_counters
.broadcast_frames_received
) },
2991 { "multicast_frames_received", MV643XX_STAT(mib_counters
.multicast_frames_received
) },
2992 { "frames_64_octets", MV643XX_STAT(mib_counters
.frames_64_octets
) },
2993 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters
.frames_65_to_127_octets
) },
2994 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters
.frames_128_to_255_octets
) },
2995 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters
.frames_256_to_511_octets
) },
2996 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters
.frames_512_to_1023_octets
) },
2997 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters
.frames_1024_to_max_octets
) },
2998 { "good_octets_sent", MV643XX_STAT(mib_counters
.good_octets_sent
) },
2999 { "good_frames_sent", MV643XX_STAT(mib_counters
.good_frames_sent
) },
3000 { "excessive_collision", MV643XX_STAT(mib_counters
.excessive_collision
) },
3001 { "multicast_frames_sent", MV643XX_STAT(mib_counters
.multicast_frames_sent
) },
3002 { "broadcast_frames_sent", MV643XX_STAT(mib_counters
.broadcast_frames_sent
) },
3003 { "unrec_mac_control_received", MV643XX_STAT(mib_counters
.unrec_mac_control_received
) },
3004 { "fc_sent", MV643XX_STAT(mib_counters
.fc_sent
) },
3005 { "good_fc_received", MV643XX_STAT(mib_counters
.good_fc_received
) },
3006 { "bad_fc_received", MV643XX_STAT(mib_counters
.bad_fc_received
) },
3007 { "undersize_received", MV643XX_STAT(mib_counters
.undersize_received
) },
3008 { "fragments_received", MV643XX_STAT(mib_counters
.fragments_received
) },
3009 { "oversize_received", MV643XX_STAT(mib_counters
.oversize_received
) },
3010 { "jabber_received", MV643XX_STAT(mib_counters
.jabber_received
) },
3011 { "mac_receive_error", MV643XX_STAT(mib_counters
.mac_receive_error
) },
3012 { "bad_crc_event", MV643XX_STAT(mib_counters
.bad_crc_event
) },
3013 { "collision", MV643XX_STAT(mib_counters
.collision
) },
3014 { "late_collision", MV643XX_STAT(mib_counters
.late_collision
) },
3017 #define MV643XX_STATS_LEN \
3018 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
3021 mv643xx_get_settings(struct net_device
*netdev
, struct ethtool_cmd
*ecmd
)
3023 struct mv643xx_private
*mp
= netdev
->priv
;
3024 int port_num
= mp
->port_num
;
3025 int autoneg
= eth_port_autoneg_supported(port_num
);
3028 int half_duplex
= 0;
3029 int full_duplex
= 0;
3035 u32 pcs
= mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
));
3036 u32 psr
= mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num
));
3038 mode_10_bit
= psr
& MV643XX_ETH_PORT_STATUS_MODE_10_BIT
;
3041 ecmd
->supported
= SUPPORTED_10baseT_Half
;
3043 ecmd
->supported
= (SUPPORTED_10baseT_Half
|
3044 SUPPORTED_10baseT_Full
|
3045 SUPPORTED_100baseT_Half
|
3046 SUPPORTED_100baseT_Full
|
3047 SUPPORTED_1000baseT_Full
|
3048 (autoneg
? SUPPORTED_Autoneg
: 0) |
3051 auto_duplex
= !(pcs
& MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX
);
3052 auto_speed
= !(pcs
& MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII
);
3054 ecmd
->advertising
= ADVERTISED_TP
;
3057 ecmd
->advertising
|= ADVERTISED_Autoneg
;
3063 if (pcs
& MV643XX_ETH_SET_FULL_DUPLEX_MODE
)
3074 if (pcs
& MV643XX_ETH_SET_GMII_SPEED_TO_1000
)
3076 else if (pcs
& MV643XX_ETH_SET_MII_SPEED_TO_100
)
3082 if (speed_10
& half_duplex
)
3083 ecmd
->advertising
|= ADVERTISED_10baseT_Half
;
3084 if (speed_10
& full_duplex
)
3085 ecmd
->advertising
|= ADVERTISED_10baseT_Full
;
3086 if (speed_100
& half_duplex
)
3087 ecmd
->advertising
|= ADVERTISED_100baseT_Half
;
3088 if (speed_100
& full_duplex
)
3089 ecmd
->advertising
|= ADVERTISED_100baseT_Full
;
3091 ecmd
->advertising
|= ADVERTISED_1000baseT_Full
;
3095 ecmd
->port
= PORT_TP
;
3096 ecmd
->phy_address
= ethernet_phy_get(port_num
);
3098 ecmd
->transceiver
= XCVR_EXTERNAL
;
3100 if (netif_carrier_ok(netdev
)) {
3102 ecmd
->speed
= SPEED_10
;
3104 if (psr
& MV643XX_ETH_PORT_STATUS_GMII_1000
)
3105 ecmd
->speed
= SPEED_1000
;
3106 else if (psr
& MV643XX_ETH_PORT_STATUS_MII_100
)
3107 ecmd
->speed
= SPEED_100
;
3109 ecmd
->speed
= SPEED_10
;
3112 if (psr
& MV643XX_ETH_PORT_STATUS_FULL_DUPLEX
)
3113 ecmd
->duplex
= DUPLEX_FULL
;
3115 ecmd
->duplex
= DUPLEX_HALF
;
3121 ecmd
->autoneg
= autoneg
? AUTONEG_ENABLE
: AUTONEG_DISABLE
;
3125 static void mv643xx_get_drvinfo(struct net_device
*netdev
,
3126 struct ethtool_drvinfo
*drvinfo
)
3128 strncpy(drvinfo
->driver
, mv643xx_driver_name
, 32);
3129 strncpy(drvinfo
->version
, mv643xx_driver_version
, 32);
3130 strncpy(drvinfo
->fw_version
, "N/A", 32);
3131 strncpy(drvinfo
->bus_info
, "mv643xx", 32);
3132 drvinfo
->n_stats
= MV643XX_STATS_LEN
;
3135 static int mv643xx_get_stats_count(struct net_device
*netdev
)
3137 return MV643XX_STATS_LEN
;
3140 static void mv643xx_get_ethtool_stats(struct net_device
*netdev
,
3141 struct ethtool_stats
*stats
, uint64_t *data
)
3143 struct mv643xx_private
*mp
= netdev
->priv
;
3146 eth_update_mib_counters(mp
);
3148 for (i
= 0; i
< MV643XX_STATS_LEN
; i
++) {
3149 char *p
= (char *)mp
+mv643xx_gstrings_stats
[i
].stat_offset
;
3150 data
[i
] = (mv643xx_gstrings_stats
[i
].sizeof_stat
==
3151 sizeof(uint64_t)) ? *(uint64_t *)p
: *(uint32_t *)p
;
3155 static void mv643xx_get_strings(struct net_device
*netdev
, uint32_t stringset
,
3162 for (i
=0; i
< MV643XX_STATS_LEN
; i
++) {
3163 memcpy(data
+ i
* ETH_GSTRING_LEN
,
3164 mv643xx_gstrings_stats
[i
].stat_string
,
3171 static struct ethtool_ops mv643xx_ethtool_ops
= {
3172 .get_settings
= mv643xx_get_settings
,
3173 .get_drvinfo
= mv643xx_get_drvinfo
,
3174 .get_link
= ethtool_op_get_link
,
3175 .get_sg
= ethtool_op_get_sg
,
3176 .set_sg
= ethtool_op_set_sg
,
3177 .get_strings
= mv643xx_get_strings
,
3178 .get_stats_count
= mv643xx_get_stats_count
,
3179 .get_ethtool_stats
= mv643xx_get_ethtool_stats
,
3182 /************* End ethtool support *************************/