drivers/scsi/lpfc/lpfc_hw.h

   1 /*******************************************************************
   2  * This file is part of the Emulex Linux Device Driver for         *
   3  * Fibre Channel Host Bus Adapters.                                *
   4  * Copyright (C) 2004-2006 Emulex.  All rights reserved.           *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *******************************************************************/
  20
  21 #define FDMI_DID        0xfffffaU
  22 #define NameServer_DID  0xfffffcU
  23 #define SCR_DID         0xfffffdU
  24 #define Fabric_DID      0xfffffeU
  25 #define Bcast_DID       0xffffffU
  26 #define Mask_DID        0xffffffU
  27 #define CT_DID_MASK     0xffff00U
  28 #define Fabric_DID_MASK 0xfff000U
  29 #define WELL_KNOWN_DID_MASK 0xfffff0U
  30
  31 #define PT2PT_LocalID   1
  32 #define PT2PT_RemoteID  2
  33
  34 #define FF_DEF_EDTOV          2000      /* Default E_D_TOV (2000ms) */
  35 #define FF_DEF_ALTOV            15      /* Default AL_TIME (15ms) */
  36 #define FF_DEF_RATOV             2      /* Default RA_TOV (2s) */
  37 #define FF_DEF_ARBTOV         1900      /* Default ARB_TOV (1900ms) */
  38
  39 #define LPFC_BUF_RING0        64        /* Number of buffers to post to RING
  40                                            0 */
  41
  42 #define FCELSSIZE             1024      /* maximum ELS transfer size */
  43
  44 #define LPFC_FCP_RING            0      /* ring 0 for FCP initiator commands */
  45 #define LPFC_IP_RING             1      /* ring 1 for IP commands */
  46 #define LPFC_ELS_RING            2      /* ring 2 for ELS commands */
  47 #define LPFC_FCP_NEXT_RING       3
  48
  49 #define SLI2_IOCB_CMD_R0_ENTRIES    172 /* SLI-2 FCP command ring entries */
  50 #define SLI2_IOCB_RSP_R0_ENTRIES    134 /* SLI-2 FCP response ring entries */
  51 #define SLI2_IOCB_CMD_R1_ENTRIES      4 /* SLI-2 IP command ring entries */
  52 #define SLI2_IOCB_RSP_R1_ENTRIES      4 /* SLI-2 IP response ring entries */
  53 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
  54 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
  55 #define SLI2_IOCB_CMD_R2_ENTRIES     20 /* SLI-2 ELS command ring entries */
  56 #define SLI2_IOCB_RSP_R2_ENTRIES     20 /* SLI-2 ELS response ring entries */
  57 #define SLI2_IOCB_CMD_R3_ENTRIES      0
  58 #define SLI2_IOCB_RSP_R3_ENTRIES      0
  59 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
  60 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
  61
  62 /* Common Transport structures and definitions */
  63
  64 union CtRevisionId {
  65         /* Structure is in Big Endian format */
  66         struct {
  67                 uint32_t Revision:8;
  68                 uint32_t InId:24;
  69         } bits;
  70         uint32_t word;
  71 };
  72
  73 union CtCommandResponse {
  74         /* Structure is in Big Endian format */
  75         struct {
  76                 uint32_t CmdRsp:16;
  77                 uint32_t Size:16;
  78         } bits;
  79         uint32_t word;
  80 };
  81
  82 struct lpfc_sli_ct_request {
  83         /* Structure is in Big Endian format */
  84         union CtRevisionId RevisionId;
  85         uint8_t FsType;
  86         uint8_t FsSubType;
  87         uint8_t Options;
  88         uint8_t Rsrvd1;
  89         union CtCommandResponse CommandResponse;
  90         uint8_t Rsrvd2;
  91         uint8_t ReasonCode;
  92         uint8_t Explanation;
  93         uint8_t VendorUnique;
  94
  95         union {
  96                 uint32_t PortID;
  97                 struct gid {
  98                         uint8_t PortType;       /* for GID_PT requests */
  99                         uint8_t DomainScope;
 100                         uint8_t AreaScope;
 101                         uint8_t Fc4Type;        /* for GID_FT requests */
 102                 } gid;
 103                 struct rft {
 104                         uint32_t PortId;        /* For RFT_ID requests */
 105
 106 #ifdef __BIG_ENDIAN_BITFIELD
 107                         uint32_t rsvd0:16;
 108                         uint32_t rsvd1:7;
 109                         uint32_t fcpReg:1;      /* Type 8 */
 110                         uint32_t rsvd2:2;
 111                         uint32_t ipReg:1;       /* Type 5 */
 112                         uint32_t rsvd3:5;
 113 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 114                         uint32_t rsvd0:16;
 115                         uint32_t fcpReg:1;      /* Type 8 */
 116                         uint32_t rsvd1:7;
 117                         uint32_t rsvd3:5;
 118                         uint32_t ipReg:1;       /* Type 5 */
 119                         uint32_t rsvd2:2;
 120 #endif
 121
 122                         uint32_t rsvd[7];
 123                 } rft;
 124                 struct rnn {
 125                         uint32_t PortId;        /* For RNN_ID requests */
 126                         uint8_t wwnn[8];
 127                 } rnn;
 128                 struct rsnn {   /* For RSNN_ID requests */
 129                         uint8_t wwnn[8];
 130                         uint8_t len;
 131                         uint8_t symbname[255];
 132                 } rsnn;
 133         } un;
 134 };
 135
 136 #define  SLI_CT_REVISION        1
 137 #define  GID_REQUEST_SZ         (sizeof(struct lpfc_sli_ct_request) - 260)
 138 #define  RFT_REQUEST_SZ         (sizeof(struct lpfc_sli_ct_request) - 228)
 139 #define  RNN_REQUEST_SZ         (sizeof(struct lpfc_sli_ct_request) - 252)
 140 #define  RSNN_REQUEST_SZ        (sizeof(struct lpfc_sli_ct_request))
 141
 142 /*
 143  * FsType Definitions
 144  */
 145
 146 #define  SLI_CT_MANAGEMENT_SERVICE        0xFA
 147 #define  SLI_CT_TIME_SERVICE              0xFB
 148 #define  SLI_CT_DIRECTORY_SERVICE         0xFC
 149 #define  SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
 150
 151 /*
 152  * Directory Service Subtypes
 153  */
 154
 155 #define  SLI_CT_DIRECTORY_NAME_SERVER     0x02
 156
 157 /*
 158  * Response Codes
 159  */
 160
 161 #define  SLI_CT_RESPONSE_FS_RJT           0x8001
 162 #define  SLI_CT_RESPONSE_FS_ACC           0x8002
 163
 164 /*
 165  * Reason Codes
 166  */
 167
 168 #define  SLI_CT_NO_ADDITIONAL_EXPL        0x0
 169 #define  SLI_CT_INVALID_COMMAND           0x01
 170 #define  SLI_CT_INVALID_VERSION           0x02
 171 #define  SLI_CT_LOGICAL_ERROR             0x03
 172 #define  SLI_CT_INVALID_IU_SIZE           0x04
 173 #define  SLI_CT_LOGICAL_BUSY              0x05
 174 #define  SLI_CT_PROTOCOL_ERROR            0x07
 175 #define  SLI_CT_UNABLE_TO_PERFORM_REQ     0x09
 176 #define  SLI_CT_REQ_NOT_SUPPORTED         0x0b
 177 #define  SLI_CT_HBA_INFO_NOT_REGISTERED   0x10
 178 #define  SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE  0x11
 179 #define  SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN      0x12
 180 #define  SLI_CT_HBA_ATTR_NOT_PRESENT      0x13
 181 #define  SLI_CT_PORT_INFO_NOT_REGISTERED  0x20
 182 #define  SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
 183 #define  SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN     0x22
 184 #define  SLI_CT_VENDOR_UNIQUE             0xff
 185
 186 /*
 187  * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
 188  */
 189
 190 #define  SLI_CT_NO_PORT_ID                0x01
 191 #define  SLI_CT_NO_PORT_NAME              0x02
 192 #define  SLI_CT_NO_NODE_NAME              0x03
 193 #define  SLI_CT_NO_CLASS_OF_SERVICE       0x04
 194 #define  SLI_CT_NO_IP_ADDRESS             0x05
 195 #define  SLI_CT_NO_IPA                    0x06
 196 #define  SLI_CT_NO_FC4_TYPES              0x07
 197 #define  SLI_CT_NO_SYMBOLIC_PORT_NAME     0x08
 198 #define  SLI_CT_NO_SYMBOLIC_NODE_NAME     0x09
 199 #define  SLI_CT_NO_PORT_TYPE              0x0A
 200 #define  SLI_CT_ACCESS_DENIED             0x10
 201 #define  SLI_CT_INVALID_PORT_ID           0x11
 202 #define  SLI_CT_DATABASE_EMPTY            0x12
 203
 204 /*
 205  * Name Server Command Codes
 206  */
 207
 208 #define  SLI_CTNS_GA_NXT      0x0100
 209 #define  SLI_CTNS_GPN_ID      0x0112
 210 #define  SLI_CTNS_GNN_ID      0x0113
 211 #define  SLI_CTNS_GCS_ID      0x0114
 212 #define  SLI_CTNS_GFT_ID      0x0117
 213 #define  SLI_CTNS_GSPN_ID     0x0118
 214 #define  SLI_CTNS_GPT_ID      0x011A
 215 #define  SLI_CTNS_GID_PN      0x0121
 216 #define  SLI_CTNS_GID_NN      0x0131
 217 #define  SLI_CTNS_GIP_NN      0x0135
 218 #define  SLI_CTNS_GIPA_NN     0x0136
 219 #define  SLI_CTNS_GSNN_NN     0x0139
 220 #define  SLI_CTNS_GNN_IP      0x0153
 221 #define  SLI_CTNS_GIPA_IP     0x0156
 222 #define  SLI_CTNS_GID_FT      0x0171
 223 #define  SLI_CTNS_GID_PT      0x01A1
 224 #define  SLI_CTNS_RPN_ID      0x0212
 225 #define  SLI_CTNS_RNN_ID      0x0213
 226 #define  SLI_CTNS_RCS_ID      0x0214
 227 #define  SLI_CTNS_RFT_ID      0x0217
 228 #define  SLI_CTNS_RSPN_ID     0x0218
 229 #define  SLI_CTNS_RPT_ID      0x021A
 230 #define  SLI_CTNS_RIP_NN      0x0235
 231 #define  SLI_CTNS_RIPA_NN     0x0236
 232 #define  SLI_CTNS_RSNN_NN     0x0239
 233 #define  SLI_CTNS_DA_ID       0x0300
 234
 235 /*
 236  * Port Types
 237  */
 238
 239 #define  SLI_CTPT_N_PORT      0x01
 240 #define  SLI_CTPT_NL_PORT     0x02
 241 #define  SLI_CTPT_FNL_PORT    0x03
 242 #define  SLI_CTPT_IP          0x04
 243 #define  SLI_CTPT_FCP         0x08
 244 #define  SLI_CTPT_NX_PORT     0x7F
 245 #define  SLI_CTPT_F_PORT      0x81
 246 #define  SLI_CTPT_FL_PORT     0x82
 247 #define  SLI_CTPT_E_PORT      0x84
 248
 249 #define SLI_CT_LAST_ENTRY     0x80000000
 250
 251 /* Fibre Channel Service Parameter definitions */
 252
 253 #define FC_PH_4_0   6           /* FC-PH version 4.0 */
 254 #define FC_PH_4_1   7           /* FC-PH version 4.1 */
 255 #define FC_PH_4_2   8           /* FC-PH version 4.2 */
 256 #define FC_PH_4_3   9           /* FC-PH version 4.3 */
 257
 258 #define FC_PH_LOW   8           /* Lowest supported FC-PH version */
 259 #define FC_PH_HIGH  9           /* Highest supported FC-PH version */
 260 #define FC_PH3   0x20           /* FC-PH-3 version */
 261
 262 #define FF_FRAME_SIZE     2048
 263
 264 struct lpfc_name {
 265         union {
 266                 struct {
 267 #ifdef __BIG_ENDIAN_BITFIELD
 268                         uint8_t nameType:4;     /* FC Word 0, bit 28:31 */
 269                         uint8_t IEEEextMsn:4;   /* FC Word 0, bit 24:27, bit
 270                                                    8:11 of IEEE ext */
 271 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 272                         uint8_t IEEEextMsn:4;   /* FC Word 0, bit 24:27, bit
 273                                                    8:11 of IEEE ext */
 274                         uint8_t nameType:4;     /* FC Word 0, bit 28:31 */
 275 #endif
 276
 277 #define NAME_IEEE           0x1 /* IEEE name - nameType */
 278 #define NAME_IEEE_EXT       0x2 /* IEEE extended name */
 279 #define NAME_FC_TYPE        0x3 /* FC native name type */
 280 #define NAME_IP_TYPE        0x4 /* IP address */
 281 #define NAME_CCITT_TYPE     0xC
 282 #define NAME_CCITT_GR_TYPE  0xE
 283                         uint8_t IEEEextLsb;     /* FC Word 0, bit 16:23, IEEE
 284                                                    extended Lsb */
 285                         uint8_t IEEE[6];        /* FC IEEE address */
 286                 } s;
 287                 uint8_t wwn[8];
 288         } u;
 289 };
 290
 291 struct csp {
 292         uint8_t fcphHigh;       /* FC Word 0, byte 0 */
 293         uint8_t fcphLow;
 294         uint8_t bbCreditMsb;
 295         uint8_t bbCreditlsb;    /* FC Word 0, byte 3 */
 296
 297 #ifdef __BIG_ENDIAN_BITFIELD
 298         uint16_t increasingOffset:1;    /* FC Word 1, bit 31 */
 299         uint16_t randomOffset:1;        /* FC Word 1, bit 30 */
 300         uint16_t word1Reserved2:1;      /* FC Word 1, bit 29 */
 301         uint16_t fPort:1;       /* FC Word 1, bit 28 */
 302         uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
 303         uint16_t edtovResolution:1;     /* FC Word 1, bit 26 */
 304         uint16_t multicast:1;   /* FC Word 1, bit 25 */
 305         uint16_t broadcast:1;   /* FC Word 1, bit 24 */
 306
 307         uint16_t huntgroup:1;   /* FC Word 1, bit 23 */
 308         uint16_t simplex:1;     /* FC Word 1, bit 22 */
 309         uint16_t word1Reserved1:3;      /* FC Word 1, bit 21:19 */
 310         uint16_t dhd:1;         /* FC Word 1, bit 18 */
 311         uint16_t contIncSeqCnt:1;       /* FC Word 1, bit 17 */
 312         uint16_t payloadlength:1;       /* FC Word 1, bit 16 */
 313 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 314         uint16_t broadcast:1;   /* FC Word 1, bit 24 */
 315         uint16_t multicast:1;   /* FC Word 1, bit 25 */
 316         uint16_t edtovResolution:1;     /* FC Word 1, bit 26 */
 317         uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
 318         uint16_t fPort:1;       /* FC Word 1, bit 28 */
 319         uint16_t word1Reserved2:1;      /* FC Word 1, bit 29 */
 320         uint16_t randomOffset:1;        /* FC Word 1, bit 30 */
 321         uint16_t increasingOffset:1;    /* FC Word 1, bit 31 */
 322
 323         uint16_t payloadlength:1;       /* FC Word 1, bit 16 */
 324         uint16_t contIncSeqCnt:1;       /* FC Word 1, bit 17 */
 325         uint16_t dhd:1;         /* FC Word 1, bit 18 */
 326         uint16_t word1Reserved1:3;      /* FC Word 1, bit 21:19 */
 327         uint16_t simplex:1;     /* FC Word 1, bit 22 */
 328         uint16_t huntgroup:1;   /* FC Word 1, bit 23 */
 329 #endif
 330
 331         uint8_t bbRcvSizeMsb;   /* Upper nibble is reserved */
 332         uint8_t bbRcvSizeLsb;   /* FC Word 1, byte 3 */
 333         union {
 334                 struct {
 335                         uint8_t word2Reserved1; /* FC Word 2 byte 0 */
 336
 337                         uint8_t totalConcurrSeq;        /* FC Word 2 byte 1 */
 338                         uint8_t roByCategoryMsb;        /* FC Word 2 byte 2 */
 339
 340                         uint8_t roByCategoryLsb;        /* FC Word 2 byte 3 */
 341                 } nPort;
 342                 uint32_t r_a_tov;       /* R_A_TOV must be in B.E. format */
 343         } w2;
 344
 345         uint32_t e_d_tov;       /* E_D_TOV must be in B.E. format */
 346 };
 347
 348 struct class_parms {
 349 #ifdef __BIG_ENDIAN_BITFIELD
 350         uint8_t classValid:1;   /* FC Word 0, bit 31 */
 351         uint8_t intermix:1;     /* FC Word 0, bit 30 */
 352         uint8_t stackedXparent:1;       /* FC Word 0, bit 29 */
 353         uint8_t stackedLockDown:1;      /* FC Word 0, bit 28 */
 354         uint8_t seqDelivery:1;  /* FC Word 0, bit 27 */
 355         uint8_t word0Reserved1:3;       /* FC Word 0, bit 24:26 */
 356 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 357         uint8_t word0Reserved1:3;       /* FC Word 0, bit 24:26 */
 358         uint8_t seqDelivery:1;  /* FC Word 0, bit 27 */
 359         uint8_t stackedLockDown:1;      /* FC Word 0, bit 28 */
 360         uint8_t stackedXparent:1;       /* FC Word 0, bit 29 */
 361         uint8_t intermix:1;     /* FC Word 0, bit 30 */
 362         uint8_t classValid:1;   /* FC Word 0, bit 31 */
 363
 364 #endif
 365
 366         uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
 367
 368 #ifdef __BIG_ENDIAN_BITFIELD
 369         uint8_t iCtlXidReAssgn:2;       /* FC Word 0, Bit 14:15 */
 370         uint8_t iCtlInitialPa:2;        /* FC Word 0, bit 12:13 */
 371         uint8_t iCtlAck0capable:1;      /* FC Word 0, bit 11 */
 372         uint8_t iCtlAckNcapable:1;      /* FC Word 0, bit 10 */
 373         uint8_t word0Reserved3:2;       /* FC Word 0, bit  8: 9 */
 374 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 375         uint8_t word0Reserved3:2;       /* FC Word 0, bit  8: 9 */
 376         uint8_t iCtlAckNcapable:1;      /* FC Word 0, bit 10 */
 377         uint8_t iCtlAck0capable:1;      /* FC Word 0, bit 11 */
 378         uint8_t iCtlInitialPa:2;        /* FC Word 0, bit 12:13 */
 379         uint8_t iCtlXidReAssgn:2;       /* FC Word 0, Bit 14:15 */
 380 #endif
 381
 382         uint8_t word0Reserved4; /* FC Word 0, bit  0: 7 */
 383
 384 #ifdef __BIG_ENDIAN_BITFIELD
 385         uint8_t rCtlAck0capable:1;      /* FC Word 1, bit 31 */
 386         uint8_t rCtlAckNcapable:1;      /* FC Word 1, bit 30 */
 387         uint8_t rCtlXidInterlck:1;      /* FC Word 1, bit 29 */
 388         uint8_t rCtlErrorPolicy:2;      /* FC Word 1, bit 27:28 */
 389         uint8_t word1Reserved1:1;       /* FC Word 1, bit 26 */
 390         uint8_t rCtlCatPerSeq:2;        /* FC Word 1, bit 24:25 */
 391 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 392         uint8_t rCtlCatPerSeq:2;        /* FC Word 1, bit 24:25 */
 393         uint8_t word1Reserved1:1;       /* FC Word 1, bit 26 */
 394         uint8_t rCtlErrorPolicy:2;      /* FC Word 1, bit 27:28 */
 395         uint8_t rCtlXidInterlck:1;      /* FC Word 1, bit 29 */
 396         uint8_t rCtlAckNcapable:1;      /* FC Word 1, bit 30 */
 397         uint8_t rCtlAck0capable:1;      /* FC Word 1, bit 31 */
 398 #endif
 399
 400         uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
 401         uint8_t rcvDataSizeMsb; /* FC Word 1, bit  8:15 */
 402         uint8_t rcvDataSizeLsb; /* FC Word 1, bit  0: 7 */
 403
 404         uint8_t concurrentSeqMsb;       /* FC Word 2, bit 24:31 */
 405         uint8_t concurrentSeqLsb;       /* FC Word 2, bit 16:23 */
 406         uint8_t EeCreditSeqMsb; /* FC Word 2, bit  8:15 */
 407         uint8_t EeCreditSeqLsb; /* FC Word 2, bit  0: 7 */
 408
 409         uint8_t openSeqPerXchgMsb;      /* FC Word 3, bit 24:31 */
 410         uint8_t openSeqPerXchgLsb;      /* FC Word 3, bit 16:23 */
 411         uint8_t word3Reserved1; /* Fc Word 3, bit  8:15 */
 412         uint8_t word3Reserved2; /* Fc Word 3, bit  0: 7 */
 413 };
 414
 415 struct serv_parm {      /* Structure is in Big Endian format */
 416         struct csp cmn;
 417         struct lpfc_name portName;
 418         struct lpfc_name nodeName;
 419         struct class_parms cls1;
 420         struct class_parms cls2;
 421         struct class_parms cls3;
 422         struct class_parms cls4;
 423         uint8_t vendorVersion[16];
 424 };
 425
 426 /*
 427  *  Extended Link Service LS_COMMAND codes (Payload Word 0)
 428  */
 429 #ifdef __BIG_ENDIAN_BITFIELD
 430 #define ELS_CMD_MASK      0xffff0000
 431 #define ELS_RSP_MASK      0xff000000
 432 #define ELS_CMD_LS_RJT    0x01000000
 433 #define ELS_CMD_ACC       0x02000000
 434 #define ELS_CMD_PLOGI     0x03000000
 435 #define ELS_CMD_FLOGI     0x04000000
 436 #define ELS_CMD_LOGO      0x05000000
 437 #define ELS_CMD_ABTX      0x06000000
 438 #define ELS_CMD_RCS       0x07000000
 439 #define ELS_CMD_RES       0x08000000
 440 #define ELS_CMD_RSS       0x09000000
 441 #define ELS_CMD_RSI       0x0A000000
 442 #define ELS_CMD_ESTS      0x0B000000
 443 #define ELS_CMD_ESTC      0x0C000000
 444 #define ELS_CMD_ADVC      0x0D000000
 445 #define ELS_CMD_RTV       0x0E000000
 446 #define ELS_CMD_RLS       0x0F000000
 447 #define ELS_CMD_ECHO      0x10000000
 448 #define ELS_CMD_TEST      0x11000000
 449 #define ELS_CMD_RRQ       0x12000000
 450 #define ELS_CMD_PRLI      0x20100014
 451 #define ELS_CMD_PRLO      0x21100014
 452 #define ELS_CMD_PRLO_ACC  0x02100014
 453 #define ELS_CMD_PDISC     0x50000000
 454 #define ELS_CMD_FDISC     0x51000000
 455 #define ELS_CMD_ADISC     0x52000000
 456 #define ELS_CMD_FARP      0x54000000
 457 #define ELS_CMD_FARPR     0x55000000
 458 #define ELS_CMD_RPS       0x56000000
 459 #define ELS_CMD_RPL       0x57000000
 460 #define ELS_CMD_FAN       0x60000000
 461 #define ELS_CMD_RSCN      0x61040000
 462 #define ELS_CMD_SCR       0x62000000
 463 #define ELS_CMD_RNID      0x78000000
 464 #define ELS_CMD_LIRR      0x7A000000
 465 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 466 #define ELS_CMD_MASK      0xffff
 467 #define ELS_RSP_MASK      0xff
 468 #define ELS_CMD_LS_RJT    0x01
 469 #define ELS_CMD_ACC       0x02
 470 #define ELS_CMD_PLOGI     0x03
 471 #define ELS_CMD_FLOGI     0x04
 472 #define ELS_CMD_LOGO      0x05
 473 #define ELS_CMD_ABTX      0x06
 474 #define ELS_CMD_RCS       0x07
 475 #define ELS_CMD_RES       0x08
 476 #define ELS_CMD_RSS       0x09
 477 #define ELS_CMD_RSI       0x0A
 478 #define ELS_CMD_ESTS      0x0B
 479 #define ELS_CMD_ESTC      0x0C
 480 #define ELS_CMD_ADVC      0x0D
 481 #define ELS_CMD_RTV       0x0E
 482 #define ELS_CMD_RLS       0x0F
 483 #define ELS_CMD_ECHO      0x10
 484 #define ELS_CMD_TEST      0x11
 485 #define ELS_CMD_RRQ       0x12
 486 #define ELS_CMD_PRLI      0x14001020
 487 #define ELS_CMD_PRLO      0x14001021
 488 #define ELS_CMD_PRLO_ACC  0x14001002
 489 #define ELS_CMD_PDISC     0x50
 490 #define ELS_CMD_FDISC     0x51
 491 #define ELS_CMD_ADISC     0x52
 492 #define ELS_CMD_FARP      0x54
 493 #define ELS_CMD_FARPR     0x55
 494 #define ELS_CMD_RPS       0x56
 495 #define ELS_CMD_RPL       0x57
 496 #define ELS_CMD_FAN       0x60
 497 #define ELS_CMD_RSCN      0x0461
 498 #define ELS_CMD_SCR       0x62
 499 #define ELS_CMD_RNID      0x78
 500 #define ELS_CMD_LIRR      0x7A
 501 #endif
 502
 503 /*
 504  *  LS_RJT Payload Definition
 505  */
 506
 507 struct ls_rjt { /* Structure is in Big Endian format */
 508         union {
 509                 uint32_t lsRjtError;
 510                 struct {
 511                         uint8_t lsRjtRsvd0;     /* FC Word 0, bit 24:31 */
 512
 513                         uint8_t lsRjtRsnCode;   /* FC Word 0, bit 16:23 */
 514                         /* LS_RJT reason codes */
 515 #define LSRJT_INVALID_CMD     0x01
 516 #define LSRJT_LOGICAL_ERR     0x03
 517 #define LSRJT_LOGICAL_BSY     0x05
 518 #define LSRJT_PROTOCOL_ERR    0x07
 519 #define LSRJT_UNABLE_TPC      0x09      /* Unable to perform command */
 520 #define LSRJT_CMD_UNSUPPORTED 0x0B
 521 #define LSRJT_VENDOR_UNIQUE   0xFF      /* See Byte 3 */
 522
 523                         uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
 524                         /* LS_RJT reason explanation */
 525 #define LSEXP_NOTHING_MORE      0x00
 526 #define LSEXP_SPARM_OPTIONS     0x01
 527 #define LSEXP_SPARM_ICTL        0x03
 528 #define LSEXP_SPARM_RCTL        0x05
 529 #define LSEXP_SPARM_RCV_SIZE    0x07
 530 #define LSEXP_SPARM_CONCUR_SEQ  0x09
 531 #define LSEXP_SPARM_CREDIT      0x0B
 532 #define LSEXP_INVALID_PNAME     0x0D
 533 #define LSEXP_INVALID_NNAME     0x0E
 534 #define LSEXP_INVALID_CSP       0x0F
 535 #define LSEXP_INVALID_ASSOC_HDR 0x11
 536 #define LSEXP_ASSOC_HDR_REQ     0x13
 537 #define LSEXP_INVALID_O_SID     0x15
 538 #define LSEXP_INVALID_OX_RX     0x17
 539 #define LSEXP_CMD_IN_PROGRESS   0x19
 540 #define LSEXP_INVALID_NPORT_ID  0x1F
 541 #define LSEXP_INVALID_SEQ_ID    0x21
 542 #define LSEXP_INVALID_XCHG      0x23
 543 #define LSEXP_INACTIVE_XCHG     0x25
 544 #define LSEXP_RQ_REQUIRED       0x27
 545 #define LSEXP_OUT_OF_RESOURCE   0x29
 546 #define LSEXP_CANT_GIVE_DATA    0x2A
 547 #define LSEXP_REQ_UNSUPPORTED   0x2C
 548                         uint8_t vendorUnique;   /* FC Word 0, bit  0: 7 */
 549                 } b;
 550         } un;
 551 };
 552
 553 /*
 554  *  N_Port Login (FLOGO/PLOGO Request) Payload Definition
 555  */
 556
 557 typedef struct _LOGO {          /* Structure is in Big Endian format */
 558         union {
 559                 uint32_t nPortId32;     /* Access nPortId as a word */
 560                 struct {
 561                         uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
 562                         uint8_t nPortIdByte0;   /* N_port  ID bit 16:23 */
 563                         uint8_t nPortIdByte1;   /* N_port  ID bit  8:15 */
 564                         uint8_t nPortIdByte2;   /* N_port  ID bit  0: 7 */
 565                 } b;
 566         } un;
 567         struct lpfc_name portName;      /* N_port name field */
 568 } LOGO;
 569
 570 /*
 571  *  FCP Login (PRLI Request / ACC) Payload Definition
 572  */
 573
 574 #define PRLX_PAGE_LEN   0x10
 575 #define TPRLO_PAGE_LEN  0x14
 576
 577 typedef struct _PRLI {          /* Structure is in Big Endian format */
 578         uint8_t prliType;       /* FC Parm Word 0, bit 24:31 */
 579
 580 #define PRLI_FCP_TYPE 0x08
 581         uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
 582
 583 #ifdef __BIG_ENDIAN_BITFIELD
 584         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 585         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 586         uint8_t estabImagePair:1;       /* FC Parm Word 0, bit 13 */
 587
 588         /*    ACC = imagePairEstablished */
 589         uint8_t word0Reserved2:1;       /* FC Parm Word 0, bit 12 */
 590         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 591 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 592         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 593         uint8_t word0Reserved2:1;       /* FC Parm Word 0, bit 12 */
 594         uint8_t estabImagePair:1;       /* FC Parm Word 0, bit 13 */
 595         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 596         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 597         /*    ACC = imagePairEstablished */
 598 #endif
 599
 600 #define PRLI_REQ_EXECUTED     0x1       /* acceptRspCode */
 601 #define PRLI_NO_RESOURCES     0x2
 602 #define PRLI_INIT_INCOMPLETE  0x3
 603 #define PRLI_NO_SUCH_PA       0x4
 604 #define PRLI_PREDEF_CONFIG    0x5
 605 #define PRLI_PARTIAL_SUCCESS  0x6
 606 #define PRLI_INVALID_PAGE_CNT 0x7
 607         uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
 608
 609         uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
 610
 611         uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
 612
 613         uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
 614         uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
 615
 616 #ifdef __BIG_ENDIAN_BITFIELD
 617         uint16_t Word3bit15Resved:1;    /* FC Parm Word 3, bit 15 */
 618         uint16_t Word3bit14Resved:1;    /* FC Parm Word 3, bit 14 */
 619         uint16_t Word3bit13Resved:1;    /* FC Parm Word 3, bit 13 */
 620         uint16_t Word3bit12Resved:1;    /* FC Parm Word 3, bit 12 */
 621         uint16_t Word3bit11Resved:1;    /* FC Parm Word 3, bit 11 */
 622         uint16_t Word3bit10Resved:1;    /* FC Parm Word 3, bit 10 */
 623         uint16_t TaskRetryIdReq:1;      /* FC Parm Word 3, bit  9 */
 624         uint16_t Retry:1;       /* FC Parm Word 3, bit  8 */
 625         uint16_t ConfmComplAllowed:1;   /* FC Parm Word 3, bit  7 */
 626         uint16_t dataOverLay:1; /* FC Parm Word 3, bit  6 */
 627         uint16_t initiatorFunc:1;       /* FC Parm Word 3, bit  5 */
 628         uint16_t targetFunc:1;  /* FC Parm Word 3, bit  4 */
 629         uint16_t cmdDataMixEna:1;       /* FC Parm Word 3, bit  3 */
 630         uint16_t dataRspMixEna:1;       /* FC Parm Word 3, bit  2 */
 631         uint16_t readXferRdyDis:1;      /* FC Parm Word 3, bit  1 */
 632         uint16_t writeXferRdyDis:1;     /* FC Parm Word 3, bit  0 */
 633 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 634         uint16_t Retry:1;       /* FC Parm Word 3, bit  8 */
 635         uint16_t TaskRetryIdReq:1;      /* FC Parm Word 3, bit  9 */
 636         uint16_t Word3bit10Resved:1;    /* FC Parm Word 3, bit 10 */
 637         uint16_t Word3bit11Resved:1;    /* FC Parm Word 3, bit 11 */
 638         uint16_t Word3bit12Resved:1;    /* FC Parm Word 3, bit 12 */
 639         uint16_t Word3bit13Resved:1;    /* FC Parm Word 3, bit 13 */
 640         uint16_t Word3bit14Resved:1;    /* FC Parm Word 3, bit 14 */
 641         uint16_t Word3bit15Resved:1;    /* FC Parm Word 3, bit 15 */
 642         uint16_t writeXferRdyDis:1;     /* FC Parm Word 3, bit  0 */
 643         uint16_t readXferRdyDis:1;      /* FC Parm Word 3, bit  1 */
 644         uint16_t dataRspMixEna:1;       /* FC Parm Word 3, bit  2 */
 645         uint16_t cmdDataMixEna:1;       /* FC Parm Word 3, bit  3 */
 646         uint16_t targetFunc:1;  /* FC Parm Word 3, bit  4 */
 647         uint16_t initiatorFunc:1;       /* FC Parm Word 3, bit  5 */
 648         uint16_t dataOverLay:1; /* FC Parm Word 3, bit  6 */
 649         uint16_t ConfmComplAllowed:1;   /* FC Parm Word 3, bit  7 */
 650 #endif
 651 } PRLI;
 652
 653 /*
 654  *  FCP Logout (PRLO Request / ACC) Payload Definition
 655  */
 656
 657 typedef struct _PRLO {          /* Structure is in Big Endian format */
 658         uint8_t prloType;       /* FC Parm Word 0, bit 24:31 */
 659
 660 #define PRLO_FCP_TYPE  0x08
 661         uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
 662
 663 #ifdef __BIG_ENDIAN_BITFIELD
 664         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 665         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 666         uint8_t word0Reserved2:2;       /* FC Parm Word 0, bit 12:13 */
 667         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 668 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 669         uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 670         uint8_t word0Reserved2:2;       /* FC Parm Word 0, bit 12:13 */
 671         uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 672         uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 673 #endif
 674
 675 #define PRLO_REQ_EXECUTED     0x1       /* acceptRspCode */
 676 #define PRLO_NO_SUCH_IMAGE    0x4
 677 #define PRLO_INVALID_PAGE_CNT 0x7
 678
 679         uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
 680
 681         uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
 682
 683         uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
 684
 685         uint32_t word3Reserved1;        /* FC Parm Word 3, bit 0:31 */
 686 } PRLO;
 687
 688 typedef struct _ADISC {         /* Structure is in Big Endian format */
 689         uint32_t hardAL_PA;
 690         struct lpfc_name portName;
 691         struct lpfc_name nodeName;
 692         uint32_t DID;
 693 } ADISC;
 694
 695 typedef struct _FARP {          /* Structure is in Big Endian format */
 696         uint32_t Mflags:8;
 697         uint32_t Odid:24;
 698 #define FARP_NO_ACTION          0       /* FARP information enclosed, no
 699                                            action */
 700 #define FARP_MATCH_PORT         0x1     /* Match on Responder Port Name */
 701 #define FARP_MATCH_NODE         0x2     /* Match on Responder Node Name */
 702 #define FARP_MATCH_IP           0x4     /* Match on IP address, not supported */
 703 #define FARP_MATCH_IPV4         0x5     /* Match on IPV4 address, not
 704                                            supported */
 705 #define FARP_MATCH_IPV6         0x6     /* Match on IPV6 address, not
 706                                            supported */
 707         uint32_t Rflags:8;
 708         uint32_t Rdid:24;
 709 #define FARP_REQUEST_PLOGI      0x1     /* Request for PLOGI */
 710 #define FARP_REQUEST_FARPR      0x2     /* Request for FARP Response */
 711         struct lpfc_name OportName;
 712         struct lpfc_name OnodeName;
 713         struct lpfc_name RportName;
 714         struct lpfc_name RnodeName;
 715         uint8_t Oipaddr[16];
 716         uint8_t Ripaddr[16];
 717 } FARP;
 718
 719 typedef struct _FAN {           /* Structure is in Big Endian format */
 720         uint32_t Fdid;
 721         struct lpfc_name FportName;
 722         struct lpfc_name FnodeName;
 723 } FAN;
 724
 725 typedef struct _SCR {           /* Structure is in Big Endian format */
 726         uint8_t resvd1;
 727         uint8_t resvd2;
 728         uint8_t resvd3;
 729         uint8_t Function;
 730 #define  SCR_FUNC_FABRIC     0x01
 731 #define  SCR_FUNC_NPORT      0x02
 732 #define  SCR_FUNC_FULL       0x03
 733 #define  SCR_CLEAR           0xff
 734 } SCR;
 735
 736 typedef struct _RNID_TOP_DISC {
 737         struct lpfc_name portName;
 738         uint8_t resvd[8];
 739         uint32_t unitType;
 740 #define RNID_HBA            0x7
 741 #define RNID_HOST           0xa
 742 #define RNID_DRIVER         0xd
 743         uint32_t physPort;
 744         uint32_t attachedNodes;
 745         uint16_t ipVersion;
 746 #define RNID_IPV4           0x1
 747 #define RNID_IPV6           0x2
 748         uint16_t UDPport;
 749         uint8_t ipAddr[16];
 750         uint16_t resvd1;
 751         uint16_t flags;
 752 #define RNID_TD_SUPPORT     0x1
 753 #define RNID_LP_VALID       0x2
 754 } RNID_TOP_DISC;
 755
 756 typedef struct _RNID {          /* Structure is in Big Endian format */
 757         uint8_t Format;
 758 #define RNID_TOPOLOGY_DISC  0xdf
 759         uint8_t CommonLen;
 760         uint8_t resvd1;
 761         uint8_t SpecificLen;
 762         struct lpfc_name portName;
 763         struct lpfc_name nodeName;
 764         union {
 765                 RNID_TOP_DISC topologyDisc;     /* topology disc (0xdf) */
 766         } un;
 767 } RNID;
 768
 769 typedef struct  _RPS {          /* Structure is in Big Endian format */
 770         union {
 771                 uint32_t portNum;
 772                 struct lpfc_name portName;
 773         } un;
 774 } RPS;
 775
 776 typedef struct  _RPS_RSP {      /* Structure is in Big Endian format */
 777         uint16_t rsvd1;
 778         uint16_t portStatus;
 779         uint32_t linkFailureCnt;
 780         uint32_t lossSyncCnt;
 781         uint32_t lossSignalCnt;
 782         uint32_t primSeqErrCnt;
 783         uint32_t invalidXmitWord;
 784         uint32_t crcCnt;
 785 } RPS_RSP;
 786
 787 typedef struct  _RPL {          /* Structure is in Big Endian format */
 788         uint32_t maxsize;
 789         uint32_t index;
 790 } RPL;
 791
 792 typedef struct  _PORT_NUM_BLK {
 793         uint32_t portNum;
 794         uint32_t portID;
 795         struct lpfc_name portName;
 796 } PORT_NUM_BLK;
 797
 798 typedef struct  _RPL_RSP {      /* Structure is in Big Endian format */
 799         uint32_t listLen;
 800         uint32_t index;
 801         PORT_NUM_BLK port_num_blk;
 802 } RPL_RSP;
 803
 804 /* This is used for RSCN command */
 805 typedef struct _D_ID {          /* Structure is in Big Endian format */
 806         union {
 807                 uint32_t word;
 808                 struct {
 809 #ifdef __BIG_ENDIAN_BITFIELD
 810                         uint8_t resv;
 811                         uint8_t domain;
 812                         uint8_t area;
 813                         uint8_t id;
 814 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 815                         uint8_t id;
 816                         uint8_t area;
 817                         uint8_t domain;
 818                         uint8_t resv;
 819 #endif
 820                 } b;
 821         } un;
 822 } D_ID;
 823
 824 /*
 825  *  Structure to define all ELS Payload types
 826  */
 827
 828 typedef struct _ELS_PKT {       /* Structure is in Big Endian format */
 829         uint8_t elsCode;        /* FC Word 0, bit 24:31 */
 830         uint8_t elsByte1;
 831         uint8_t elsByte2;
 832         uint8_t elsByte3;
 833         union {
 834                 struct ls_rjt lsRjt;    /* Payload for LS_RJT ELS response */
 835                 struct serv_parm logi;  /* Payload for PLOGI/FLOGI/PDISC/ACC */
 836                 LOGO logo;      /* Payload for PLOGO/FLOGO/ACC */
 837                 PRLI prli;      /* Payload for PRLI/ACC */
 838                 PRLO prlo;      /* Payload for PRLO/ACC */
 839                 ADISC adisc;    /* Payload for ADISC/ACC */
 840                 FARP farp;      /* Payload for FARP/ACC */
 841                 FAN fan;        /* Payload for FAN */
 842                 SCR scr;        /* Payload for SCR/ACC */
 843                 RNID rnid;      /* Payload for RNID */
 844                 uint8_t pad[128 - 4];   /* Pad out to payload of 128 bytes */
 845         } un;
 846 } ELS_PKT;
 847
 848 /*
 849  * FDMI
 850  * HBA MAnagement Operations Command Codes
 851  */
 852 #define  SLI_MGMT_GRHL     0x100        /* Get registered HBA list */
 853 #define  SLI_MGMT_GHAT     0x101        /* Get HBA attributes */
 854 #define  SLI_MGMT_GRPL     0x102        /* Get registered Port list */
 855 #define  SLI_MGMT_GPAT     0x110        /* Get Port attributes */
 856 #define  SLI_MGMT_RHBA     0x200        /* Register HBA */
 857 #define  SLI_MGMT_RHAT     0x201        /* Register HBA atttributes */
 858 #define  SLI_MGMT_RPRT     0x210        /* Register Port */
 859 #define  SLI_MGMT_RPA      0x211        /* Register Port attributes */
 860 #define  SLI_MGMT_DHBA     0x300        /* De-register HBA */
 861 #define  SLI_MGMT_DPRT     0x310        /* De-register Port */
 862
 863 /*
 864  * Management Service Subtypes
 865  */
 866 #define  SLI_CT_FDMI_Subtypes     0x10
 867
 868 /*
 869  * HBA Management Service Reject Code
 870  */
 871 #define  REJECT_CODE             0x9    /* Unable to perform command request */
 872
 873 /*
 874  * HBA Management Service Reject Reason Code
 875  * Please refer to the Reason Codes above
 876  */
 877
 878 /*
 879  * HBA Attribute Types
 880  */
 881 #define  NODE_NAME               0x1
 882 #define  MANUFACTURER            0x2
 883 #define  SERIAL_NUMBER           0x3
 884 #define  MODEL                   0x4
 885 #define  MODEL_DESCRIPTION       0x5
 886 #define  HARDWARE_VERSION        0x6
 887 #define  DRIVER_VERSION          0x7
 888 #define  OPTION_ROM_VERSION      0x8
 889 #define  FIRMWARE_VERSION        0x9
 890 #define  OS_NAME_VERSION         0xa
 891 #define  MAX_CT_PAYLOAD_LEN      0xb
 892
 893 /*
 894  * Port Attrubute Types
 895  */
 896 #define  SUPPORTED_FC4_TYPES     0x1
 897 #define  SUPPORTED_SPEED         0x2
 898 #define  PORT_SPEED              0x3
 899 #define  MAX_FRAME_SIZE          0x4
 900 #define  OS_DEVICE_NAME          0x5
 901 #define  HOST_NAME               0x6
 902
 903 union AttributesDef {
 904         /* Structure is in Big Endian format */
 905         struct {
 906                 uint32_t AttrType:16;
 907                 uint32_t AttrLen:16;
 908         } bits;
 909         uint32_t word;
 910 };
 911
 912
 913 /*
 914  * HBA Attribute Entry (8 - 260 bytes)
 915  */
 916 typedef struct {
 917         union AttributesDef ad;
 918         union {
 919                 uint32_t VendorSpecific;
 920                 uint8_t Manufacturer[64];
 921                 uint8_t SerialNumber[64];
 922                 uint8_t Model[256];
 923                 uint8_t ModelDescription[256];
 924                 uint8_t HardwareVersion[256];
 925                 uint8_t DriverVersion[256];
 926                 uint8_t OptionROMVersion[256];
 927                 uint8_t FirmwareVersion[256];
 928                 struct lpfc_name NodeName;
 929                 uint8_t SupportFC4Types[32];
 930                 uint32_t SupportSpeed;
 931                 uint32_t PortSpeed;
 932                 uint32_t MaxFrameSize;
 933                 uint8_t OsDeviceName[256];
 934                 uint8_t OsNameVersion[256];
 935                 uint32_t MaxCTPayloadLen;
 936                 uint8_t HostName[256];
 937         } un;
 938 } ATTRIBUTE_ENTRY;
 939
 940 /*
 941  * HBA Attribute Block
 942  */
 943 typedef struct {
 944         uint32_t EntryCnt;      /* Number of HBA attribute entries */
 945         ATTRIBUTE_ENTRY Entry;  /* Variable-length array */
 946 } ATTRIBUTE_BLOCK;
 947
 948 /*
 949  * Port Entry
 950  */
 951 typedef struct {
 952         struct lpfc_name PortName;
 953 } PORT_ENTRY;
 954
 955 /*
 956  * HBA Identifier
 957  */
 958 typedef struct {
 959         struct lpfc_name PortName;
 960 } HBA_IDENTIFIER;
 961
 962 /*
 963  * Registered Port List Format
 964  */
 965 typedef struct {
 966         uint32_t EntryCnt;
 967         PORT_ENTRY pe;          /* Variable-length array */
 968 } REG_PORT_LIST;
 969
 970 /*
 971  * Register HBA(RHBA)
 972  */
 973 typedef struct {
 974         HBA_IDENTIFIER hi;
 975         REG_PORT_LIST rpl;      /* variable-length array */
 976 /* ATTRIBUTE_BLOCK   ab; */
 977 } REG_HBA;
 978
 979 /*
 980  * Register HBA Attributes (RHAT)
 981  */
 982 typedef struct {
 983         struct lpfc_name HBA_PortName;
 984         ATTRIBUTE_BLOCK ab;
 985 } REG_HBA_ATTRIBUTE;
 986
 987 /*
 988  * Register Port Attributes (RPA)
 989  */
 990 typedef struct {
 991         struct lpfc_name PortName;
 992         ATTRIBUTE_BLOCK ab;
 993 } REG_PORT_ATTRIBUTE;
 994
 995 /*
 996  * Get Registered HBA List (GRHL) Accept Payload Format
 997  */
 998 typedef struct {
 999         uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */
1000         struct lpfc_name HBA_PortName;  /* Variable-length array */
1001 } GRHL_ACC_PAYLOAD;
1002
1003 /*
1004  * Get Registered Port List (GRPL) Accept Payload Format
1005  */
1006 typedef struct {
1007         uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */
1008         PORT_ENTRY Reg_Port_Entry[1];   /* Variable-length array */
1009 } GRPL_ACC_PAYLOAD;
1010
1011 /*
1012  * Get Port Attributes (GPAT) Accept Payload Format
1013  */
1014
1015 typedef struct {
1016         ATTRIBUTE_BLOCK pab;
1017 } GPAT_ACC_PAYLOAD;
1018
1019
1020 /*
1021  *  Begin HBA configuration parameters.
1022  *  The PCI configuration register BAR assignments are:
1023  *  BAR0, offset 0x10 - SLIM base memory address
1024  *  BAR1, offset 0x14 - SLIM base memory high address
1025  *  BAR2, offset 0x18 - REGISTER base memory address
1026  *  BAR3, offset 0x1c - REGISTER base memory high address
1027  *  BAR4, offset 0x20 - BIU I/O registers
1028  *  BAR5, offset 0x24 - REGISTER base io high address
1029  */
1030
1031 /* Number of rings currently used and available. */
1032 #define MAX_CONFIGURED_RINGS     3
1033 #define MAX_RINGS                4
1034
1035 /* IOCB / Mailbox is owned by FireFly */
1036 #define OWN_CHIP        1
1037
1038 /* IOCB / Mailbox is owned by Host */
1039 #define OWN_HOST        0
1040
1041 /* Number of 4-byte words in an IOCB. */
1042 #define IOCB_WORD_SZ    8
1043
1044 /* defines for type field in fc header */
1045 #define FC_ELS_DATA     0x1
1046 #define FC_LLC_SNAP     0x5
1047 #define FC_FCP_DATA     0x8
1048 #define FC_COMMON_TRANSPORT_ULP 0x20
1049
1050 /* defines for rctl field in fc header */
1051 #define FC_DEV_DATA     0x0
1052 #define FC_UNSOL_CTL    0x2
1053 #define FC_SOL_CTL      0x3
1054 #define FC_UNSOL_DATA   0x4
1055 #define FC_FCP_CMND     0x6
1056 #define FC_ELS_REQ      0x22
1057 #define FC_ELS_RSP      0x23
1058
1059 /* network headers for Dfctl field */
1060 #define FC_NET_HDR      0x20
1061
1062 /* Start FireFly Register definitions */
1063 #define PCI_VENDOR_ID_EMULEX        0x10df
1064 #define PCI_DEVICE_ID_FIREFLY       0x1ae5
1065 #define PCI_DEVICE_ID_RFLY          0xf095
1066 #define PCI_DEVICE_ID_PFLY          0xf098
1067 #define PCI_DEVICE_ID_LP101         0xf0a1
1068 #define PCI_DEVICE_ID_TFLY          0xf0a5
1069 #define PCI_DEVICE_ID_BSMB          0xf0d1
1070 #define PCI_DEVICE_ID_BMID          0xf0d5
1071 #define PCI_DEVICE_ID_ZSMB          0xf0e1
1072 #define PCI_DEVICE_ID_ZMID          0xf0e5
1073 #define PCI_DEVICE_ID_NEPTUNE       0xf0f5
1074 #define PCI_DEVICE_ID_NEPTUNE_SCSP  0xf0f6
1075 #define PCI_DEVICE_ID_NEPTUNE_DCSP  0xf0f7
1076 #define PCI_DEVICE_ID_SUPERFLY      0xf700
1077 #define PCI_DEVICE_ID_DRAGONFLY     0xf800
1078 #define PCI_DEVICE_ID_CENTAUR       0xf900
1079 #define PCI_DEVICE_ID_PEGASUS       0xf980
1080 #define PCI_DEVICE_ID_THOR          0xfa00
1081 #define PCI_DEVICE_ID_VIPER         0xfb00
1082 #define PCI_DEVICE_ID_LP10000S      0xfc00
1083 #define PCI_DEVICE_ID_LP11000S      0xfc10
1084 #define PCI_DEVICE_ID_LPE11000S     0xfc20
1085 #define PCI_DEVICE_ID_HELIOS        0xfd00
1086 #define PCI_DEVICE_ID_HELIOS_SCSP   0xfd11
1087 #define PCI_DEVICE_ID_HELIOS_DCSP   0xfd12
1088 #define PCI_DEVICE_ID_ZEPHYR        0xfe00
1089 #define PCI_DEVICE_ID_ZEPHYR_SCSP   0xfe11
1090 #define PCI_DEVICE_ID_ZEPHYR_DCSP   0xfe12
1091
1092 #define PCI_SUBSYSTEM_ID_LP11000S      0xfc11
1093 #define PCI_SUBSYSTEM_ID_LP11002S      0xfc12
1094 #define PCI_SUBSYSTEM_ID_LPE11000S     0xfc21
1095 #define PCI_SUBSYSTEM_ID_LPE11002S     0xfc22
1096 #define PCI_SUBSYSTEM_ID_LPE11010S     0xfc2A
1097
1098 #define JEDEC_ID_ADDRESS            0x0080001c
1099 #define FIREFLY_JEDEC_ID            0x1ACC
1100 #define SUPERFLY_JEDEC_ID           0x0020
1101 #define DRAGONFLY_JEDEC_ID          0x0021
1102 #define DRAGONFLY_V2_JEDEC_ID       0x0025
1103 #define CENTAUR_2G_JEDEC_ID         0x0026
1104 #define CENTAUR_1G_JEDEC_ID         0x0028
1105 #define PEGASUS_ORION_JEDEC_ID      0x0036
1106 #define PEGASUS_JEDEC_ID            0x0038
1107 #define THOR_JEDEC_ID               0x0012
1108 #define HELIOS_JEDEC_ID             0x0364
1109 #define ZEPHYR_JEDEC_ID             0x0577
1110 #define VIPER_JEDEC_ID              0x4838
1111
1112 #define JEDEC_ID_MASK               0x0FFFF000
1113 #define JEDEC_ID_SHIFT              12
1114 #define FC_JEDEC_ID(id)             ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1115
1116 typedef struct {                /* FireFly BIU registers */
1117         uint32_t hostAtt;       /* See definitions for Host Attention
1118                                    register */
1119         uint32_t chipAtt;       /* See definitions for Chip Attention
1120                                    register */
1121         uint32_t hostStatus;    /* See definitions for Host Status register */
1122         uint32_t hostControl;   /* See definitions for Host Control register */
1123         uint32_t buiConfig;     /* See definitions for BIU configuration
1124                                    register */
1125 } FF_REGS;
1126
1127 /* IO Register size in bytes */
1128 #define FF_REG_AREA_SIZE       256
1129
1130 /* Host Attention Register */
1131
1132 #define HA_REG_OFFSET  0        /* Byte offset from register base address */
1133
1134 #define HA_R0RE_REQ    0x00000001       /* Bit  0 */
1135 #define HA_R0CE_RSP    0x00000002       /* Bit  1 */
1136 #define HA_R0ATT       0x00000008       /* Bit  3 */
1137 #define HA_R1RE_REQ    0x00000010       /* Bit  4 */
1138 #define HA_R1CE_RSP    0x00000020       /* Bit  5 */
1139 #define HA_R1ATT       0x00000080       /* Bit  7 */
1140 #define HA_R2RE_REQ    0x00000100       /* Bit  8 */
1141 #define HA_R2CE_RSP    0x00000200       /* Bit  9 */
1142 #define HA_R2ATT       0x00000800       /* Bit 11 */
1143 #define HA_R3RE_REQ    0x00001000       /* Bit 12 */
1144 #define HA_R3CE_RSP    0x00002000       /* Bit 13 */
1145 #define HA_R3ATT       0x00008000       /* Bit 15 */
1146 #define HA_LATT        0x20000000       /* Bit 29 */
1147 #define HA_MBATT       0x40000000       /* Bit 30 */
1148 #define HA_ERATT       0x80000000       /* Bit 31 */
1149
1150 #define HA_RXRE_REQ    0x00000001       /* Bit  0 */
1151 #define HA_RXCE_RSP    0x00000002       /* Bit  1 */
1152 #define HA_RXATT       0x00000008       /* Bit  3 */
1153 #define HA_RXMASK      0x0000000f
1154
1155 /* Chip Attention Register */
1156
1157 #define CA_REG_OFFSET  4        /* Byte offset from register base address */
1158
1159 #define CA_R0CE_REQ    0x00000001       /* Bit  0 */
1160 #define CA_R0RE_RSP    0x00000002       /* Bit  1 */
1161 #define CA_R0ATT       0x00000008       /* Bit  3 */
1162 #define CA_R1CE_REQ    0x00000010       /* Bit  4 */
1163 #define CA_R1RE_RSP    0x00000020       /* Bit  5 */
1164 #define CA_R1ATT       0x00000080       /* Bit  7 */
1165 #define CA_R2CE_REQ    0x00000100       /* Bit  8 */
1166 #define CA_R2RE_RSP    0x00000200       /* Bit  9 */
1167 #define CA_R2ATT       0x00000800       /* Bit 11 */
1168 #define CA_R3CE_REQ    0x00001000       /* Bit 12 */
1169 #define CA_R3RE_RSP    0x00002000       /* Bit 13 */
1170 #define CA_R3ATT       0x00008000       /* Bit 15 */
1171 #define CA_MBATT       0x40000000       /* Bit 30 */
1172
1173 /* Host Status Register */
1174
1175 #define HS_REG_OFFSET  8        /* Byte offset from register base address */
1176
1177 #define HS_MBRDY       0x00400000       /* Bit 22 */
1178 #define HS_FFRDY       0x00800000       /* Bit 23 */
1179 #define HS_FFER8       0x01000000       /* Bit 24 */
1180 #define HS_FFER7       0x02000000       /* Bit 25 */
1181 #define HS_FFER6       0x04000000       /* Bit 26 */
1182 #define HS_FFER5       0x08000000       /* Bit 27 */
1183 #define HS_FFER4       0x10000000       /* Bit 28 */
1184 #define HS_FFER3       0x20000000       /* Bit 29 */
1185 #define HS_FFER2       0x40000000       /* Bit 30 */
1186 #define HS_FFER1       0x80000000       /* Bit 31 */
1187 #define HS_FFERM       0xFF000000       /* Mask for error bits 31:24 */
1188
1189 /* Host Control Register */
1190
1191 #define HC_REG_OFFSET  12       /* Word offset from register base address */
1192
1193 #define HC_MBINT_ENA   0x00000001       /* Bit  0 */
1194 #define HC_R0INT_ENA   0x00000002       /* Bit  1 */
1195 #define HC_R1INT_ENA   0x00000004       /* Bit  2 */
1196 #define HC_R2INT_ENA   0x00000008       /* Bit  3 */
1197 #define HC_R3INT_ENA   0x00000010       /* Bit  4 */
1198 #define HC_INITHBI     0x02000000       /* Bit 25 */
1199 #define HC_INITMB      0x04000000       /* Bit 26 */
1200 #define HC_INITFF      0x08000000       /* Bit 27 */
1201 #define HC_LAINT_ENA   0x20000000       /* Bit 29 */
1202 #define HC_ERINT_ENA   0x80000000       /* Bit 31 */
1203
1204 /* Mailbox Commands */
1205 #define MBX_SHUTDOWN        0x00        /* terminate testing */
1206 #define MBX_LOAD_SM         0x01
1207 #define MBX_READ_NV         0x02
1208 #define MBX_WRITE_NV        0x03
1209 #define MBX_RUN_BIU_DIAG    0x04
1210 #define MBX_INIT_LINK       0x05
1211 #define MBX_DOWN_LINK       0x06
1212 #define MBX_CONFIG_LINK     0x07
1213 #define MBX_CONFIG_RING     0x09
1214 #define MBX_RESET_RING      0x0A
1215 #define MBX_READ_CONFIG     0x0B
1216 #define MBX_READ_RCONFIG    0x0C
1217 #define MBX_READ_SPARM      0x0D
1218 #define MBX_READ_STATUS     0x0E
1219 #define MBX_READ_RPI        0x0F
1220 #define MBX_READ_XRI        0x10
1221 #define MBX_READ_REV        0x11
1222 #define MBX_READ_LNK_STAT   0x12
1223 #define MBX_REG_LOGIN       0x13
1224 #define MBX_UNREG_LOGIN     0x14
1225 #define MBX_READ_LA         0x15
1226 #define MBX_CLEAR_LA        0x16
1227 #define MBX_DUMP_MEMORY     0x17
1228 #define MBX_DUMP_CONTEXT    0x18
1229 #define MBX_RUN_DIAGS       0x19
1230 #define MBX_RESTART         0x1A
1231 #define MBX_UPDATE_CFG      0x1B
1232 #define MBX_DOWN_LOAD       0x1C
1233 #define MBX_DEL_LD_ENTRY    0x1D
1234 #define MBX_RUN_PROGRAM     0x1E
1235 #define MBX_SET_MASK        0x20
1236 #define MBX_SET_SLIM        0x21
1237 #define MBX_UNREG_D_ID      0x23
1238 #define MBX_KILL_BOARD      0x24
1239 #define MBX_CONFIG_FARP     0x25
1240 #define MBX_BEACON          0x2A
1241
1242 #define MBX_LOAD_AREA       0x81
1243 #define MBX_RUN_BIU_DIAG64  0x84
1244 #define MBX_CONFIG_PORT     0x88
1245 #define MBX_READ_SPARM64    0x8D
1246 #define MBX_READ_RPI64      0x8F
1247 #define MBX_REG_LOGIN64     0x93
1248 #define MBX_READ_LA64       0x95
1249
1250 #define MBX_FLASH_WR_ULA    0x98
1251 #define MBX_SET_DEBUG       0x99
1252 #define MBX_LOAD_EXP_ROM    0x9C
1253
1254 #define MBX_MAX_CMDS        0x9D
1255 #define MBX_SLI2_CMD_MASK   0x80
1256
1257 /* IOCB Commands */
1258
1259 #define CMD_RCV_SEQUENCE_CX     0x01
1260 #define CMD_XMIT_SEQUENCE_CR    0x02
1261 #define CMD_XMIT_SEQUENCE_CX    0x03
1262 #define CMD_XMIT_BCAST_CN       0x04
1263 #define CMD_XMIT_BCAST_CX       0x05
1264 #define CMD_QUE_RING_BUF_CN     0x06
1265 #define CMD_QUE_XRI_BUF_CX      0x07
1266 #define CMD_IOCB_CONTINUE_CN    0x08
1267 #define CMD_RET_XRI_BUF_CX      0x09
1268 #define CMD_ELS_REQUEST_CR      0x0A
1269 #define CMD_ELS_REQUEST_CX      0x0B
1270 #define CMD_RCV_ELS_REQ_CX      0x0D
1271 #define CMD_ABORT_XRI_CN        0x0E
1272 #define CMD_ABORT_XRI_CX        0x0F
1273 #define CMD_CLOSE_XRI_CN        0x10
1274 #define CMD_CLOSE_XRI_CX        0x11
1275 #define CMD_CREATE_XRI_CR       0x12
1276 #define CMD_CREATE_XRI_CX       0x13
1277 #define CMD_GET_RPI_CN          0x14
1278 #define CMD_XMIT_ELS_RSP_CX     0x15
1279 #define CMD_GET_RPI_CR          0x16
1280 #define CMD_XRI_ABORTED_CX      0x17
1281 #define CMD_FCP_IWRITE_CR       0x18
1282 #define CMD_FCP_IWRITE_CX       0x19
1283 #define CMD_FCP_IREAD_CR        0x1A
1284 #define CMD_FCP_IREAD_CX        0x1B
1285 #define CMD_FCP_ICMND_CR        0x1C
1286 #define CMD_FCP_ICMND_CX        0x1D
1287
1288 #define CMD_ADAPTER_MSG         0x20
1289 #define CMD_ADAPTER_DUMP        0x22
1290
1291 /*  SLI_2 IOCB Command Set */
1292
1293 #define CMD_RCV_SEQUENCE64_CX   0x81
1294 #define CMD_XMIT_SEQUENCE64_CR  0x82
1295 #define CMD_XMIT_SEQUENCE64_CX  0x83
1296 #define CMD_XMIT_BCAST64_CN     0x84
1297 #define CMD_XMIT_BCAST64_CX     0x85
1298 #define CMD_QUE_RING_BUF64_CN   0x86
1299 #define CMD_QUE_XRI_BUF64_CX    0x87
1300 #define CMD_IOCB_CONTINUE64_CN  0x88
1301 #define CMD_RET_XRI_BUF64_CX    0x89
1302 #define CMD_ELS_REQUEST64_CR    0x8A
1303 #define CMD_ELS_REQUEST64_CX    0x8B
1304 #define CMD_ABORT_MXRI64_CN     0x8C
1305 #define CMD_RCV_ELS_REQ64_CX    0x8D
1306 #define CMD_XMIT_ELS_RSP64_CX   0x95
1307 #define CMD_FCP_IWRITE64_CR     0x98
1308 #define CMD_FCP_IWRITE64_CX     0x99
1309 #define CMD_FCP_IREAD64_CR      0x9A
1310 #define CMD_FCP_IREAD64_CX      0x9B
1311 #define CMD_FCP_ICMND64_CR      0x9C
1312 #define CMD_FCP_ICMND64_CX      0x9D
1313
1314 #define CMD_GEN_REQUEST64_CR    0xC2
1315 #define CMD_GEN_REQUEST64_CX    0xC3
1316
1317 #define CMD_MAX_IOCB_CMD        0xE6
1318 #define CMD_IOCB_MASK           0xff
1319
1320 #define MAX_MSG_DATA            28      /* max msg data in CMD_ADAPTER_MSG
1321                                            iocb */
1322 #define LPFC_MAX_ADPTMSG         32     /* max msg data */
1323 /*
1324  *  Define Status
1325  */
1326 #define MBX_SUCCESS                 0
1327 #define MBXERR_NUM_RINGS            1
1328 #define MBXERR_NUM_IOCBS            2
1329 #define MBXERR_IOCBS_EXCEEDED       3
1330 #define MBXERR_BAD_RING_NUMBER      4
1331 #define MBXERR_MASK_ENTRIES_RANGE   5
1332 #define MBXERR_MASKS_EXCEEDED       6
1333 #define MBXERR_BAD_PROFILE          7
1334 #define MBXERR_BAD_DEF_CLASS        8
1335 #define MBXERR_BAD_MAX_RESPONDER    9
1336 #define MBXERR_BAD_MAX_ORIGINATOR   10
1337 #define MBXERR_RPI_REGISTERED       11
1338 #define MBXERR_RPI_FULL             12
1339 #define MBXERR_NO_RESOURCES         13
1340 #define MBXERR_BAD_RCV_LENGTH       14
1341 #define MBXERR_DMA_ERROR            15
1342 #define MBXERR_ERROR                16
1343 #define MBX_NOT_FINISHED           255
1344
1345 #define MBX_BUSY                   0xffffff /* Attempted cmd to busy Mailbox */
1346 #define MBX_TIMEOUT                0xfffffe /* time-out expired waiting for */
1347
1348 /*
1349  *    Begin Structure Definitions for Mailbox Commands
1350  */
1351
1352 typedef struct {
1353 #ifdef __BIG_ENDIAN_BITFIELD
1354         uint8_t tval;
1355         uint8_t tmask;
1356         uint8_t rval;
1357         uint8_t rmask;
1358 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1359         uint8_t rmask;
1360         uint8_t rval;
1361         uint8_t tmask;
1362         uint8_t tval;
1363 #endif
1364 } RR_REG;
1365
1366 struct ulp_bde {
1367         uint32_t bdeAddress;
1368 #ifdef __BIG_ENDIAN_BITFIELD
1369         uint32_t bdeReserved:4;
1370         uint32_t bdeAddrHigh:4;
1371         uint32_t bdeSize:24;
1372 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1373         uint32_t bdeSize:24;
1374         uint32_t bdeAddrHigh:4;
1375         uint32_t bdeReserved:4;
1376 #endif
1377 };
1378
1379 struct ulp_bde64 {      /* SLI-2 */
1380         union ULP_BDE_TUS {
1381                 uint32_t w;
1382                 struct {
1383 #ifdef __BIG_ENDIAN_BITFIELD
1384                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
1385                                                    VALUE !! */
1386                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
1387 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1388                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
1389                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
1390                                                    VALUE !! */
1391 #endif
1392
1393 #define BUFF_USE_RSVD       0x01        /* bdeFlags */
1394 #define BUFF_USE_INTRPT     0x02        /* Not Implemented with LP6000 */
1395 #define BUFF_USE_CMND       0x04        /* Optional, 1=cmd/rsp 0=data buffer */
1396 #define BUFF_USE_RCV        0x08        /*  "" "", 1=rcv buffer, 0=xmit
1397                                             buffer */
1398 #define BUFF_TYPE_32BIT     0x10        /*  "" "", 1=32 bit addr 0=64 bit
1399                                             addr */
1400 #define BUFF_TYPE_SPECIAL   0x20        /* Not Implemented with LP6000  */
1401 #define BUFF_TYPE_BDL       0x40        /* Optional,  may be set in BDL */
1402 #define BUFF_TYPE_INVALID   0x80        /*  ""  "" */
1403                 } f;
1404         } tus;
1405         uint32_t addrLow;
1406         uint32_t addrHigh;
1407 };
1408 #define BDE64_SIZE_WORD 0
1409 #define BPL64_SIZE_WORD 0x40
1410
1411 typedef struct ULP_BDL {        /* SLI-2 */
1412 #ifdef __BIG_ENDIAN_BITFIELD
1413         uint32_t bdeFlags:8;    /* BDL Flags */
1414         uint32_t bdeSize:24;    /* Size of BDL array in host memory (bytes) */
1415 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1416         uint32_t bdeSize:24;    /* Size of BDL array in host memory (bytes) */
1417         uint32_t bdeFlags:8;    /* BDL Flags */
1418 #endif
1419
1420         uint32_t addrLow;       /* Address 0:31 */
1421         uint32_t addrHigh;      /* Address 32:63 */
1422         uint32_t ulpIoTag32;    /* Can be used for 32 bit I/O Tag */
1423 } ULP_BDL;
1424
1425 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
1426
1427 typedef struct {
1428 #ifdef __BIG_ENDIAN_BITFIELD
1429         uint32_t rsvd2:25;
1430         uint32_t acknowledgment:1;
1431         uint32_t version:1;
1432         uint32_t erase_or_prog:1;
1433         uint32_t update_flash:1;
1434         uint32_t update_ram:1;
1435         uint32_t method:1;
1436         uint32_t load_cmplt:1;
1437 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1438         uint32_t load_cmplt:1;
1439         uint32_t method:1;
1440         uint32_t update_ram:1;
1441         uint32_t update_flash:1;
1442         uint32_t erase_or_prog:1;
1443         uint32_t version:1;
1444         uint32_t acknowledgment:1;
1445         uint32_t rsvd2:25;
1446 #endif
1447
1448         uint32_t dl_to_adr_low;
1449         uint32_t dl_to_adr_high;
1450         uint32_t dl_len;
1451         union {
1452                 uint32_t dl_from_mbx_offset;
1453                 struct ulp_bde dl_from_bde;
1454                 struct ulp_bde64 dl_from_bde64;
1455         } un;
1456
1457 } LOAD_SM_VAR;
1458
1459 /* Structure for MB Command READ_NVPARM (02) */
1460
1461 typedef struct {
1462         uint32_t rsvd1[3];      /* Read as all one's */
1463         uint32_t rsvd2;         /* Read as all zero's */
1464         uint32_t portname[2];   /* N_PORT name */
1465         uint32_t nodename[2];   /* NODE name */
1466
1467 #ifdef __BIG_ENDIAN_BITFIELD
1468         uint32_t pref_DID:24;
1469         uint32_t hardAL_PA:8;
1470 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1471         uint32_t hardAL_PA:8;
1472         uint32_t pref_DID:24;
1473 #endif
1474
1475         uint32_t rsvd3[21];     /* Read as all one's */
1476 } READ_NV_VAR;
1477
1478 /* Structure for MB Command WRITE_NVPARMS (03) */
1479
1480 typedef struct {
1481         uint32_t rsvd1[3];      /* Must be all one's */
1482         uint32_t rsvd2;         /* Must be all zero's */
1483         uint32_t portname[2];   /* N_PORT name */
1484         uint32_t nodename[2];   /* NODE name */
1485
1486 #ifdef __BIG_ENDIAN_BITFIELD
1487         uint32_t pref_DID:24;
1488         uint32_t hardAL_PA:8;
1489 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1490         uint32_t hardAL_PA:8;
1491         uint32_t pref_DID:24;
1492 #endif
1493
1494         uint32_t rsvd3[21];     /* Must be all one's */
1495 } WRITE_NV_VAR;
1496
1497 /* Structure for MB Command RUN_BIU_DIAG (04) */
1498 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
1499
1500 typedef struct {
1501         uint32_t rsvd1;
1502         union {
1503                 struct {
1504                         struct ulp_bde xmit_bde;
1505                         struct ulp_bde rcv_bde;
1506                 } s1;
1507                 struct {
1508                         struct ulp_bde64 xmit_bde64;
1509                         struct ulp_bde64 rcv_bde64;
1510                 } s2;
1511         } un;
1512 } BIU_DIAG_VAR;
1513
1514 /* Structure for MB Command INIT_LINK (05) */
1515
1516 typedef struct {
1517 #ifdef __BIG_ENDIAN_BITFIELD
1518         uint32_t rsvd1:24;
1519         uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1520 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1521         uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1522         uint32_t rsvd1:24;
1523 #endif
1524
1525 #ifdef __BIG_ENDIAN_BITFIELD
1526         uint8_t fabric_AL_PA;   /* If using a Fabric Assigned AL_PA */
1527         uint8_t rsvd2;
1528         uint16_t link_flags;
1529 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1530         uint16_t link_flags;
1531         uint8_t rsvd2;
1532         uint8_t fabric_AL_PA;   /* If using a Fabric Assigned AL_PA */
1533 #endif
1534
1535 #define FLAGS_LOCAL_LB               0x01 /* link_flags (=1) ENDEC loopback */
1536 #define FLAGS_TOPOLOGY_MODE_LOOP_PT  0x00 /* Attempt loop then pt-pt */
1537 #define FLAGS_TOPOLOGY_MODE_PT_PT    0x02 /* Attempt pt-pt only */
1538 #define FLAGS_TOPOLOGY_MODE_LOOP     0x04 /* Attempt loop only */
1539 #define FLAGS_TOPOLOGY_MODE_PT_LOOP  0x06 /* Attempt pt-pt then loop */
1540 #define FLAGS_LIRP_LILP              0x80 /* LIRP / LILP is disabled */
1541
1542 #define FLAGS_TOPOLOGY_FAILOVER      0x0400     /* Bit 10 */
1543 #define FLAGS_LINK_SPEED             0x0800     /* Bit 11 */
1544 #define FLAGS_IMED_ABORT             0x04000    /* Bit 14 */
1545
1546         uint32_t link_speed;
1547 #define LINK_SPEED_AUTO 0       /* Auto selection */
1548 #define LINK_SPEED_1G   1       /* 1 Gigabaud */
1549 #define LINK_SPEED_2G   2       /* 2 Gigabaud */
1550 #define LINK_SPEED_4G   4       /* 4 Gigabaud */
1551 #define LINK_SPEED_8G   8       /* 4 Gigabaud */
1552 #define LINK_SPEED_10G   16      /* 10 Gigabaud */
1553
1554 } INIT_LINK_VAR;
1555
1556 /* Structure for MB Command DOWN_LINK (06) */
1557
1558 typedef struct {
1559         uint32_t rsvd1;
1560 } DOWN_LINK_VAR;
1561
1562 /* Structure for MB Command CONFIG_LINK (07) */
1563
1564 typedef struct {
1565 #ifdef __BIG_ENDIAN_BITFIELD
1566         uint32_t cr:1;
1567         uint32_t ci:1;
1568         uint32_t cr_delay:6;
1569         uint32_t cr_count:8;
1570         uint32_t rsvd1:8;
1571         uint32_t MaxBBC:8;
1572 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1573         uint32_t MaxBBC:8;
1574         uint32_t rsvd1:8;
1575         uint32_t cr_count:8;
1576         uint32_t cr_delay:6;
1577         uint32_t ci:1;
1578         uint32_t cr:1;
1579 #endif
1580
1581         uint32_t myId;
1582         uint32_t rsvd2;
1583         uint32_t edtov;
1584         uint32_t arbtov;
1585         uint32_t ratov;
1586         uint32_t rttov;
1587         uint32_t altov;
1588         uint32_t crtov;
1589         uint32_t citov;
1590 #ifdef __BIG_ENDIAN_BITFIELD
1591         uint32_t rrq_enable:1;
1592         uint32_t rrq_immed:1;
1593         uint32_t rsvd4:29;
1594         uint32_t ack0_enable:1;
1595 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1596         uint32_t ack0_enable:1;
1597         uint32_t rsvd4:29;
1598         uint32_t rrq_immed:1;
1599         uint32_t rrq_enable:1;
1600 #endif
1601 } CONFIG_LINK;
1602
1603 /* Structure for MB Command PART_SLIM (08)
1604  * will be removed since SLI1 is no longer supported!
1605  */
1606 typedef struct {
1607 #ifdef __BIG_ENDIAN_BITFIELD
1608         uint16_t offCiocb;
1609         uint16_t numCiocb;
1610         uint16_t offRiocb;
1611         uint16_t numRiocb;
1612 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1613         uint16_t numCiocb;
1614         uint16_t offCiocb;
1615         uint16_t numRiocb;
1616         uint16_t offRiocb;
1617 #endif
1618 } RING_DEF;
1619
1620 typedef struct {
1621 #ifdef __BIG_ENDIAN_BITFIELD
1622         uint32_t unused1:24;
1623         uint32_t numRing:8;
1624 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1625         uint32_t numRing:8;
1626         uint32_t unused1:24;
1627 #endif
1628
1629         RING_DEF ringdef[4];
1630         uint32_t hbainit;
1631 } PART_SLIM_VAR;
1632
1633 /* Structure for MB Command CONFIG_RING (09) */
1634
1635 typedef struct {
1636 #ifdef __BIG_ENDIAN_BITFIELD
1637         uint32_t unused2:6;
1638         uint32_t recvSeq:1;
1639         uint32_t recvNotify:1;
1640         uint32_t numMask:8;
1641         uint32_t profile:8;
1642         uint32_t unused1:4;
1643         uint32_t ring:4;
1644 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1645         uint32_t ring:4;
1646         uint32_t unused1:4;
1647         uint32_t profile:8;
1648         uint32_t numMask:8;
1649         uint32_t recvNotify:1;
1650         uint32_t recvSeq:1;
1651         uint32_t unused2:6;
1652 #endif
1653
1654 #ifdef __BIG_ENDIAN_BITFIELD
1655         uint16_t maxRespXchg;
1656         uint16_t maxOrigXchg;
1657 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1658         uint16_t maxOrigXchg;
1659         uint16_t maxRespXchg;
1660 #endif
1661
1662         RR_REG rrRegs[6];
1663 } CONFIG_RING_VAR;
1664
1665 /* Structure for MB Command RESET_RING (10) */
1666
1667 typedef struct {
1668         uint32_t ring_no;
1669 } RESET_RING_VAR;
1670
1671 /* Structure for MB Command READ_CONFIG (11) */
1672
1673 typedef struct {
1674 #ifdef __BIG_ENDIAN_BITFIELD
1675         uint32_t cr:1;
1676         uint32_t ci:1;
1677         uint32_t cr_delay:6;
1678         uint32_t cr_count:8;
1679         uint32_t InitBBC:8;
1680         uint32_t MaxBBC:8;
1681 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1682         uint32_t MaxBBC:8;
1683         uint32_t InitBBC:8;
1684         uint32_t cr_count:8;
1685         uint32_t cr_delay:6;
1686         uint32_t ci:1;
1687         uint32_t cr:1;
1688 #endif
1689
1690 #ifdef __BIG_ENDIAN_BITFIELD
1691         uint32_t topology:8;
1692         uint32_t myDid:24;
1693 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1694         uint32_t myDid:24;
1695         uint32_t topology:8;
1696 #endif
1697
1698         /* Defines for topology (defined previously) */
1699 #ifdef __BIG_ENDIAN_BITFIELD
1700         uint32_t AR:1;
1701         uint32_t IR:1;
1702         uint32_t rsvd1:29;
1703         uint32_t ack0:1;
1704 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1705         uint32_t ack0:1;
1706         uint32_t rsvd1:29;
1707         uint32_t IR:1;
1708         uint32_t AR:1;
1709 #endif
1710
1711         uint32_t edtov;
1712         uint32_t arbtov;
1713         uint32_t ratov;
1714         uint32_t rttov;
1715         uint32_t altov;
1716         uint32_t lmt;
1717 #define LMT_RESERVED  0x000    /* Not used */
1718 #define LMT_1Gb       0x004
1719 #define LMT_2Gb       0x008
1720 #define LMT_4Gb       0x040
1721 #define LMT_8Gb       0x080
1722 #define LMT_10Gb      0x100
1723
1724
1725         uint32_t rsvd2;
1726         uint32_t rsvd3;
1727         uint32_t max_xri;
1728         uint32_t max_iocb;
1729         uint32_t max_rpi;
1730         uint32_t avail_xri;
1731         uint32_t avail_iocb;
1732         uint32_t avail_rpi;
1733         uint32_t default_rpi;
1734 } READ_CONFIG_VAR;
1735
1736 /* Structure for MB Command READ_RCONFIG (12) */
1737
1738 typedef struct {
1739 #ifdef __BIG_ENDIAN_BITFIELD
1740         uint32_t rsvd2:7;
1741         uint32_t recvNotify:1;
1742         uint32_t numMask:8;
1743         uint32_t profile:8;
1744         uint32_t rsvd1:4;
1745         uint32_t ring:4;
1746 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1747         uint32_t ring:4;
1748         uint32_t rsvd1:4;
1749         uint32_t profile:8;
1750         uint32_t numMask:8;
1751         uint32_t recvNotify:1;
1752         uint32_t rsvd2:7;
1753 #endif
1754
1755 #ifdef __BIG_ENDIAN_BITFIELD
1756         uint16_t maxResp;
1757         uint16_t maxOrig;
1758 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1759         uint16_t maxOrig;
1760         uint16_t maxResp;
1761 #endif
1762
1763         RR_REG rrRegs[6];
1764
1765 #ifdef __BIG_ENDIAN_BITFIELD
1766         uint16_t cmdRingOffset;
1767         uint16_t cmdEntryCnt;
1768         uint16_t rspRingOffset;
1769         uint16_t rspEntryCnt;
1770         uint16_t nextCmdOffset;
1771         uint16_t rsvd3;
1772         uint16_t nextRspOffset;
1773         uint16_t rsvd4;
1774 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1775         uint16_t cmdEntryCnt;
1776         uint16_t cmdRingOffset;
1777         uint16_t rspEntryCnt;
1778         uint16_t rspRingOffset;
1779         uint16_t rsvd3;
1780         uint16_t nextCmdOffset;
1781         uint16_t rsvd4;
1782         uint16_t nextRspOffset;
1783 #endif
1784 } READ_RCONF_VAR;
1785
1786 /* Structure for MB Command READ_SPARM (13) */
1787 /* Structure for MB Command READ_SPARM64 (0x8D) */
1788
1789 typedef struct {
1790         uint32_t rsvd1;
1791         uint32_t rsvd2;
1792         union {
1793                 struct ulp_bde sp; /* This BDE points to struct serv_parm
1794                                       structure */
1795                 struct ulp_bde64 sp64;
1796         } un;
1797 } READ_SPARM_VAR;
1798
1799 /* Structure for MB Command READ_STATUS (14) */
1800
1801 typedef struct {
1802 #ifdef __BIG_ENDIAN_BITFIELD
1803         uint32_t rsvd1:31;
1804         uint32_t clrCounters:1;
1805         uint16_t activeXriCnt;
1806         uint16_t activeRpiCnt;
1807 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1808         uint32_t clrCounters:1;
1809         uint32_t rsvd1:31;
1810         uint16_t activeRpiCnt;
1811         uint16_t activeXriCnt;
1812 #endif
1813
1814         uint32_t xmitByteCnt;
1815         uint32_t rcvByteCnt;
1816         uint32_t xmitFrameCnt;
1817         uint32_t rcvFrameCnt;
1818         uint32_t xmitSeqCnt;
1819         uint32_t rcvSeqCnt;
1820         uint32_t totalOrigExchanges;
1821         uint32_t totalRespExchanges;
1822         uint32_t rcvPbsyCnt;
1823         uint32_t rcvFbsyCnt;
1824 } READ_STATUS_VAR;
1825
1826 /* Structure for MB Command READ_RPI (15) */
1827 /* Structure for MB Command READ_RPI64 (0x8F) */
1828
1829 typedef struct {
1830 #ifdef __BIG_ENDIAN_BITFIELD
1831         uint16_t nextRpi;
1832         uint16_t reqRpi;
1833         uint32_t rsvd2:8;
1834         uint32_t DID:24;
1835 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1836         uint16_t reqRpi;
1837         uint16_t nextRpi;
1838         uint32_t DID:24;
1839         uint32_t rsvd2:8;
1840 #endif
1841
1842         union {
1843                 struct ulp_bde sp;
1844                 struct ulp_bde64 sp64;
1845         } un;
1846
1847 } READ_RPI_VAR;
1848
1849 /* Structure for MB Command READ_XRI (16) */
1850
1851 typedef struct {
1852 #ifdef __BIG_ENDIAN_BITFIELD
1853         uint16_t nextXri;
1854         uint16_t reqXri;
1855         uint16_t rsvd1;
1856         uint16_t rpi;
1857         uint32_t rsvd2:8;
1858         uint32_t DID:24;
1859         uint32_t rsvd3:8;
1860         uint32_t SID:24;
1861         uint32_t rsvd4;
1862         uint8_t seqId;
1863         uint8_t rsvd5;
1864         uint16_t seqCount;
1865         uint16_t oxId;
1866         uint16_t rxId;
1867         uint32_t rsvd6:30;
1868         uint32_t si:1;
1869         uint32_t exchOrig:1;
1870 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1871         uint16_t reqXri;
1872         uint16_t nextXri;
1873         uint16_t rpi;
1874         uint16_t rsvd1;
1875         uint32_t DID:24;
1876         uint32_t rsvd2:8;
1877         uint32_t SID:24;
1878         uint32_t rsvd3:8;
1879         uint32_t rsvd4;
1880         uint16_t seqCount;
1881         uint8_t rsvd5;
1882         uint8_t seqId;
1883         uint16_t rxId;
1884         uint16_t oxId;
1885         uint32_t exchOrig:1;
1886         uint32_t si:1;
1887         uint32_t rsvd6:30;
1888 #endif
1889 } READ_XRI_VAR;
1890
1891 /* Structure for MB Command READ_REV (17) */
1892
1893 typedef struct {
1894 #ifdef __BIG_ENDIAN_BITFIELD
1895         uint32_t cv:1;
1896         uint32_t rr:1;
1897         uint32_t rsvd1:29;
1898         uint32_t rv:1;
1899 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1900         uint32_t rv:1;
1901         uint32_t rsvd1:29;
1902         uint32_t rr:1;
1903         uint32_t cv:1;
1904 #endif
1905
1906         uint32_t biuRev;
1907         uint32_t smRev;
1908         union {
1909                 uint32_t smFwRev;
1910                 struct {
1911 #ifdef __BIG_ENDIAN_BITFIELD
1912                         uint8_t ProgType;
1913                         uint8_t ProgId;
1914                         uint16_t ProgVer:4;
1915                         uint16_t ProgRev:4;
1916                         uint16_t ProgFixLvl:2;
1917                         uint16_t ProgDistType:2;
1918                         uint16_t DistCnt:4;
1919 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1920                         uint16_t DistCnt:4;
1921                         uint16_t ProgDistType:2;
1922                         uint16_t ProgFixLvl:2;
1923                         uint16_t ProgRev:4;
1924                         uint16_t ProgVer:4;
1925                         uint8_t ProgId;
1926                         uint8_t ProgType;
1927 #endif
1928
1929                 } b;
1930         } un;
1931         uint32_t endecRev;
1932 #ifdef __BIG_ENDIAN_BITFIELD
1933         uint8_t feaLevelHigh;
1934         uint8_t feaLevelLow;
1935         uint8_t fcphHigh;
1936         uint8_t fcphLow;
1937 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1938         uint8_t fcphLow;
1939         uint8_t fcphHigh;
1940         uint8_t feaLevelLow;
1941         uint8_t feaLevelHigh;
1942 #endif
1943
1944         uint32_t postKernRev;
1945         uint32_t opFwRev;
1946         uint8_t opFwName[16];
1947         uint32_t sli1FwRev;
1948         uint8_t sli1FwName[16];
1949         uint32_t sli2FwRev;
1950         uint8_t sli2FwName[16];
1951         uint32_t rsvd2;
1952         uint32_t RandomData[7];
1953 } READ_REV_VAR;
1954
1955 /* Structure for MB Command READ_LINK_STAT (18) */
1956
1957 typedef struct {
1958         uint32_t rsvd1;
1959         uint32_t linkFailureCnt;
1960         uint32_t lossSyncCnt;
1961
1962         uint32_t lossSignalCnt;
1963         uint32_t primSeqErrCnt;
1964         uint32_t invalidXmitWord;
1965         uint32_t crcCnt;
1966         uint32_t primSeqTimeout;
1967         uint32_t elasticOverrun;
1968         uint32_t arbTimeout;
1969 } READ_LNK_VAR;
1970
1971 /* Structure for MB Command REG_LOGIN (19) */
1972 /* Structure for MB Command REG_LOGIN64 (0x93) */
1973
1974 typedef struct {
1975 #ifdef __BIG_ENDIAN_BITFIELD
1976         uint16_t rsvd1;
1977         uint16_t rpi;
1978         uint32_t rsvd2:8;
1979         uint32_t did:24;
1980 #else   /*  __LITTLE_ENDIAN_BITFIELD */
1981         uint16_t rpi;
1982         uint16_t rsvd1;
1983         uint32_t did:24;
1984         uint32_t rsvd2:8;
1985 #endif
1986
1987         union {
1988                 struct ulp_bde sp;
1989                 struct ulp_bde64 sp64;
1990         } un;
1991
1992 } REG_LOGIN_VAR;
1993
1994 /* Word 30 contents for REG_LOGIN */
1995 typedef union {
1996         struct {
1997 #ifdef __BIG_ENDIAN_BITFIELD
1998                 uint16_t rsvd1:12;
1999                 uint16_t wd30_class:4;
2000                 uint16_t xri;
2001 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2002                 uint16_t xri;
2003                 uint16_t wd30_class:4;
2004                 uint16_t rsvd1:12;
2005 #endif
2006         } f;
2007         uint32_t word;
2008 } REG_WD30;
2009
2010 /* Structure for MB Command UNREG_LOGIN (20) */
2011
2012 typedef struct {
2013 #ifdef __BIG_ENDIAN_BITFIELD
2014         uint16_t rsvd1;
2015         uint16_t rpi;
2016 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2017         uint16_t rpi;
2018         uint16_t rsvd1;
2019 #endif
2020 } UNREG_LOGIN_VAR;
2021
2022 /* Structure for MB Command UNREG_D_ID (0x23) */
2023
2024 typedef struct {
2025         uint32_t did;
2026 } UNREG_D_ID_VAR;
2027
2028 /* Structure for MB Command READ_LA (21) */
2029 /* Structure for MB Command READ_LA64 (0x95) */
2030
2031 typedef struct {
2032         uint32_t eventTag;      /* Event tag */
2033 #ifdef __BIG_ENDIAN_BITFIELD
2034         uint32_t rsvd1:22;
2035         uint32_t pb:1;
2036         uint32_t il:1;
2037         uint32_t attType:8;
2038 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2039         uint32_t attType:8;
2040         uint32_t il:1;
2041         uint32_t pb:1;
2042         uint32_t rsvd1:22;
2043 #endif
2044
2045 #define AT_RESERVED    0x00     /* Reserved - attType */
2046 #define AT_LINK_UP     0x01     /* Link is up */
2047 #define AT_LINK_DOWN   0x02     /* Link is down */
2048
2049 #ifdef __BIG_ENDIAN_BITFIELD
2050         uint8_t granted_AL_PA;
2051         uint8_t lipAlPs;
2052         uint8_t lipType;
2053         uint8_t topology;
2054 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2055         uint8_t topology;
2056         uint8_t lipType;
2057         uint8_t lipAlPs;
2058         uint8_t granted_AL_PA;
2059 #endif
2060
2061 #define TOPOLOGY_PT_PT 0x01     /* Topology is pt-pt / pt-fabric */
2062 #define TOPOLOGY_LOOP  0x02     /* Topology is FC-AL */
2063
2064         union {
2065                 struct ulp_bde lilpBde; /* This BDE points to a 128 byte buffer
2066                                            to */
2067                 /* store the LILP AL_PA position map into */
2068                 struct ulp_bde64 lilpBde64;
2069         } un;
2070
2071 #ifdef __BIG_ENDIAN_BITFIELD
2072         uint32_t Dlu:1;
2073         uint32_t Dtf:1;
2074         uint32_t Drsvd2:14;
2075         uint32_t DlnkSpeed:8;
2076         uint32_t DnlPort:4;
2077         uint32_t Dtx:2;
2078         uint32_t Drx:2;
2079 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2080         uint32_t Drx:2;
2081         uint32_t Dtx:2;
2082         uint32_t DnlPort:4;
2083         uint32_t DlnkSpeed:8;
2084         uint32_t Drsvd2:14;
2085         uint32_t Dtf:1;
2086         uint32_t Dlu:1;
2087 #endif
2088
2089 #ifdef __BIG_ENDIAN_BITFIELD
2090         uint32_t Ulu:1;
2091         uint32_t Utf:1;
2092         uint32_t Ursvd2:14;
2093         uint32_t UlnkSpeed:8;
2094         uint32_t UnlPort:4;
2095         uint32_t Utx:2;
2096         uint32_t Urx:2;
2097 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2098         uint32_t Urx:2;
2099         uint32_t Utx:2;
2100         uint32_t UnlPort:4;
2101         uint32_t UlnkSpeed:8;
2102         uint32_t Ursvd2:14;
2103         uint32_t Utf:1;
2104         uint32_t Ulu:1;
2105 #endif
2106
2107 #define LA_UNKNW_LINK  0x0    /* lnkSpeed */
2108 #define LA_1GHZ_LINK   0x04   /* lnkSpeed */
2109 #define LA_2GHZ_LINK   0x08   /* lnkSpeed */
2110 #define LA_4GHZ_LINK   0x10   /* lnkSpeed */
2111 #define LA_8GHZ_LINK   0x20   /* lnkSpeed */
2112 #define LA_10GHZ_LINK  0x40   /* lnkSpeed */
2113
2114 } READ_LA_VAR;
2115
2116 /* Structure for MB Command CLEAR_LA (22) */
2117
2118 typedef struct {
2119         uint32_t eventTag;      /* Event tag */
2120         uint32_t rsvd1;
2121 } CLEAR_LA_VAR;
2122
2123 /* Structure for MB Command DUMP */
2124
2125 typedef struct {
2126 #ifdef __BIG_ENDIAN_BITFIELD
2127         uint32_t rsvd:25;
2128         uint32_t ra:1;
2129         uint32_t co:1;
2130         uint32_t cv:1;
2131         uint32_t type:4;
2132         uint32_t entry_index:16;
2133         uint32_t region_id:16;
2134 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2135         uint32_t type:4;
2136         uint32_t cv:1;
2137         uint32_t co:1;
2138         uint32_t ra:1;
2139         uint32_t rsvd:25;
2140         uint32_t region_id:16;
2141         uint32_t entry_index:16;
2142 #endif
2143
2144         uint32_t rsvd1;
2145         uint32_t word_cnt;
2146         uint32_t resp_offset;
2147 } DUMP_VAR;
2148
2149 #define  DMP_MEM_REG             0x1
2150 #define  DMP_NV_PARAMS           0x2
2151
2152 #define  DMP_REGION_VPD          0xe
2153 #define  DMP_VPD_SIZE            0x400  /* maximum amount of VPD */
2154 #define  DMP_RSP_OFFSET          0x14   /* word 5 contains first word of rsp */
2155 #define  DMP_RSP_SIZE            0x6C   /* maximum of 27 words of rsp data */
2156
2157 /* Structure for MB Command CONFIG_PORT (0x88) */
2158
2159 typedef struct {
2160         uint32_t pcbLen;
2161         uint32_t pcbLow;       /* bit 31:0  of memory based port config block */
2162         uint32_t pcbHigh;      /* bit 63:32 of memory based port config block */
2163         uint32_t hbainit[5];
2164 } CONFIG_PORT_VAR;
2165
2166 /* SLI-2 Port Control Block */
2167
2168 /* SLIM POINTER */
2169 #define SLIMOFF 0x30            /* WORD */
2170
2171 typedef struct _SLI2_RDSC {
2172         uint32_t cmdEntries;
2173         uint32_t cmdAddrLow;
2174         uint32_t cmdAddrHigh;
2175
2176         uint32_t rspEntries;
2177         uint32_t rspAddrLow;
2178         uint32_t rspAddrHigh;
2179 } SLI2_RDSC;
2180
2181 typedef struct _PCB {
2182 #ifdef __BIG_ENDIAN_BITFIELD
2183         uint32_t type:8;
2184 #define TYPE_NATIVE_SLI2       0x01;
2185         uint32_t feature:8;
2186 #define FEATURE_INITIAL_SLI2   0x01;
2187         uint32_t rsvd:12;
2188         uint32_t maxRing:4;
2189 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2190         uint32_t maxRing:4;
2191         uint32_t rsvd:12;
2192         uint32_t feature:8;
2193 #define FEATURE_INITIAL_SLI2   0x01;
2194         uint32_t type:8;
2195 #define TYPE_NATIVE_SLI2       0x01;
2196 #endif
2197
2198         uint32_t mailBoxSize;
2199         uint32_t mbAddrLow;
2200         uint32_t mbAddrHigh;
2201
2202         uint32_t hgpAddrLow;
2203         uint32_t hgpAddrHigh;
2204
2205         uint32_t pgpAddrLow;
2206         uint32_t pgpAddrHigh;
2207         SLI2_RDSC rdsc[MAX_RINGS];
2208 } PCB_t;
2209
2210 /* NEW_FEATURE */
2211 typedef struct {
2212 #ifdef __BIG_ENDIAN_BITFIELD
2213         uint32_t rsvd0:27;
2214         uint32_t discardFarp:1;
2215         uint32_t IPEnable:1;
2216         uint32_t nodeName:1;
2217         uint32_t portName:1;
2218         uint32_t filterEnable:1;
2219 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2220         uint32_t filterEnable:1;
2221         uint32_t portName:1;
2222         uint32_t nodeName:1;
2223         uint32_t IPEnable:1;
2224         uint32_t discardFarp:1;
2225         uint32_t rsvd:27;
2226 #endif
2227
2228         uint8_t portname[8];    /* Used to be struct lpfc_name */
2229         uint8_t nodename[8];
2230         uint32_t rsvd1;
2231         uint32_t rsvd2;
2232         uint32_t rsvd3;
2233         uint32_t IPAddress;
2234 } CONFIG_FARP_VAR;
2235
2236 /* Union of all Mailbox Command types */
2237 #define MAILBOX_CMD_WSIZE       32
2238 #define MAILBOX_CMD_SIZE        (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
2239
2240 typedef union {
2241         uint32_t varWords[MAILBOX_CMD_WSIZE - 1];
2242         LOAD_SM_VAR varLdSM;    /* cmd =  1 (LOAD_SM)        */
2243         READ_NV_VAR varRDnvp;   /* cmd =  2 (READ_NVPARMS)   */
2244         WRITE_NV_VAR varWTnvp;  /* cmd =  3 (WRITE_NVPARMS)  */
2245         BIU_DIAG_VAR varBIUdiag;        /* cmd =  4 (RUN_BIU_DIAG)   */
2246         INIT_LINK_VAR varInitLnk;       /* cmd =  5 (INIT_LINK)      */
2247         DOWN_LINK_VAR varDwnLnk;        /* cmd =  6 (DOWN_LINK)      */
2248         CONFIG_LINK varCfgLnk;  /* cmd =  7 (CONFIG_LINK)    */
2249         PART_SLIM_VAR varSlim;  /* cmd =  8 (PART_SLIM)      */
2250         CONFIG_RING_VAR varCfgRing;     /* cmd =  9 (CONFIG_RING)    */
2251         RESET_RING_VAR varRstRing;      /* cmd = 10 (RESET_RING)     */
2252         READ_CONFIG_VAR varRdConfig;    /* cmd = 11 (READ_CONFIG)    */
2253         READ_RCONF_VAR varRdRConfig;    /* cmd = 12 (READ_RCONFIG)   */
2254         READ_SPARM_VAR varRdSparm;      /* cmd = 13 (READ_SPARM(64)) */
2255         READ_STATUS_VAR varRdStatus;    /* cmd = 14 (READ_STATUS)    */
2256         READ_RPI_VAR varRdRPI;  /* cmd = 15 (READ_RPI(64))   */
2257         READ_XRI_VAR varRdXRI;  /* cmd = 16 (READ_XRI)       */
2258         READ_REV_VAR varRdRev;  /* cmd = 17 (READ_REV)       */
2259         READ_LNK_VAR varRdLnk;  /* cmd = 18 (READ_LNK_STAT)  */
2260         REG_LOGIN_VAR varRegLogin;      /* cmd = 19 (REG_LOGIN(64))  */
2261         UNREG_LOGIN_VAR varUnregLogin;  /* cmd = 20 (UNREG_LOGIN)    */
2262         READ_LA_VAR varReadLA;  /* cmd = 21 (READ_LA(64))    */
2263         CLEAR_LA_VAR varClearLA;        /* cmd = 22 (CLEAR_LA)       */
2264         DUMP_VAR varDmp;        /* Warm Start DUMP mbx cmd   */
2265         UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID)   */
2266         CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)  NEW_FEATURE */
2267         CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT)  */
2268 } MAILVARIANTS;
2269
2270 /*
2271  * SLI-2 specific structures
2272  */
2273
2274 struct lpfc_hgp {
2275         __le32 cmdPutInx;
2276         __le32 rspGetInx;
2277 };
2278
2279 struct lpfc_pgp {
2280         __le32 cmdGetInx;
2281         __le32 rspPutInx;
2282 };
2283
2284 typedef struct _SLI2_DESC {
2285         struct lpfc_hgp host[MAX_RINGS];
2286         uint32_t unused1[16];
2287         struct lpfc_pgp port[MAX_RINGS];
2288 } SLI2_DESC;
2289
2290 typedef union {
2291         SLI2_DESC s2;
2292 } SLI_VAR;
2293
2294 typedef struct {
2295 #ifdef __BIG_ENDIAN_BITFIELD
2296         uint16_t mbxStatus;
2297         uint8_t mbxCommand;
2298         uint8_t mbxReserved:6;
2299         uint8_t mbxHc:1;
2300         uint8_t mbxOwner:1;     /* Low order bit first word */
2301 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2302         uint8_t mbxOwner:1;     /* Low order bit first word */
2303         uint8_t mbxHc:1;
2304         uint8_t mbxReserved:6;
2305         uint8_t mbxCommand;
2306         uint16_t mbxStatus;
2307 #endif
2308
2309         MAILVARIANTS un;
2310         SLI_VAR us;
2311 } MAILBOX_t;
2312
2313 /*
2314  *    Begin Structure Definitions for IOCB Commands
2315  */
2316
2317 typedef struct {
2318 #ifdef __BIG_ENDIAN_BITFIELD
2319         uint8_t statAction;
2320         uint8_t statRsn;
2321         uint8_t statBaExp;
2322         uint8_t statLocalError;
2323 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2324         uint8_t statLocalError;
2325         uint8_t statBaExp;
2326         uint8_t statRsn;
2327         uint8_t statAction;
2328 #endif
2329         /* statRsn  P/F_RJT reason codes */
2330 #define RJT_BAD_D_ID       0x01 /* Invalid D_ID field */
2331 #define RJT_BAD_S_ID       0x02 /* Invalid S_ID field */
2332 #define RJT_UNAVAIL_TEMP   0x03 /* N_Port unavailable temp. */
2333 #define RJT_UNAVAIL_PERM   0x04 /* N_Port unavailable perm. */
2334 #define RJT_UNSUP_CLASS    0x05 /* Class not supported */
2335 #define RJT_DELIM_ERR      0x06 /* Delimiter usage error */
2336 #define RJT_UNSUP_TYPE     0x07 /* Type not supported */
2337 #define RJT_BAD_CONTROL    0x08 /* Invalid link conrtol */
2338 #define RJT_BAD_RCTL       0x09 /* R_CTL invalid */
2339 #define RJT_BAD_FCTL       0x0A /* F_CTL invalid */
2340 #define RJT_BAD_OXID       0x0B /* OX_ID invalid */
2341 #define RJT_BAD_RXID       0x0C /* RX_ID invalid */
2342 #define RJT_BAD_SEQID      0x0D /* SEQ_ID invalid */
2343 #define RJT_BAD_DFCTL      0x0E /* DF_CTL invalid */
2344 #define RJT_BAD_SEQCNT     0x0F /* SEQ_CNT invalid */
2345 #define RJT_BAD_PARM       0x10 /* Param. field invalid */
2346 #define RJT_XCHG_ERR       0x11 /* Exchange error */
2347 #define RJT_PROT_ERR       0x12 /* Protocol error */
2348 #define RJT_BAD_LENGTH     0x13 /* Invalid Length */
2349 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
2350 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
2351 #define RJT_TOO_MANY_SEQ   0x17 /* Excessive sequences */
2352 #define RJT_XCHG_NOT_STRT  0x18 /* Exchange not started */
2353 #define RJT_UNSUP_SEC_HDR  0x19 /* Security hdr not supported */
2354 #define RJT_UNAVAIL_PATH   0x1A /* Fabric Path not available */
2355 #define RJT_VENDOR_UNIQUE  0xFF /* Vendor unique error */
2356
2357 #define IOERR_SUCCESS                 0x00      /* statLocalError */
2358 #define IOERR_MISSING_CONTINUE        0x01
2359 #define IOERR_SEQUENCE_TIMEOUT        0x02
2360 #define IOERR_INTERNAL_ERROR          0x03
2361 #define IOERR_INVALID_RPI             0x04
2362 #define IOERR_NO_XRI                  0x05
2363 #define IOERR_ILLEGAL_COMMAND         0x06
2364 #define IOERR_XCHG_DROPPED            0x07
2365 #define IOERR_ILLEGAL_FIELD           0x08
2366 #define IOERR_BAD_CONTINUE            0x09
2367 #define IOERR_TOO_MANY_BUFFERS        0x0A
2368 #define IOERR_RCV_BUFFER_WAITING      0x0B
2369 #define IOERR_NO_CONNECTION           0x0C
2370 #define IOERR_TX_DMA_FAILED           0x0D
2371 #define IOERR_RX_DMA_FAILED           0x0E
2372 #define IOERR_ILLEGAL_FRAME           0x0F
2373 #define IOERR_EXTRA_DATA              0x10
2374 #define IOERR_NO_RESOURCES            0x11
2375 #define IOERR_RESERVED                0x12
2376 #define IOERR_ILLEGAL_LENGTH          0x13
2377 #define IOERR_UNSUPPORTED_FEATURE     0x14
2378 #define IOERR_ABORT_IN_PROGRESS       0x15
2379 #define IOERR_ABORT_REQUESTED         0x16
2380 #define IOERR_RECEIVE_BUFFER_TIMEOUT  0x17
2381 #define IOERR_LOOP_OPEN_FAILURE       0x18
2382 #define IOERR_RING_RESET              0x19
2383 #define IOERR_LINK_DOWN               0x1A
2384 #define IOERR_CORRUPTED_DATA          0x1B
2385 #define IOERR_CORRUPTED_RPI           0x1C
2386 #define IOERR_OUT_OF_ORDER_DATA       0x1D
2387 #define IOERR_OUT_OF_ORDER_ACK        0x1E
2388 #define IOERR_DUP_FRAME               0x1F
2389 #define IOERR_LINK_CONTROL_FRAME      0x20      /* ACK_N received */
2390 #define IOERR_BAD_HOST_ADDRESS        0x21
2391 #define IOERR_RCV_HDRBUF_WAITING      0x22
2392 #define IOERR_MISSING_HDR_BUFFER      0x23
2393 #define IOERR_MSEQ_CHAIN_CORRUPTED    0x24
2394 #define IOERR_ABORTMULT_REQUESTED     0x25
2395 #define IOERR_BUFFER_SHORTAGE         0x28
2396 #define IOERR_DEFAULT                 0x29
2397 #define IOERR_CNT                     0x2A
2398
2399 #define IOERR_DRVR_MASK               0x100
2400 #define IOERR_SLI_DOWN                0x101  /* ulpStatus  - Driver defined */
2401 #define IOERR_SLI_BRESET              0x102
2402 #define IOERR_SLI_ABORTED             0x103
2403 } PARM_ERR;
2404
2405 typedef union {
2406         struct {
2407 #ifdef __BIG_ENDIAN_BITFIELD
2408                 uint8_t Rctl;   /* R_CTL field */
2409                 uint8_t Type;   /* TYPE field */
2410                 uint8_t Dfctl;  /* DF_CTL field */
2411                 uint8_t Fctl;   /* Bits 0-7 of IOCB word 5 */
2412 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2413                 uint8_t Fctl;   /* Bits 0-7 of IOCB word 5 */
2414                 uint8_t Dfctl;  /* DF_CTL field */
2415                 uint8_t Type;   /* TYPE field */
2416                 uint8_t Rctl;   /* R_CTL field */
2417 #endif
2418
2419 #define BC      0x02            /* Broadcast Received  - Fctl */
2420 #define SI      0x04            /* Sequence Initiative */
2421 #define LA      0x08            /* Ignore Link Attention state */
2422 #define LS      0x80            /* Last Sequence */
2423         } hcsw;
2424         uint32_t reserved;
2425 } WORD5;
2426
2427 /* IOCB Command template for a generic response */
2428 typedef struct {
2429         uint32_t reserved[4];
2430         PARM_ERR perr;
2431 } GENERIC_RSP;
2432
2433 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
2434 typedef struct {
2435         struct ulp_bde xrsqbde[2];
2436         uint32_t xrsqRo;        /* Starting Relative Offset */
2437         WORD5 w5;               /* Header control/status word */
2438 } XR_SEQ_FIELDS;
2439
2440 /* IOCB Command template for ELS_REQUEST */
2441 typedef struct {
2442         struct ulp_bde elsReq;
2443         struct ulp_bde elsRsp;
2444
2445 #ifdef __BIG_ENDIAN_BITFIELD
2446         uint32_t word4Rsvd:7;
2447         uint32_t fl:1;
2448         uint32_t myID:24;
2449         uint32_t word5Rsvd:8;
2450         uint32_t remoteID:24;
2451 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2452         uint32_t myID:24;
2453         uint32_t fl:1;
2454         uint32_t word4Rsvd:7;
2455         uint32_t remoteID:24;
2456         uint32_t word5Rsvd:8;
2457 #endif
2458 } ELS_REQUEST;
2459
2460 /* IOCB Command template for RCV_ELS_REQ */
2461 typedef struct {
2462         struct ulp_bde elsReq[2];
2463         uint32_t parmRo;
2464
2465 #ifdef __BIG_ENDIAN_BITFIELD
2466         uint32_t word5Rsvd:8;
2467         uint32_t remoteID:24;
2468 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2469         uint32_t remoteID:24;
2470         uint32_t word5Rsvd:8;
2471 #endif
2472 } RCV_ELS_REQ;
2473
2474 /* IOCB Command template for ABORT / CLOSE_XRI */
2475 typedef struct {
2476         uint32_t rsvd[3];
2477         uint32_t abortType;
2478 #define ABORT_TYPE_ABTX  0x00000000
2479 #define ABORT_TYPE_ABTS  0x00000001
2480         uint32_t parm;
2481 #ifdef __BIG_ENDIAN_BITFIELD
2482         uint16_t abortContextTag; /* ulpContext from command to abort/close */
2483         uint16_t abortIoTag;    /* ulpIoTag from command to abort/close */
2484 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2485         uint16_t abortIoTag;    /* ulpIoTag from command to abort/close */
2486         uint16_t abortContextTag; /* ulpContext from command to abort/close */
2487 #endif
2488 } AC_XRI;
2489
2490 /* IOCB Command template for ABORT_MXRI64 */
2491 typedef struct {
2492         uint32_t rsvd[3];
2493         uint32_t abortType;
2494         uint32_t parm;
2495         uint32_t iotag32;
2496 } A_MXRI64;
2497
2498 /* IOCB Command template for GET_RPI */
2499 typedef struct {
2500         uint32_t rsvd[4];
2501         uint32_t parmRo;
2502 #ifdef __BIG_ENDIAN_BITFIELD
2503         uint32_t word5Rsvd:8;
2504         uint32_t remoteID:24;
2505 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2506         uint32_t remoteID:24;
2507         uint32_t word5Rsvd:8;
2508 #endif
2509 } GET_RPI;
2510
2511 /* IOCB Command template for all FCP Initiator commands */
2512 typedef struct {
2513         struct ulp_bde fcpi_cmnd;       /* FCP_CMND payload descriptor */
2514         struct ulp_bde fcpi_rsp;        /* Rcv buffer */
2515         uint32_t fcpi_parm;
2516         uint32_t fcpi_XRdy;     /* transfer ready for IWRITE */
2517 } FCPI_FIELDS;
2518
2519 /* IOCB Command template for all FCP Target commands */
2520 typedef struct {
2521         struct ulp_bde fcpt_Buffer[2];  /* FCP_CMND payload descriptor */
2522         uint32_t fcpt_Offset;
2523         uint32_t fcpt_Length;   /* transfer ready for IWRITE */
2524 } FCPT_FIELDS;
2525
2526 /* SLI-2 IOCB structure definitions */
2527
2528 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
2529 typedef struct {
2530         ULP_BDL bdl;
2531         uint32_t xrsqRo;        /* Starting Relative Offset */
2532         WORD5 w5;               /* Header control/status word */
2533 } XMT_SEQ_FIELDS64;
2534
2535 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
2536 typedef struct {
2537         struct ulp_bde64 rcvBde;
2538         uint32_t rsvd1;
2539         uint32_t xrsqRo;        /* Starting Relative Offset */
2540         WORD5 w5;               /* Header control/status word */
2541 } RCV_SEQ_FIELDS64;
2542
2543 /* IOCB Command template for ELS_REQUEST64 */
2544 typedef struct {
2545         ULP_BDL bdl;
2546 #ifdef __BIG_ENDIAN_BITFIELD
2547         uint32_t word4Rsvd:7;
2548         uint32_t fl:1;
2549         uint32_t myID:24;
2550         uint32_t word5Rsvd:8;
2551         uint32_t remoteID:24;
2552 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2553         uint32_t myID:24;
2554         uint32_t fl:1;
2555         uint32_t word4Rsvd:7;
2556         uint32_t remoteID:24;
2557         uint32_t word5Rsvd:8;
2558 #endif
2559 } ELS_REQUEST64;
2560
2561 /* IOCB Command template for GEN_REQUEST64 */
2562 typedef struct {
2563         ULP_BDL bdl;
2564         uint32_t xrsqRo;        /* Starting Relative Offset */
2565         WORD5 w5;               /* Header control/status word */
2566 } GEN_REQUEST64;
2567
2568 /* IOCB Command template for RCV_ELS_REQ64 */
2569 typedef struct {
2570         struct ulp_bde64 elsReq;
2571         uint32_t rcvd1;
2572         uint32_t parmRo;
2573
2574 #ifdef __BIG_ENDIAN_BITFIELD
2575         uint32_t word5Rsvd:8;
2576         uint32_t remoteID:24;
2577 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2578         uint32_t remoteID:24;
2579         uint32_t word5Rsvd:8;
2580 #endif
2581 } RCV_ELS_REQ64;
2582
2583 /* IOCB Command template for all 64 bit FCP Initiator commands */
2584 typedef struct {
2585         ULP_BDL bdl;
2586         uint32_t fcpi_parm;
2587         uint32_t fcpi_XRdy;     /* transfer ready for IWRITE */
2588 } FCPI_FIELDS64;
2589
2590 /* IOCB Command template for all 64 bit FCP Target commands */
2591 typedef struct {
2592         ULP_BDL bdl;
2593         uint32_t fcpt_Offset;
2594         uint32_t fcpt_Length;   /* transfer ready for IWRITE */
2595 } FCPT_FIELDS64;
2596
2597 typedef struct _IOCB {  /* IOCB structure */
2598         union {
2599                 GENERIC_RSP grsp;       /* Generic response */
2600                 XR_SEQ_FIELDS xrseq;    /* XMIT / BCAST / RCV_SEQUENCE cmd */
2601                 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
2602                 RCV_ELS_REQ rcvels;     /* RCV_ELS_REQ template */
2603                 AC_XRI acxri;   /* ABORT / CLOSE_XRI template */
2604                 A_MXRI64 amxri; /* abort multiple xri command overlay */
2605                 GET_RPI getrpi; /* GET_RPI template */
2606                 FCPI_FIELDS fcpi;       /* FCP Initiator template */
2607                 FCPT_FIELDS fcpt;       /* FCP target template */
2608
2609                 /* SLI-2 structures */
2610
2611                 struct ulp_bde64 cont64[2];     /* up to 2 64 bit continuation
2612                                            bde_64s */
2613                 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
2614                 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
2615                 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
2616                 XMT_SEQ_FIELDS64 xseq64;        /* XMIT / BCAST cmd */
2617                 FCPI_FIELDS64 fcpi64;   /* FCP 64 bit Initiator template */
2618                 FCPT_FIELDS64 fcpt64;   /* FCP 64 bit target template */
2619
2620                 uint32_t ulpWord[IOCB_WORD_SZ - 2];     /* generic 6 'words' */
2621         } un;
2622         union {
2623                 struct {
2624 #ifdef __BIG_ENDIAN_BITFIELD
2625                         uint16_t ulpContext;    /* High order bits word 6 */
2626                         uint16_t ulpIoTag;      /* Low  order bits word 6 */
2627 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2628                         uint16_t ulpIoTag;      /* Low  order bits word 6 */
2629                         uint16_t ulpContext;    /* High order bits word 6 */
2630 #endif
2631                 } t1;
2632                 struct {
2633 #ifdef __BIG_ENDIAN_BITFIELD
2634                         uint16_t ulpContext;    /* High order bits word 6 */
2635                         uint16_t ulpIoTag1:2;   /* Low  order bits word 6 */
2636                         uint16_t ulpIoTag0:14;  /* Low  order bits word 6 */
2637 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2638                         uint16_t ulpIoTag0:14;  /* Low  order bits word 6 */
2639                         uint16_t ulpIoTag1:2;   /* Low  order bits word 6 */
2640                         uint16_t ulpContext;    /* High order bits word 6 */
2641 #endif
2642                 } t2;
2643         } un1;
2644 #define ulpContext un1.t1.ulpContext
2645 #define ulpIoTag   un1.t1.ulpIoTag
2646 #define ulpIoTag0  un1.t2.ulpIoTag0
2647
2648 #ifdef __BIG_ENDIAN_BITFIELD
2649         uint32_t ulpTimeout:8;
2650         uint32_t ulpXS:1;
2651         uint32_t ulpFCP2Rcvy:1;
2652         uint32_t ulpPU:2;
2653         uint32_t ulpIr:1;
2654         uint32_t ulpClass:3;
2655         uint32_t ulpCommand:8;
2656         uint32_t ulpStatus:4;
2657         uint32_t ulpBdeCount:2;
2658         uint32_t ulpLe:1;
2659         uint32_t ulpOwner:1;    /* Low order bit word 7 */
2660 #else   /*  __LITTLE_ENDIAN_BITFIELD */
2661         uint32_t ulpOwner:1;    /* Low order bit word 7 */
2662         uint32_t ulpLe:1;
2663         uint32_t ulpBdeCount:2;
2664         uint32_t ulpStatus:4;
2665         uint32_t ulpCommand:8;
2666         uint32_t ulpClass:3;
2667         uint32_t ulpIr:1;
2668         uint32_t ulpPU:2;
2669         uint32_t ulpFCP2Rcvy:1;
2670         uint32_t ulpXS:1;
2671         uint32_t ulpTimeout:8;
2672 #endif
2673
2674 #define PARM_UNUSED        0    /* PU field (Word 4) not used */
2675 #define PARM_REL_OFF       1    /* PU field (Word 4) = R. O. */
2676 #define PARM_READ_CHECK    2    /* PU field (Word 4) = Data Transfer Length */
2677 #define CLASS1             0    /* Class 1 */
2678 #define CLASS2             1    /* Class 2 */
2679 #define CLASS3             2    /* Class 3 */
2680 #define CLASS_FCP_INTERMIX 7    /* FCP Data->Cls 1, all else->Cls 2 */
2681
2682 #define IOSTAT_SUCCESS         0x0      /* ulpStatus  - HBA defined */
2683 #define IOSTAT_FCP_RSP_ERROR   0x1
2684 #define IOSTAT_REMOTE_STOP     0x2
2685 #define IOSTAT_LOCAL_REJECT    0x3
2686 #define IOSTAT_NPORT_RJT       0x4
2687 #define IOSTAT_FABRIC_RJT      0x5
2688 #define IOSTAT_NPORT_BSY       0x6
2689 #define IOSTAT_FABRIC_BSY      0x7
2690 #define IOSTAT_INTERMED_RSP    0x8
2691 #define IOSTAT_LS_RJT          0x9
2692 #define IOSTAT_BA_RJT          0xA
2693 #define IOSTAT_RSVD1           0xB
2694 #define IOSTAT_RSVD2           0xC
2695 #define IOSTAT_RSVD3           0xD
2696 #define IOSTAT_RSVD4           0xE
2697 #define IOSTAT_RSVD5           0xF
2698 #define IOSTAT_DRIVER_REJECT   0x10   /* ulpStatus  - Driver defined */
2699 #define IOSTAT_DEFAULT         0xF    /* Same as rsvd5 for now */
2700 #define IOSTAT_CNT             0x11
2701
2702 } IOCB_t;
2703
2704
2705 #define SLI1_SLIM_SIZE   (4 * 1024)
2706
2707 /* Up to 498 IOCBs will fit into 16k
2708  * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
2709  */
2710 #define SLI2_SLIM_SIZE   (16 * 1024)
2711
2712 /* Maximum IOCBs that will fit in SLI2 slim */
2713 #define MAX_SLI2_IOCB    498
2714
2715 struct lpfc_sli2_slim {
2716         MAILBOX_t mbx;
2717         PCB_t pcb;
2718         IOCB_t IOCBs[MAX_SLI2_IOCB];
2719 };
2720
2721 /*******************************************************************
2722 This macro check PCI device to allow special handling for LC HBAs.
2723
2724 Parameters:
2725 device : struct pci_dev 's device field
2726
2727 return 1 => TRUE
2728        0 => FALSE
2729  *******************************************************************/
2730 static inline int
2731 lpfc_is_LC_HBA(unsigned short device)
2732 {
2733         if ((device == PCI_DEVICE_ID_TFLY) ||
2734             (device == PCI_DEVICE_ID_PFLY) ||
2735             (device == PCI_DEVICE_ID_LP101) ||
2736             (device == PCI_DEVICE_ID_BMID) ||
2737             (device == PCI_DEVICE_ID_BSMB) ||
2738             (device == PCI_DEVICE_ID_ZMID) ||
2739             (device == PCI_DEVICE_ID_ZSMB) ||
2740             (device == PCI_DEVICE_ID_RFLY))
2741                 return 1;
2742         else
2743                 return 0;
2744 }