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Build fixes for struct pt_regs removal
[linux-2.6/x86.git] / drivers / net / typhoon.c
blob3bf9e630404f85283a08cca2e0e42cfcabf190f3
1 /* typhoon.c: A Linux Ethernet device driver for 3Com 3CR990 family of NICs */
2 /*
3 Written 2002-2004 by David Dillow <dave@thedillows.org>
4 Based on code written 1998-2000 by Donald Becker <becker@scyld.com> and
5 Linux 2.2.x driver by David P. McLean <davidpmclean@yahoo.com>.
6
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
13
14 This software is available on a public web site. It may enable
15 cryptographic capabilities of the 3Com hardware, and may be
16 exported from the United States under License Exception "TSU"
17 pursuant to 15 C.F.R. Section 740.13(e).
18
19 This work was funded by the National Library of Medicine under
20 the Department of Energy project number 0274DD06D1 and NLM project
21 number Y1-LM-2015-01.
22
23 This driver is designed for the 3Com 3CR990 Family of cards with the
24 3XP Processor. It has been tested on x86 and sparc64.
25
26 KNOWN ISSUES:
27 *) The current firmware always strips the VLAN tag off, even if
28 we tell it not to. You should filter VLANs at the switch
29 as a workaround (good practice in any event) until we can
30 get this fixed.
31 *) Cannot DMA Rx packets to a 2 byte aligned address. Also firmware
32 issue. Hopefully 3Com will fix it.
33 *) Waiting for a command response takes 8ms due to non-preemptable
34 polling. Only significant for getting stats and creating
35 SAs, but an ugly wart never the less.
36
37 TODO:
38 *) Doesn't do IPSEC offloading. Yet. Keep yer pants on, it's coming.
39 *) Add more support for ethtool (especially for NIC stats)
40 *) Allow disabling of RX checksum offloading
41 *) Fix MAC changing to work while the interface is up
42 (Need to put commands on the TX ring, which changes
43 the locking)
44 *) Add in FCS to {rx,tx}_bytes, since the hardware doesn't. See
45 http://oss.sgi.com/cgi-bin/mesg.cgi?a=netdev&i=20031215152211.7003fe8e.rddunlap%40osdl.org
46 */
47
48 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
49 * Setting to > 1518 effectively disables this feature.
50 */
51 static int rx_copybreak = 200;
52
53 /* Should we use MMIO or Port IO?
54 * 0: Port IO
55 * 1: MMIO
56 * 2: Try MMIO, fallback to Port IO
57 */
58 static unsigned int use_mmio = 2;
59
60 /* end user-configurable values */
61
62 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
63 */
64 static const int multicast_filter_limit = 32;
65
66 /* Operational parameters that are set at compile time. */
67
68 /* Keep the ring sizes a power of two for compile efficiency.
69 * The compiler will convert <unsigned>'%'<2^N> into a bit mask.
70 * Making the Tx ring too large decreases the effectiveness of channel
71 * bonding and packet priority.
72 * There are no ill effects from too-large receive rings.
73 *
74 * We don't currently use the Hi Tx ring so, don't make it very big.
75 *
76 * Beware that if we start using the Hi Tx ring, we will need to change
77 * typhoon_num_free_tx() and typhoon_tx_complete() to account for that.
78 */
79 #define TXHI_ENTRIES 2
80 #define TXLO_ENTRIES 128
81 #define RX_ENTRIES 32
82 #define COMMAND_ENTRIES 16
83 #define RESPONSE_ENTRIES 32
84
85 #define COMMAND_RING_SIZE (COMMAND_ENTRIES * sizeof(struct cmd_desc))
86 #define RESPONSE_RING_SIZE (RESPONSE_ENTRIES * sizeof(struct resp_desc))
87
88 /* The 3XP will preload and remove 64 entries from the free buffer
89 * list, and we need one entry to keep the ring from wrapping, so
90 * to keep this a power of two, we use 128 entries.
91 */
92 #define RXFREE_ENTRIES 128
93 #define RXENT_ENTRIES (RXFREE_ENTRIES - 1)
94
95 /* Operational parameters that usually are not changed. */
96
97 /* Time in jiffies before concluding the transmitter is hung. */
98 #define TX_TIMEOUT (2*HZ)
99
100 #define PKT_BUF_SZ 1536
101
102 #define DRV_MODULE_NAME "typhoon"
103 #define DRV_MODULE_VERSION "1.5.8"
104 #define DRV_MODULE_RELDATE "06/11/09"
105 #define PFX DRV_MODULE_NAME ": "
106 #define ERR_PFX KERN_ERR PFX
107
108 #include <linux/module.h>
109 #include <linux/kernel.h>
110 #include <linux/string.h>
111 #include <linux/timer.h>
112 #include <linux/errno.h>
113 #include <linux/ioport.h>
114 #include <linux/slab.h>
115 #include <linux/interrupt.h>
116 #include <linux/pci.h>
117 #include <linux/netdevice.h>
118 #include <linux/etherdevice.h>
119 #include <linux/skbuff.h>
120 #include <linux/init.h>
121 #include <linux/delay.h>
122 #include <linux/ethtool.h>
123 #include <linux/if_vlan.h>
124 #include <linux/crc32.h>
125 #include <linux/bitops.h>
126 #include <asm/processor.h>
127 #include <asm/io.h>
128 #include <asm/uaccess.h>
129 #include <linux/in6.h>
130 #include <asm/checksum.h>
131 #include <linux/version.h>
132 #include <linux/dma-mapping.h>
133
134 #include "typhoon.h"
135 #include "typhoon-firmware.h"
136
137 static const char version[] __devinitdata =
138 "typhoon.c: version " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
139
140 MODULE_AUTHOR("David Dillow <dave@thedillows.org>");
141 MODULE_VERSION(DRV_MODULE_VERSION);
142 MODULE_LICENSE("GPL");
143 MODULE_DESCRIPTION("3Com Typhoon Family (3C990, 3CR990, and variants)");
144 MODULE_PARM_DESC(rx_copybreak, "Packets smaller than this are copied and "
145 "the buffer given back to the NIC. Default "
146 "is 200.");
147 MODULE_PARM_DESC(use_mmio, "Use MMIO (1) or PIO(0) to access the NIC. "
148 "Default is to try MMIO and fallback to PIO.");
149 module_param(rx_copybreak, int, 0);
150 module_param(use_mmio, int, 0);
151
152 #if defined(NETIF_F_TSO) && MAX_SKB_FRAGS > 32
153 #warning Typhoon only supports 32 entries in its SG list for TSO, disabling TSO
154 #undef NETIF_F_TSO
155 #endif
156
157 #if TXLO_ENTRIES <= (2 * MAX_SKB_FRAGS)
158 #error TX ring too small!
159 #endif
160
161 struct typhoon_card_info {
162 char *name;
163 int capabilities;
164 };
165
166 #define TYPHOON_CRYPTO_NONE 0x00
167 #define TYPHOON_CRYPTO_DES 0x01
168 #define TYPHOON_CRYPTO_3DES 0x02
169 #define TYPHOON_CRYPTO_VARIABLE 0x04
170 #define TYPHOON_FIBER 0x08
171 #define TYPHOON_WAKEUP_NEEDS_RESET 0x10
172
173 enum typhoon_cards {
174 TYPHOON_TX = 0, TYPHOON_TX95, TYPHOON_TX97, TYPHOON_SVR,
175 TYPHOON_SVR95, TYPHOON_SVR97, TYPHOON_TXM, TYPHOON_BSVR,
176 TYPHOON_FX95, TYPHOON_FX97, TYPHOON_FX95SVR, TYPHOON_FX97SVR,
177 TYPHOON_FXM,
178 };
179
180 /* directly indexed by enum typhoon_cards, above */
181 static const struct typhoon_card_info typhoon_card_info[] __devinitdata = {
182 { "3Com Typhoon (3C990-TX)",
183 TYPHOON_CRYPTO_NONE},
184 { "3Com Typhoon (3CR990-TX-95)",
185 TYPHOON_CRYPTO_DES},
186 { "3Com Typhoon (3CR990-TX-97)",
187 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
188 { "3Com Typhoon (3C990SVR)",
189 TYPHOON_CRYPTO_NONE},
190 { "3Com Typhoon (3CR990SVR95)",
191 TYPHOON_CRYPTO_DES},
192 { "3Com Typhoon (3CR990SVR97)",
193 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
194 { "3Com Typhoon2 (3C990B-TX-M)",
195 TYPHOON_CRYPTO_VARIABLE},
196 { "3Com Typhoon2 (3C990BSVR)",
197 TYPHOON_CRYPTO_VARIABLE},
198 { "3Com Typhoon (3CR990-FX-95)",
199 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
200 { "3Com Typhoon (3CR990-FX-97)",
201 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
202 { "3Com Typhoon (3CR990-FX-95 Server)",
203 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
204 { "3Com Typhoon (3CR990-FX-97 Server)",
205 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
206 { "3Com Typhoon2 (3C990B-FX-97)",
207 TYPHOON_CRYPTO_VARIABLE | TYPHOON_FIBER},
208 };
209
210 /* Notes on the new subsystem numbering scheme:
211 * bits 0-1 indicate crypto capabilities: (0) variable, (1) DES, or (2) 3DES
212 * bit 4 indicates if this card has secured firmware (we don't support it)
213 * bit 8 indicates if this is a (0) copper or (1) fiber card
214 * bits 12-16 indicate card type: (0) client and (1) server
215 */
216 static struct pci_device_id typhoon_pci_tbl[] = {
217 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0,TYPHOON_TX },
219 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_95,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX95 },
221 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_97,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX97 },
223 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
224 PCI_ANY_ID, 0x1000, 0, 0, TYPHOON_TXM },
225 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
226 PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FXM },
227 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
228 PCI_ANY_ID, 0x2000, 0, 0, TYPHOON_BSVR },
229 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
230 PCI_ANY_ID, 0x1101, 0, 0, TYPHOON_FX95 },
231 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
232 PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FX97 },
233 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
234 PCI_ANY_ID, 0x2101, 0, 0, TYPHOON_FX95SVR },
235 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
236 PCI_ANY_ID, 0x2102, 0, 0, TYPHOON_FX97SVR },
237 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR95,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR95 },
239 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR97,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR97 },
241 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR },
243 { 0, }
244 };
245 MODULE_DEVICE_TABLE(pci, typhoon_pci_tbl);
246
247 /* Define the shared memory area
248 * Align everything the 3XP will normally be using.
249 * We'll need to move/align txHi if we start using that ring.
250 */
251 #define __3xp_aligned ____cacheline_aligned
252 struct typhoon_shared {
253 struct typhoon_interface iface;
254 struct typhoon_indexes indexes __3xp_aligned;
255 struct tx_desc txLo[TXLO_ENTRIES] __3xp_aligned;
256 struct rx_desc rxLo[RX_ENTRIES] __3xp_aligned;
257 struct rx_desc rxHi[RX_ENTRIES] __3xp_aligned;
258 struct cmd_desc cmd[COMMAND_ENTRIES] __3xp_aligned;
259 struct resp_desc resp[RESPONSE_ENTRIES] __3xp_aligned;
260 struct rx_free rxBuff[RXFREE_ENTRIES] __3xp_aligned;
261 u32 zeroWord;
262 struct tx_desc txHi[TXHI_ENTRIES];
263 } __attribute__ ((packed));
264
265 struct rxbuff_ent {
266 struct sk_buff *skb;
267 dma_addr_t dma_addr;
268 };
269
270 struct typhoon {
271 /* Tx cache line section */
272 struct transmit_ring txLoRing ____cacheline_aligned;
273 struct pci_dev * tx_pdev;
274 void __iomem *tx_ioaddr;
275 u32 txlo_dma_addr;
276
277 /* Irq/Rx cache line section */
278 void __iomem *ioaddr ____cacheline_aligned;
279 struct typhoon_indexes *indexes;
280 u8 awaiting_resp;
281 u8 duplex;
282 u8 speed;
283 u8 card_state;
284 struct basic_ring rxLoRing;
285 struct pci_dev * pdev;
286 struct net_device * dev;
287 spinlock_t state_lock;
288 struct vlan_group * vlgrp;
289 struct basic_ring rxHiRing;
290 struct basic_ring rxBuffRing;
291 struct rxbuff_ent rxbuffers[RXENT_ENTRIES];
292
293 /* general section */
294 spinlock_t command_lock ____cacheline_aligned;
295 struct basic_ring cmdRing;
296 struct basic_ring respRing;
297 struct net_device_stats stats;
298 struct net_device_stats stats_saved;
299 const char * name;
300 struct typhoon_shared * shared;
301 dma_addr_t shared_dma;
302 u16 xcvr_select;
303 u16 wol_events;
304 u32 offload;
305
306 /* unused stuff (future use) */
307 int capabilities;
308 struct transmit_ring txHiRing;
309 };
310
311 enum completion_wait_values {
312 NoWait = 0, WaitNoSleep, WaitSleep,
313 };
314
315 /* These are the values for the typhoon.card_state variable.
316 * These determine where the statistics will come from in get_stats().
317 * The sleep image does not support the statistics we need.
318 */
319 enum state_values {
320 Sleeping = 0, Running,
321 };
322
323 /* PCI writes are not guaranteed to be posted in order, but outstanding writes
324 * cannot pass a read, so this forces current writes to post.
325 */
326 #define typhoon_post_pci_writes(x) \
327 do { if(likely(use_mmio)) ioread32(x+TYPHOON_REG_HEARTBEAT); } while(0)
328
329 /* We'll wait up to six seconds for a reset, and half a second normally.
330 */
331 #define TYPHOON_UDELAY 50
332 #define TYPHOON_RESET_TIMEOUT_SLEEP (6 * HZ)
333 #define TYPHOON_RESET_TIMEOUT_NOSLEEP ((6 * 1000000) / TYPHOON_UDELAY)
334 #define TYPHOON_WAIT_TIMEOUT ((1000000 / 2) / TYPHOON_UDELAY)
335
336 #define typhoon_synchronize_irq(x) synchronize_irq(x)
337
338 #if defined(NETIF_F_TSO)
339 #define skb_tso_size(x) (skb_shinfo(x)->gso_size)
340 #define TSO_NUM_DESCRIPTORS 2
341 #define TSO_OFFLOAD_ON TYPHOON_OFFLOAD_TCP_SEGMENT
342 #else
343 #define NETIF_F_TSO 0
344 #define skb_tso_size(x) 0
345 #define TSO_NUM_DESCRIPTORS 0
346 #define TSO_OFFLOAD_ON 0
347 #endif
348
349 static inline void
350 typhoon_inc_index(u32 *index, const int count, const int num_entries)
351 {
352 /* Increment a ring index -- we can use this for all rings execept
353 * the Rx rings, as they use different size descriptors
354 * otherwise, everything is the same size as a cmd_desc
355 */
356 *index += count * sizeof(struct cmd_desc);
357 *index %= num_entries * sizeof(struct cmd_desc);
358 }
359
360 static inline void
361 typhoon_inc_cmd_index(u32 *index, const int count)
362 {
363 typhoon_inc_index(index, count, COMMAND_ENTRIES);
364 }
365
366 static inline void
367 typhoon_inc_resp_index(u32 *index, const int count)
368 {
369 typhoon_inc_index(index, count, RESPONSE_ENTRIES);
370 }
371
372 static inline void
373 typhoon_inc_rxfree_index(u32 *index, const int count)
374 {
375 typhoon_inc_index(index, count, RXFREE_ENTRIES);
376 }
377
378 static inline void
379 typhoon_inc_tx_index(u32 *index, const int count)
380 {
381 /* if we start using the Hi Tx ring, this needs updateing */
382 typhoon_inc_index(index, count, TXLO_ENTRIES);
383 }
384
385 static inline void
386 typhoon_inc_rx_index(u32 *index, const int count)
387 {
388 /* sizeof(struct rx_desc) != sizeof(struct cmd_desc) */
389 *index += count * sizeof(struct rx_desc);
390 *index %= RX_ENTRIES * sizeof(struct rx_desc);
391 }
392
393 static int
394 typhoon_reset(void __iomem *ioaddr, int wait_type)
395 {
396 int i, err = 0;
397 int timeout;
398
399 if(wait_type == WaitNoSleep)
400 timeout = TYPHOON_RESET_TIMEOUT_NOSLEEP;
401 else
402 timeout = TYPHOON_RESET_TIMEOUT_SLEEP;
403
404 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
405 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
406
407 iowrite32(TYPHOON_RESET_ALL, ioaddr + TYPHOON_REG_SOFT_RESET);
408 typhoon_post_pci_writes(ioaddr);
409 udelay(1);
410 iowrite32(TYPHOON_RESET_NONE, ioaddr + TYPHOON_REG_SOFT_RESET);
411
412 if(wait_type != NoWait) {
413 for(i = 0; i < timeout; i++) {
414 if(ioread32(ioaddr + TYPHOON_REG_STATUS) ==
415 TYPHOON_STATUS_WAITING_FOR_HOST)
416 goto out;
417
418 if(wait_type == WaitSleep)
419 schedule_timeout_uninterruptible(1);
420 else
421 udelay(TYPHOON_UDELAY);
422 }
423
424 err = -ETIMEDOUT;
425 }
426
427 out:
428 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
429 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
430
431 /* The 3XP seems to need a little extra time to complete the load
432 * of the sleep image before we can reliably boot it. Failure to
433 * do this occasionally results in a hung adapter after boot in
434 * typhoon_init_one() while trying to read the MAC address or
435 * putting the card to sleep. 3Com's driver waits 5ms, but
436 * that seems to be overkill. However, if we can sleep, we might
437 * as well give it that much time. Otherwise, we'll give it 500us,
438 * which should be enough (I've see it work well at 100us, but still
439 * saw occasional problems.)
440 */
441 if(wait_type == WaitSleep)
442 msleep(5);
443 else
444 udelay(500);
445 return err;
446 }
447
448 static int
449 typhoon_wait_status(void __iomem *ioaddr, u32 wait_value)
450 {
451 int i, err = 0;
452
453 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
454 if(ioread32(ioaddr + TYPHOON_REG_STATUS) == wait_value)
455 goto out;
456 udelay(TYPHOON_UDELAY);
457 }
458
459 err = -ETIMEDOUT;
460
461 out:
462 return err;
463 }
464
465 static inline void
466 typhoon_media_status(struct net_device *dev, struct resp_desc *resp)
467 {
468 if(resp->parm1 & TYPHOON_MEDIA_STAT_NO_LINK)
469 netif_carrier_off(dev);
470 else
471 netif_carrier_on(dev);
472 }
473
474 static inline void
475 typhoon_hello(struct typhoon *tp)
476 {
477 struct basic_ring *ring = &tp->cmdRing;
478 struct cmd_desc *cmd;
479
480 /* We only get a hello request if we've not sent anything to the
481 * card in a long while. If the lock is held, then we're in the
482 * process of issuing a command, so we don't need to respond.
483 */
484 if(spin_trylock(&tp->command_lock)) {
485 cmd = (struct cmd_desc *)(ring->ringBase + ring->lastWrite);
486 typhoon_inc_cmd_index(&ring->lastWrite, 1);
487
488 INIT_COMMAND_NO_RESPONSE(cmd, TYPHOON_CMD_HELLO_RESP);
489 smp_wmb();
490 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
491 spin_unlock(&tp->command_lock);
492 }
493 }
494
495 static int
496 typhoon_process_response(struct typhoon *tp, int resp_size,
497 struct resp_desc *resp_save)
498 {
499 struct typhoon_indexes *indexes = tp->indexes;
500 struct resp_desc *resp;
501 u8 *base = tp->respRing.ringBase;
502 int count, len, wrap_len;
503 u32 cleared;
504 u32 ready;
505
506 cleared = le32_to_cpu(indexes->respCleared);
507 ready = le32_to_cpu(indexes->respReady);
508 while(cleared != ready) {
509 resp = (struct resp_desc *)(base + cleared);
510 count = resp->numDesc + 1;
511 if(resp_save && resp->seqNo) {
512 if(count > resp_size) {
513 resp_save->flags = TYPHOON_RESP_ERROR;
514 goto cleanup;
515 }
516
517 wrap_len = 0;
518 len = count * sizeof(*resp);
519 if(unlikely(cleared + len > RESPONSE_RING_SIZE)) {
520 wrap_len = cleared + len - RESPONSE_RING_SIZE;
521 len = RESPONSE_RING_SIZE - cleared;
522 }
523
524 memcpy(resp_save, resp, len);
525 if(unlikely(wrap_len)) {
526 resp_save += len / sizeof(*resp);
527 memcpy(resp_save, base, wrap_len);
528 }
529
530 resp_save = NULL;
531 } else if(resp->cmd == TYPHOON_CMD_READ_MEDIA_STATUS) {
532 typhoon_media_status(tp->dev, resp);
533 } else if(resp->cmd == TYPHOON_CMD_HELLO_RESP) {
534 typhoon_hello(tp);
535 } else {
536 printk(KERN_ERR "%s: dumping unexpected response "
537 "0x%04x:%d:0x%02x:0x%04x:%08x:%08x\n",
538 tp->name, le16_to_cpu(resp->cmd),
539 resp->numDesc, resp->flags,
540 le16_to_cpu(resp->parm1),
541 le32_to_cpu(resp->parm2),
542 le32_to_cpu(resp->parm3));
543 }
544
545 cleanup:
546 typhoon_inc_resp_index(&cleared, count);
547 }
548
549 indexes->respCleared = cpu_to_le32(cleared);
550 wmb();
551 return (resp_save == NULL);
552 }
553
554 static inline int
555 typhoon_num_free(int lastWrite, int lastRead, int ringSize)
556 {
557 /* this works for all descriptors but rx_desc, as they are a
558 * different size than the cmd_desc -- everyone else is the same
559 */
560 lastWrite /= sizeof(struct cmd_desc);
561 lastRead /= sizeof(struct cmd_desc);
562 return (ringSize + lastRead - lastWrite - 1) % ringSize;
563 }
564
565 static inline int
566 typhoon_num_free_cmd(struct typhoon *tp)
567 {
568 int lastWrite = tp->cmdRing.lastWrite;
569 int cmdCleared = le32_to_cpu(tp->indexes->cmdCleared);
570
571 return typhoon_num_free(lastWrite, cmdCleared, COMMAND_ENTRIES);
572 }
573
574 static inline int
575 typhoon_num_free_resp(struct typhoon *tp)
576 {
577 int respReady = le32_to_cpu(tp->indexes->respReady);
578 int respCleared = le32_to_cpu(tp->indexes->respCleared);
579
580 return typhoon_num_free(respReady, respCleared, RESPONSE_ENTRIES);
581 }
582
583 static inline int
584 typhoon_num_free_tx(struct transmit_ring *ring)
585 {
586 /* if we start using the Hi Tx ring, this needs updating */
587 return typhoon_num_free(ring->lastWrite, ring->lastRead, TXLO_ENTRIES);
588 }
589
590 static int
591 typhoon_issue_command(struct typhoon *tp, int num_cmd, struct cmd_desc *cmd,
592 int num_resp, struct resp_desc *resp)
593 {
594 struct typhoon_indexes *indexes = tp->indexes;
595 struct basic_ring *ring = &tp->cmdRing;
596 struct resp_desc local_resp;
597 int i, err = 0;
598 int got_resp;
599 int freeCmd, freeResp;
600 int len, wrap_len;
601
602 spin_lock(&tp->command_lock);
603
604 freeCmd = typhoon_num_free_cmd(tp);
605 freeResp = typhoon_num_free_resp(tp);
606
607 if(freeCmd < num_cmd || freeResp < num_resp) {
608 printk("%s: no descs for cmd, had (needed) %d (%d) cmd, "
609 "%d (%d) resp\n", tp->name, freeCmd, num_cmd,
610 freeResp, num_resp);
611 err = -ENOMEM;
612 goto out;
613 }
614
615 if(cmd->flags & TYPHOON_CMD_RESPOND) {
616 /* If we're expecting a response, but the caller hasn't given
617 * us a place to put it, we'll provide one.
618 */
619 tp->awaiting_resp = 1;
620 if(resp == NULL) {
621 resp = &local_resp;
622 num_resp = 1;
623 }
624 }
625
626 wrap_len = 0;
627 len = num_cmd * sizeof(*cmd);
628 if(unlikely(ring->lastWrite + len > COMMAND_RING_SIZE)) {
629 wrap_len = ring->lastWrite + len - COMMAND_RING_SIZE;
630 len = COMMAND_RING_SIZE - ring->lastWrite;
631 }
632
633 memcpy(ring->ringBase + ring->lastWrite, cmd, len);
634 if(unlikely(wrap_len)) {
635 struct cmd_desc *wrap_ptr = cmd;
636 wrap_ptr += len / sizeof(*cmd);
637 memcpy(ring->ringBase, wrap_ptr, wrap_len);
638 }
639
640 typhoon_inc_cmd_index(&ring->lastWrite, num_cmd);
641
642 /* "I feel a presence... another warrior is on the the mesa."
643 */
644 wmb();
645 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
646 typhoon_post_pci_writes(tp->ioaddr);
647
648 if((cmd->flags & TYPHOON_CMD_RESPOND) == 0)
649 goto out;
650
651 /* Ugh. We'll be here about 8ms, spinning our thumbs, unable to
652 * preempt or do anything other than take interrupts. So, don't
653 * wait for a response unless you have to.
654 *
655 * I've thought about trying to sleep here, but we're called
656 * from many contexts that don't allow that. Also, given the way
657 * 3Com has implemented irq coalescing, we would likely timeout --
658 * this has been observed in real life!
659 *
660 * The big killer is we have to wait to get stats from the card,
661 * though we could go to a periodic refresh of those if we don't
662 * mind them getting somewhat stale. The rest of the waiting
663 * commands occur during open/close/suspend/resume, so they aren't
664 * time critical. Creating SAs in the future will also have to
665 * wait here.
666 */
667 got_resp = 0;
668 for(i = 0; i < TYPHOON_WAIT_TIMEOUT && !got_resp; i++) {
669 if(indexes->respCleared != indexes->respReady)
670 got_resp = typhoon_process_response(tp, num_resp,
671 resp);
672 udelay(TYPHOON_UDELAY);
673 }
674
675 if(!got_resp) {
676 err = -ETIMEDOUT;
677 goto out;
678 }
679
680 /* Collect the error response even if we don't care about the
681 * rest of the response
682 */
683 if(resp->flags & TYPHOON_RESP_ERROR)
684 err = -EIO;
685
686 out:
687 if(tp->awaiting_resp) {
688 tp->awaiting_resp = 0;
689 smp_wmb();
690
691 /* Ugh. If a response was added to the ring between
692 * the call to typhoon_process_response() and the clearing
693 * of tp->awaiting_resp, we could have missed the interrupt
694 * and it could hang in the ring an indeterminate amount of
695 * time. So, check for it, and interrupt ourselves if this
696 * is the case.
697 */
698 if(indexes->respCleared != indexes->respReady)
699 iowrite32(1, tp->ioaddr + TYPHOON_REG_SELF_INTERRUPT);
700 }
701
702 spin_unlock(&tp->command_lock);
703 return err;
704 }
705
706 static void
707 typhoon_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
708 {
709 struct typhoon *tp = netdev_priv(dev);
710 struct cmd_desc xp_cmd;
711 int err;
712
713 spin_lock_bh(&tp->state_lock);
714 if(!tp->vlgrp != !grp) {
715 /* We've either been turned on for the first time, or we've
716 * been turned off. Update the 3XP.
717 */
718 if(grp)
719 tp->offload |= TYPHOON_OFFLOAD_VLAN;
720 else
721 tp->offload &= ~TYPHOON_OFFLOAD_VLAN;
722
723 /* If the interface is up, the runtime is running -- and we
724 * must be up for the vlan core to call us.
725 *
726 * Do the command outside of the spin lock, as it is slow.
727 */
728 INIT_COMMAND_WITH_RESPONSE(&xp_cmd,
729 TYPHOON_CMD_SET_OFFLOAD_TASKS);
730 xp_cmd.parm2 = tp->offload;
731 xp_cmd.parm3 = tp->offload;
732 spin_unlock_bh(&tp->state_lock);
733 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
734 if(err < 0)
735 printk("%s: vlan offload error %d\n", tp->name, -err);
736 spin_lock_bh(&tp->state_lock);
737 }
738
739 /* now make the change visible */
740 tp->vlgrp = grp;
741 spin_unlock_bh(&tp->state_lock);
742 }
743
744 static void
745 typhoon_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
746 {
747 struct typhoon *tp = netdev_priv(dev);
748 spin_lock_bh(&tp->state_lock);
749 if(tp->vlgrp)
750 tp->vlgrp->vlan_devices[vid] = NULL;
751 spin_unlock_bh(&tp->state_lock);
752 }
753
754 static inline void
755 typhoon_tso_fill(struct sk_buff *skb, struct transmit_ring *txRing,
756 u32 ring_dma)
757 {
758 struct tcpopt_desc *tcpd;
759 u32 tcpd_offset = ring_dma;
760
761 tcpd = (struct tcpopt_desc *) (txRing->ringBase + txRing->lastWrite);
762 tcpd_offset += txRing->lastWrite;
763 tcpd_offset += offsetof(struct tcpopt_desc, bytesTx);
764 typhoon_inc_tx_index(&txRing->lastWrite, 1);
765
766 tcpd->flags = TYPHOON_OPT_DESC | TYPHOON_OPT_TCP_SEG;
767 tcpd->numDesc = 1;
768 tcpd->mss_flags = cpu_to_le16(skb_tso_size(skb));
769 tcpd->mss_flags |= TYPHOON_TSO_FIRST | TYPHOON_TSO_LAST;
770 tcpd->respAddrLo = cpu_to_le32(tcpd_offset);
771 tcpd->bytesTx = cpu_to_le32(skb->len);
772 tcpd->status = 0;
773 }
774
775 static int
776 typhoon_start_tx(struct sk_buff *skb, struct net_device *dev)
777 {
778 struct typhoon *tp = netdev_priv(dev);
779 struct transmit_ring *txRing;
780 struct tx_desc *txd, *first_txd;
781 dma_addr_t skb_dma;
782 int numDesc;
783
784 /* we have two rings to choose from, but we only use txLo for now
785 * If we start using the Hi ring as well, we'll need to update
786 * typhoon_stop_runtime(), typhoon_interrupt(), typhoon_num_free_tx(),
787 * and TXHI_ENTRIES to match, as well as update the TSO code below
788 * to get the right DMA address
789 */
790 txRing = &tp->txLoRing;
791
792 /* We need one descriptor for each fragment of the sk_buff, plus the
793 * one for the ->data area of it.
794 *
795 * The docs say a maximum of 16 fragment descriptors per TCP option
796 * descriptor, then make a new packet descriptor and option descriptor
797 * for the next 16 fragments. The engineers say just an option
798 * descriptor is needed. I've tested up to 26 fragments with a single
799 * packet descriptor/option descriptor combo, so I use that for now.
800 *
801 * If problems develop with TSO, check this first.
802 */
803 numDesc = skb_shinfo(skb)->nr_frags + 1;
804 if (skb_is_gso(skb))
805 numDesc++;
806
807 /* When checking for free space in the ring, we need to also
808 * account for the initial Tx descriptor, and we always must leave
809 * at least one descriptor unused in the ring so that it doesn't
810 * wrap and look empty.
811 *
812 * The only time we should loop here is when we hit the race
813 * between marking the queue awake and updating the cleared index.
814 * Just loop and it will appear. This comes from the acenic driver.
815 */
816 while(unlikely(typhoon_num_free_tx(txRing) < (numDesc + 2)))
817 smp_rmb();
818
819 first_txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
820 typhoon_inc_tx_index(&txRing->lastWrite, 1);
821
822 first_txd->flags = TYPHOON_TX_DESC | TYPHOON_DESC_VALID;
823 first_txd->numDesc = 0;
824 first_txd->len = 0;
825 first_txd->addr = (u64)((unsigned long) skb) & 0xffffffff;
826 first_txd->addrHi = (u64)((unsigned long) skb) >> 32;
827 first_txd->processFlags = 0;
828
829 if(skb->ip_summed == CHECKSUM_PARTIAL) {
830 /* The 3XP will figure out if this is UDP/TCP */
831 first_txd->processFlags |= TYPHOON_TX_PF_TCP_CHKSUM;
832 first_txd->processFlags |= TYPHOON_TX_PF_UDP_CHKSUM;
833 first_txd->processFlags |= TYPHOON_TX_PF_IP_CHKSUM;
834 }
835
836 if(vlan_tx_tag_present(skb)) {
837 first_txd->processFlags |=
838 TYPHOON_TX_PF_INSERT_VLAN | TYPHOON_TX_PF_VLAN_PRIORITY;
839 first_txd->processFlags |=
840 cpu_to_le32(htons(vlan_tx_tag_get(skb)) <<
841 TYPHOON_TX_PF_VLAN_TAG_SHIFT);
842 }
843
844 if (skb_is_gso(skb)) {
845 first_txd->processFlags |= TYPHOON_TX_PF_TCP_SEGMENT;
846 first_txd->numDesc++;
847
848 typhoon_tso_fill(skb, txRing, tp->txlo_dma_addr);
849 }
850
851 txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
852 typhoon_inc_tx_index(&txRing->lastWrite, 1);
853
854 /* No need to worry about padding packet -- the firmware pads
855 * it with zeros to ETH_ZLEN for us.
856 */
857 if(skb_shinfo(skb)->nr_frags == 0) {
858 skb_dma = pci_map_single(tp->tx_pdev, skb->data, skb->len,
859 PCI_DMA_TODEVICE);
860 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
861 txd->len = cpu_to_le16(skb->len);
862 txd->addr = cpu_to_le32(skb_dma);
863 txd->addrHi = 0;
864 first_txd->numDesc++;
865 } else {
866 int i, len;
867
868 len = skb_headlen(skb);
869 skb_dma = pci_map_single(tp->tx_pdev, skb->data, len,
870 PCI_DMA_TODEVICE);
871 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
872 txd->len = cpu_to_le16(len);
873 txd->addr = cpu_to_le32(skb_dma);
874 txd->addrHi = 0;
875 first_txd->numDesc++;
876
877 for(i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
878 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
879 void *frag_addr;
880
881 txd = (struct tx_desc *) (txRing->ringBase +
882 txRing->lastWrite);
883 typhoon_inc_tx_index(&txRing->lastWrite, 1);
884
885 len = frag->size;
886 frag_addr = (void *) page_address(frag->page) +
887 frag->page_offset;
888 skb_dma = pci_map_single(tp->tx_pdev, frag_addr, len,
889 PCI_DMA_TODEVICE);
890 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
891 txd->len = cpu_to_le16(len);
892 txd->addr = cpu_to_le32(skb_dma);
893 txd->addrHi = 0;
894 first_txd->numDesc++;
895 }
896 }
897
898 /* Kick the 3XP
899 */
900 wmb();
901 iowrite32(txRing->lastWrite, tp->tx_ioaddr + txRing->writeRegister);
902
903 dev->trans_start = jiffies;
904
905 /* If we don't have room to put the worst case packet on the
906 * queue, then we must stop the queue. We need 2 extra
907 * descriptors -- one to prevent ring wrap, and one for the
908 * Tx header.
909 */
910 numDesc = MAX_SKB_FRAGS + TSO_NUM_DESCRIPTORS + 1;
911
912 if(typhoon_num_free_tx(txRing) < (numDesc + 2)) {
913 netif_stop_queue(dev);
914
915 /* A Tx complete IRQ could have gotten inbetween, making
916 * the ring free again. Only need to recheck here, since
917 * Tx is serialized.
918 */
919 if(typhoon_num_free_tx(txRing) >= (numDesc + 2))
920 netif_wake_queue(dev);
921 }
922
923 return 0;
924 }
925
926 static void
927 typhoon_set_rx_mode(struct net_device *dev)
928 {
929 struct typhoon *tp = netdev_priv(dev);
930 struct cmd_desc xp_cmd;
931 u32 mc_filter[2];
932 u16 filter;
933
934 filter = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
935 if(dev->flags & IFF_PROMISC) {
936 filter |= TYPHOON_RX_FILTER_PROMISCOUS;
937 } else if((dev->mc_count > multicast_filter_limit) ||
938 (dev->flags & IFF_ALLMULTI)) {
939 /* Too many to match, or accept all multicasts. */
940 filter |= TYPHOON_RX_FILTER_ALL_MCAST;
941 } else if(dev->mc_count) {
942 struct dev_mc_list *mclist;
943 int i;
944
945 memset(mc_filter, 0, sizeof(mc_filter));
946 for(i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
947 i++, mclist = mclist->next) {
948 int bit = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3f;
949 mc_filter[bit >> 5] |= 1 << (bit & 0x1f);
950 }
951
952 INIT_COMMAND_NO_RESPONSE(&xp_cmd,
953 TYPHOON_CMD_SET_MULTICAST_HASH);
954 xp_cmd.parm1 = TYPHOON_MCAST_HASH_SET;
955 xp_cmd.parm2 = cpu_to_le32(mc_filter[0]);
956 xp_cmd.parm3 = cpu_to_le32(mc_filter[1]);
957 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
958
959 filter |= TYPHOON_RX_FILTER_MCAST_HASH;
960 }
961
962 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
963 xp_cmd.parm1 = filter;
964 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
965 }
966
967 static int
968 typhoon_do_get_stats(struct typhoon *tp)
969 {
970 struct net_device_stats *stats = &tp->stats;
971 struct net_device_stats *saved = &tp->stats_saved;
972 struct cmd_desc xp_cmd;
973 struct resp_desc xp_resp[7];
974 struct stats_resp *s = (struct stats_resp *) xp_resp;
975 int err;
976
977 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_STATS);
978 err = typhoon_issue_command(tp, 1, &xp_cmd, 7, xp_resp);
979 if(err < 0)
980 return err;
981
982 /* 3Com's Linux driver uses txMultipleCollisions as it's
983 * collisions value, but there is some other collision info as well...
984 *
985 * The extra status reported would be a good candidate for
986 * ethtool_ops->get_{strings,stats}()
987 */
988 stats->tx_packets = le32_to_cpu(s->txPackets);
989 stats->tx_bytes = le32_to_cpu(s->txBytes);
990 stats->tx_errors = le32_to_cpu(s->txCarrierLost);
991 stats->tx_carrier_errors = le32_to_cpu(s->txCarrierLost);
992 stats->collisions = le32_to_cpu(s->txMultipleCollisions);
993 stats->rx_packets = le32_to_cpu(s->rxPacketsGood);
994 stats->rx_bytes = le32_to_cpu(s->rxBytesGood);
995 stats->rx_fifo_errors = le32_to_cpu(s->rxFifoOverruns);
996 stats->rx_errors = le32_to_cpu(s->rxFifoOverruns) +
997 le32_to_cpu(s->BadSSD) + le32_to_cpu(s->rxCrcErrors);
998 stats->rx_crc_errors = le32_to_cpu(s->rxCrcErrors);
999 stats->rx_length_errors = le32_to_cpu(s->rxOversized);
1000 tp->speed = (s->linkStatus & TYPHOON_LINK_100MBPS) ?
1001 SPEED_100 : SPEED_10;
1002 tp->duplex = (s->linkStatus & TYPHOON_LINK_FULL_DUPLEX) ?
1003 DUPLEX_FULL : DUPLEX_HALF;
1004
1005 /* add in the saved statistics
1006 */
1007 stats->tx_packets += saved->tx_packets;
1008 stats->tx_bytes += saved->tx_bytes;
1009 stats->tx_errors += saved->tx_errors;
1010 stats->collisions += saved->collisions;
1011 stats->rx_packets += saved->rx_packets;
1012 stats->rx_bytes += saved->rx_bytes;
1013 stats->rx_fifo_errors += saved->rx_fifo_errors;
1014 stats->rx_errors += saved->rx_errors;
1015 stats->rx_crc_errors += saved->rx_crc_errors;
1016 stats->rx_length_errors += saved->rx_length_errors;
1017
1018 return 0;
1019 }
1020
1021 static struct net_device_stats *
1022 typhoon_get_stats(struct net_device *dev)
1023 {
1024 struct typhoon *tp = netdev_priv(dev);
1025 struct net_device_stats *stats = &tp->stats;
1026 struct net_device_stats *saved = &tp->stats_saved;
1027
1028 smp_rmb();
1029 if(tp->card_state == Sleeping)
1030 return saved;
1031
1032 if(typhoon_do_get_stats(tp) < 0) {
1033 printk(KERN_ERR "%s: error getting stats\n", dev->name);
1034 return saved;
1035 }
1036
1037 return stats;
1038 }
1039
1040 static int
1041 typhoon_set_mac_address(struct net_device *dev, void *addr)
1042 {
1043 struct sockaddr *saddr = (struct sockaddr *) addr;
1044
1045 if(netif_running(dev))
1046 return -EBUSY;
1047
1048 memcpy(dev->dev_addr, saddr->sa_data, dev->addr_len);
1049 return 0;
1050 }
1051
1052 static void
1053 typhoon_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1054 {
1055 struct typhoon *tp = netdev_priv(dev);
1056 struct pci_dev *pci_dev = tp->pdev;
1057 struct cmd_desc xp_cmd;
1058 struct resp_desc xp_resp[3];
1059
1060 smp_rmb();
1061 if(tp->card_state == Sleeping) {
1062 strcpy(info->fw_version, "Sleep image");
1063 } else {
1064 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
1065 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
1066 strcpy(info->fw_version, "Unknown runtime");
1067 } else {
1068 u32 sleep_ver = xp_resp[0].parm2;
1069 snprintf(info->fw_version, 32, "%02x.%03x.%03x",
1070 sleep_ver >> 24, (sleep_ver >> 12) & 0xfff,
1071 sleep_ver & 0xfff);
1072 }
1073 }
1074
1075 strcpy(info->driver, DRV_MODULE_NAME);
1076 strcpy(info->version, DRV_MODULE_VERSION);
1077 strcpy(info->bus_info, pci_name(pci_dev));
1078 }
1079
1080 static int
1081 typhoon_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1082 {
1083 struct typhoon *tp = netdev_priv(dev);
1084
1085 cmd->supported = SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1086 SUPPORTED_Autoneg;
1087
1088 switch (tp->xcvr_select) {
1089 case TYPHOON_XCVR_10HALF:
1090 cmd->advertising = ADVERTISED_10baseT_Half;
1091 break;
1092 case TYPHOON_XCVR_10FULL:
1093 cmd->advertising = ADVERTISED_10baseT_Full;
1094 break;
1095 case TYPHOON_XCVR_100HALF:
1096 cmd->advertising = ADVERTISED_100baseT_Half;
1097 break;
1098 case TYPHOON_XCVR_100FULL:
1099 cmd->advertising = ADVERTISED_100baseT_Full;
1100 break;
1101 case TYPHOON_XCVR_AUTONEG:
1102 cmd->advertising = ADVERTISED_10baseT_Half |
1103 ADVERTISED_10baseT_Full |
1104 ADVERTISED_100baseT_Half |
1105 ADVERTISED_100baseT_Full |
1106 ADVERTISED_Autoneg;
1107 break;
1108 }
1109
1110 if(tp->capabilities & TYPHOON_FIBER) {
1111 cmd->supported |= SUPPORTED_FIBRE;
1112 cmd->advertising |= ADVERTISED_FIBRE;
1113 cmd->port = PORT_FIBRE;
1114 } else {
1115 cmd->supported |= SUPPORTED_10baseT_Half |
1116 SUPPORTED_10baseT_Full |
1117 SUPPORTED_TP;
1118 cmd->advertising |= ADVERTISED_TP;
1119 cmd->port = PORT_TP;
1120 }
1121
1122 /* need to get stats to make these link speed/duplex valid */
1123 typhoon_do_get_stats(tp);
1124 cmd->speed = tp->speed;
1125 cmd->duplex = tp->duplex;
1126 cmd->phy_address = 0;
1127 cmd->transceiver = XCVR_INTERNAL;
1128 if(tp->xcvr_select == TYPHOON_XCVR_AUTONEG)
1129 cmd->autoneg = AUTONEG_ENABLE;
1130 else
1131 cmd->autoneg = AUTONEG_DISABLE;
1132 cmd->maxtxpkt = 1;
1133 cmd->maxrxpkt = 1;
1134
1135 return 0;
1136 }
1137
1138 static int
1139 typhoon_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1140 {
1141 struct typhoon *tp = netdev_priv(dev);
1142 struct cmd_desc xp_cmd;
1143 int xcvr;
1144 int err;
1145
1146 err = -EINVAL;
1147 if(cmd->autoneg == AUTONEG_ENABLE) {
1148 xcvr = TYPHOON_XCVR_AUTONEG;
1149 } else {
1150 if(cmd->duplex == DUPLEX_HALF) {
1151 if(cmd->speed == SPEED_10)
1152 xcvr = TYPHOON_XCVR_10HALF;
1153 else if(cmd->speed == SPEED_100)
1154 xcvr = TYPHOON_XCVR_100HALF;
1155 else
1156 goto out;
1157 } else if(cmd->duplex == DUPLEX_FULL) {
1158 if(cmd->speed == SPEED_10)
1159 xcvr = TYPHOON_XCVR_10FULL;
1160 else if(cmd->speed == SPEED_100)
1161 xcvr = TYPHOON_XCVR_100FULL;
1162 else
1163 goto out;
1164 } else
1165 goto out;
1166 }
1167
1168 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1169 xp_cmd.parm1 = cpu_to_le16(xcvr);
1170 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1171 if(err < 0)
1172 goto out;
1173
1174 tp->xcvr_select = xcvr;
1175 if(cmd->autoneg == AUTONEG_ENABLE) {
1176 tp->speed = 0xff; /* invalid */
1177 tp->duplex = 0xff; /* invalid */
1178 } else {
1179 tp->speed = cmd->speed;
1180 tp->duplex = cmd->duplex;
1181 }
1182
1183 out:
1184 return err;
1185 }
1186
1187 static void
1188 typhoon_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1189 {
1190 struct typhoon *tp = netdev_priv(dev);
1191
1192 wol->supported = WAKE_PHY | WAKE_MAGIC;
1193 wol->wolopts = 0;
1194 if(tp->wol_events & TYPHOON_WAKE_LINK_EVENT)
1195 wol->wolopts |= WAKE_PHY;
1196 if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
1197 wol->wolopts |= WAKE_MAGIC;
1198 memset(&wol->sopass, 0, sizeof(wol->sopass));
1199 }
1200
1201 static int
1202 typhoon_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1203 {
1204 struct typhoon *tp = netdev_priv(dev);
1205
1206 if(wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
1207 return -EINVAL;
1208
1209 tp->wol_events = 0;
1210 if(wol->wolopts & WAKE_PHY)
1211 tp->wol_events |= TYPHOON_WAKE_LINK_EVENT;
1212 if(wol->wolopts & WAKE_MAGIC)
1213 tp->wol_events |= TYPHOON_WAKE_MAGIC_PKT;
1214
1215 return 0;
1216 }
1217
1218 static u32
1219 typhoon_get_rx_csum(struct net_device *dev)
1220 {
1221 /* For now, we don't allow turning off RX checksums.
1222 */
1223 return 1;
1224 }
1225
1226 static void
1227 typhoon_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
1228 {
1229 ering->rx_max_pending = RXENT_ENTRIES;
1230 ering->rx_mini_max_pending = 0;
1231 ering->rx_jumbo_max_pending = 0;
1232 ering->tx_max_pending = TXLO_ENTRIES - 1;
1233
1234 ering->rx_pending = RXENT_ENTRIES;
1235 ering->rx_mini_pending = 0;
1236 ering->rx_jumbo_pending = 0;
1237 ering->tx_pending = TXLO_ENTRIES - 1;
1238 }
1239
1240 static const struct ethtool_ops typhoon_ethtool_ops = {
1241 .get_settings = typhoon_get_settings,
1242 .set_settings = typhoon_set_settings,
1243 .get_drvinfo = typhoon_get_drvinfo,
1244 .get_wol = typhoon_get_wol,
1245 .set_wol = typhoon_set_wol,
1246 .get_link = ethtool_op_get_link,
1247 .get_rx_csum = typhoon_get_rx_csum,
1248 .get_tx_csum = ethtool_op_get_tx_csum,
1249 .set_tx_csum = ethtool_op_set_tx_csum,
1250 .get_sg = ethtool_op_get_sg,
1251 .set_sg = ethtool_op_set_sg,
1252 .get_tso = ethtool_op_get_tso,
1253 .set_tso = ethtool_op_set_tso,
1254 .get_ringparam = typhoon_get_ringparam,
1255 };
1256
1257 static int
1258 typhoon_wait_interrupt(void __iomem *ioaddr)
1259 {
1260 int i, err = 0;
1261
1262 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1263 if(ioread32(ioaddr + TYPHOON_REG_INTR_STATUS) &
1264 TYPHOON_INTR_BOOTCMD)
1265 goto out;
1266 udelay(TYPHOON_UDELAY);
1267 }
1268
1269 err = -ETIMEDOUT;
1270
1271 out:
1272 iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1273 return err;
1274 }
1275
1276 #define shared_offset(x) offsetof(struct typhoon_shared, x)
1277
1278 static void
1279 typhoon_init_interface(struct typhoon *tp)
1280 {
1281 struct typhoon_interface *iface = &tp->shared->iface;
1282 dma_addr_t shared_dma;
1283
1284 memset(tp->shared, 0, sizeof(struct typhoon_shared));
1285
1286 /* The *Hi members of iface are all init'd to zero by the memset().
1287 */
1288 shared_dma = tp->shared_dma + shared_offset(indexes);
1289 iface->ringIndex = cpu_to_le32(shared_dma);
1290
1291 shared_dma = tp->shared_dma + shared_offset(txLo);
1292 iface->txLoAddr = cpu_to_le32(shared_dma);
1293 iface->txLoSize = cpu_to_le32(TXLO_ENTRIES * sizeof(struct tx_desc));
1294
1295 shared_dma = tp->shared_dma + shared_offset(txHi);
1296 iface->txHiAddr = cpu_to_le32(shared_dma);
1297 iface->txHiSize = cpu_to_le32(TXHI_ENTRIES * sizeof(struct tx_desc));
1298
1299 shared_dma = tp->shared_dma + shared_offset(rxBuff);
1300 iface->rxBuffAddr = cpu_to_le32(shared_dma);
1301 iface->rxBuffSize = cpu_to_le32(RXFREE_ENTRIES *
1302 sizeof(struct rx_free));
1303
1304 shared_dma = tp->shared_dma + shared_offset(rxLo);
1305 iface->rxLoAddr = cpu_to_le32(shared_dma);
1306 iface->rxLoSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1307
1308 shared_dma = tp->shared_dma + shared_offset(rxHi);
1309 iface->rxHiAddr = cpu_to_le32(shared_dma);
1310 iface->rxHiSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1311
1312 shared_dma = tp->shared_dma + shared_offset(cmd);
1313 iface->cmdAddr = cpu_to_le32(shared_dma);
1314 iface->cmdSize = cpu_to_le32(COMMAND_RING_SIZE);
1315
1316 shared_dma = tp->shared_dma + shared_offset(resp);
1317 iface->respAddr = cpu_to_le32(shared_dma);
1318 iface->respSize = cpu_to_le32(RESPONSE_RING_SIZE);
1319
1320 shared_dma = tp->shared_dma + shared_offset(zeroWord);
1321 iface->zeroAddr = cpu_to_le32(shared_dma);
1322
1323 tp->indexes = &tp->shared->indexes;
1324 tp->txLoRing.ringBase = (u8 *) tp->shared->txLo;
1325 tp->txHiRing.ringBase = (u8 *) tp->shared->txHi;
1326 tp->rxLoRing.ringBase = (u8 *) tp->shared->rxLo;
1327 tp->rxHiRing.ringBase = (u8 *) tp->shared->rxHi;
1328 tp->rxBuffRing.ringBase = (u8 *) tp->shared->rxBuff;
1329 tp->cmdRing.ringBase = (u8 *) tp->shared->cmd;
1330 tp->respRing.ringBase = (u8 *) tp->shared->resp;
1331
1332 tp->txLoRing.writeRegister = TYPHOON_REG_TX_LO_READY;
1333 tp->txHiRing.writeRegister = TYPHOON_REG_TX_HI_READY;
1334
1335 tp->txlo_dma_addr = iface->txLoAddr;
1336 tp->card_state = Sleeping;
1337 smp_wmb();
1338
1339 tp->offload = TYPHOON_OFFLOAD_IP_CHKSUM | TYPHOON_OFFLOAD_TCP_CHKSUM;
1340 tp->offload |= TYPHOON_OFFLOAD_UDP_CHKSUM | TSO_OFFLOAD_ON;
1341
1342 spin_lock_init(&tp->command_lock);
1343 spin_lock_init(&tp->state_lock);
1344 }
1345
1346 static void
1347 typhoon_init_rings(struct typhoon *tp)
1348 {
1349 memset(tp->indexes, 0, sizeof(struct typhoon_indexes));
1350
1351 tp->txLoRing.lastWrite = 0;
1352 tp->txHiRing.lastWrite = 0;
1353 tp->rxLoRing.lastWrite = 0;
1354 tp->rxHiRing.lastWrite = 0;
1355 tp->rxBuffRing.lastWrite = 0;
1356 tp->cmdRing.lastWrite = 0;
1357 tp->cmdRing.lastWrite = 0;
1358
1359 tp->txLoRing.lastRead = 0;
1360 tp->txHiRing.lastRead = 0;
1361 }
1362
1363 static int
1364 typhoon_download_firmware(struct typhoon *tp)
1365 {
1366 void __iomem *ioaddr = tp->ioaddr;
1367 struct pci_dev *pdev = tp->pdev;
1368 struct typhoon_file_header *fHdr;
1369 struct typhoon_section_header *sHdr;
1370 u8 *image_data;
1371 void *dpage;
1372 dma_addr_t dpage_dma;
1373 unsigned int csum;
1374 u32 irqEnabled;
1375 u32 irqMasked;
1376 u32 numSections;
1377 u32 section_len;
1378 u32 len;
1379 u32 load_addr;
1380 u32 hmac;
1381 int i;
1382 int err;
1383
1384 err = -EINVAL;
1385 fHdr = (struct typhoon_file_header *) typhoon_firmware_image;
1386 image_data = (u8 *) fHdr;
1387
1388 if(memcmp(fHdr->tag, "TYPHOON", 8)) {
1389 printk(KERN_ERR "%s: Invalid firmware image!\n", tp->name);
1390 goto err_out;
1391 }
1392
1393 /* Cannot just map the firmware image using pci_map_single() as
1394 * the firmware is part of the kernel/module image, so we allocate
1395 * some consistent memory to copy the sections into, as it is simpler,
1396 * and short-lived. If we ever split out and require a userland
1397 * firmware loader, then we can revisit this.
1398 */
1399 err = -ENOMEM;
1400 dpage = pci_alloc_consistent(pdev, PAGE_SIZE, &dpage_dma);
1401 if(!dpage) {
1402 printk(KERN_ERR "%s: no DMA mem for firmware\n", tp->name);
1403 goto err_out;
1404 }
1405
1406 irqEnabled = ioread32(ioaddr + TYPHOON_REG_INTR_ENABLE);
1407 iowrite32(irqEnabled | TYPHOON_INTR_BOOTCMD,
1408 ioaddr + TYPHOON_REG_INTR_ENABLE);
1409 irqMasked = ioread32(ioaddr + TYPHOON_REG_INTR_MASK);
1410 iowrite32(irqMasked | TYPHOON_INTR_BOOTCMD,
1411 ioaddr + TYPHOON_REG_INTR_MASK);
1412
1413 err = -ETIMEDOUT;
1414 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
1415 printk(KERN_ERR "%s: card ready timeout\n", tp->name);
1416 goto err_out_irq;
1417 }
1418
1419 numSections = le32_to_cpu(fHdr->numSections);
1420 load_addr = le32_to_cpu(fHdr->startAddr);
1421
1422 iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1423 iowrite32(load_addr, ioaddr + TYPHOON_REG_DOWNLOAD_BOOT_ADDR);
1424 hmac = le32_to_cpu(fHdr->hmacDigest[0]);
1425 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_0);
1426 hmac = le32_to_cpu(fHdr->hmacDigest[1]);
1427 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_1);
1428 hmac = le32_to_cpu(fHdr->hmacDigest[2]);
1429 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_2);
1430 hmac = le32_to_cpu(fHdr->hmacDigest[3]);
1431 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_3);
1432 hmac = le32_to_cpu(fHdr->hmacDigest[4]);
1433 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_4);
1434 typhoon_post_pci_writes(ioaddr);
1435 iowrite32(TYPHOON_BOOTCMD_RUNTIME_IMAGE, ioaddr + TYPHOON_REG_COMMAND);
1436
1437 image_data += sizeof(struct typhoon_file_header);
1438
1439 /* The ioread32() in typhoon_wait_interrupt() will force the
1440 * last write to the command register to post, so
1441 * we don't need a typhoon_post_pci_writes() after it.
1442 */
1443 for(i = 0; i < numSections; i++) {
1444 sHdr = (struct typhoon_section_header *) image_data;
1445 image_data += sizeof(struct typhoon_section_header);
1446 load_addr = le32_to_cpu(sHdr->startAddr);
1447 section_len = le32_to_cpu(sHdr->len);
1448
1449 while(section_len) {
1450 len = min_t(u32, section_len, PAGE_SIZE);
1451
1452 if(typhoon_wait_interrupt(ioaddr) < 0 ||
1453 ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1454 TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1455 printk(KERN_ERR "%s: segment ready timeout\n",
1456 tp->name);
1457 goto err_out_irq;
1458 }
1459
1460 /* Do an pseudo IPv4 checksum on the data -- first
1461 * need to convert each u16 to cpu order before
1462 * summing. Fortunately, due to the properties of
1463 * the checksum, we can do this once, at the end.
1464 */
1465 csum = csum_partial_copy_nocheck(image_data, dpage,
1466 len, 0);
1467 csum = csum_fold(csum);
1468 csum = le16_to_cpu(csum);
1469
1470 iowrite32(len, ioaddr + TYPHOON_REG_BOOT_LENGTH);
1471 iowrite32(csum, ioaddr + TYPHOON_REG_BOOT_CHECKSUM);
1472 iowrite32(load_addr,
1473 ioaddr + TYPHOON_REG_BOOT_DEST_ADDR);
1474 iowrite32(0, ioaddr + TYPHOON_REG_BOOT_DATA_HI);
1475 iowrite32(dpage_dma, ioaddr + TYPHOON_REG_BOOT_DATA_LO);
1476 typhoon_post_pci_writes(ioaddr);
1477 iowrite32(TYPHOON_BOOTCMD_SEG_AVAILABLE,
1478 ioaddr + TYPHOON_REG_COMMAND);
1479
1480 image_data += len;
1481 load_addr += len;
1482 section_len -= len;
1483 }
1484 }
1485
1486 if(typhoon_wait_interrupt(ioaddr) < 0 ||
1487 ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1488 TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1489 printk(KERN_ERR "%s: final segment ready timeout\n", tp->name);
1490 goto err_out_irq;
1491 }
1492
1493 iowrite32(TYPHOON_BOOTCMD_DNLD_COMPLETE, ioaddr + TYPHOON_REG_COMMAND);
1494
1495 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1496 printk(KERN_ERR "%s: boot ready timeout, status 0x%0x\n",
1497 tp->name, ioread32(ioaddr + TYPHOON_REG_STATUS));
1498 goto err_out_irq;
1499 }
1500
1501 err = 0;
1502
1503 err_out_irq:
1504 iowrite32(irqMasked, ioaddr + TYPHOON_REG_INTR_MASK);
1505 iowrite32(irqEnabled, ioaddr + TYPHOON_REG_INTR_ENABLE);
1506
1507 pci_free_consistent(pdev, PAGE_SIZE, dpage, dpage_dma);
1508
1509 err_out:
1510 return err;
1511 }
1512
1513 static int
1514 typhoon_boot_3XP(struct typhoon *tp, u32 initial_status)
1515 {
1516 void __iomem *ioaddr = tp->ioaddr;
1517
1518 if(typhoon_wait_status(ioaddr, initial_status) < 0) {
1519 printk(KERN_ERR "%s: boot ready timeout\n", tp->name);
1520 goto out_timeout;
1521 }
1522
1523 iowrite32(0, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_HI);
1524 iowrite32(tp->shared_dma, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_LO);
1525 typhoon_post_pci_writes(ioaddr);
1526 iowrite32(TYPHOON_BOOTCMD_REG_BOOT_RECORD,
1527 ioaddr + TYPHOON_REG_COMMAND);
1528
1529 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_RUNNING) < 0) {
1530 printk(KERN_ERR "%s: boot finish timeout (status 0x%x)\n",
1531 tp->name, ioread32(ioaddr + TYPHOON_REG_STATUS));
1532 goto out_timeout;
1533 }
1534
1535 /* Clear the Transmit and Command ready registers
1536 */
1537 iowrite32(0, ioaddr + TYPHOON_REG_TX_HI_READY);
1538 iowrite32(0, ioaddr + TYPHOON_REG_CMD_READY);
1539 iowrite32(0, ioaddr + TYPHOON_REG_TX_LO_READY);
1540 typhoon_post_pci_writes(ioaddr);
1541 iowrite32(TYPHOON_BOOTCMD_BOOT, ioaddr + TYPHOON_REG_COMMAND);
1542
1543 return 0;
1544
1545 out_timeout:
1546 return -ETIMEDOUT;
1547 }
1548
1549 static u32
1550 typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing,
1551 volatile u32 * index)
1552 {
1553 u32 lastRead = txRing->lastRead;
1554 struct tx_desc *tx;
1555 dma_addr_t skb_dma;
1556 int dma_len;
1557 int type;
1558
1559 while(lastRead != le32_to_cpu(*index)) {
1560 tx = (struct tx_desc *) (txRing->ringBase + lastRead);
1561 type = tx->flags & TYPHOON_TYPE_MASK;
1562
1563 if(type == TYPHOON_TX_DESC) {
1564 /* This tx_desc describes a packet.
1565 */
1566 unsigned long ptr = tx->addr | ((u64)tx->addrHi << 32);
1567 struct sk_buff *skb = (struct sk_buff *) ptr;
1568 dev_kfree_skb_irq(skb);
1569 } else if(type == TYPHOON_FRAG_DESC) {
1570 /* This tx_desc describes a memory mapping. Free it.
1571 */
1572 skb_dma = (dma_addr_t) le32_to_cpu(tx->addr);
1573 dma_len = le16_to_cpu(tx->len);
1574 pci_unmap_single(tp->pdev, skb_dma, dma_len,
1575 PCI_DMA_TODEVICE);
1576 }
1577
1578 tx->flags = 0;
1579 typhoon_inc_tx_index(&lastRead, 1);
1580 }
1581
1582 return lastRead;
1583 }
1584
1585 static void
1586 typhoon_tx_complete(struct typhoon *tp, struct transmit_ring *txRing,
1587 volatile u32 * index)
1588 {
1589 u32 lastRead;
1590 int numDesc = MAX_SKB_FRAGS + 1;
1591
1592 /* This will need changing if we start to use the Hi Tx ring. */
1593 lastRead = typhoon_clean_tx(tp, txRing, index);
1594 if(netif_queue_stopped(tp->dev) && typhoon_num_free(txRing->lastWrite,
1595 lastRead, TXLO_ENTRIES) > (numDesc + 2))
1596 netif_wake_queue(tp->dev);
1597
1598 txRing->lastRead = lastRead;
1599 smp_wmb();
1600 }
1601
1602 static void
1603 typhoon_recycle_rx_skb(struct typhoon *tp, u32 idx)
1604 {
1605 struct typhoon_indexes *indexes = tp->indexes;
1606 struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1607 struct basic_ring *ring = &tp->rxBuffRing;
1608 struct rx_free *r;
1609
1610 if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1611 indexes->rxBuffCleared) {
1612 /* no room in ring, just drop the skb
1613 */
1614 dev_kfree_skb_any(rxb->skb);
1615 rxb->skb = NULL;
1616 return;
1617 }
1618
1619 r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1620 typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1621 r->virtAddr = idx;
1622 r->physAddr = cpu_to_le32(rxb->dma_addr);
1623
1624 /* Tell the card about it */
1625 wmb();
1626 indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1627 }
1628
1629 static int
1630 typhoon_alloc_rx_skb(struct typhoon *tp, u32 idx)
1631 {
1632 struct typhoon_indexes *indexes = tp->indexes;
1633 struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1634 struct basic_ring *ring = &tp->rxBuffRing;
1635 struct rx_free *r;
1636 struct sk_buff *skb;
1637 dma_addr_t dma_addr;
1638
1639 rxb->skb = NULL;
1640
1641 if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1642 indexes->rxBuffCleared)
1643 return -ENOMEM;
1644
1645 skb = dev_alloc_skb(PKT_BUF_SZ);
1646 if(!skb)
1647 return -ENOMEM;
1648
1649 #if 0
1650 /* Please, 3com, fix the firmware to allow DMA to a unaligned
1651 * address! Pretty please?
1652 */
1653 skb_reserve(skb, 2);
1654 #endif
1655
1656 skb->dev = tp->dev;
1657 dma_addr = pci_map_single(tp->pdev, skb->data,
1658 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
1659
1660 /* Since no card does 64 bit DAC, the high bits will never
1661 * change from zero.
1662 */
1663 r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1664 typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1665 r->virtAddr = idx;
1666 r->physAddr = cpu_to_le32(dma_addr);
1667 rxb->skb = skb;
1668 rxb->dma_addr = dma_addr;
1669
1670 /* Tell the card about it */
1671 wmb();
1672 indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1673 return 0;
1674 }
1675
1676 static int
1677 typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile u32 * ready,
1678 volatile u32 * cleared, int budget)
1679 {
1680 struct rx_desc *rx;
1681 struct sk_buff *skb, *new_skb;
1682 struct rxbuff_ent *rxb;
1683 dma_addr_t dma_addr;
1684 u32 local_ready;
1685 u32 rxaddr;
1686 int pkt_len;
1687 u32 idx;
1688 u32 csum_bits;
1689 int received;
1690
1691 received = 0;
1692 local_ready = le32_to_cpu(*ready);
1693 rxaddr = le32_to_cpu(*cleared);
1694 while(rxaddr != local_ready && budget > 0) {
1695 rx = (struct rx_desc *) (rxRing->ringBase + rxaddr);
1696 idx = rx->addr;
1697 rxb = &tp->rxbuffers[idx];
1698 skb = rxb->skb;
1699 dma_addr = rxb->dma_addr;
1700
1701 typhoon_inc_rx_index(&rxaddr, 1);
1702
1703 if(rx->flags & TYPHOON_RX_ERROR) {
1704 typhoon_recycle_rx_skb(tp, idx);
1705 continue;
1706 }
1707
1708 pkt_len = le16_to_cpu(rx->frameLen);
1709
1710 if(pkt_len < rx_copybreak &&
1711 (new_skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1712 new_skb->dev = tp->dev;
1713 skb_reserve(new_skb, 2);
1714 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr,
1715 PKT_BUF_SZ,
1716 PCI_DMA_FROMDEVICE);
1717 eth_copy_and_sum(new_skb, skb->data, pkt_len, 0);
1718 pci_dma_sync_single_for_device(tp->pdev, dma_addr,
1719 PKT_BUF_SZ,
1720 PCI_DMA_FROMDEVICE);
1721 skb_put(new_skb, pkt_len);
1722 typhoon_recycle_rx_skb(tp, idx);
1723 } else {
1724 new_skb = skb;
1725 skb_put(new_skb, pkt_len);
1726 pci_unmap_single(tp->pdev, dma_addr, PKT_BUF_SZ,
1727 PCI_DMA_FROMDEVICE);
1728 typhoon_alloc_rx_skb(tp, idx);
1729 }
1730 new_skb->protocol = eth_type_trans(new_skb, tp->dev);
1731 csum_bits = rx->rxStatus & (TYPHOON_RX_IP_CHK_GOOD |
1732 TYPHOON_RX_UDP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD);
1733 if(csum_bits ==
1734 (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD)
1735 || csum_bits ==
1736 (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_UDP_CHK_GOOD)) {
1737 new_skb->ip_summed = CHECKSUM_UNNECESSARY;
1738 } else
1739 new_skb->ip_summed = CHECKSUM_NONE;
1740
1741 spin_lock(&tp->state_lock);
1742 if(tp->vlgrp != NULL && rx->rxStatus & TYPHOON_RX_VLAN)
1743 vlan_hwaccel_receive_skb(new_skb, tp->vlgrp,
1744 ntohl(rx->vlanTag) & 0xffff);
1745 else
1746 netif_receive_skb(new_skb);
1747 spin_unlock(&tp->state_lock);
1748
1749 tp->dev->last_rx = jiffies;
1750 received++;
1751 budget--;
1752 }
1753 *cleared = cpu_to_le32(rxaddr);
1754
1755 return received;
1756 }
1757
1758 static void
1759 typhoon_fill_free_ring(struct typhoon *tp)
1760 {
1761 u32 i;
1762
1763 for(i = 0; i < RXENT_ENTRIES; i++) {
1764 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1765 if(rxb->skb)
1766 continue;
1767 if(typhoon_alloc_rx_skb(tp, i) < 0)
1768 break;
1769 }
1770 }
1771
1772 static int
1773 typhoon_poll(struct net_device *dev, int *total_budget)
1774 {
1775 struct typhoon *tp = netdev_priv(dev);
1776 struct typhoon_indexes *indexes = tp->indexes;
1777 int orig_budget = *total_budget;
1778 int budget, work_done, done;
1779
1780 rmb();
1781 if(!tp->awaiting_resp && indexes->respReady != indexes->respCleared)
1782 typhoon_process_response(tp, 0, NULL);
1783
1784 if(le32_to_cpu(indexes->txLoCleared) != tp->txLoRing.lastRead)
1785 typhoon_tx_complete(tp, &tp->txLoRing, &indexes->txLoCleared);
1786
1787 if(orig_budget > dev->quota)
1788 orig_budget = dev->quota;
1789
1790 budget = orig_budget;
1791 work_done = 0;
1792 done = 1;
1793
1794 if(indexes->rxHiCleared != indexes->rxHiReady) {
1795 work_done = typhoon_rx(tp, &tp->rxHiRing, &indexes->rxHiReady,
1796 &indexes->rxHiCleared, budget);
1797 budget -= work_done;
1798 }
1799
1800 if(indexes->rxLoCleared != indexes->rxLoReady) {
1801 work_done += typhoon_rx(tp, &tp->rxLoRing, &indexes->rxLoReady,
1802 &indexes->rxLoCleared, budget);
1803 }
1804
1805 if(work_done) {
1806 *total_budget -= work_done;
1807 dev->quota -= work_done;
1808
1809 if(work_done >= orig_budget)
1810 done = 0;
1811 }
1812
1813 if(le32_to_cpu(indexes->rxBuffCleared) == tp->rxBuffRing.lastWrite) {
1814 /* rxBuff ring is empty, try to fill it. */
1815 typhoon_fill_free_ring(tp);
1816 }
1817
1818 if(done) {
1819 netif_rx_complete(dev);
1820 iowrite32(TYPHOON_INTR_NONE,
1821 tp->ioaddr + TYPHOON_REG_INTR_MASK);
1822 typhoon_post_pci_writes(tp->ioaddr);
1823 }
1824
1825 return (done ? 0 : 1);
1826 }
1827
1828 static irqreturn_t
1829 typhoon_interrupt(int irq, void *dev_instance)
1830 {
1831 struct net_device *dev = (struct net_device *) dev_instance;
1832 struct typhoon *tp = dev->priv;
1833 void __iomem *ioaddr = tp->ioaddr;
1834 u32 intr_status;
1835
1836 intr_status = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
1837 if(!(intr_status & TYPHOON_INTR_HOST_INT))
1838 return IRQ_NONE;
1839
1840 iowrite32(intr_status, ioaddr + TYPHOON_REG_INTR_STATUS);
1841
1842 if(netif_rx_schedule_prep(dev)) {
1843 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
1844 typhoon_post_pci_writes(ioaddr);
1845 __netif_rx_schedule(dev);
1846 } else {
1847 printk(KERN_ERR "%s: Error, poll already scheduled\n",
1848 dev->name);
1849 }
1850 return IRQ_HANDLED;
1851 }
1852
1853 static void
1854 typhoon_free_rx_rings(struct typhoon *tp)
1855 {
1856 u32 i;
1857
1858 for(i = 0; i < RXENT_ENTRIES; i++) {
1859 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1860 if(rxb->skb) {
1861 pci_unmap_single(tp->pdev, rxb->dma_addr, PKT_BUF_SZ,
1862 PCI_DMA_FROMDEVICE);
1863 dev_kfree_skb(rxb->skb);
1864 rxb->skb = NULL;
1865 }
1866 }
1867 }
1868
1869 static int
1870 typhoon_sleep(struct typhoon *tp, pci_power_t state, u16 events)
1871 {
1872 struct pci_dev *pdev = tp->pdev;
1873 void __iomem *ioaddr = tp->ioaddr;
1874 struct cmd_desc xp_cmd;
1875 int err;
1876
1877 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_ENABLE_WAKE_EVENTS);
1878 xp_cmd.parm1 = events;
1879 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1880 if(err < 0) {
1881 printk(KERN_ERR "%s: typhoon_sleep(): wake events cmd err %d\n",
1882 tp->name, err);
1883 return err;
1884 }
1885
1886 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_GOTO_SLEEP);
1887 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1888 if(err < 0) {
1889 printk(KERN_ERR "%s: typhoon_sleep(): sleep cmd err %d\n",
1890 tp->name, err);
1891 return err;
1892 }
1893
1894 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_SLEEPING) < 0)
1895 return -ETIMEDOUT;
1896
1897 /* Since we cannot monitor the status of the link while sleeping,
1898 * tell the world it went away.
1899 */
1900 netif_carrier_off(tp->dev);
1901
1902 pci_enable_wake(tp->pdev, state, 1);
1903 pci_disable_device(pdev);
1904 return pci_set_power_state(pdev, state);
1905 }
1906
1907 static int
1908 typhoon_wakeup(struct typhoon *tp, int wait_type)
1909 {
1910 struct pci_dev *pdev = tp->pdev;
1911 void __iomem *ioaddr = tp->ioaddr;
1912
1913 pci_set_power_state(pdev, PCI_D0);
1914 pci_restore_state(pdev);
1915
1916 /* Post 2.x.x versions of the Sleep Image require a reset before
1917 * we can download the Runtime Image. But let's not make users of
1918 * the old firmware pay for the reset.
1919 */
1920 iowrite32(TYPHOON_BOOTCMD_WAKEUP, ioaddr + TYPHOON_REG_COMMAND);
1921 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0 ||
1922 (tp->capabilities & TYPHOON_WAKEUP_NEEDS_RESET))
1923 return typhoon_reset(ioaddr, wait_type);
1924
1925 return 0;
1926 }
1927
1928 static int
1929 typhoon_start_runtime(struct typhoon *tp)
1930 {
1931 struct net_device *dev = tp->dev;
1932 void __iomem *ioaddr = tp->ioaddr;
1933 struct cmd_desc xp_cmd;
1934 int err;
1935
1936 typhoon_init_rings(tp);
1937 typhoon_fill_free_ring(tp);
1938
1939 err = typhoon_download_firmware(tp);
1940 if(err < 0) {
1941 printk("%s: cannot load runtime on 3XP\n", tp->name);
1942 goto error_out;
1943 }
1944
1945 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1946 printk("%s: cannot boot 3XP\n", tp->name);
1947 err = -EIO;
1948 goto error_out;
1949 }
1950
1951 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAX_PKT_SIZE);
1952 xp_cmd.parm1 = cpu_to_le16(PKT_BUF_SZ);
1953 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1954 if(err < 0)
1955 goto error_out;
1956
1957 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
1958 xp_cmd.parm1 = cpu_to_le16(ntohs(*(u16 *)&dev->dev_addr[0]));
1959 xp_cmd.parm2 = cpu_to_le32(ntohl(*(u32 *)&dev->dev_addr[2]));
1960 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1961 if(err < 0)
1962 goto error_out;
1963
1964 /* Disable IRQ coalescing -- we can reenable it when 3Com gives
1965 * us some more information on how to control it.
1966 */
1967 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_IRQ_COALESCE_CTRL);
1968 xp_cmd.parm1 = 0;
1969 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1970 if(err < 0)
1971 goto error_out;
1972
1973 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1974 xp_cmd.parm1 = tp->xcvr_select;
1975 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1976 if(err < 0)
1977 goto error_out;
1978
1979 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_VLAN_TYPE_WRITE);
1980 xp_cmd.parm1 = __constant_cpu_to_le16(ETH_P_8021Q);
1981 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1982 if(err < 0)
1983 goto error_out;
1984
1985 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_OFFLOAD_TASKS);
1986 spin_lock_bh(&tp->state_lock);
1987 xp_cmd.parm2 = tp->offload;
1988 xp_cmd.parm3 = tp->offload;
1989 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1990 spin_unlock_bh(&tp->state_lock);
1991 if(err < 0)
1992 goto error_out;
1993
1994 typhoon_set_rx_mode(dev);
1995
1996 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_ENABLE);
1997 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1998 if(err < 0)
1999 goto error_out;
2000
2001 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_ENABLE);
2002 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2003 if(err < 0)
2004 goto error_out;
2005
2006 tp->card_state = Running;
2007 smp_wmb();
2008
2009 iowrite32(TYPHOON_INTR_ENABLE_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
2010 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_MASK);
2011 typhoon_post_pci_writes(ioaddr);
2012
2013 return 0;
2014
2015 error_out:
2016 typhoon_reset(ioaddr, WaitNoSleep);
2017 typhoon_free_rx_rings(tp);
2018 typhoon_init_rings(tp);
2019 return err;
2020 }
2021
2022 static int
2023 typhoon_stop_runtime(struct typhoon *tp, int wait_type)
2024 {
2025 struct typhoon_indexes *indexes = tp->indexes;
2026 struct transmit_ring *txLo = &tp->txLoRing;
2027 void __iomem *ioaddr = tp->ioaddr;
2028 struct cmd_desc xp_cmd;
2029 int i;
2030
2031 /* Disable interrupts early, since we can't schedule a poll
2032 * when called with !netif_running(). This will be posted
2033 * when we force the posting of the command.
2034 */
2035 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2036
2037 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_DISABLE);
2038 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2039
2040 /* Wait 1/2 sec for any outstanding transmits to occur
2041 * We'll cleanup after the reset if this times out.
2042 */
2043 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
2044 if(indexes->txLoCleared == cpu_to_le32(txLo->lastWrite))
2045 break;
2046 udelay(TYPHOON_UDELAY);
2047 }
2048
2049 if(i == TYPHOON_WAIT_TIMEOUT)
2050 printk(KERN_ERR
2051 "%s: halt timed out waiting for Tx to complete\n",
2052 tp->name);
2053
2054 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_DISABLE);
2055 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2056
2057 /* save the statistics so when we bring the interface up again,
2058 * the values reported to userspace are correct.
2059 */
2060 tp->card_state = Sleeping;
2061 smp_wmb();
2062 typhoon_do_get_stats(tp);
2063 memcpy(&tp->stats_saved, &tp->stats, sizeof(struct net_device_stats));
2064
2065 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_HALT);
2066 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2067
2068 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_HALTED) < 0)
2069 printk(KERN_ERR "%s: timed out waiting for 3XP to halt\n",
2070 tp->name);
2071
2072 if(typhoon_reset(ioaddr, wait_type) < 0) {
2073 printk(KERN_ERR "%s: unable to reset 3XP\n", tp->name);
2074 return -ETIMEDOUT;
2075 }
2076
2077 /* cleanup any outstanding Tx packets */
2078 if(indexes->txLoCleared != cpu_to_le32(txLo->lastWrite)) {
2079 indexes->txLoCleared = cpu_to_le32(txLo->lastWrite);
2080 typhoon_clean_tx(tp, &tp->txLoRing, &indexes->txLoCleared);
2081 }
2082
2083 return 0;
2084 }
2085
2086 static void
2087 typhoon_tx_timeout(struct net_device *dev)
2088 {
2089 struct typhoon *tp = netdev_priv(dev);
2090
2091 if(typhoon_reset(tp->ioaddr, WaitNoSleep) < 0) {
2092 printk(KERN_WARNING "%s: could not reset in tx timeout\n",
2093 dev->name);
2094 goto truely_dead;
2095 }
2096
2097 /* If we ever start using the Hi ring, it will need cleaning too */
2098 typhoon_clean_tx(tp, &tp->txLoRing, &tp->indexes->txLoCleared);
2099 typhoon_free_rx_rings(tp);
2100
2101 if(typhoon_start_runtime(tp) < 0) {
2102 printk(KERN_ERR "%s: could not start runtime in tx timeout\n",
2103 dev->name);
2104 goto truely_dead;
2105 }
2106
2107 netif_wake_queue(dev);
2108 return;
2109
2110 truely_dead:
2111 /* Reset the hardware, and turn off carrier to avoid more timeouts */
2112 typhoon_reset(tp->ioaddr, NoWait);
2113 netif_carrier_off(dev);
2114 }
2115
2116 static int
2117 typhoon_open(struct net_device *dev)
2118 {
2119 struct typhoon *tp = netdev_priv(dev);
2120 int err;
2121
2122 err = typhoon_wakeup(tp, WaitSleep);
2123 if(err < 0) {
2124 printk(KERN_ERR "%s: unable to wakeup device\n", dev->name);
2125 goto out_sleep;
2126 }
2127
2128 err = request_irq(dev->irq, &typhoon_interrupt, IRQF_SHARED,
2129 dev->name, dev);
2130 if(err < 0)
2131 goto out_sleep;
2132
2133 err = typhoon_start_runtime(tp);
2134 if(err < 0)
2135 goto out_irq;
2136
2137 netif_start_queue(dev);
2138 return 0;
2139
2140 out_irq:
2141 free_irq(dev->irq, dev);
2142
2143 out_sleep:
2144 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2145 printk(KERN_ERR "%s: unable to reboot into sleep img\n",
2146 dev->name);
2147 typhoon_reset(tp->ioaddr, NoWait);
2148 goto out;
2149 }
2150
2151 if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2152 printk(KERN_ERR "%s: unable to go back to sleep\n", dev->name);
2153
2154 out:
2155 return err;
2156 }
2157
2158 static int
2159 typhoon_close(struct net_device *dev)
2160 {
2161 struct typhoon *tp = netdev_priv(dev);
2162
2163 netif_stop_queue(dev);
2164
2165 if(typhoon_stop_runtime(tp, WaitSleep) < 0)
2166 printk(KERN_ERR "%s: unable to stop runtime\n", dev->name);
2167
2168 /* Make sure there is no irq handler running on a different CPU. */
2169 typhoon_synchronize_irq(dev->irq);
2170 free_irq(dev->irq, dev);
2171
2172 typhoon_free_rx_rings(tp);
2173 typhoon_init_rings(tp);
2174
2175 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0)
2176 printk(KERN_ERR "%s: unable to boot sleep image\n", dev->name);
2177
2178 if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2179 printk(KERN_ERR "%s: unable to put card to sleep\n", dev->name);
2180
2181 return 0;
2182 }
2183
2184 #ifdef CONFIG_PM
2185 static int
2186 typhoon_resume(struct pci_dev *pdev)
2187 {
2188 struct net_device *dev = pci_get_drvdata(pdev);
2189 struct typhoon *tp = netdev_priv(dev);
2190
2191 /* If we're down, resume when we are upped.
2192 */
2193 if(!netif_running(dev))
2194 return 0;
2195
2196 if(typhoon_wakeup(tp, WaitNoSleep) < 0) {
2197 printk(KERN_ERR "%s: critical: could not wake up in resume\n",
2198 dev->name);
2199 goto reset;
2200 }
2201
2202 if(typhoon_start_runtime(tp) < 0) {
2203 printk(KERN_ERR "%s: critical: could not start runtime in "
2204 "resume\n", dev->name);
2205 goto reset;
2206 }
2207
2208 netif_device_attach(dev);
2209 netif_start_queue(dev);
2210 return 0;
2211
2212 reset:
2213 typhoon_reset(tp->ioaddr, NoWait);
2214 return -EBUSY;
2215 }
2216
2217 static int
2218 typhoon_suspend(struct pci_dev *pdev, pm_message_t state)
2219 {
2220 struct net_device *dev = pci_get_drvdata(pdev);
2221 struct typhoon *tp = netdev_priv(dev);
2222 struct cmd_desc xp_cmd;
2223
2224 /* If we're down, we're already suspended.
2225 */
2226 if(!netif_running(dev))
2227 return 0;
2228
2229 spin_lock_bh(&tp->state_lock);
2230 if(tp->vlgrp && tp->wol_events & TYPHOON_WAKE_MAGIC_PKT) {
2231 spin_unlock_bh(&tp->state_lock);
2232 printk(KERN_ERR "%s: cannot do WAKE_MAGIC with VLANS\n",
2233 dev->name);
2234 return -EBUSY;
2235 }
2236 spin_unlock_bh(&tp->state_lock);
2237
2238 netif_device_detach(dev);
2239
2240 if(typhoon_stop_runtime(tp, WaitNoSleep) < 0) {
2241 printk(KERN_ERR "%s: unable to stop runtime\n", dev->name);
2242 goto need_resume;
2243 }
2244
2245 typhoon_free_rx_rings(tp);
2246 typhoon_init_rings(tp);
2247
2248 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2249 printk(KERN_ERR "%s: unable to boot sleep image\n", dev->name);
2250 goto need_resume;
2251 }
2252
2253 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
2254 xp_cmd.parm1 = cpu_to_le16(ntohs(*(u16 *)&dev->dev_addr[0]));
2255 xp_cmd.parm2 = cpu_to_le32(ntohl(*(u32 *)&dev->dev_addr[2]));
2256 if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2257 printk(KERN_ERR "%s: unable to set mac address in suspend\n",
2258 dev->name);
2259 goto need_resume;
2260 }
2261
2262 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
2263 xp_cmd.parm1 = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
2264 if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2265 printk(KERN_ERR "%s: unable to set rx filter in suspend\n",
2266 dev->name);
2267 goto need_resume;
2268 }
2269
2270 if(typhoon_sleep(tp, pci_choose_state(pdev, state), tp->wol_events) < 0) {
2271 printk(KERN_ERR "%s: unable to put card to sleep\n", dev->name);
2272 goto need_resume;
2273 }
2274
2275 return 0;
2276
2277 need_resume:
2278 typhoon_resume(pdev);
2279 return -EBUSY;
2280 }
2281
2282 static int
2283 typhoon_enable_wake(struct pci_dev *pdev, pci_power_t state, int enable)
2284 {
2285 return pci_enable_wake(pdev, state, enable);
2286 }
2287 #endif
2288
2289 static int __devinit
2290 typhoon_test_mmio(struct pci_dev *pdev)
2291 {
2292 void __iomem *ioaddr = pci_iomap(pdev, 1, 128);
2293 int mode = 0;
2294 u32 val;
2295
2296 if(!ioaddr)
2297 goto out;
2298
2299 if(ioread32(ioaddr + TYPHOON_REG_STATUS) !=
2300 TYPHOON_STATUS_WAITING_FOR_HOST)
2301 goto out_unmap;
2302
2303 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2304 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2305 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
2306
2307 /* Ok, see if we can change our interrupt status register by
2308 * sending ourselves an interrupt. If so, then MMIO works.
2309 * The 50usec delay is arbitrary -- it could probably be smaller.
2310 */
2311 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2312 if((val & TYPHOON_INTR_SELF) == 0) {
2313 iowrite32(1, ioaddr + TYPHOON_REG_SELF_INTERRUPT);
2314 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2315 udelay(50);
2316 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2317 if(val & TYPHOON_INTR_SELF)
2318 mode = 1;
2319 }
2320
2321 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2322 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2323 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2324 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2325
2326 out_unmap:
2327 pci_iounmap(pdev, ioaddr);
2328
2329 out:
2330 if(!mode)
2331 printk(KERN_INFO PFX "falling back to port IO\n");
2332 return mode;
2333 }
2334
2335 static int __devinit
2336 typhoon_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2337 {
2338 static int did_version = 0;
2339 struct net_device *dev;
2340 struct typhoon *tp;
2341 int card_id = (int) ent->driver_data;
2342 void __iomem *ioaddr;
2343 void *shared;
2344 dma_addr_t shared_dma;
2345 struct cmd_desc xp_cmd;
2346 struct resp_desc xp_resp[3];
2347 int i;
2348 int err = 0;
2349
2350 if(!did_version++)
2351 printk(KERN_INFO "%s", version);
2352
2353 dev = alloc_etherdev(sizeof(*tp));
2354 if(dev == NULL) {
2355 printk(ERR_PFX "%s: unable to alloc new net device\n",
2356 pci_name(pdev));
2357 err = -ENOMEM;
2358 goto error_out;
2359 }
2360 SET_MODULE_OWNER(dev);
2361 SET_NETDEV_DEV(dev, &pdev->dev);
2362
2363 err = pci_enable_device(pdev);
2364 if(err < 0) {
2365 printk(ERR_PFX "%s: unable to enable device\n",
2366 pci_name(pdev));
2367 goto error_out_dev;
2368 }
2369
2370 err = pci_set_mwi(pdev);
2371 if(err < 0) {
2372 printk(ERR_PFX "%s: unable to set MWI\n", pci_name(pdev));
2373 goto error_out_disable;
2374 }
2375
2376 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2377 if(err < 0) {
2378 printk(ERR_PFX "%s: No usable DMA configuration\n",
2379 pci_name(pdev));
2380 goto error_out_mwi;
2381 }
2382
2383 /* sanity checks on IO and MMIO BARs
2384 */
2385 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
2386 printk(ERR_PFX
2387 "%s: region #1 not a PCI IO resource, aborting\n",
2388 pci_name(pdev));
2389 err = -ENODEV;
2390 goto error_out_mwi;
2391 }
2392 if(pci_resource_len(pdev, 0) < 128) {
2393 printk(ERR_PFX "%s: Invalid PCI IO region size, aborting\n",
2394 pci_name(pdev));
2395 err = -ENODEV;
2396 goto error_out_mwi;
2397 }
2398 if(!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
2399 printk(ERR_PFX
2400 "%s: region #1 not a PCI MMIO resource, aborting\n",
2401 pci_name(pdev));
2402 err = -ENODEV;
2403 goto error_out_mwi;
2404 }
2405 if(pci_resource_len(pdev, 1) < 128) {
2406 printk(ERR_PFX "%s: Invalid PCI MMIO region size, aborting\n",
2407 pci_name(pdev));
2408 err = -ENODEV;
2409 goto error_out_mwi;
2410 }
2411
2412 err = pci_request_regions(pdev, "typhoon");
2413 if(err < 0) {
2414 printk(ERR_PFX "%s: could not request regions\n",
2415 pci_name(pdev));
2416 goto error_out_mwi;
2417 }
2418
2419 /* map our registers
2420 */
2421 if(use_mmio != 0 && use_mmio != 1)
2422 use_mmio = typhoon_test_mmio(pdev);
2423
2424 ioaddr = pci_iomap(pdev, use_mmio, 128);
2425 if (!ioaddr) {
2426 printk(ERR_PFX "%s: cannot remap registers, aborting\n",
2427 pci_name(pdev));
2428 err = -EIO;
2429 goto error_out_regions;
2430 }
2431
2432 /* allocate pci dma space for rx and tx descriptor rings
2433 */
2434 shared = pci_alloc_consistent(pdev, sizeof(struct typhoon_shared),
2435 &shared_dma);
2436 if(!shared) {
2437 printk(ERR_PFX "%s: could not allocate DMA memory\n",
2438 pci_name(pdev));
2439 err = -ENOMEM;
2440 goto error_out_remap;
2441 }
2442
2443 dev->irq = pdev->irq;
2444 tp = netdev_priv(dev);
2445 tp->shared = (struct typhoon_shared *) shared;
2446 tp->shared_dma = shared_dma;
2447 tp->pdev = pdev;
2448 tp->tx_pdev = pdev;
2449 tp->ioaddr = ioaddr;
2450 tp->tx_ioaddr = ioaddr;
2451 tp->dev = dev;
2452
2453 /* Init sequence:
2454 * 1) Reset the adapter to clear any bad juju
2455 * 2) Reload the sleep image
2456 * 3) Boot the sleep image
2457 * 4) Get the hardware address.
2458 * 5) Put the card to sleep.
2459 */
2460 if (typhoon_reset(ioaddr, WaitSleep) < 0) {
2461 printk(ERR_PFX "%s: could not reset 3XP\n", pci_name(pdev));
2462 err = -EIO;
2463 goto error_out_dma;
2464 }
2465
2466 /* Now that we've reset the 3XP and are sure it's not going to
2467 * write all over memory, enable bus mastering, and save our
2468 * state for resuming after a suspend.
2469 */
2470 pci_set_master(pdev);
2471 pci_save_state(pdev);
2472
2473 /* dev->name is not valid until we register, but we need to
2474 * use some common routines to initialize the card. So that those
2475 * routines print the right name, we keep our oun pointer to the name
2476 */
2477 tp->name = pci_name(pdev);
2478
2479 typhoon_init_interface(tp);
2480 typhoon_init_rings(tp);
2481
2482 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2483 printk(ERR_PFX "%s: cannot boot 3XP sleep image\n",
2484 pci_name(pdev));
2485 err = -EIO;
2486 goto error_out_reset;
2487 }
2488
2489 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_MAC_ADDRESS);
2490 if(typhoon_issue_command(tp, 1, &xp_cmd, 1, xp_resp) < 0) {
2491 printk(ERR_PFX "%s: cannot read MAC address\n",
2492 pci_name(pdev));
2493 err = -EIO;
2494 goto error_out_reset;
2495 }
2496
2497 *(u16 *)&dev->dev_addr[0] = htons(le16_to_cpu(xp_resp[0].parm1));
2498 *(u32 *)&dev->dev_addr[2] = htonl(le32_to_cpu(xp_resp[0].parm2));
2499
2500 if(!is_valid_ether_addr(dev->dev_addr)) {
2501 printk(ERR_PFX "%s: Could not obtain valid ethernet address, "
2502 "aborting\n", pci_name(pdev));
2503 goto error_out_reset;
2504 }
2505
2506 /* Read the Sleep Image version last, so the response is valid
2507 * later when we print out the version reported.
2508 */
2509 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
2510 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
2511 printk(ERR_PFX "%s: Could not get Sleep Image version\n",
2512 pci_name(pdev));
2513 goto error_out_reset;
2514 }
2515
2516 tp->capabilities = typhoon_card_info[card_id].capabilities;
2517 tp->xcvr_select = TYPHOON_XCVR_AUTONEG;
2518
2519 /* Typhoon 1.0 Sleep Images return one response descriptor to the
2520 * READ_VERSIONS command. Those versions are OK after waking up
2521 * from sleep without needing a reset. Typhoon 1.1+ Sleep Images
2522 * seem to need a little extra help to get started. Since we don't
2523 * know how to nudge it along, just kick it.
2524 */
2525 if(xp_resp[0].numDesc != 0)
2526 tp->capabilities |= TYPHOON_WAKEUP_NEEDS_RESET;
2527
2528 if(typhoon_sleep(tp, PCI_D3hot, 0) < 0) {
2529 printk(ERR_PFX "%s: cannot put adapter to sleep\n",
2530 pci_name(pdev));
2531 err = -EIO;
2532 goto error_out_reset;
2533 }
2534
2535 /* The chip-specific entries in the device structure. */
2536 dev->open = typhoon_open;
2537 dev->hard_start_xmit = typhoon_start_tx;
2538 dev->stop = typhoon_close;
2539 dev->set_multicast_list = typhoon_set_rx_mode;
2540 dev->tx_timeout = typhoon_tx_timeout;
2541 dev->poll = typhoon_poll;
2542 dev->weight = 16;
2543 dev->watchdog_timeo = TX_TIMEOUT;
2544 dev->get_stats = typhoon_get_stats;
2545 dev->set_mac_address = typhoon_set_mac_address;
2546 dev->vlan_rx_register = typhoon_vlan_rx_register;
2547 dev->vlan_rx_kill_vid = typhoon_vlan_rx_kill_vid;
2548 SET_ETHTOOL_OPS(dev, &typhoon_ethtool_ops);
2549
2550 /* We can handle scatter gather, up to 16 entries, and
2551 * we can do IP checksumming (only version 4, doh...)
2552 */
2553 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2554 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2555 dev->features |= NETIF_F_TSO;
2556
2557 if(register_netdev(dev) < 0)
2558 goto error_out_reset;
2559
2560 /* fixup our local name */
2561 tp->name = dev->name;
2562
2563 pci_set_drvdata(pdev, dev);
2564
2565 printk(KERN_INFO "%s: %s at %s 0x%llx, ",
2566 dev->name, typhoon_card_info[card_id].name,
2567 use_mmio ? "MMIO" : "IO",
2568 (unsigned long long)pci_resource_start(pdev, use_mmio));
2569 for(i = 0; i < 5; i++)
2570 printk("%2.2x:", dev->dev_addr[i]);
2571 printk("%2.2x\n", dev->dev_addr[i]);
2572
2573 /* xp_resp still contains the response to the READ_VERSIONS command.
2574 * For debugging, let the user know what version he has.
2575 */
2576 if(xp_resp[0].numDesc == 0) {
2577 /* This is the Typhoon 1.0 type Sleep Image, last 16 bits
2578 * of version is Month/Day of build.
2579 */
2580 u16 monthday = le32_to_cpu(xp_resp[0].parm2) & 0xffff;
2581 printk(KERN_INFO "%s: Typhoon 1.0 Sleep Image built "
2582 "%02u/%02u/2000\n", dev->name, monthday >> 8,
2583 monthday & 0xff);
2584 } else if(xp_resp[0].numDesc == 2) {
2585 /* This is the Typhoon 1.1+ type Sleep Image
2586 */
2587 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
2588 u8 *ver_string = (u8 *) &xp_resp[1];
2589 ver_string[25] = 0;
2590 printk(KERN_INFO "%s: Typhoon 1.1+ Sleep Image version "
2591 "%02x.%03x.%03x %s\n", dev->name, sleep_ver >> 24,
2592 (sleep_ver >> 12) & 0xfff, sleep_ver & 0xfff,
2593 ver_string);
2594 } else {
2595 printk(KERN_WARNING "%s: Unknown Sleep Image version "
2596 "(%u:%04x)\n", dev->name, xp_resp[0].numDesc,
2597 le32_to_cpu(xp_resp[0].parm2));
2598 }
2599
2600 return 0;
2601
2602 error_out_reset:
2603 typhoon_reset(ioaddr, NoWait);
2604
2605 error_out_dma:
2606 pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2607 shared, shared_dma);
2608 error_out_remap:
2609 pci_iounmap(pdev, ioaddr);
2610 error_out_regions:
2611 pci_release_regions(pdev);
2612 error_out_mwi:
2613 pci_clear_mwi(pdev);
2614 error_out_disable:
2615 pci_disable_device(pdev);
2616 error_out_dev:
2617 free_netdev(dev);
2618 error_out:
2619 return err;
2620 }
2621
2622 static void __devexit
2623 typhoon_remove_one(struct pci_dev *pdev)
2624 {
2625 struct net_device *dev = pci_get_drvdata(pdev);
2626 struct typhoon *tp = netdev_priv(dev);
2627
2628 unregister_netdev(dev);
2629 pci_set_power_state(pdev, PCI_D0);
2630 pci_restore_state(pdev);
2631 typhoon_reset(tp->ioaddr, NoWait);
2632 pci_iounmap(pdev, tp->ioaddr);
2633 pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2634 tp->shared, tp->shared_dma);
2635 pci_release_regions(pdev);
2636 pci_clear_mwi(pdev);
2637 pci_disable_device(pdev);
2638 pci_set_drvdata(pdev, NULL);
2639 free_netdev(dev);
2640 }
2641
2642 static struct pci_driver typhoon_driver = {
2643 .name = DRV_MODULE_NAME,
2644 .id_table = typhoon_pci_tbl,
2645 .probe = typhoon_init_one,
2646 .remove = __devexit_p(typhoon_remove_one),
2647 #ifdef CONFIG_PM
2648 .suspend = typhoon_suspend,
2649 .resume = typhoon_resume,
2650 .enable_wake = typhoon_enable_wake,
2651 #endif
2652 };
2653
2654 static int __init
2655 typhoon_init(void)
2656 {
2657 return pci_register_driver(&typhoon_driver);
2658 }
2659
2660 static void __exit
2661 typhoon_cleanup(void)
2662 {
2663 pci_unregister_driver(&typhoon_driver);
2664 }
2665
2666 module_init(typhoon_init);
2667 module_exit(typhoon_cleanup);
x86 "subsystem" repository