2 * linux/arch/arm/mach-omap2/clock2xxx_data.c
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/clk.h>
18 #include <linux/list.h>
20 #include <plat/clkdev_omap.h>
23 #include "clock2xxx.h"
27 #include "prm-regbits-24xx.h"
28 #include "cm-regbits-24xx.h"
31 /*-------------------------------------------------------------------------
34 * NOTE:In many cases here we are assigning a 'default' parent. In many
35 * cases the parent is selectable. The get/set parent calls will also
38 * Many some clocks say always_enabled, but they can be auto idled for
39 * power savings. They will always be available upon clock request.
41 * Several sources are given initial rates which may be wrong, this will
42 * be fixed up in the init func.
44 * Things are broadly separated below by clock domains. It is
45 * noteworthy that most periferals have dependencies on multiple clock
46 * domains. Many get their interface clocks from the L4 domain, but get
47 * functional clocks from fixed sources or other core domain derived
49 *-------------------------------------------------------------------------*/
51 /* Base external input clocks */
52 static struct clk func_32k_ck
= {
53 .name
= "func_32k_ck",
57 .clkdm_name
= "wkup_clkdm",
60 static struct clk secure_32k_ck
= {
61 .name
= "secure_32k_ck",
65 .clkdm_name
= "wkup_clkdm",
68 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
69 static struct clk osc_ck
= { /* (*12, *13, 19.2, *26, 38.4)MHz */
72 .clkdm_name
= "wkup_clkdm",
73 .recalc
= &omap2_osc_clk_recalc
,
76 /* Without modem likely 12MHz, with modem likely 13MHz */
77 static struct clk sys_ck
= { /* (*12, *13, 19.2, 26, 38.4)MHz */
78 .name
= "sys_ck", /* ~ ref_clk also */
81 .clkdm_name
= "wkup_clkdm",
82 .recalc
= &omap2xxx_sys_clk_recalc
,
85 static struct clk alt_ck
= { /* Typical 54M or 48M, may not exist */
90 .clkdm_name
= "wkup_clkdm",
94 * Analog domain root source clocks
97 /* dpll_ck, is broken out in to special cases through clksel */
98 /* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
102 static struct dpll_data dpll_dd
= {
103 .mult_div1_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
104 .mult_mask
= OMAP24XX_DPLL_MULT_MASK
,
105 .div1_mask
= OMAP24XX_DPLL_DIV_MASK
,
106 .clk_bypass
= &sys_ck
,
108 .control_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
109 .enable_mask
= OMAP24XX_EN_DPLL_MASK
,
110 .max_multiplier
= 1023,
113 .rate_tolerance
= DEFAULT_DPLL_RATE_TOLERANCE
117 * XXX Cannot add round_rate here yet, as this is still a composite clock,
120 static struct clk dpll_ck
= {
123 .parent
= &sys_ck
, /* Can be func_32k also */
124 .dpll_data
= &dpll_dd
,
125 .clkdm_name
= "wkup_clkdm",
126 .recalc
= &omap2_dpllcore_recalc
,
127 .set_rate
= &omap2_reprogram_dpllcore
,
130 static struct clk apll96_ck
= {
132 .ops
= &clkops_apll96
,
135 .flags
= RATE_FIXED
| ENABLE_ON_INIT
,
136 .clkdm_name
= "wkup_clkdm",
137 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
138 .enable_bit
= OMAP24XX_EN_96M_PLL_SHIFT
,
141 static struct clk apll54_ck
= {
143 .ops
= &clkops_apll54
,
146 .flags
= RATE_FIXED
| ENABLE_ON_INIT
,
147 .clkdm_name
= "wkup_clkdm",
148 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
149 .enable_bit
= OMAP24XX_EN_54M_PLL_SHIFT
,
153 * PRCM digital base sources
158 static const struct clksel_rate func_54m_apll54_rates
[] = {
159 { .div
= 1, .val
= 0, .flags
= RATE_IN_24XX
| DEFAULT_RATE
},
163 static const struct clksel_rate func_54m_alt_rates
[] = {
164 { .div
= 1, .val
= 1, .flags
= RATE_IN_24XX
| DEFAULT_RATE
},
168 static const struct clksel func_54m_clksel
[] = {
169 { .parent
= &apll54_ck
, .rates
= func_54m_apll54_rates
, },
170 { .parent
= &alt_ck
, .rates
= func_54m_alt_rates
, },
174 static struct clk func_54m_ck
= {
175 .name
= "func_54m_ck",
177 .parent
= &apll54_ck
, /* can also be alt_clk */
178 .clkdm_name
= "wkup_clkdm",
179 .init
= &omap2_init_clksel_parent
,
180 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
181 .clksel_mask
= OMAP24XX_54M_SOURCE
,
182 .clksel
= func_54m_clksel
,
183 .recalc
= &omap2_clksel_recalc
,
186 static struct clk core_ck
= {
189 .parent
= &dpll_ck
, /* can also be 32k */
190 .clkdm_name
= "wkup_clkdm",
191 .recalc
= &followparent_recalc
,
195 static const struct clksel_rate func_96m_apll96_rates
[] = {
196 { .div
= 1, .val
= 0, .flags
= RATE_IN_24XX
| DEFAULT_RATE
},
200 static const struct clksel_rate func_96m_alt_rates
[] = {
201 { .div
= 1, .val
= 1, .flags
= RATE_IN_243X
| DEFAULT_RATE
},
205 static const struct clksel func_96m_clksel
[] = {
206 { .parent
= &apll96_ck
, .rates
= func_96m_apll96_rates
},
207 { .parent
= &alt_ck
, .rates
= func_96m_alt_rates
},
211 /* The parent of this clock is not selectable on 2420. */
212 static struct clk func_96m_ck
= {
213 .name
= "func_96m_ck",
215 .parent
= &apll96_ck
,
216 .clkdm_name
= "wkup_clkdm",
217 .init
= &omap2_init_clksel_parent
,
218 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
219 .clksel_mask
= OMAP2430_96M_SOURCE
,
220 .clksel
= func_96m_clksel
,
221 .recalc
= &omap2_clksel_recalc
,
222 .round_rate
= &omap2_clksel_round_rate
,
223 .set_rate
= &omap2_clksel_set_rate
228 static const struct clksel_rate func_48m_apll96_rates
[] = {
229 { .div
= 2, .val
= 0, .flags
= RATE_IN_24XX
| DEFAULT_RATE
},
233 static const struct clksel_rate func_48m_alt_rates
[] = {
234 { .div
= 1, .val
= 1, .flags
= RATE_IN_24XX
| DEFAULT_RATE
},
238 static const struct clksel func_48m_clksel
[] = {
239 { .parent
= &apll96_ck
, .rates
= func_48m_apll96_rates
},
240 { .parent
= &alt_ck
, .rates
= func_48m_alt_rates
},
244 static struct clk func_48m_ck
= {
245 .name
= "func_48m_ck",
247 .parent
= &apll96_ck
, /* 96M or Alt */
248 .clkdm_name
= "wkup_clkdm",
249 .init
= &omap2_init_clksel_parent
,
250 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
251 .clksel_mask
= OMAP24XX_48M_SOURCE
,
252 .clksel
= func_48m_clksel
,
253 .recalc
= &omap2_clksel_recalc
,
254 .round_rate
= &omap2_clksel_round_rate
,
255 .set_rate
= &omap2_clksel_set_rate
258 static struct clk func_12m_ck
= {
259 .name
= "func_12m_ck",
261 .parent
= &func_48m_ck
,
263 .clkdm_name
= "wkup_clkdm",
264 .recalc
= &omap_fixed_divisor_recalc
,
267 /* Secure timer, only available in secure mode */
268 static struct clk wdt1_osc_ck
= {
269 .name
= "ck_wdt1_osc",
270 .ops
= &clkops_null
, /* RMK: missing? */
272 .recalc
= &followparent_recalc
,
276 * The common_clkout* clksel_rate structs are common to
277 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
278 * sys_clkout2_* are 2420-only, so the
279 * clksel_rate flags fields are inaccurate for those clocks. This is
280 * harmless since access to those clocks are gated by the struct clk
281 * flags fields, which mark them as 2420-only.
283 static const struct clksel_rate common_clkout_src_core_rates
[] = {
284 { .div
= 1, .val
= 0, .flags
= RATE_IN_24XX
| DEFAULT_RATE
},
288 static const struct clksel_rate common_clkout_src_sys_rates
[] = {
289 { .div
= 1, .val
= 1, .flags
= RATE_IN_24XX
| DEFAULT_RATE
},
293 static const struct clksel_rate common_clkout_src_96m_rates
[] = {
294 { .div
= 1, .val
= 2, .flags
= RATE_IN_24XX
| DEFAULT_RATE
},
298 static const struct clksel_rate common_clkout_src_54m_rates
[] = {
299 { .div
= 1, .val
= 3, .flags
= RATE_IN_24XX
| DEFAULT_RATE
},
303 static const struct clksel common_clkout_src_clksel
[] = {
304 { .parent
= &core_ck
, .rates
= common_clkout_src_core_rates
},
305 { .parent
= &sys_ck
, .rates
= common_clkout_src_sys_rates
},
306 { .parent
= &func_96m_ck
, .rates
= common_clkout_src_96m_rates
},
307 { .parent
= &func_54m_ck
, .rates
= common_clkout_src_54m_rates
},
311 static struct clk sys_clkout_src
= {
312 .name
= "sys_clkout_src",
313 .ops
= &clkops_omap2_dflt
,
314 .parent
= &func_54m_ck
,
315 .clkdm_name
= "wkup_clkdm",
316 .enable_reg
= OMAP24XX_PRCM_CLKOUT_CTRL
,
317 .enable_bit
= OMAP24XX_CLKOUT_EN_SHIFT
,
318 .init
= &omap2_init_clksel_parent
,
319 .clksel_reg
= OMAP24XX_PRCM_CLKOUT_CTRL
,
320 .clksel_mask
= OMAP24XX_CLKOUT_SOURCE_MASK
,
321 .clksel
= common_clkout_src_clksel
,
322 .recalc
= &omap2_clksel_recalc
,
323 .round_rate
= &omap2_clksel_round_rate
,
324 .set_rate
= &omap2_clksel_set_rate
327 static const struct clksel_rate common_clkout_rates
[] = {
328 { .div
= 1, .val
= 0, .flags
= RATE_IN_24XX
| DEFAULT_RATE
},
329 { .div
= 2, .val
= 1, .flags
= RATE_IN_24XX
},
330 { .div
= 4, .val
= 2, .flags
= RATE_IN_24XX
},
331 { .div
= 8, .val
= 3, .flags
= RATE_IN_24XX
},
332 { .div
= 16, .val
= 4, .flags
= RATE_IN_24XX
},
336 static const struct clksel sys_clkout_clksel
[] = {
337 { .parent
= &sys_clkout_src
, .rates
= common_clkout_rates
},
341 static struct clk sys_clkout
= {
342 .name
= "sys_clkout",
344 .parent
= &sys_clkout_src
,
345 .clkdm_name
= "wkup_clkdm",
346 .clksel_reg
= OMAP24XX_PRCM_CLKOUT_CTRL
,
347 .clksel_mask
= OMAP24XX_CLKOUT_DIV_MASK
,
348 .clksel
= sys_clkout_clksel
,
349 .recalc
= &omap2_clksel_recalc
,
350 .round_rate
= &omap2_clksel_round_rate
,
351 .set_rate
= &omap2_clksel_set_rate
354 /* In 2430, new in 2420 ES2 */
355 static struct clk sys_clkout2_src
= {
356 .name
= "sys_clkout2_src",
357 .ops
= &clkops_omap2_dflt
,
358 .parent
= &func_54m_ck
,
359 .clkdm_name
= "wkup_clkdm",
360 .enable_reg
= OMAP24XX_PRCM_CLKOUT_CTRL
,
361 .enable_bit
= OMAP2420_CLKOUT2_EN_SHIFT
,
362 .init
= &omap2_init_clksel_parent
,
363 .clksel_reg
= OMAP24XX_PRCM_CLKOUT_CTRL
,
364 .clksel_mask
= OMAP2420_CLKOUT2_SOURCE_MASK
,
365 .clksel
= common_clkout_src_clksel
,
366 .recalc
= &omap2_clksel_recalc
,
367 .round_rate
= &omap2_clksel_round_rate
,
368 .set_rate
= &omap2_clksel_set_rate
371 static const struct clksel sys_clkout2_clksel
[] = {
372 { .parent
= &sys_clkout2_src
, .rates
= common_clkout_rates
},
376 /* In 2430, new in 2420 ES2 */
377 static struct clk sys_clkout2
= {
378 .name
= "sys_clkout2",
380 .parent
= &sys_clkout2_src
,
381 .clkdm_name
= "wkup_clkdm",
382 .clksel_reg
= OMAP24XX_PRCM_CLKOUT_CTRL
,
383 .clksel_mask
= OMAP2420_CLKOUT2_DIV_MASK
,
384 .clksel
= sys_clkout2_clksel
,
385 .recalc
= &omap2_clksel_recalc
,
386 .round_rate
= &omap2_clksel_round_rate
,
387 .set_rate
= &omap2_clksel_set_rate
390 static struct clk emul_ck
= {
392 .ops
= &clkops_omap2_dflt
,
393 .parent
= &func_54m_ck
,
394 .clkdm_name
= "wkup_clkdm",
395 .enable_reg
= OMAP24XX_PRCM_CLKEMUL_CTRL
,
396 .enable_bit
= OMAP24XX_EMULATION_EN_SHIFT
,
397 .recalc
= &followparent_recalc
,
405 * INT_M_FCLK, INT_M_I_CLK
407 * - Individual clocks are hardware managed.
408 * - Base divider comes from: CM_CLKSEL_MPU
411 static const struct clksel_rate mpu_core_rates
[] = {
412 { .div
= 1, .val
= 1, .flags
= RATE_IN_24XX
| DEFAULT_RATE
},
413 { .div
= 2, .val
= 2, .flags
= RATE_IN_24XX
},
414 { .div
= 4, .val
= 4, .flags
= RATE_IN_242X
},
415 { .div
= 6, .val
= 6, .flags
= RATE_IN_242X
},
416 { .div
= 8, .val
= 8, .flags
= RATE_IN_242X
},
420 static const struct clksel mpu_clksel
[] = {
421 { .parent
= &core_ck
, .rates
= mpu_core_rates
},
425 static struct clk mpu_ck
= { /* Control cpu */
429 .flags
= DELAYED_APP
,
430 .clkdm_name
= "mpu_clkdm",
431 .init
= &omap2_init_clksel_parent
,
432 .clksel_reg
= OMAP_CM_REGADDR(MPU_MOD
, CM_CLKSEL
),
433 .clksel_mask
= OMAP24XX_CLKSEL_MPU_MASK
,
434 .clksel
= mpu_clksel
,
435 .recalc
= &omap2_clksel_recalc
,
439 * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
441 * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
442 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
444 * Won't be too specific here. The core clock comes into this block
445 * it is divided then tee'ed. One branch goes directly to xyz enable
446 * controls. The other branch gets further divided by 2 then possibly
447 * routed into a synchronizer and out of clocks abc.
449 static const struct clksel_rate dsp_fck_core_rates
[] = {
450 { .div
= 1, .val
= 1, .flags
= RATE_IN_24XX
| DEFAULT_RATE
},
451 { .div
= 2, .val
= 2, .flags
= RATE_IN_24XX
},
452 { .div
= 3, .val
= 3, .flags
= RATE_IN_24XX
},
453 { .div
= 4, .val
= 4, .flags
= RATE_IN_24XX
},
454 { .div
= 6, .val
= 6, .flags
= RATE_IN_242X
},
455 { .div
= 8, .val
= 8, .flags
= RATE_IN_242X
},
456 { .div
= 12, .val
= 12, .flags
= RATE_IN_242X
},
460 static const struct clksel dsp_fck_clksel
[] = {
461 { .parent
= &core_ck
, .rates
= dsp_fck_core_rates
},
465 static struct clk dsp_fck
= {
467 .ops
= &clkops_omap2_dflt_wait
,
469 .flags
= DELAYED_APP
,
470 .clkdm_name
= "dsp_clkdm",
471 .enable_reg
= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD
, CM_FCLKEN
),
472 .enable_bit
= OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT
,
473 .clksel_reg
= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD
, CM_CLKSEL
),
474 .clksel_mask
= OMAP24XX_CLKSEL_DSP_MASK
,
475 .clksel
= dsp_fck_clksel
,
476 .recalc
= &omap2_clksel_recalc
,
479 /* DSP interface clock */
480 static const struct clksel_rate dsp_irate_ick_rates
[] = {
481 { .div
= 1, .val
= 1, .flags
= RATE_IN_24XX
| DEFAULT_RATE
},
482 { .div
= 2, .val
= 2, .flags
= RATE_IN_24XX
},
483 { .div
= 3, .val
= 3, .flags
= RATE_IN_243X
},
487 static const struct clksel dsp_irate_ick_clksel
[] = {
488 { .parent
= &dsp_fck
, .rates
= dsp_irate_ick_rates
},
492 /* This clock does not exist as such in the TRM. */
493 static struct clk dsp_irate_ick
= {
494 .name
= "dsp_irate_ick",
497 .flags
= DELAYED_APP
,
498 .clksel_reg
= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD
, CM_CLKSEL
),
499 .clksel_mask
= OMAP24XX_CLKSEL_DSP_IF_MASK
,
500 .clksel
= dsp_irate_ick_clksel
,
501 .recalc
= &omap2_clksel_recalc
,
505 static struct clk dsp_ick
= {
506 .name
= "dsp_ick", /* apparently ipi and isp */
507 .ops
= &clkops_omap2_dflt_wait
,
508 .parent
= &dsp_irate_ick
,
509 .enable_reg
= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD
, CM_ICLKEN
),
510 .enable_bit
= OMAP2420_EN_DSP_IPI_SHIFT
, /* for ipi */
513 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
514 static struct clk iva2_1_ick
= {
515 .name
= "iva2_1_ick",
516 .ops
= &clkops_omap2_dflt_wait
,
517 .parent
= &dsp_irate_ick
,
518 .enable_reg
= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD
, CM_FCLKEN
),
519 .enable_bit
= OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT
,
523 * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
524 * the C54x, but which is contained in the DSP powerdomain. Does not
525 * exist on later OMAPs.
527 static struct clk iva1_ifck
= {
529 .ops
= &clkops_omap2_dflt_wait
,
531 .flags
= DELAYED_APP
,
532 .clkdm_name
= "iva1_clkdm",
533 .enable_reg
= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD
, CM_FCLKEN
),
534 .enable_bit
= OMAP2420_EN_IVA_COP_SHIFT
,
535 .clksel_reg
= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD
, CM_CLKSEL
),
536 .clksel_mask
= OMAP2420_CLKSEL_IVA_MASK
,
537 .clksel
= dsp_fck_clksel
,
538 .recalc
= &omap2_clksel_recalc
,
541 /* IVA1 mpu/int/i/f clocks are /2 of parent */
542 static struct clk iva1_mpu_int_ifck
= {
543 .name
= "iva1_mpu_int_ifck",
544 .ops
= &clkops_omap2_dflt_wait
,
545 .parent
= &iva1_ifck
,
546 .clkdm_name
= "iva1_clkdm",
547 .enable_reg
= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD
, CM_FCLKEN
),
548 .enable_bit
= OMAP2420_EN_IVA_MPU_SHIFT
,
550 .recalc
= &omap_fixed_divisor_recalc
,
555 * L3 clocks are used for both interface and functional clocks to
556 * multiple entities. Some of these clocks are completely managed
557 * by hardware, and some others allow software control. Hardware
558 * managed ones general are based on directly CLK_REQ signals and
559 * various auto idle settings. The functional spec sets many of these
560 * as 'tie-high' for their enables.
563 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
568 * GPMC memories and SDRC have timing and clock sensitive registers which
569 * may very well need notification when the clock changes. Currently for low
570 * operating points, these are taken care of in sleep.S.
572 static const struct clksel_rate core_l3_core_rates
[] = {
573 { .div
= 1, .val
= 1, .flags
= RATE_IN_24XX
},
574 { .div
= 2, .val
= 2, .flags
= RATE_IN_242X
},
575 { .div
= 4, .val
= 4, .flags
= RATE_IN_24XX
| DEFAULT_RATE
},
576 { .div
= 6, .val
= 6, .flags
= RATE_IN_24XX
},
577 { .div
= 8, .val
= 8, .flags
= RATE_IN_242X
},
578 { .div
= 12, .val
= 12, .flags
= RATE_IN_242X
},
579 { .div
= 16, .val
= 16, .flags
= RATE_IN_242X
},
583 static const struct clksel core_l3_clksel
[] = {
584 { .parent
= &core_ck
, .rates
= core_l3_core_rates
},
588 static struct clk core_l3_ck
= { /* Used for ick and fck, interconnect */
589 .name
= "core_l3_ck",
592 .flags
= DELAYED_APP
,
593 .clkdm_name
= "core_l3_clkdm",
594 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL1
),
595 .clksel_mask
= OMAP24XX_CLKSEL_L3_MASK
,
596 .clksel
= core_l3_clksel
,
597 .recalc
= &omap2_clksel_recalc
,
601 static const struct clksel_rate usb_l4_ick_core_l3_rates
[] = {
602 { .div
= 1, .val
= 1, .flags
= RATE_IN_24XX
},
603 { .div
= 2, .val
= 2, .flags
= RATE_IN_24XX
| DEFAULT_RATE
},
604 { .div
= 4, .val
= 4, .flags
= RATE_IN_24XX
},
608 static const struct clksel usb_l4_ick_clksel
[] = {
609 { .parent
= &core_l3_ck
, .rates
= usb_l4_ick_core_l3_rates
},
613 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
614 static struct clk usb_l4_ick
= { /* FS-USB interface clock */
615 .name
= "usb_l4_ick",
616 .ops
= &clkops_omap2_dflt_wait
,
617 .parent
= &core_l3_ck
,
618 .flags
= DELAYED_APP
,
619 .clkdm_name
= "core_l4_clkdm",
620 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
621 .enable_bit
= OMAP24XX_EN_USB_SHIFT
,
622 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL1
),
623 .clksel_mask
= OMAP24XX_CLKSEL_USB_MASK
,
624 .clksel
= usb_l4_ick_clksel
,
625 .recalc
= &omap2_clksel_recalc
,
629 * L4 clock management domain
631 * This domain contains lots of interface clocks from the L4 interface, some
632 * functional clocks. Fixed APLL functional source clocks are managed in
635 static const struct clksel_rate l4_core_l3_rates
[] = {
636 { .div
= 1, .val
= 1, .flags
= RATE_IN_24XX
| DEFAULT_RATE
},
637 { .div
= 2, .val
= 2, .flags
= RATE_IN_24XX
},
641 static const struct clksel l4_clksel
[] = {
642 { .parent
= &core_l3_ck
, .rates
= l4_core_l3_rates
},
646 static struct clk l4_ck
= { /* used both as an ick and fck */
649 .parent
= &core_l3_ck
,
650 .flags
= DELAYED_APP
,
651 .clkdm_name
= "core_l4_clkdm",
652 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL1
),
653 .clksel_mask
= OMAP24XX_CLKSEL_L4_MASK
,
655 .recalc
= &omap2_clksel_recalc
,
656 .round_rate
= &omap2_clksel_round_rate
,
657 .set_rate
= &omap2_clksel_set_rate
661 * SSI is in L3 management domain, its direct parent is core not l3,
662 * many core power domain entities are grouped into the L3 clock
664 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
666 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
668 static const struct clksel_rate ssi_ssr_sst_fck_core_rates
[] = {
669 { .div
= 1, .val
= 1, .flags
= RATE_IN_24XX
},
670 { .div
= 2, .val
= 2, .flags
= RATE_IN_24XX
| DEFAULT_RATE
},
671 { .div
= 3, .val
= 3, .flags
= RATE_IN_24XX
},
672 { .div
= 4, .val
= 4, .flags
= RATE_IN_24XX
},
673 { .div
= 5, .val
= 5, .flags
= RATE_IN_243X
},
674 { .div
= 6, .val
= 6, .flags
= RATE_IN_242X
},
675 { .div
= 8, .val
= 8, .flags
= RATE_IN_242X
},
679 static const struct clksel ssi_ssr_sst_fck_clksel
[] = {
680 { .parent
= &core_ck
, .rates
= ssi_ssr_sst_fck_core_rates
},
684 static struct clk ssi_ssr_sst_fck
= {
686 .ops
= &clkops_omap2_dflt_wait
,
688 .flags
= DELAYED_APP
,
689 .clkdm_name
= "core_l3_clkdm",
690 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP24XX_CM_FCLKEN2
),
691 .enable_bit
= OMAP24XX_EN_SSI_SHIFT
,
692 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL1
),
693 .clksel_mask
= OMAP24XX_CLKSEL_SSI_MASK
,
694 .clksel
= ssi_ssr_sst_fck_clksel
,
695 .recalc
= &omap2_clksel_recalc
,
696 .round_rate
= &omap2_clksel_round_rate
,
697 .set_rate
= &omap2_clksel_set_rate
701 * Presumably this is the same as SSI_ICLK.
702 * TRM contradicts itself on what clockdomain SSI_ICLK is in
704 static struct clk ssi_l4_ick
= {
705 .name
= "ssi_l4_ick",
706 .ops
= &clkops_omap2_dflt_wait
,
708 .clkdm_name
= "core_l4_clkdm",
709 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
710 .enable_bit
= OMAP24XX_EN_SSI_SHIFT
,
711 .recalc
= &followparent_recalc
,
719 * GFX_CG1(2d), GFX_CG2(3d)
721 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
722 * The 2d and 3d clocks run at a hardware determined
723 * divided value of fclk.
727 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
728 static const struct clksel gfx_fck_clksel
[] = {
729 { .parent
= &core_l3_ck
, .rates
= gfx_l3_rates
},
733 static struct clk gfx_3d_fck
= {
734 .name
= "gfx_3d_fck",
735 .ops
= &clkops_omap2_dflt_wait
,
736 .parent
= &core_l3_ck
,
737 .clkdm_name
= "gfx_clkdm",
738 .enable_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_FCLKEN
),
739 .enable_bit
= OMAP24XX_EN_3D_SHIFT
,
740 .clksel_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_CLKSEL
),
741 .clksel_mask
= OMAP_CLKSEL_GFX_MASK
,
742 .clksel
= gfx_fck_clksel
,
743 .recalc
= &omap2_clksel_recalc
,
744 .round_rate
= &omap2_clksel_round_rate
,
745 .set_rate
= &omap2_clksel_set_rate
748 static struct clk gfx_2d_fck
= {
749 .name
= "gfx_2d_fck",
750 .ops
= &clkops_omap2_dflt_wait
,
751 .parent
= &core_l3_ck
,
752 .flags
= DELAYED_APP
,
753 .clkdm_name
= "gfx_clkdm",
754 .enable_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_FCLKEN
),
755 .enable_bit
= OMAP24XX_EN_2D_SHIFT
,
756 .clksel_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_CLKSEL
),
757 .clksel_mask
= OMAP_CLKSEL_GFX_MASK
,
758 .clksel
= gfx_fck_clksel
,
759 .recalc
= &omap2_clksel_recalc
,
762 static struct clk gfx_ick
= {
763 .name
= "gfx_ick", /* From l3 */
764 .ops
= &clkops_omap2_dflt_wait
,
765 .parent
= &core_l3_ck
,
766 .clkdm_name
= "gfx_clkdm",
767 .enable_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_ICLKEN
),
768 .enable_bit
= OMAP_EN_GFX_SHIFT
,
769 .recalc
= &followparent_recalc
,
773 * Modem clock domain (2430)
777 * These clocks are usable in chassis mode only.
779 static const struct clksel_rate mdm_ick_core_rates
[] = {
780 { .div
= 1, .val
= 1, .flags
= RATE_IN_243X
},
781 { .div
= 4, .val
= 4, .flags
= RATE_IN_243X
| DEFAULT_RATE
},
782 { .div
= 6, .val
= 6, .flags
= RATE_IN_243X
},
783 { .div
= 9, .val
= 9, .flags
= RATE_IN_243X
},
787 static const struct clksel mdm_ick_clksel
[] = {
788 { .parent
= &core_ck
, .rates
= mdm_ick_core_rates
},
792 static struct clk mdm_ick
= { /* used both as a ick and fck */
794 .ops
= &clkops_omap2_dflt_wait
,
796 .flags
= DELAYED_APP
,
797 .clkdm_name
= "mdm_clkdm",
798 .enable_reg
= OMAP_CM_REGADDR(OMAP2430_MDM_MOD
, CM_ICLKEN
),
799 .enable_bit
= OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT
,
800 .clksel_reg
= OMAP_CM_REGADDR(OMAP2430_MDM_MOD
, CM_CLKSEL
),
801 .clksel_mask
= OMAP2430_CLKSEL_MDM_MASK
,
802 .clksel
= mdm_ick_clksel
,
803 .recalc
= &omap2_clksel_recalc
,
806 static struct clk mdm_osc_ck
= {
807 .name
= "mdm_osc_ck",
808 .ops
= &clkops_omap2_dflt_wait
,
810 .clkdm_name
= "mdm_clkdm",
811 .enable_reg
= OMAP_CM_REGADDR(OMAP2430_MDM_MOD
, CM_FCLKEN
),
812 .enable_bit
= OMAP2430_EN_OSC_SHIFT
,
813 .recalc
= &followparent_recalc
,
819 * DSS_L4_ICLK, DSS_L3_ICLK,
820 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
822 * DSS is both initiator and target.
824 /* XXX Add RATE_NOT_VALIDATED */
826 static const struct clksel_rate dss1_fck_sys_rates
[] = {
827 { .div
= 1, .val
= 0, .flags
= RATE_IN_24XX
| DEFAULT_RATE
},
831 static const struct clksel_rate dss1_fck_core_rates
[] = {
832 { .div
= 1, .val
= 1, .flags
= RATE_IN_24XX
},
833 { .div
= 2, .val
= 2, .flags
= RATE_IN_24XX
},
834 { .div
= 3, .val
= 3, .flags
= RATE_IN_24XX
},
835 { .div
= 4, .val
= 4, .flags
= RATE_IN_24XX
},
836 { .div
= 5, .val
= 5, .flags
= RATE_IN_24XX
},
837 { .div
= 6, .val
= 6, .flags
= RATE_IN_24XX
},
838 { .div
= 8, .val
= 8, .flags
= RATE_IN_24XX
},
839 { .div
= 9, .val
= 9, .flags
= RATE_IN_24XX
},
840 { .div
= 12, .val
= 12, .flags
= RATE_IN_24XX
},
841 { .div
= 16, .val
= 16, .flags
= RATE_IN_24XX
| DEFAULT_RATE
},
845 static const struct clksel dss1_fck_clksel
[] = {
846 { .parent
= &sys_ck
, .rates
= dss1_fck_sys_rates
},
847 { .parent
= &core_ck
, .rates
= dss1_fck_core_rates
},
851 static struct clk dss_ick
= { /* Enables both L3,L4 ICLK's */
853 .ops
= &clkops_omap2_dflt
,
854 .parent
= &l4_ck
, /* really both l3 and l4 */
855 .clkdm_name
= "dss_clkdm",
856 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
857 .enable_bit
= OMAP24XX_EN_DSS1_SHIFT
,
858 .recalc
= &followparent_recalc
,
861 static struct clk dss1_fck
= {
863 .ops
= &clkops_omap2_dflt
,
864 .parent
= &core_ck
, /* Core or sys */
865 .flags
= DELAYED_APP
,
866 .clkdm_name
= "dss_clkdm",
867 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
868 .enable_bit
= OMAP24XX_EN_DSS1_SHIFT
,
869 .init
= &omap2_init_clksel_parent
,
870 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL1
),
871 .clksel_mask
= OMAP24XX_CLKSEL_DSS1_MASK
,
872 .clksel
= dss1_fck_clksel
,
873 .recalc
= &omap2_clksel_recalc
,
874 .round_rate
= &omap2_clksel_round_rate
,
875 .set_rate
= &omap2_clksel_set_rate
878 static const struct clksel_rate dss2_fck_sys_rates
[] = {
879 { .div
= 1, .val
= 0, .flags
= RATE_IN_24XX
| DEFAULT_RATE
},
883 static const struct clksel_rate dss2_fck_48m_rates
[] = {
884 { .div
= 1, .val
= 1, .flags
= RATE_IN_24XX
| DEFAULT_RATE
},
888 static const struct clksel dss2_fck_clksel
[] = {
889 { .parent
= &sys_ck
, .rates
= dss2_fck_sys_rates
},
890 { .parent
= &func_48m_ck
, .rates
= dss2_fck_48m_rates
},
894 static struct clk dss2_fck
= { /* Alt clk used in power management */
896 .ops
= &clkops_omap2_dflt
,
897 .parent
= &sys_ck
, /* fixed at sys_ck or 48MHz */
898 .flags
= DELAYED_APP
,
899 .clkdm_name
= "dss_clkdm",
900 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
901 .enable_bit
= OMAP24XX_EN_DSS2_SHIFT
,
902 .init
= &omap2_init_clksel_parent
,
903 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL1
),
904 .clksel_mask
= OMAP24XX_CLKSEL_DSS2_MASK
,
905 .clksel
= dss2_fck_clksel
,
906 .recalc
= &followparent_recalc
,
909 static struct clk dss_54m_fck
= { /* Alt clk used in power management */
910 .name
= "dss_54m_fck", /* 54m tv clk */
911 .ops
= &clkops_omap2_dflt_wait
,
912 .parent
= &func_54m_ck
,
913 .clkdm_name
= "dss_clkdm",
914 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
915 .enable_bit
= OMAP24XX_EN_TV_SHIFT
,
916 .recalc
= &followparent_recalc
,
920 * CORE power domain ICLK & FCLK defines.
921 * Many of the these can have more than one possible parent. Entries
922 * here will likely have an L4 interface parent, and may have multiple
923 * functional clock parents.
925 static const struct clksel_rate gpt_alt_rates
[] = {
926 { .div
= 1, .val
= 2, .flags
= RATE_IN_24XX
| DEFAULT_RATE
},
930 static const struct clksel omap24xx_gpt_clksel
[] = {
931 { .parent
= &func_32k_ck
, .rates
= gpt_32k_rates
},
932 { .parent
= &sys_ck
, .rates
= gpt_sys_rates
},
933 { .parent
= &alt_ck
, .rates
= gpt_alt_rates
},
937 static struct clk gpt1_ick
= {
939 .ops
= &clkops_omap2_dflt_wait
,
941 .clkdm_name
= "core_l4_clkdm",
942 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
943 .enable_bit
= OMAP24XX_EN_GPT1_SHIFT
,
944 .recalc
= &followparent_recalc
,
947 static struct clk gpt1_fck
= {
949 .ops
= &clkops_omap2_dflt_wait
,
950 .parent
= &func_32k_ck
,
951 .clkdm_name
= "core_l4_clkdm",
952 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
953 .enable_bit
= OMAP24XX_EN_GPT1_SHIFT
,
954 .init
= &omap2_init_clksel_parent
,
955 .clksel_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_CLKSEL1
),
956 .clksel_mask
= OMAP24XX_CLKSEL_GPT1_MASK
,
957 .clksel
= omap24xx_gpt_clksel
,
958 .recalc
= &omap2_clksel_recalc
,
959 .round_rate
= &omap2_clksel_round_rate
,
960 .set_rate
= &omap2_clksel_set_rate
963 static struct clk gpt2_ick
= {
965 .ops
= &clkops_omap2_dflt_wait
,
967 .clkdm_name
= "core_l4_clkdm",
968 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
969 .enable_bit
= OMAP24XX_EN_GPT2_SHIFT
,
970 .recalc
= &followparent_recalc
,
973 static struct clk gpt2_fck
= {
975 .ops
= &clkops_omap2_dflt_wait
,
976 .parent
= &func_32k_ck
,
977 .clkdm_name
= "core_l4_clkdm",
978 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
979 .enable_bit
= OMAP24XX_EN_GPT2_SHIFT
,
980 .init
= &omap2_init_clksel_parent
,
981 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL2
),
982 .clksel_mask
= OMAP24XX_CLKSEL_GPT2_MASK
,
983 .clksel
= omap24xx_gpt_clksel
,
984 .recalc
= &omap2_clksel_recalc
,
987 static struct clk gpt3_ick
= {
989 .ops
= &clkops_omap2_dflt_wait
,
991 .clkdm_name
= "core_l4_clkdm",
992 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
993 .enable_bit
= OMAP24XX_EN_GPT3_SHIFT
,
994 .recalc
= &followparent_recalc
,
997 static struct clk gpt3_fck
= {
999 .ops
= &clkops_omap2_dflt_wait
,
1000 .parent
= &func_32k_ck
,
1001 .clkdm_name
= "core_l4_clkdm",
1002 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1003 .enable_bit
= OMAP24XX_EN_GPT3_SHIFT
,
1004 .init
= &omap2_init_clksel_parent
,
1005 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL2
),
1006 .clksel_mask
= OMAP24XX_CLKSEL_GPT3_MASK
,
1007 .clksel
= omap24xx_gpt_clksel
,
1008 .recalc
= &omap2_clksel_recalc
,
1011 static struct clk gpt4_ick
= {
1013 .ops
= &clkops_omap2_dflt_wait
,
1015 .clkdm_name
= "core_l4_clkdm",
1016 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1017 .enable_bit
= OMAP24XX_EN_GPT4_SHIFT
,
1018 .recalc
= &followparent_recalc
,
1021 static struct clk gpt4_fck
= {
1023 .ops
= &clkops_omap2_dflt_wait
,
1024 .parent
= &func_32k_ck
,
1025 .clkdm_name
= "core_l4_clkdm",
1026 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1027 .enable_bit
= OMAP24XX_EN_GPT4_SHIFT
,
1028 .init
= &omap2_init_clksel_parent
,
1029 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL2
),
1030 .clksel_mask
= OMAP24XX_CLKSEL_GPT4_MASK
,
1031 .clksel
= omap24xx_gpt_clksel
,
1032 .recalc
= &omap2_clksel_recalc
,
1035 static struct clk gpt5_ick
= {
1037 .ops
= &clkops_omap2_dflt_wait
,
1039 .clkdm_name
= "core_l4_clkdm",
1040 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1041 .enable_bit
= OMAP24XX_EN_GPT5_SHIFT
,
1042 .recalc
= &followparent_recalc
,
1045 static struct clk gpt5_fck
= {
1047 .ops
= &clkops_omap2_dflt_wait
,
1048 .parent
= &func_32k_ck
,
1049 .clkdm_name
= "core_l4_clkdm",
1050 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1051 .enable_bit
= OMAP24XX_EN_GPT5_SHIFT
,
1052 .init
= &omap2_init_clksel_parent
,
1053 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL2
),
1054 .clksel_mask
= OMAP24XX_CLKSEL_GPT5_MASK
,
1055 .clksel
= omap24xx_gpt_clksel
,
1056 .recalc
= &omap2_clksel_recalc
,
1059 static struct clk gpt6_ick
= {
1061 .ops
= &clkops_omap2_dflt_wait
,
1063 .clkdm_name
= "core_l4_clkdm",
1064 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1065 .enable_bit
= OMAP24XX_EN_GPT6_SHIFT
,
1066 .recalc
= &followparent_recalc
,
1069 static struct clk gpt6_fck
= {
1071 .ops
= &clkops_omap2_dflt_wait
,
1072 .parent
= &func_32k_ck
,
1073 .clkdm_name
= "core_l4_clkdm",
1074 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1075 .enable_bit
= OMAP24XX_EN_GPT6_SHIFT
,
1076 .init
= &omap2_init_clksel_parent
,
1077 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL2
),
1078 .clksel_mask
= OMAP24XX_CLKSEL_GPT6_MASK
,
1079 .clksel
= omap24xx_gpt_clksel
,
1080 .recalc
= &omap2_clksel_recalc
,
1083 static struct clk gpt7_ick
= {
1085 .ops
= &clkops_omap2_dflt_wait
,
1087 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1088 .enable_bit
= OMAP24XX_EN_GPT7_SHIFT
,
1089 .recalc
= &followparent_recalc
,
1092 static struct clk gpt7_fck
= {
1094 .ops
= &clkops_omap2_dflt_wait
,
1095 .parent
= &func_32k_ck
,
1096 .clkdm_name
= "core_l4_clkdm",
1097 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1098 .enable_bit
= OMAP24XX_EN_GPT7_SHIFT
,
1099 .init
= &omap2_init_clksel_parent
,
1100 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL2
),
1101 .clksel_mask
= OMAP24XX_CLKSEL_GPT7_MASK
,
1102 .clksel
= omap24xx_gpt_clksel
,
1103 .recalc
= &omap2_clksel_recalc
,
1106 static struct clk gpt8_ick
= {
1108 .ops
= &clkops_omap2_dflt_wait
,
1110 .clkdm_name
= "core_l4_clkdm",
1111 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1112 .enable_bit
= OMAP24XX_EN_GPT8_SHIFT
,
1113 .recalc
= &followparent_recalc
,
1116 static struct clk gpt8_fck
= {
1118 .ops
= &clkops_omap2_dflt_wait
,
1119 .parent
= &func_32k_ck
,
1120 .clkdm_name
= "core_l4_clkdm",
1121 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1122 .enable_bit
= OMAP24XX_EN_GPT8_SHIFT
,
1123 .init
= &omap2_init_clksel_parent
,
1124 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL2
),
1125 .clksel_mask
= OMAP24XX_CLKSEL_GPT8_MASK
,
1126 .clksel
= omap24xx_gpt_clksel
,
1127 .recalc
= &omap2_clksel_recalc
,
1130 static struct clk gpt9_ick
= {
1132 .ops
= &clkops_omap2_dflt_wait
,
1134 .clkdm_name
= "core_l4_clkdm",
1135 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1136 .enable_bit
= OMAP24XX_EN_GPT9_SHIFT
,
1137 .recalc
= &followparent_recalc
,
1140 static struct clk gpt9_fck
= {
1142 .ops
= &clkops_omap2_dflt_wait
,
1143 .parent
= &func_32k_ck
,
1144 .clkdm_name
= "core_l4_clkdm",
1145 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1146 .enable_bit
= OMAP24XX_EN_GPT9_SHIFT
,
1147 .init
= &omap2_init_clksel_parent
,
1148 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL2
),
1149 .clksel_mask
= OMAP24XX_CLKSEL_GPT9_MASK
,
1150 .clksel
= omap24xx_gpt_clksel
,
1151 .recalc
= &omap2_clksel_recalc
,
1154 static struct clk gpt10_ick
= {
1155 .name
= "gpt10_ick",
1156 .ops
= &clkops_omap2_dflt_wait
,
1158 .clkdm_name
= "core_l4_clkdm",
1159 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1160 .enable_bit
= OMAP24XX_EN_GPT10_SHIFT
,
1161 .recalc
= &followparent_recalc
,
1164 static struct clk gpt10_fck
= {
1165 .name
= "gpt10_fck",
1166 .ops
= &clkops_omap2_dflt_wait
,
1167 .parent
= &func_32k_ck
,
1168 .clkdm_name
= "core_l4_clkdm",
1169 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1170 .enable_bit
= OMAP24XX_EN_GPT10_SHIFT
,
1171 .init
= &omap2_init_clksel_parent
,
1172 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL2
),
1173 .clksel_mask
= OMAP24XX_CLKSEL_GPT10_MASK
,
1174 .clksel
= omap24xx_gpt_clksel
,
1175 .recalc
= &omap2_clksel_recalc
,
1178 static struct clk gpt11_ick
= {
1179 .name
= "gpt11_ick",
1180 .ops
= &clkops_omap2_dflt_wait
,
1182 .clkdm_name
= "core_l4_clkdm",
1183 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1184 .enable_bit
= OMAP24XX_EN_GPT11_SHIFT
,
1185 .recalc
= &followparent_recalc
,
1188 static struct clk gpt11_fck
= {
1189 .name
= "gpt11_fck",
1190 .ops
= &clkops_omap2_dflt_wait
,
1191 .parent
= &func_32k_ck
,
1192 .clkdm_name
= "core_l4_clkdm",
1193 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1194 .enable_bit
= OMAP24XX_EN_GPT11_SHIFT
,
1195 .init
= &omap2_init_clksel_parent
,
1196 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL2
),
1197 .clksel_mask
= OMAP24XX_CLKSEL_GPT11_MASK
,
1198 .clksel
= omap24xx_gpt_clksel
,
1199 .recalc
= &omap2_clksel_recalc
,
1202 static struct clk gpt12_ick
= {
1203 .name
= "gpt12_ick",
1204 .ops
= &clkops_omap2_dflt_wait
,
1206 .clkdm_name
= "core_l4_clkdm",
1207 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1208 .enable_bit
= OMAP24XX_EN_GPT12_SHIFT
,
1209 .recalc
= &followparent_recalc
,
1212 static struct clk gpt12_fck
= {
1213 .name
= "gpt12_fck",
1214 .ops
= &clkops_omap2_dflt_wait
,
1215 .parent
= &secure_32k_ck
,
1216 .clkdm_name
= "core_l4_clkdm",
1217 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1218 .enable_bit
= OMAP24XX_EN_GPT12_SHIFT
,
1219 .init
= &omap2_init_clksel_parent
,
1220 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL2
),
1221 .clksel_mask
= OMAP24XX_CLKSEL_GPT12_MASK
,
1222 .clksel
= omap24xx_gpt_clksel
,
1223 .recalc
= &omap2_clksel_recalc
,
1226 static struct clk mcbsp1_ick
= {
1227 .name
= "mcbsp1_ick",
1228 .ops
= &clkops_omap2_dflt_wait
,
1230 .clkdm_name
= "core_l4_clkdm",
1231 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1232 .enable_bit
= OMAP24XX_EN_MCBSP1_SHIFT
,
1233 .recalc
= &followparent_recalc
,
1236 static struct clk mcbsp1_fck
= {
1237 .name
= "mcbsp1_fck",
1238 .ops
= &clkops_omap2_dflt_wait
,
1239 .parent
= &func_96m_ck
,
1240 .clkdm_name
= "core_l4_clkdm",
1241 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1242 .enable_bit
= OMAP24XX_EN_MCBSP1_SHIFT
,
1243 .recalc
= &followparent_recalc
,
1246 static struct clk mcbsp2_ick
= {
1247 .name
= "mcbsp2_ick",
1248 .ops
= &clkops_omap2_dflt_wait
,
1250 .clkdm_name
= "core_l4_clkdm",
1251 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1252 .enable_bit
= OMAP24XX_EN_MCBSP2_SHIFT
,
1253 .recalc
= &followparent_recalc
,
1256 static struct clk mcbsp2_fck
= {
1257 .name
= "mcbsp2_fck",
1258 .ops
= &clkops_omap2_dflt_wait
,
1259 .parent
= &func_96m_ck
,
1260 .clkdm_name
= "core_l4_clkdm",
1261 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1262 .enable_bit
= OMAP24XX_EN_MCBSP2_SHIFT
,
1263 .recalc
= &followparent_recalc
,
1266 static struct clk mcbsp3_ick
= {
1267 .name
= "mcbsp3_ick",
1268 .ops
= &clkops_omap2_dflt_wait
,
1270 .clkdm_name
= "core_l4_clkdm",
1271 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
1272 .enable_bit
= OMAP2430_EN_MCBSP3_SHIFT
,
1273 .recalc
= &followparent_recalc
,
1276 static struct clk mcbsp3_fck
= {
1277 .name
= "mcbsp3_fck",
1278 .ops
= &clkops_omap2_dflt_wait
,
1279 .parent
= &func_96m_ck
,
1280 .clkdm_name
= "core_l4_clkdm",
1281 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP24XX_CM_FCLKEN2
),
1282 .enable_bit
= OMAP2430_EN_MCBSP3_SHIFT
,
1283 .recalc
= &followparent_recalc
,
1286 static struct clk mcbsp4_ick
= {
1287 .name
= "mcbsp4_ick",
1288 .ops
= &clkops_omap2_dflt_wait
,
1290 .clkdm_name
= "core_l4_clkdm",
1291 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
1292 .enable_bit
= OMAP2430_EN_MCBSP4_SHIFT
,
1293 .recalc
= &followparent_recalc
,
1296 static struct clk mcbsp4_fck
= {
1297 .name
= "mcbsp4_fck",
1298 .ops
= &clkops_omap2_dflt_wait
,
1299 .parent
= &func_96m_ck
,
1300 .clkdm_name
= "core_l4_clkdm",
1301 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP24XX_CM_FCLKEN2
),
1302 .enable_bit
= OMAP2430_EN_MCBSP4_SHIFT
,
1303 .recalc
= &followparent_recalc
,
1306 static struct clk mcbsp5_ick
= {
1307 .name
= "mcbsp5_ick",
1308 .ops
= &clkops_omap2_dflt_wait
,
1310 .clkdm_name
= "core_l4_clkdm",
1311 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
1312 .enable_bit
= OMAP2430_EN_MCBSP5_SHIFT
,
1313 .recalc
= &followparent_recalc
,
1316 static struct clk mcbsp5_fck
= {
1317 .name
= "mcbsp5_fck",
1318 .ops
= &clkops_omap2_dflt_wait
,
1319 .parent
= &func_96m_ck
,
1320 .clkdm_name
= "core_l4_clkdm",
1321 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP24XX_CM_FCLKEN2
),
1322 .enable_bit
= OMAP2430_EN_MCBSP5_SHIFT
,
1323 .recalc
= &followparent_recalc
,
1326 static struct clk mcspi1_ick
= {
1327 .name
= "mcspi1_ick",
1328 .ops
= &clkops_omap2_dflt_wait
,
1330 .clkdm_name
= "core_l4_clkdm",
1331 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1332 .enable_bit
= OMAP24XX_EN_MCSPI1_SHIFT
,
1333 .recalc
= &followparent_recalc
,
1336 static struct clk mcspi1_fck
= {
1337 .name
= "mcspi1_fck",
1338 .ops
= &clkops_omap2_dflt_wait
,
1339 .parent
= &func_48m_ck
,
1340 .clkdm_name
= "core_l4_clkdm",
1341 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1342 .enable_bit
= OMAP24XX_EN_MCSPI1_SHIFT
,
1343 .recalc
= &followparent_recalc
,
1346 static struct clk mcspi2_ick
= {
1347 .name
= "mcspi2_ick",
1348 .ops
= &clkops_omap2_dflt_wait
,
1350 .clkdm_name
= "core_l4_clkdm",
1351 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1352 .enable_bit
= OMAP24XX_EN_MCSPI2_SHIFT
,
1353 .recalc
= &followparent_recalc
,
1356 static struct clk mcspi2_fck
= {
1357 .name
= "mcspi2_fck",
1358 .ops
= &clkops_omap2_dflt_wait
,
1359 .parent
= &func_48m_ck
,
1360 .clkdm_name
= "core_l4_clkdm",
1361 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1362 .enable_bit
= OMAP24XX_EN_MCSPI2_SHIFT
,
1363 .recalc
= &followparent_recalc
,
1366 static struct clk mcspi3_ick
= {
1367 .name
= "mcspi3_ick",
1368 .ops
= &clkops_omap2_dflt_wait
,
1370 .clkdm_name
= "core_l4_clkdm",
1371 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
1372 .enable_bit
= OMAP2430_EN_MCSPI3_SHIFT
,
1373 .recalc
= &followparent_recalc
,
1376 static struct clk mcspi3_fck
= {
1377 .name
= "mcspi3_fck",
1378 .ops
= &clkops_omap2_dflt_wait
,
1379 .parent
= &func_48m_ck
,
1380 .clkdm_name
= "core_l4_clkdm",
1381 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP24XX_CM_FCLKEN2
),
1382 .enable_bit
= OMAP2430_EN_MCSPI3_SHIFT
,
1383 .recalc
= &followparent_recalc
,
1386 static struct clk uart1_ick
= {
1387 .name
= "uart1_ick",
1388 .ops
= &clkops_omap2_dflt_wait
,
1390 .clkdm_name
= "core_l4_clkdm",
1391 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1392 .enable_bit
= OMAP24XX_EN_UART1_SHIFT
,
1393 .recalc
= &followparent_recalc
,
1396 static struct clk uart1_fck
= {
1397 .name
= "uart1_fck",
1398 .ops
= &clkops_omap2_dflt_wait
,
1399 .parent
= &func_48m_ck
,
1400 .clkdm_name
= "core_l4_clkdm",
1401 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1402 .enable_bit
= OMAP24XX_EN_UART1_SHIFT
,
1403 .recalc
= &followparent_recalc
,
1406 static struct clk uart2_ick
= {
1407 .name
= "uart2_ick",
1408 .ops
= &clkops_omap2_dflt_wait
,
1410 .clkdm_name
= "core_l4_clkdm",
1411 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1412 .enable_bit
= OMAP24XX_EN_UART2_SHIFT
,
1413 .recalc
= &followparent_recalc
,
1416 static struct clk uart2_fck
= {
1417 .name
= "uart2_fck",
1418 .ops
= &clkops_omap2_dflt_wait
,
1419 .parent
= &func_48m_ck
,
1420 .clkdm_name
= "core_l4_clkdm",
1421 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1422 .enable_bit
= OMAP24XX_EN_UART2_SHIFT
,
1423 .recalc
= &followparent_recalc
,
1426 static struct clk uart3_ick
= {
1427 .name
= "uart3_ick",
1428 .ops
= &clkops_omap2_dflt_wait
,
1430 .clkdm_name
= "core_l4_clkdm",
1431 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
1432 .enable_bit
= OMAP24XX_EN_UART3_SHIFT
,
1433 .recalc
= &followparent_recalc
,
1436 static struct clk uart3_fck
= {
1437 .name
= "uart3_fck",
1438 .ops
= &clkops_omap2_dflt_wait
,
1439 .parent
= &func_48m_ck
,
1440 .clkdm_name
= "core_l4_clkdm",
1441 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP24XX_CM_FCLKEN2
),
1442 .enable_bit
= OMAP24XX_EN_UART3_SHIFT
,
1443 .recalc
= &followparent_recalc
,
1446 static struct clk gpios_ick
= {
1447 .name
= "gpios_ick",
1448 .ops
= &clkops_omap2_dflt_wait
,
1450 .clkdm_name
= "core_l4_clkdm",
1451 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
1452 .enable_bit
= OMAP24XX_EN_GPIOS_SHIFT
,
1453 .recalc
= &followparent_recalc
,
1456 static struct clk gpios_fck
= {
1457 .name
= "gpios_fck",
1458 .ops
= &clkops_omap2_dflt_wait
,
1459 .parent
= &func_32k_ck
,
1460 .clkdm_name
= "wkup_clkdm",
1461 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
1462 .enable_bit
= OMAP24XX_EN_GPIOS_SHIFT
,
1463 .recalc
= &followparent_recalc
,
1466 static struct clk mpu_wdt_ick
= {
1467 .name
= "mpu_wdt_ick",
1468 .ops
= &clkops_omap2_dflt_wait
,
1470 .clkdm_name
= "core_l4_clkdm",
1471 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
1472 .enable_bit
= OMAP24XX_EN_MPU_WDT_SHIFT
,
1473 .recalc
= &followparent_recalc
,
1476 static struct clk mpu_wdt_fck
= {
1477 .name
= "mpu_wdt_fck",
1478 .ops
= &clkops_omap2_dflt_wait
,
1479 .parent
= &func_32k_ck
,
1480 .clkdm_name
= "wkup_clkdm",
1481 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
1482 .enable_bit
= OMAP24XX_EN_MPU_WDT_SHIFT
,
1483 .recalc
= &followparent_recalc
,
1486 static struct clk sync_32k_ick
= {
1487 .name
= "sync_32k_ick",
1488 .ops
= &clkops_omap2_dflt_wait
,
1490 .flags
= ENABLE_ON_INIT
,
1491 .clkdm_name
= "core_l4_clkdm",
1492 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
1493 .enable_bit
= OMAP24XX_EN_32KSYNC_SHIFT
,
1494 .recalc
= &followparent_recalc
,
1497 static struct clk wdt1_ick
= {
1499 .ops
= &clkops_omap2_dflt_wait
,
1501 .clkdm_name
= "core_l4_clkdm",
1502 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
1503 .enable_bit
= OMAP24XX_EN_WDT1_SHIFT
,
1504 .recalc
= &followparent_recalc
,
1507 static struct clk omapctrl_ick
= {
1508 .name
= "omapctrl_ick",
1509 .ops
= &clkops_omap2_dflt_wait
,
1511 .flags
= ENABLE_ON_INIT
,
1512 .clkdm_name
= "core_l4_clkdm",
1513 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
1514 .enable_bit
= OMAP24XX_EN_OMAPCTRL_SHIFT
,
1515 .recalc
= &followparent_recalc
,
1518 static struct clk icr_ick
= {
1520 .ops
= &clkops_omap2_dflt_wait
,
1522 .clkdm_name
= "core_l4_clkdm",
1523 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
1524 .enable_bit
= OMAP2430_EN_ICR_SHIFT
,
1525 .recalc
= &followparent_recalc
,
1528 static struct clk cam_ick
= {
1530 .ops
= &clkops_omap2_dflt
,
1532 .clkdm_name
= "core_l4_clkdm",
1533 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1534 .enable_bit
= OMAP24XX_EN_CAM_SHIFT
,
1535 .recalc
= &followparent_recalc
,
1539 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
1540 * split into two separate clocks, since the parent clocks are different
1541 * and the clockdomains are also different.
1543 static struct clk cam_fck
= {
1545 .ops
= &clkops_omap2_dflt
,
1546 .parent
= &func_96m_ck
,
1547 .clkdm_name
= "core_l3_clkdm",
1548 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1549 .enable_bit
= OMAP24XX_EN_CAM_SHIFT
,
1550 .recalc
= &followparent_recalc
,
1553 static struct clk mailboxes_ick
= {
1554 .name
= "mailboxes_ick",
1555 .ops
= &clkops_omap2_dflt_wait
,
1557 .clkdm_name
= "core_l4_clkdm",
1558 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1559 .enable_bit
= OMAP24XX_EN_MAILBOXES_SHIFT
,
1560 .recalc
= &followparent_recalc
,
1563 static struct clk wdt4_ick
= {
1565 .ops
= &clkops_omap2_dflt_wait
,
1567 .clkdm_name
= "core_l4_clkdm",
1568 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1569 .enable_bit
= OMAP24XX_EN_WDT4_SHIFT
,
1570 .recalc
= &followparent_recalc
,
1573 static struct clk wdt4_fck
= {
1575 .ops
= &clkops_omap2_dflt_wait
,
1576 .parent
= &func_32k_ck
,
1577 .clkdm_name
= "core_l4_clkdm",
1578 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1579 .enable_bit
= OMAP24XX_EN_WDT4_SHIFT
,
1580 .recalc
= &followparent_recalc
,
1583 static struct clk wdt3_ick
= {
1585 .ops
= &clkops_omap2_dflt_wait
,
1587 .clkdm_name
= "core_l4_clkdm",
1588 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1589 .enable_bit
= OMAP2420_EN_WDT3_SHIFT
,
1590 .recalc
= &followparent_recalc
,
1593 static struct clk wdt3_fck
= {
1595 .ops
= &clkops_omap2_dflt_wait
,
1596 .parent
= &func_32k_ck
,
1597 .clkdm_name
= "core_l4_clkdm",
1598 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1599 .enable_bit
= OMAP2420_EN_WDT3_SHIFT
,
1600 .recalc
= &followparent_recalc
,
1603 static struct clk mspro_ick
= {
1604 .name
= "mspro_ick",
1605 .ops
= &clkops_omap2_dflt_wait
,
1607 .clkdm_name
= "core_l4_clkdm",
1608 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1609 .enable_bit
= OMAP24XX_EN_MSPRO_SHIFT
,
1610 .recalc
= &followparent_recalc
,
1613 static struct clk mspro_fck
= {
1614 .name
= "mspro_fck",
1615 .ops
= &clkops_omap2_dflt_wait
,
1616 .parent
= &func_96m_ck
,
1617 .clkdm_name
= "core_l4_clkdm",
1618 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1619 .enable_bit
= OMAP24XX_EN_MSPRO_SHIFT
,
1620 .recalc
= &followparent_recalc
,
1623 static struct clk mmc_ick
= {
1625 .ops
= &clkops_omap2_dflt_wait
,
1627 .clkdm_name
= "core_l4_clkdm",
1628 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1629 .enable_bit
= OMAP2420_EN_MMC_SHIFT
,
1630 .recalc
= &followparent_recalc
,
1633 static struct clk mmc_fck
= {
1635 .ops
= &clkops_omap2_dflt_wait
,
1636 .parent
= &func_96m_ck
,
1637 .clkdm_name
= "core_l4_clkdm",
1638 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1639 .enable_bit
= OMAP2420_EN_MMC_SHIFT
,
1640 .recalc
= &followparent_recalc
,
1643 static struct clk fac_ick
= {
1645 .ops
= &clkops_omap2_dflt_wait
,
1647 .clkdm_name
= "core_l4_clkdm",
1648 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1649 .enable_bit
= OMAP24XX_EN_FAC_SHIFT
,
1650 .recalc
= &followparent_recalc
,
1653 static struct clk fac_fck
= {
1655 .ops
= &clkops_omap2_dflt_wait
,
1656 .parent
= &func_12m_ck
,
1657 .clkdm_name
= "core_l4_clkdm",
1658 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1659 .enable_bit
= OMAP24XX_EN_FAC_SHIFT
,
1660 .recalc
= &followparent_recalc
,
1663 static struct clk eac_ick
= {
1665 .ops
= &clkops_omap2_dflt_wait
,
1667 .clkdm_name
= "core_l4_clkdm",
1668 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1669 .enable_bit
= OMAP2420_EN_EAC_SHIFT
,
1670 .recalc
= &followparent_recalc
,
1673 static struct clk eac_fck
= {
1675 .ops
= &clkops_omap2_dflt_wait
,
1676 .parent
= &func_96m_ck
,
1677 .clkdm_name
= "core_l4_clkdm",
1678 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1679 .enable_bit
= OMAP2420_EN_EAC_SHIFT
,
1680 .recalc
= &followparent_recalc
,
1683 static struct clk hdq_ick
= {
1685 .ops
= &clkops_omap2_dflt_wait
,
1687 .clkdm_name
= "core_l4_clkdm",
1688 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1689 .enable_bit
= OMAP24XX_EN_HDQ_SHIFT
,
1690 .recalc
= &followparent_recalc
,
1693 static struct clk hdq_fck
= {
1695 .ops
= &clkops_omap2_dflt_wait
,
1696 .parent
= &func_12m_ck
,
1697 .clkdm_name
= "core_l4_clkdm",
1698 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1699 .enable_bit
= OMAP24XX_EN_HDQ_SHIFT
,
1700 .recalc
= &followparent_recalc
,
1703 static struct clk i2c2_ick
= {
1705 .ops
= &clkops_omap2_dflt_wait
,
1707 .clkdm_name
= "core_l4_clkdm",
1708 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1709 .enable_bit
= OMAP2420_EN_I2C2_SHIFT
,
1710 .recalc
= &followparent_recalc
,
1713 static struct clk i2c2_fck
= {
1715 .ops
= &clkops_omap2_dflt_wait
,
1716 .parent
= &func_12m_ck
,
1717 .clkdm_name
= "core_l4_clkdm",
1718 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1719 .enable_bit
= OMAP2420_EN_I2C2_SHIFT
,
1720 .recalc
= &followparent_recalc
,
1723 static struct clk i2chs2_fck
= {
1724 .name
= "i2chs2_fck",
1725 .ops
= &clkops_omap2430_i2chs_wait
,
1726 .parent
= &func_96m_ck
,
1727 .clkdm_name
= "core_l4_clkdm",
1728 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP24XX_CM_FCLKEN2
),
1729 .enable_bit
= OMAP2430_EN_I2CHS2_SHIFT
,
1730 .recalc
= &followparent_recalc
,
1733 static struct clk i2c1_ick
= {
1735 .ops
= &clkops_omap2_dflt_wait
,
1737 .clkdm_name
= "core_l4_clkdm",
1738 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1739 .enable_bit
= OMAP2420_EN_I2C1_SHIFT
,
1740 .recalc
= &followparent_recalc
,
1743 static struct clk i2c1_fck
= {
1745 .ops
= &clkops_omap2_dflt_wait
,
1746 .parent
= &func_12m_ck
,
1747 .clkdm_name
= "core_l4_clkdm",
1748 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1749 .enable_bit
= OMAP2420_EN_I2C1_SHIFT
,
1750 .recalc
= &followparent_recalc
,
1753 static struct clk i2chs1_fck
= {
1754 .name
= "i2chs1_fck",
1755 .ops
= &clkops_omap2430_i2chs_wait
,
1756 .parent
= &func_96m_ck
,
1757 .clkdm_name
= "core_l4_clkdm",
1758 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP24XX_CM_FCLKEN2
),
1759 .enable_bit
= OMAP2430_EN_I2CHS1_SHIFT
,
1760 .recalc
= &followparent_recalc
,
1763 static struct clk gpmc_fck
= {
1765 .ops
= &clkops_null
, /* RMK: missing? */
1766 .parent
= &core_l3_ck
,
1767 .flags
= ENABLE_ON_INIT
,
1768 .clkdm_name
= "core_l3_clkdm",
1769 .recalc
= &followparent_recalc
,
1772 static struct clk sdma_fck
= {
1774 .ops
= &clkops_null
, /* RMK: missing? */
1775 .parent
= &core_l3_ck
,
1776 .clkdm_name
= "core_l3_clkdm",
1777 .recalc
= &followparent_recalc
,
1780 static struct clk sdma_ick
= {
1782 .ops
= &clkops_null
, /* RMK: missing? */
1784 .clkdm_name
= "core_l3_clkdm",
1785 .recalc
= &followparent_recalc
,
1788 static struct clk vlynq_ick
= {
1789 .name
= "vlynq_ick",
1790 .ops
= &clkops_omap2_dflt_wait
,
1791 .parent
= &core_l3_ck
,
1792 .clkdm_name
= "core_l3_clkdm",
1793 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1794 .enable_bit
= OMAP2420_EN_VLYNQ_SHIFT
,
1795 .recalc
= &followparent_recalc
,
1798 static const struct clksel_rate vlynq_fck_96m_rates
[] = {
1799 { .div
= 1, .val
= 0, .flags
= RATE_IN_242X
| DEFAULT_RATE
},
1803 static const struct clksel_rate vlynq_fck_core_rates
[] = {
1804 { .div
= 1, .val
= 1, .flags
= RATE_IN_242X
},
1805 { .div
= 2, .val
= 2, .flags
= RATE_IN_242X
},
1806 { .div
= 3, .val
= 3, .flags
= RATE_IN_242X
},
1807 { .div
= 4, .val
= 4, .flags
= RATE_IN_242X
},
1808 { .div
= 6, .val
= 6, .flags
= RATE_IN_242X
},
1809 { .div
= 8, .val
= 8, .flags
= RATE_IN_242X
},
1810 { .div
= 9, .val
= 9, .flags
= RATE_IN_242X
},
1811 { .div
= 12, .val
= 12, .flags
= RATE_IN_242X
},
1812 { .div
= 16, .val
= 16, .flags
= RATE_IN_242X
| DEFAULT_RATE
},
1813 { .div
= 18, .val
= 18, .flags
= RATE_IN_242X
},
1817 static const struct clksel vlynq_fck_clksel
[] = {
1818 { .parent
= &func_96m_ck
, .rates
= vlynq_fck_96m_rates
},
1819 { .parent
= &core_ck
, .rates
= vlynq_fck_core_rates
},
1823 static struct clk vlynq_fck
= {
1824 .name
= "vlynq_fck",
1825 .ops
= &clkops_omap2_dflt_wait
,
1826 .parent
= &func_96m_ck
,
1827 .flags
= DELAYED_APP
,
1828 .clkdm_name
= "core_l3_clkdm",
1829 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1830 .enable_bit
= OMAP2420_EN_VLYNQ_SHIFT
,
1831 .init
= &omap2_init_clksel_parent
,
1832 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL1
),
1833 .clksel_mask
= OMAP2420_CLKSEL_VLYNQ_MASK
,
1834 .clksel
= vlynq_fck_clksel
,
1835 .recalc
= &omap2_clksel_recalc
,
1836 .round_rate
= &omap2_clksel_round_rate
,
1837 .set_rate
= &omap2_clksel_set_rate
1840 static struct clk sdrc_ick
= {
1842 .ops
= &clkops_omap2_dflt_wait
,
1844 .flags
= ENABLE_ON_INIT
,
1845 .clkdm_name
= "core_l4_clkdm",
1846 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN3
),
1847 .enable_bit
= OMAP2430_EN_SDRC_SHIFT
,
1848 .recalc
= &followparent_recalc
,
1851 static struct clk des_ick
= {
1853 .ops
= &clkops_omap2_dflt_wait
,
1855 .clkdm_name
= "core_l4_clkdm",
1856 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP24XX_CM_ICLKEN4
),
1857 .enable_bit
= OMAP24XX_EN_DES_SHIFT
,
1858 .recalc
= &followparent_recalc
,
1861 static struct clk sha_ick
= {
1863 .ops
= &clkops_omap2_dflt_wait
,
1865 .clkdm_name
= "core_l4_clkdm",
1866 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP24XX_CM_ICLKEN4
),
1867 .enable_bit
= OMAP24XX_EN_SHA_SHIFT
,
1868 .recalc
= &followparent_recalc
,
1871 static struct clk rng_ick
= {
1873 .ops
= &clkops_omap2_dflt_wait
,
1875 .clkdm_name
= "core_l4_clkdm",
1876 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP24XX_CM_ICLKEN4
),
1877 .enable_bit
= OMAP24XX_EN_RNG_SHIFT
,
1878 .recalc
= &followparent_recalc
,
1881 static struct clk aes_ick
= {
1883 .ops
= &clkops_omap2_dflt_wait
,
1885 .clkdm_name
= "core_l4_clkdm",
1886 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP24XX_CM_ICLKEN4
),
1887 .enable_bit
= OMAP24XX_EN_AES_SHIFT
,
1888 .recalc
= &followparent_recalc
,
1891 static struct clk pka_ick
= {
1893 .ops
= &clkops_omap2_dflt_wait
,
1895 .clkdm_name
= "core_l4_clkdm",
1896 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP24XX_CM_ICLKEN4
),
1897 .enable_bit
= OMAP24XX_EN_PKA_SHIFT
,
1898 .recalc
= &followparent_recalc
,
1901 static struct clk usb_fck
= {
1903 .ops
= &clkops_omap2_dflt_wait
,
1904 .parent
= &func_48m_ck
,
1905 .clkdm_name
= "core_l3_clkdm",
1906 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP24XX_CM_FCLKEN2
),
1907 .enable_bit
= OMAP24XX_EN_USB_SHIFT
,
1908 .recalc
= &followparent_recalc
,
1911 static struct clk usbhs_ick
= {
1912 .name
= "usbhs_ick",
1913 .ops
= &clkops_omap2_dflt_wait
,
1914 .parent
= &core_l3_ck
,
1915 .clkdm_name
= "core_l3_clkdm",
1916 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
1917 .enable_bit
= OMAP2430_EN_USBHS_SHIFT
,
1918 .recalc
= &followparent_recalc
,
1921 static struct clk mmchs1_ick
= {
1922 .name
= "mmchs1_ick",
1923 .ops
= &clkops_omap2_dflt_wait
,
1925 .clkdm_name
= "core_l4_clkdm",
1926 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
1927 .enable_bit
= OMAP2430_EN_MMCHS1_SHIFT
,
1928 .recalc
= &followparent_recalc
,
1931 static struct clk mmchs1_fck
= {
1932 .name
= "mmchs1_fck",
1933 .ops
= &clkops_omap2_dflt_wait
,
1934 .parent
= &func_96m_ck
,
1935 .clkdm_name
= "core_l3_clkdm",
1936 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP24XX_CM_FCLKEN2
),
1937 .enable_bit
= OMAP2430_EN_MMCHS1_SHIFT
,
1938 .recalc
= &followparent_recalc
,
1941 static struct clk mmchs2_ick
= {
1942 .name
= "mmchs2_ick",
1943 .ops
= &clkops_omap2_dflt_wait
,
1945 .clkdm_name
= "core_l4_clkdm",
1946 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
1947 .enable_bit
= OMAP2430_EN_MMCHS2_SHIFT
,
1948 .recalc
= &followparent_recalc
,
1951 static struct clk mmchs2_fck
= {
1952 .name
= "mmchs2_fck",
1953 .ops
= &clkops_omap2_dflt_wait
,
1954 .parent
= &func_96m_ck
,
1955 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP24XX_CM_FCLKEN2
),
1956 .enable_bit
= OMAP2430_EN_MMCHS2_SHIFT
,
1957 .recalc
= &followparent_recalc
,
1960 static struct clk gpio5_ick
= {
1961 .name
= "gpio5_ick",
1962 .ops
= &clkops_omap2_dflt_wait
,
1964 .clkdm_name
= "core_l4_clkdm",
1965 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
1966 .enable_bit
= OMAP2430_EN_GPIO5_SHIFT
,
1967 .recalc
= &followparent_recalc
,
1970 static struct clk gpio5_fck
= {
1971 .name
= "gpio5_fck",
1972 .ops
= &clkops_omap2_dflt_wait
,
1973 .parent
= &func_32k_ck
,
1974 .clkdm_name
= "core_l4_clkdm",
1975 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP24XX_CM_FCLKEN2
),
1976 .enable_bit
= OMAP2430_EN_GPIO5_SHIFT
,
1977 .recalc
= &followparent_recalc
,
1980 static struct clk mdm_intc_ick
= {
1981 .name
= "mdm_intc_ick",
1982 .ops
= &clkops_omap2_dflt_wait
,
1984 .clkdm_name
= "core_l4_clkdm",
1985 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
1986 .enable_bit
= OMAP2430_EN_MDM_INTC_SHIFT
,
1987 .recalc
= &followparent_recalc
,
1990 static struct clk mmchsdb1_fck
= {
1991 .name
= "mmchsdb1_fck",
1992 .ops
= &clkops_omap2_dflt_wait
,
1993 .parent
= &func_32k_ck
,
1994 .clkdm_name
= "core_l4_clkdm",
1995 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP24XX_CM_FCLKEN2
),
1996 .enable_bit
= OMAP2430_EN_MMCHSDB1_SHIFT
,
1997 .recalc
= &followparent_recalc
,
2000 static struct clk mmchsdb2_fck
= {
2001 .name
= "mmchsdb2_fck",
2002 .ops
= &clkops_omap2_dflt_wait
,
2003 .parent
= &func_32k_ck
,
2004 .clkdm_name
= "core_l4_clkdm",
2005 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP24XX_CM_FCLKEN2
),
2006 .enable_bit
= OMAP2430_EN_MMCHSDB2_SHIFT
,
2007 .recalc
= &followparent_recalc
,
2011 * This clock is a composite clock which does entire set changes then
2012 * forces a rebalance. It keys on the MPU speed, but it really could
2013 * be any key speed part of a set in the rate table.
2015 * to really change a set, you need memory table sets which get changed
2016 * in sram, pre-notifiers & post notifiers, changing the top set, without
2017 * having low level display recalc's won't work... this is why dpm notifiers
2018 * work, isr's off, walk a list of clocks already _off_ and not messing with
2021 * This clock should have no parent. It embodies the entire upper level
2022 * active set. A parent will mess up some of the init also.
2024 static struct clk virt_prcm_set
= {
2025 .name
= "virt_prcm_set",
2026 .ops
= &clkops_null
,
2027 .parent
= &mpu_ck
, /* Indexed by mpu speed, no parent */
2028 .recalc
= &omap2_table_mpu_recalc
, /* sets are keyed on mpu rate */
2029 .set_rate
= &omap2_select_table_rate
,
2030 .round_rate
= &omap2_round_to_table_rate
,
2035 * clkdev integration
2038 static struct omap_clk omap24xx_clks
[] = {
2039 /* external root sources */
2040 CLK(NULL
, "func_32k_ck", &func_32k_ck
, CK_243X
| CK_242X
),
2041 CLK(NULL
, "secure_32k_ck", &secure_32k_ck
, CK_243X
| CK_242X
),
2042 CLK(NULL
, "osc_ck", &osc_ck
, CK_243X
| CK_242X
),
2043 CLK(NULL
, "sys_ck", &sys_ck
, CK_243X
| CK_242X
),
2044 CLK(NULL
, "alt_ck", &alt_ck
, CK_243X
| CK_242X
),
2045 /* internal analog sources */
2046 CLK(NULL
, "dpll_ck", &dpll_ck
, CK_243X
| CK_242X
),
2047 CLK(NULL
, "apll96_ck", &apll96_ck
, CK_243X
| CK_242X
),
2048 CLK(NULL
, "apll54_ck", &apll54_ck
, CK_243X
| CK_242X
),
2049 /* internal prcm root sources */
2050 CLK(NULL
, "func_54m_ck", &func_54m_ck
, CK_243X
| CK_242X
),
2051 CLK(NULL
, "core_ck", &core_ck
, CK_243X
| CK_242X
),
2052 CLK(NULL
, "func_96m_ck", &func_96m_ck
, CK_243X
| CK_242X
),
2053 CLK(NULL
, "func_48m_ck", &func_48m_ck
, CK_243X
| CK_242X
),
2054 CLK(NULL
, "func_12m_ck", &func_12m_ck
, CK_243X
| CK_242X
),
2055 CLK(NULL
, "ck_wdt1_osc", &wdt1_osc_ck
, CK_243X
| CK_242X
),
2056 CLK(NULL
, "sys_clkout_src", &sys_clkout_src
, CK_243X
| CK_242X
),
2057 CLK(NULL
, "sys_clkout", &sys_clkout
, CK_243X
| CK_242X
),
2058 CLK(NULL
, "sys_clkout2_src", &sys_clkout2_src
, CK_242X
),
2059 CLK(NULL
, "sys_clkout2", &sys_clkout2
, CK_242X
),
2060 CLK(NULL
, "emul_ck", &emul_ck
, CK_242X
),
2061 /* mpu domain clocks */
2062 CLK(NULL
, "mpu_ck", &mpu_ck
, CK_243X
| CK_242X
),
2063 /* dsp domain clocks */
2064 CLK(NULL
, "dsp_fck", &dsp_fck
, CK_243X
| CK_242X
),
2065 CLK(NULL
, "dsp_irate_ick", &dsp_irate_ick
, CK_243X
| CK_242X
),
2066 CLK(NULL
, "dsp_ick", &dsp_ick
, CK_242X
),
2067 CLK(NULL
, "iva2_1_ick", &iva2_1_ick
, CK_243X
),
2068 CLK(NULL
, "iva1_ifck", &iva1_ifck
, CK_242X
),
2069 CLK(NULL
, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck
, CK_242X
),
2070 /* GFX domain clocks */
2071 CLK(NULL
, "gfx_3d_fck", &gfx_3d_fck
, CK_243X
| CK_242X
),
2072 CLK(NULL
, "gfx_2d_fck", &gfx_2d_fck
, CK_243X
| CK_242X
),
2073 CLK(NULL
, "gfx_ick", &gfx_ick
, CK_243X
| CK_242X
),
2074 /* Modem domain clocks */
2075 CLK(NULL
, "mdm_ick", &mdm_ick
, CK_243X
),
2076 CLK(NULL
, "mdm_osc_ck", &mdm_osc_ck
, CK_243X
),
2077 /* DSS domain clocks */
2078 CLK("omapdss", "ick", &dss_ick
, CK_243X
| CK_242X
),
2079 CLK("omapdss", "dss1_fck", &dss1_fck
, CK_243X
| CK_242X
),
2080 CLK("omapdss", "dss2_fck", &dss2_fck
, CK_243X
| CK_242X
),
2081 CLK("omapdss", "tv_fck", &dss_54m_fck
, CK_243X
| CK_242X
),
2082 /* L3 domain clocks */
2083 CLK(NULL
, "core_l3_ck", &core_l3_ck
, CK_243X
| CK_242X
),
2084 CLK(NULL
, "ssi_fck", &ssi_ssr_sst_fck
, CK_243X
| CK_242X
),
2085 CLK(NULL
, "usb_l4_ick", &usb_l4_ick
, CK_243X
| CK_242X
),
2086 /* L4 domain clocks */
2087 CLK(NULL
, "l4_ck", &l4_ck
, CK_243X
| CK_242X
),
2088 CLK(NULL
, "ssi_l4_ick", &ssi_l4_ick
, CK_243X
| CK_242X
),
2089 /* virtual meta-group clock */
2090 CLK(NULL
, "virt_prcm_set", &virt_prcm_set
, CK_243X
| CK_242X
),
2091 /* general l4 interface ck, multi-parent functional clk */
2092 CLK(NULL
, "gpt1_ick", &gpt1_ick
, CK_243X
| CK_242X
),
2093 CLK(NULL
, "gpt1_fck", &gpt1_fck
, CK_243X
| CK_242X
),
2094 CLK(NULL
, "gpt2_ick", &gpt2_ick
, CK_243X
| CK_242X
),
2095 CLK(NULL
, "gpt2_fck", &gpt2_fck
, CK_243X
| CK_242X
),
2096 CLK(NULL
, "gpt3_ick", &gpt3_ick
, CK_243X
| CK_242X
),
2097 CLK(NULL
, "gpt3_fck", &gpt3_fck
, CK_243X
| CK_242X
),
2098 CLK(NULL
, "gpt4_ick", &gpt4_ick
, CK_243X
| CK_242X
),
2099 CLK(NULL
, "gpt4_fck", &gpt4_fck
, CK_243X
| CK_242X
),
2100 CLK(NULL
, "gpt5_ick", &gpt5_ick
, CK_243X
| CK_242X
),
2101 CLK(NULL
, "gpt5_fck", &gpt5_fck
, CK_243X
| CK_242X
),
2102 CLK(NULL
, "gpt6_ick", &gpt6_ick
, CK_243X
| CK_242X
),
2103 CLK(NULL
, "gpt6_fck", &gpt6_fck
, CK_243X
| CK_242X
),
2104 CLK(NULL
, "gpt7_ick", &gpt7_ick
, CK_243X
| CK_242X
),
2105 CLK(NULL
, "gpt7_fck", &gpt7_fck
, CK_243X
| CK_242X
),
2106 CLK(NULL
, "gpt8_ick", &gpt8_ick
, CK_243X
| CK_242X
),
2107 CLK(NULL
, "gpt8_fck", &gpt8_fck
, CK_243X
| CK_242X
),
2108 CLK(NULL
, "gpt9_ick", &gpt9_ick
, CK_243X
| CK_242X
),
2109 CLK(NULL
, "gpt9_fck", &gpt9_fck
, CK_243X
| CK_242X
),
2110 CLK(NULL
, "gpt10_ick", &gpt10_ick
, CK_243X
| CK_242X
),
2111 CLK(NULL
, "gpt10_fck", &gpt10_fck
, CK_243X
| CK_242X
),
2112 CLK(NULL
, "gpt11_ick", &gpt11_ick
, CK_243X
| CK_242X
),
2113 CLK(NULL
, "gpt11_fck", &gpt11_fck
, CK_243X
| CK_242X
),
2114 CLK(NULL
, "gpt12_ick", &gpt12_ick
, CK_243X
| CK_242X
),
2115 CLK(NULL
, "gpt12_fck", &gpt12_fck
, CK_243X
| CK_242X
),
2116 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick
, CK_243X
| CK_242X
),
2117 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck
, CK_243X
| CK_242X
),
2118 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick
, CK_243X
| CK_242X
),
2119 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck
, CK_243X
| CK_242X
),
2120 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick
, CK_243X
),
2121 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck
, CK_243X
),
2122 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick
, CK_243X
),
2123 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck
, CK_243X
),
2124 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick
, CK_243X
),
2125 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck
, CK_243X
),
2126 CLK("omap2_mcspi.1", "ick", &mcspi1_ick
, CK_243X
| CK_242X
),
2127 CLK("omap2_mcspi.1", "fck", &mcspi1_fck
, CK_243X
| CK_242X
),
2128 CLK("omap2_mcspi.2", "ick", &mcspi2_ick
, CK_243X
| CK_242X
),
2129 CLK("omap2_mcspi.2", "fck", &mcspi2_fck
, CK_243X
| CK_242X
),
2130 CLK("omap2_mcspi.3", "ick", &mcspi3_ick
, CK_243X
),
2131 CLK("omap2_mcspi.3", "fck", &mcspi3_fck
, CK_243X
),
2132 CLK(NULL
, "uart1_ick", &uart1_ick
, CK_243X
| CK_242X
),
2133 CLK(NULL
, "uart1_fck", &uart1_fck
, CK_243X
| CK_242X
),
2134 CLK(NULL
, "uart2_ick", &uart2_ick
, CK_243X
| CK_242X
),
2135 CLK(NULL
, "uart2_fck", &uart2_fck
, CK_243X
| CK_242X
),
2136 CLK(NULL
, "uart3_ick", &uart3_ick
, CK_243X
| CK_242X
),
2137 CLK(NULL
, "uart3_fck", &uart3_fck
, CK_243X
| CK_242X
),
2138 CLK(NULL
, "gpios_ick", &gpios_ick
, CK_243X
| CK_242X
),
2139 CLK(NULL
, "gpios_fck", &gpios_fck
, CK_243X
| CK_242X
),
2140 CLK("omap_wdt", "ick", &mpu_wdt_ick
, CK_243X
| CK_242X
),
2141 CLK("omap_wdt", "fck", &mpu_wdt_fck
, CK_243X
| CK_242X
),
2142 CLK(NULL
, "sync_32k_ick", &sync_32k_ick
, CK_243X
| CK_242X
),
2143 CLK(NULL
, "wdt1_ick", &wdt1_ick
, CK_243X
| CK_242X
),
2144 CLK(NULL
, "omapctrl_ick", &omapctrl_ick
, CK_243X
| CK_242X
),
2145 CLK(NULL
, "icr_ick", &icr_ick
, CK_243X
),
2146 CLK("omap24xxcam", "fck", &cam_fck
, CK_243X
| CK_242X
),
2147 CLK("omap24xxcam", "ick", &cam_ick
, CK_243X
| CK_242X
),
2148 CLK(NULL
, "mailboxes_ick", &mailboxes_ick
, CK_243X
| CK_242X
),
2149 CLK(NULL
, "wdt4_ick", &wdt4_ick
, CK_243X
| CK_242X
),
2150 CLK(NULL
, "wdt4_fck", &wdt4_fck
, CK_243X
| CK_242X
),
2151 CLK(NULL
, "wdt3_ick", &wdt3_ick
, CK_242X
),
2152 CLK(NULL
, "wdt3_fck", &wdt3_fck
, CK_242X
),
2153 CLK(NULL
, "mspro_ick", &mspro_ick
, CK_243X
| CK_242X
),
2154 CLK(NULL
, "mspro_fck", &mspro_fck
, CK_243X
| CK_242X
),
2155 CLK("mmci-omap.0", "ick", &mmc_ick
, CK_242X
),
2156 CLK("mmci-omap.0", "fck", &mmc_fck
, CK_242X
),
2157 CLK(NULL
, "fac_ick", &fac_ick
, CK_243X
| CK_242X
),
2158 CLK(NULL
, "fac_fck", &fac_fck
, CK_243X
| CK_242X
),
2159 CLK(NULL
, "eac_ick", &eac_ick
, CK_242X
),
2160 CLK(NULL
, "eac_fck", &eac_fck
, CK_242X
),
2161 CLK("omap_hdq.0", "ick", &hdq_ick
, CK_243X
| CK_242X
),
2162 CLK("omap_hdq.1", "fck", &hdq_fck
, CK_243X
| CK_242X
),
2163 CLK("i2c_omap.1", "ick", &i2c1_ick
, CK_243X
| CK_242X
),
2164 CLK("i2c_omap.1", "fck", &i2c1_fck
, CK_242X
),
2165 CLK("i2c_omap.1", "fck", &i2chs1_fck
, CK_243X
),
2166 CLK("i2c_omap.2", "ick", &i2c2_ick
, CK_243X
| CK_242X
),
2167 CLK("i2c_omap.2", "fck", &i2c2_fck
, CK_242X
),
2168 CLK("i2c_omap.2", "fck", &i2chs2_fck
, CK_243X
),
2169 CLK(NULL
, "gpmc_fck", &gpmc_fck
, CK_243X
| CK_242X
),
2170 CLK(NULL
, "sdma_fck", &sdma_fck
, CK_243X
| CK_242X
),
2171 CLK(NULL
, "sdma_ick", &sdma_ick
, CK_243X
| CK_242X
),
2172 CLK(NULL
, "vlynq_ick", &vlynq_ick
, CK_242X
),
2173 CLK(NULL
, "vlynq_fck", &vlynq_fck
, CK_242X
),
2174 CLK(NULL
, "sdrc_ick", &sdrc_ick
, CK_243X
),
2175 CLK(NULL
, "des_ick", &des_ick
, CK_243X
| CK_242X
),
2176 CLK(NULL
, "sha_ick", &sha_ick
, CK_243X
| CK_242X
),
2177 CLK("omap_rng", "ick", &rng_ick
, CK_243X
| CK_242X
),
2178 CLK(NULL
, "aes_ick", &aes_ick
, CK_243X
| CK_242X
),
2179 CLK(NULL
, "pka_ick", &pka_ick
, CK_243X
| CK_242X
),
2180 CLK(NULL
, "usb_fck", &usb_fck
, CK_243X
| CK_242X
),
2181 CLK("musb_hdrc", "ick", &usbhs_ick
, CK_243X
),
2182 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick
, CK_243X
),
2183 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck
, CK_243X
),
2184 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick
, CK_243X
),
2185 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck
, CK_243X
),
2186 CLK(NULL
, "gpio5_ick", &gpio5_ick
, CK_243X
),
2187 CLK(NULL
, "gpio5_fck", &gpio5_fck
, CK_243X
),
2188 CLK(NULL
, "mdm_intc_ick", &mdm_intc_ick
, CK_243X
),
2189 CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck
, CK_243X
),
2190 CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck
, CK_243X
),
2197 int __init
omap2xxx_clk_init(void)
2199 const struct prcm_config
*prcm
;
2204 if (cpu_is_omap242x()) {
2205 prcm_clksrc_ctrl
= OMAP2420_PRCM_CLKSRC_CTRL
;
2206 cpu_mask
= RATE_IN_242X
;
2207 cpu_clkflg
= CK_242X
;
2208 rate_table
= omap2420_rate_table
;
2209 } else if (cpu_is_omap2430()) {
2210 prcm_clksrc_ctrl
= OMAP2430_PRCM_CLKSRC_CTRL
;
2211 cpu_mask
= RATE_IN_243X
;
2212 cpu_clkflg
= CK_243X
;
2213 rate_table
= omap2430_rate_table
;
2216 clk_init(&omap2_clk_functions
);
2218 for (c
= omap24xx_clks
; c
< omap24xx_clks
+ ARRAY_SIZE(omap24xx_clks
); c
++)
2219 clk_preinit(c
->lk
.clk
);
2221 osc_ck
.rate
= omap2_osc_clk_recalc(&osc_ck
);
2222 propagate_rate(&osc_ck
);
2223 sys_ck
.rate
= omap2xxx_sys_clk_recalc(&sys_ck
);
2224 propagate_rate(&sys_ck
);
2226 for (c
= omap24xx_clks
; c
< omap24xx_clks
+ ARRAY_SIZE(omap24xx_clks
); c
++)
2227 if (c
->cpu
& cpu_clkflg
) {
2229 clk_register(c
->lk
.clk
);
2230 omap2_init_clk_clkdm(c
->lk
.clk
);
2233 /* Check the MPU rate set by bootloader */
2234 clkrate
= omap2xxx_clk_get_core_rate(&dpll_ck
);
2235 for (prcm
= rate_table
; prcm
->mpu_speed
; prcm
++) {
2236 if (!(prcm
->flags
& cpu_mask
))
2238 if (prcm
->xtal_speed
!= sys_ck
.rate
)
2240 if (prcm
->dpll_speed
<= clkrate
)
2243 curr_prcm_set
= prcm
;
2245 recalculate_root_clocks();
2247 printk(KERN_INFO
"Clocking rate (Crystal/DPLL/MPU): "
2248 "%ld.%01ld/%ld/%ld MHz\n",
2249 (sys_ck
.rate
/ 1000000), (sys_ck
.rate
/ 100000) % 10,
2250 (dpll_ck
.rate
/ 1000000), (mpu_ck
.rate
/ 1000000)) ;
2253 * Only enable those clocks we will need, let the drivers
2254 * enable other clocks as necessary
2256 clk_enable_init_clocks();
2258 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
2259 vclk
= clk_get(NULL
, "virt_prcm_set");
2260 sclk
= clk_get(NULL
, "sys_ck");
2261 dclk
= clk_get(NULL
, "dpll_ck");