arch/arm/mach-pxa/pxa27x.c

   1 /*
   2  *  linux/arch/arm/mach-pxa/pxa27x.c
   3  *
   4  *  Author:     Nicolas Pitre
   5  *  Created:    Nov 05, 2002
   6  *  Copyright:  MontaVista Software Inc.
   7  *
   8  * Code specific to PXA27x aka Bulverde.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/suspend.h>
  18 #include <linux/platform_device.h>
  19
  20 #include <asm/hardware.h>
  21 #include <asm/irq.h>
  22 #include <asm/arch/irqs.h>
  23 #include <asm/arch/pxa-regs.h>
  24 #include <asm/arch/ohci.h>
  25 #include <asm/arch/pm.h>
  26 #include <asm/arch/dma.h>
  27 #include <asm/arch/i2c.h>
  28
  29 #include "generic.h"
  30 #include "devices.h"
  31 #include "clock.h"
  32
  33 /* Crystal clock: 13MHz */
  34 #define BASE_CLK        13000000
  35
  36 /*
  37  * Get the clock frequency as reflected by CCSR and the turbo flag.
  38  * We assume these values have been applied via a fcs.
  39  * If info is not 0 we also display the current settings.
  40  */
  41 unsigned int pxa27x_get_clk_frequency_khz(int info)
  42 {
  43         unsigned long ccsr, clkcfg;
  44         unsigned int l, L, m, M, n2, N, S;
  45         int cccr_a, t, ht, b;
  46
  47         ccsr = CCSR;
  48         cccr_a = CCCR & (1 << 25);
  49
  50         /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
  51         asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
  52         t  = clkcfg & (1 << 0);
  53         ht = clkcfg & (1 << 2);
  54         b  = clkcfg & (1 << 3);
  55
  56         l  = ccsr & 0x1f;
  57         n2 = (ccsr>>7) & 0xf;
  58         m  = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
  59
  60         L  = l * BASE_CLK;
  61         N  = (L * n2) / 2;
  62         M  = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
  63         S  = (b) ? L : (L/2);
  64
  65         if (info) {
  66                 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
  67                         L / 1000000, (L % 1000000) / 10000, l );
  68                 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
  69                         N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
  70                         (t) ? "" : "in" );
  71                 printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
  72                         M / 1000000, (M % 1000000) / 10000, m );
  73                 printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
  74                         S / 1000000, (S % 1000000) / 10000 );
  75         }
  76
  77         return (t) ? (N/1000) : (L/1000);
  78 }
  79
  80 /*
  81  * Return the current mem clock frequency in units of 10kHz as
  82  * reflected by CCCR[A], B, and L
  83  */
  84 unsigned int pxa27x_get_memclk_frequency_10khz(void)
  85 {
  86         unsigned long ccsr, clkcfg;
  87         unsigned int l, L, m, M;
  88         int cccr_a, b;
  89
  90         ccsr = CCSR;
  91         cccr_a = CCCR & (1 << 25);
  92
  93         /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
  94         asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
  95         b = clkcfg & (1 << 3);
  96
  97         l = ccsr & 0x1f;
  98         m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
  99
 100         L = l * BASE_CLK;
 101         M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
 102
 103         return (M / 10000);
 104 }
 105
 106 /*
 107  * Return the current LCD clock frequency in units of 10kHz as
 108  */
 109 static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
 110 {
 111         unsigned long ccsr;
 112         unsigned int l, L, k, K;
 113
 114         ccsr = CCSR;
 115
 116         l = ccsr & 0x1f;
 117         k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
 118
 119         L = l * BASE_CLK;
 120         K = L / k;
 121
 122         return (K / 10000);
 123 }
 124
 125 static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
 126 {
 127         return pxa27x_get_lcdclk_frequency_10khz() * 10000;
 128 }
 129
 130 static const struct clkops clk_pxa27x_lcd_ops = {
 131         .enable         = clk_cken_enable,
 132         .disable        = clk_cken_disable,
 133         .getrate        = clk_pxa27x_lcd_getrate,
 134 };
 135
 136 static struct clk pxa27x_clks[] = {
 137         INIT_CK("LCDCLK", LCD,    &clk_pxa27x_lcd_ops, &pxa_device_fb.dev),
 138         INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL),
 139
 140         INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
 141         INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
 142         INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
 143
 144         INIT_CKEN("I2SCLK",  I2S,  14682000, 0, &pxa_device_i2s.dev),
 145         INIT_CKEN("I2CCLK",  I2C,  32842000, 0, &pxa_device_i2c.dev),
 146         INIT_CKEN("UDCCLK",  USB,  48000000, 5, &pxa_device_udc.dev),
 147         INIT_CKEN("MMCCLK",  MMC,  19500000, 0, &pxa_device_mci.dev),
 148         INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev),
 149
 150         INIT_CKEN("USBCLK", USBHOST, 48000000, 0, &pxa27x_device_ohci.dev),
 151         INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev),
 152         INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL),
 153
 154         /*
 155         INIT_CKEN("PWMCLK",  PWM0, 13000000, 0, NULL),
 156         INIT_CKEN("SSPCLK",  SSP1, 13000000, 0, NULL),
 157         INIT_CKEN("SSPCLK",  SSP2, 13000000, 0, NULL),
 158         INIT_CKEN("SSPCLK",  SSP3, 13000000, 0, NULL),
 159         INIT_CKEN("MSLCLK",  MSL,  48000000, 0, NULL),
 160         INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL),
 161         INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL),
 162         INIT_CKEN("IMCLK",   IM,   0, 0, NULL),
 163         INIT_CKEN("MEMCLK",  MEMC, 0, 0, NULL),
 164         */
 165 };
 166
 167 #ifdef CONFIG_PM
 168
 169 #define SAVE(x)         sleep_save[SLEEP_SAVE_##x] = x
 170 #define RESTORE(x)      x = sleep_save[SLEEP_SAVE_##x]
 171
 172 #define RESTORE_GPLEVEL(n) do { \
 173         GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
 174         GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
 175 } while (0)
 176
 177 /*
 178  * List of global PXA peripheral registers to preserve.
 179  * More ones like CP and general purpose register values are preserved
 180  * with the stack pointer in sleep.S.
 181  */
 182 enum {  SLEEP_SAVE_START = 0,
 183
 184         SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3,
 185         SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3,
 186         SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3,
 187         SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3,
 188         SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
 189
 190         SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
 191         SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
 192         SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
 193         SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U,
 194
 195         SLEEP_SAVE_PSTR,
 196
 197         SLEEP_SAVE_ICMR,
 198         SLEEP_SAVE_CKEN,
 199
 200         SLEEP_SAVE_MDREFR,
 201         SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
 202         SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
 203
 204         SLEEP_SAVE_SIZE
 205 };
 206
 207 void pxa27x_cpu_pm_save(unsigned long *sleep_save)
 208 {
 209         SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); SAVE(GPLR3);
 210         SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); SAVE(GPDR3);
 211         SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); SAVE(GRER3);
 212         SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); SAVE(GFER3);
 213         SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3);
 214
 215         SAVE(GAFR0_L); SAVE(GAFR0_U);
 216         SAVE(GAFR1_L); SAVE(GAFR1_U);
 217         SAVE(GAFR2_L); SAVE(GAFR2_U);
 218         SAVE(GAFR3_L); SAVE(GAFR3_U);
 219
 220         SAVE(MDREFR);
 221         SAVE(PWER); SAVE(PCFR); SAVE(PRER);
 222         SAVE(PFER); SAVE(PKWR);
 223
 224         SAVE(ICMR); ICMR = 0;
 225         SAVE(CKEN);
 226         SAVE(PSTR);
 227
 228         /* Clear GPIO transition detect bits */
 229         GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; GEDR3 = GEDR3;
 230 }
 231
 232 void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
 233 {
 234         /* ensure not to come back here if it wasn't intended */
 235         PSPR = 0;
 236
 237         /* restore registers */
 238         RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1);
 239         RESTORE_GPLEVEL(2); RESTORE_GPLEVEL(3);
 240         RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); RESTORE(GPDR3);
 241         RESTORE(GAFR0_L); RESTORE(GAFR0_U);
 242         RESTORE(GAFR1_L); RESTORE(GAFR1_U);
 243         RESTORE(GAFR2_L); RESTORE(GAFR2_U);
 244         RESTORE(GAFR3_L); RESTORE(GAFR3_U);
 245         RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); RESTORE(GRER3);
 246         RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); RESTORE(GFER3);
 247         RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3);
 248
 249         RESTORE(MDREFR);
 250         RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
 251         RESTORE(PFER); RESTORE(PKWR);
 252
 253         PSSR = PSSR_RDH | PSSR_PH;
 254
 255         RESTORE(CKEN);
 256
 257         ICLR = 0;
 258         ICCR = 1;
 259         RESTORE(ICMR);
 260         RESTORE(PSTR);
 261 }
 262
 263 void pxa27x_cpu_pm_enter(suspend_state_t state)
 264 {
 265         extern void pxa_cpu_standby(void);
 266
 267         if (state == PM_SUSPEND_STANDBY)
 268                 CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER) |
 269                         (1 << CKEN_LCD) | (1 << CKEN_PWM0);
 270         else
 271                 CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER);
 272
 273         /* ensure voltage-change sequencer not initiated, which hangs */
 274         PCFR &= ~PCFR_FVC;
 275
 276         /* Clear edge-detect status register. */
 277         PEDR = 0xDF12FE1B;
 278
 279         switch (state) {
 280         case PM_SUSPEND_STANDBY:
 281                 pxa_cpu_standby();
 282                 break;
 283         case PM_SUSPEND_MEM:
 284                 /* set resume return address */
 285                 PSPR = virt_to_phys(pxa_cpu_resume);
 286                 pxa27x_cpu_suspend(PWRMODE_SLEEP);
 287                 break;
 288         }
 289 }
 290
 291 static int pxa27x_cpu_pm_valid(suspend_state_t state)
 292 {
 293         return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
 294 }
 295
 296 static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
 297         .save_size      = SLEEP_SAVE_SIZE,
 298         .save           = pxa27x_cpu_pm_save,
 299         .restore        = pxa27x_cpu_pm_restore,
 300         .valid          = pxa27x_cpu_pm_valid,
 301         .enter          = pxa27x_cpu_pm_enter,
 302 };
 303
 304 static void __init pxa27x_init_pm(void)
 305 {
 306         pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
 307 }
 308 #endif
 309
 310 /* PXA27x:  Various gpios can issue wakeup events.  This logic only
 311  * handles the simple cases, not the WEMUX2 and WEMUX3 options
 312  */
 313 #define PXA27x_GPIO_NOWAKE_MASK \
 314         ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2))
 315 #define WAKEMASK(gpio) \
 316         (((gpio) <= 15) \
 317                  ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \
 318                  : ((gpio == 35) ? (1 << 24) : 0))
 319
 320 static int pxa27x_set_wake(unsigned int irq, unsigned int on)
 321 {
 322         int gpio = IRQ_TO_GPIO(irq);
 323         uint32_t mask;
 324
 325         if ((gpio >= 0 && gpio <= 15) || (gpio == 35)) {
 326                 if (WAKEMASK(gpio) == 0)
 327                         return -EINVAL;
 328
 329                 mask = WAKEMASK(gpio);
 330
 331                 if (on) {
 332                         if (GRER(gpio) | GPIO_bit(gpio))
 333                                 PRER |= mask;
 334                         else
 335                                 PRER &= ~mask;
 336
 337                         if (GFER(gpio) | GPIO_bit(gpio))
 338                                 PFER |= mask;
 339                         else
 340                                 PFER &= ~mask;
 341                 }
 342                 goto set_pwer;
 343         }
 344
 345         switch (irq) {
 346         case IRQ_RTCAlrm:
 347                 mask = PWER_RTC;
 348                 break;
 349         case IRQ_USB:
 350                 mask = 1u << 26;
 351                 break;
 352         default:
 353                 return -EINVAL;
 354         }
 355
 356 set_pwer:
 357         if (on)
 358                 PWER |= mask;
 359         else
 360                 PWER &=~mask;
 361
 362         return 0;
 363 }
 364
 365 void __init pxa27x_init_irq(void)
 366 {
 367         pxa_init_irq_low();
 368         pxa_init_irq_high();
 369         pxa_init_irq_gpio(128);
 370         pxa_init_irq_set_wake(pxa27x_set_wake);
 371 }
 372
 373 /*
 374  * device registration specific to PXA27x.
 375  */
 376
 377 static u64 pxa27x_dmamask = 0xffffffffUL;
 378
 379 static struct resource pxa27x_ohci_resources[] = {
 380         [0] = {
 381                 .start  = 0x4C000000,
 382                 .end    = 0x4C00ff6f,
 383                 .flags  = IORESOURCE_MEM,
 384         },
 385         [1] = {
 386                 .start  = IRQ_USBH1,
 387                 .end    = IRQ_USBH1,
 388                 .flags  = IORESOURCE_IRQ,
 389         },
 390 };
 391
 392 struct platform_device pxa27x_device_ohci = {
 393         .name           = "pxa27x-ohci",
 394         .id             = -1,
 395         .dev            = {
 396                 .dma_mask = &pxa27x_dmamask,
 397                 .coherent_dma_mask = 0xffffffff,
 398         },
 399         .num_resources  = ARRAY_SIZE(pxa27x_ohci_resources),
 400         .resource       = pxa27x_ohci_resources,
 401 };
 402
 403 void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
 404 {
 405         pxa27x_device_ohci.dev.platform_data = info;
 406 }
 407
 408 static struct resource i2c_power_resources[] = {
 409         {
 410                 .start  = 0x40f00180,
 411                 .end    = 0x40f001a3,
 412                 .flags  = IORESOURCE_MEM,
 413         }, {
 414                 .start  = IRQ_PWRI2C,
 415                 .end    = IRQ_PWRI2C,
 416                 .flags  = IORESOURCE_IRQ,
 417         },
 418 };
 419
 420 struct platform_device pxa27x_device_i2c_power = {
 421         .name           = "pxa2xx-i2c",
 422         .id             = 1,
 423         .resource       = i2c_power_resources,
 424         .num_resources  = ARRAY_SIZE(i2c_power_resources),
 425 };
 426
 427 void __init pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 428 {
 429         pxa27x_device_i2c_power.dev.platform_data = info;
 430 }
 431
 432 static struct platform_device *devices[] __initdata = {
 433         &pxa_device_mci,
 434         &pxa_device_udc,
 435         &pxa_device_fb,
 436         &pxa_device_ffuart,
 437         &pxa_device_btuart,
 438         &pxa_device_stuart,
 439         &pxa_device_i2c,
 440         &pxa_device_i2s,
 441         &pxa_device_ficp,
 442         &pxa_device_rtc,
 443         &pxa27x_device_i2c_power,
 444         &pxa27x_device_ohci,
 445 };
 446
 447 static int __init pxa27x_init(void)
 448 {
 449         int ret = 0;
 450         if (cpu_is_pxa27x()) {
 451                 clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks));
 452
 453                 if ((ret = pxa_init_dma(32)))
 454                         return ret;
 455 #ifdef CONFIG_PM
 456                 pxa27x_init_pm();
 457 #endif
 458                 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
 459         }
 460         return ret;
 461 }
 462
 463 subsys_initcall(pxa27x_init);