2 # DSP Bridge Driver Support
6 tristate "DSP Bridge driver"
10 DSP/BIOS Bridge is designed for platforms that contain a GPP and
11 one or more attached DSPs. The GPP is considered the master or
12 "host" processor, and the attached DSPs are processing resources
13 that can be utilized by applications and drivers running on the GPP.
15 This driver depends on OMAP Mailbox (OMAP_MBOX_FWK).
17 config TIDSPBRIDGE_DVFS
18 bool "Enable Bridge Dynamic Voltage and Frequency Scaling (DVFS)"
19 depends on TIDSPBRIDGE && OMAP_PM_SRF && CPU_FREQ
22 DVFS allows DSP Bridge to initiate the operating point change to
23 scale the chip voltage and frequency in order to match the
24 performance and power consumption to the current processing
27 config TIDSPBRIDGE_MEMPOOL_SIZE
28 hex "Physical memory pool size (Byte)"
29 depends on TIDSPBRIDGE
32 Allocate specified size of memory at booting time to avoid allocation
33 failure under heavy memory fragmentation after some use time.
35 config TIDSPBRIDGE_DEBUG
36 bool "DSP Bridge Debug Support"
37 depends on TIDSPBRIDGE
39 Say Y to enable Bridge debugging capabilities
41 config TIDSPBRIDGE_RECOVERY
42 bool "DSP Recovery Support"
43 depends on TIDSPBRIDGE
45 In case of DSP fatal error, BRIDGE driver will try to
48 config TIDSPBRIDGE_CACHE_LINE_CHECK
49 bool "Check buffers to be 128 byte aligned"
50 depends on TIDSPBRIDGE
53 When the DSP processes data, the DSP cache controller loads 128-Byte
54 chunks (lines) from SDRAM and writes the data back in 128-Byte chunks.
55 If a DMM buffer does not start and end on a 128-Byte boundary, the data
56 preceding the start address (SA) from the 128-Byte boundary to the SA
57 and the data at addresses trailing the end address (EA) from the EA to
58 the next 128-Byte boundary will be loaded and written back as well.
59 This can lead to heap corruption. Say Y, to enforce the check for 128
60 byte alignment, buffers failing this check will be rejected.
62 config TIDSPBRIDGE_WDT3
63 bool "Enable WDT3 interruptions"
64 depends on TIDSPBRIDGE
67 WTD3 is managed by DSP and once it is enabled, DSP side bridge is in
68 charge of refreshing the timer before overflow, if the DSP hangs MPU
69 will caught the interrupt and try to recover DSP.
71 config TIDSPBRIDGE_WDT_TIMEOUT
72 int "DSP watchdog timer timeout (in secs)"
73 depends on TIDSPBRIDGE_WDT3
76 Watchdog timer timeout value, after that time if the watchdog timer
77 counter is not reset the wdt overflow interrupt will be triggered
79 comment "Bridge Notifications"
80 depends on TIDSPBRIDGE
82 config TIDSPBRIDGE_NTFY_PWRERR
83 bool "Notify DSP Power Error"
84 depends on TIDSPBRIDGE
86 Enable notifications to registered clients on the event of power errror
87 trying to suspend bridge driver. Say Y, to signal this event as a fatal
88 error, this will require a bridge restart to recover.