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ixgbe: always set header length in SRRCTL
[linux-2.6/x86.git] / drivers / net / ixgbe / ixgbe_main.c
blob4c38d51397ce9b3515ba13d3c668622ea37dd942
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/ipv6.h>
38 #include <net/checksum.h>
39 #include <net/ip6_checksum.h>
40 #include <linux/ethtool.h>
41 #include <linux/if_vlan.h>
42
43 #include "ixgbe.h"
44 #include "ixgbe_common.h"
45
46 char ixgbe_driver_name[] = "ixgbe";
47 static const char ixgbe_driver_string[] =
48 "Intel(R) 10 Gigabit PCI Express Network Driver";
49
50 #define DRV_VERSION "2.0.16-k2"
51 const char ixgbe_driver_version[] = DRV_VERSION;
52 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
53
54 static const struct ixgbe_info *ixgbe_info_tbl[] = {
55 [board_82598] = &ixgbe_82598_info,
56 [board_82599] = &ixgbe_82599_info,
57 };
58
59 /* ixgbe_pci_tbl - PCI Device ID Table
60 *
61 * Wildcard entries (PCI_ANY_ID) should come last
62 * Last entry must be all 0s
63 *
64 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
65 * Class, Class Mask, private data (not used) }
66 */
67 static struct pci_device_id ixgbe_pci_tbl[] = {
68 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
69 board_82598 },
70 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
71 board_82598 },
72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
73 board_82598 },
74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
75 board_82598 },
76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
77 board_82598 },
78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
79 board_82598 },
80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
81 board_82598 },
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
83 board_82598 },
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
85 board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
87 board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
89 board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
91 board_82599 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
93 board_82599 },
94
95 /* required last entry */
96 {0, }
97 };
98 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
99
100 #ifdef CONFIG_IXGBE_DCA
101 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
102 void *p);
103 static struct notifier_block dca_notifier = {
104 .notifier_call = ixgbe_notify_dca,
105 .next = NULL,
106 .priority = 0
107 };
108 #endif
109
110 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
111 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
112 MODULE_LICENSE("GPL");
113 MODULE_VERSION(DRV_VERSION);
114
115 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
116
117 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
118 {
119 u32 ctrl_ext;
120
121 /* Let firmware take over control of h/w */
122 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
123 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
124 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
125 }
126
127 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
128 {
129 u32 ctrl_ext;
130
131 /* Let firmware know the driver has taken over */
132 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
133 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
134 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
135 }
136
137 /*
138 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
139 * @adapter: pointer to adapter struct
140 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
141 * @queue: queue to map the corresponding interrupt to
142 * @msix_vector: the vector to map to the corresponding queue
143 *
144 */
145 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
146 u8 queue, u8 msix_vector)
147 {
148 u32 ivar, index;
149 struct ixgbe_hw *hw = &adapter->hw;
150 switch (hw->mac.type) {
151 case ixgbe_mac_82598EB:
152 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
153 if (direction == -1)
154 direction = 0;
155 index = (((direction * 64) + queue) >> 2) & 0x1F;
156 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
157 ivar &= ~(0xFF << (8 * (queue & 0x3)));
158 ivar |= (msix_vector << (8 * (queue & 0x3)));
159 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
160 break;
161 case ixgbe_mac_82599EB:
162 if (direction == -1) {
163 /* other causes */
164 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
165 index = ((queue & 1) * 8);
166 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
167 ivar &= ~(0xFF << index);
168 ivar |= (msix_vector << index);
169 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
170 break;
171 } else {
172 /* tx or rx causes */
173 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
174 index = ((16 * (queue & 1)) + (8 * direction));
175 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
176 ivar &= ~(0xFF << index);
177 ivar |= (msix_vector << index);
178 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
179 break;
180 }
181 default:
182 break;
183 }
184 }
185
186 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
187 struct ixgbe_tx_buffer
188 *tx_buffer_info)
189 {
190 tx_buffer_info->dma = 0;
191 if (tx_buffer_info->skb) {
192 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
193 DMA_TO_DEVICE);
194 dev_kfree_skb_any(tx_buffer_info->skb);
195 tx_buffer_info->skb = NULL;
196 }
197 tx_buffer_info->time_stamp = 0;
198 /* tx_buffer_info must be completely set up in the transmit path */
199 }
200
201 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
202 struct ixgbe_ring *tx_ring,
203 unsigned int eop)
204 {
205 struct ixgbe_hw *hw = &adapter->hw;
206
207 /* Detect a transmit hang in hardware, this serializes the
208 * check with the clearing of time_stamp and movement of eop */
209 adapter->detect_tx_hung = false;
210 if (tx_ring->tx_buffer_info[eop].time_stamp &&
211 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
212 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
213 /* detected Tx unit hang */
214 union ixgbe_adv_tx_desc *tx_desc;
215 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
216 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
217 " Tx Queue <%d>\n"
218 " TDH, TDT <%x>, <%x>\n"
219 " next_to_use <%x>\n"
220 " next_to_clean <%x>\n"
221 "tx_buffer_info[next_to_clean]\n"
222 " time_stamp <%lx>\n"
223 " jiffies <%lx>\n",
224 tx_ring->queue_index,
225 IXGBE_READ_REG(hw, tx_ring->head),
226 IXGBE_READ_REG(hw, tx_ring->tail),
227 tx_ring->next_to_use, eop,
228 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
229 return true;
230 }
231
232 return false;
233 }
234
235 #define IXGBE_MAX_TXD_PWR 14
236 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
237
238 /* Tx Descriptors needed, worst case */
239 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
240 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
241 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
242 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
243
244 static void ixgbe_tx_timeout(struct net_device *netdev);
245
246 /**
247 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
248 * @adapter: board private structure
249 * @tx_ring: tx ring to clean
250 *
251 * returns true if transmit work is done
252 **/
253 static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
254 struct ixgbe_ring *tx_ring)
255 {
256 struct net_device *netdev = adapter->netdev;
257 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
258 struct ixgbe_tx_buffer *tx_buffer_info;
259 unsigned int i, eop, count = 0;
260 unsigned int total_bytes = 0, total_packets = 0;
261
262 i = tx_ring->next_to_clean;
263 eop = tx_ring->tx_buffer_info[i].next_to_watch;
264 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
265
266 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
267 (count < tx_ring->work_limit)) {
268 bool cleaned = false;
269 for ( ; !cleaned; count++) {
270 struct sk_buff *skb;
271 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
272 tx_buffer_info = &tx_ring->tx_buffer_info[i];
273 cleaned = (i == eop);
274 skb = tx_buffer_info->skb;
275
276 if (cleaned && skb) {
277 unsigned int segs, bytecount;
278
279 /* gso_segs is currently only valid for tcp */
280 segs = skb_shinfo(skb)->gso_segs ?: 1;
281 /* multiply data chunks by size of headers */
282 bytecount = ((segs - 1) * skb_headlen(skb)) +
283 skb->len;
284 total_packets += segs;
285 total_bytes += bytecount;
286 }
287
288 ixgbe_unmap_and_free_tx_resource(adapter,
289 tx_buffer_info);
290
291 tx_desc->wb.status = 0;
292
293 i++;
294 if (i == tx_ring->count)
295 i = 0;
296 }
297
298 eop = tx_ring->tx_buffer_info[i].next_to_watch;
299 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
300 }
301
302 tx_ring->next_to_clean = i;
303
304 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
305 if (unlikely(count && netif_carrier_ok(netdev) &&
306 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
307 /* Make sure that anybody stopping the queue after this
308 * sees the new next_to_clean.
309 */
310 smp_mb();
311 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
312 !test_bit(__IXGBE_DOWN, &adapter->state)) {
313 netif_wake_subqueue(netdev, tx_ring->queue_index);
314 ++adapter->restart_queue;
315 }
316 }
317
318 if (adapter->detect_tx_hung) {
319 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
320 /* schedule immediate reset if we believe we hung */
321 DPRINTK(PROBE, INFO,
322 "tx hang %d detected, resetting adapter\n",
323 adapter->tx_timeout_count + 1);
324 ixgbe_tx_timeout(adapter->netdev);
325 }
326 }
327
328 /* re-arm the interrupt */
329 if (count >= tx_ring->work_limit) {
330 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
331 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
332 tx_ring->v_idx);
333 else if (tx_ring->v_idx & 0xFFFFFFFF)
334 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0),
335 tx_ring->v_idx);
336 else
337 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1),
338 (tx_ring->v_idx >> 32));
339 }
340
341
342 tx_ring->total_bytes += total_bytes;
343 tx_ring->total_packets += total_packets;
344 tx_ring->stats.packets += total_packets;
345 tx_ring->stats.bytes += total_bytes;
346 adapter->net_stats.tx_bytes += total_bytes;
347 adapter->net_stats.tx_packets += total_packets;
348 return (count < tx_ring->work_limit);
349 }
350
351 #ifdef CONFIG_IXGBE_DCA
352 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
353 struct ixgbe_ring *rx_ring)
354 {
355 u32 rxctrl;
356 int cpu = get_cpu();
357 int q = rx_ring - adapter->rx_ring;
358
359 if (rx_ring->cpu != cpu) {
360 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
361 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
362 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
363 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
364 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
365 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
366 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
367 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
368 }
369 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
370 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
371 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
372 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
373 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
374 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
375 rx_ring->cpu = cpu;
376 }
377 put_cpu();
378 }
379
380 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
381 struct ixgbe_ring *tx_ring)
382 {
383 u32 txctrl;
384 int cpu = get_cpu();
385 int q = tx_ring - adapter->tx_ring;
386
387 if (tx_ring->cpu != cpu) {
388 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
389 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
390 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
391 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
392 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
393 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
394 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
395 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
396 }
397 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
398 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
399 tx_ring->cpu = cpu;
400 }
401 put_cpu();
402 }
403
404 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
405 {
406 int i;
407
408 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
409 return;
410
411 for (i = 0; i < adapter->num_tx_queues; i++) {
412 adapter->tx_ring[i].cpu = -1;
413 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
414 }
415 for (i = 0; i < adapter->num_rx_queues; i++) {
416 adapter->rx_ring[i].cpu = -1;
417 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
418 }
419 }
420
421 static int __ixgbe_notify_dca(struct device *dev, void *data)
422 {
423 struct net_device *netdev = dev_get_drvdata(dev);
424 struct ixgbe_adapter *adapter = netdev_priv(netdev);
425 unsigned long event = *(unsigned long *)data;
426
427 switch (event) {
428 case DCA_PROVIDER_ADD:
429 /* if we're already enabled, don't do it again */
430 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
431 break;
432 /* Always use CB2 mode, difference is masked
433 * in the CB driver. */
434 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
435 if (dca_add_requester(dev) == 0) {
436 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
437 ixgbe_setup_dca(adapter);
438 break;
439 }
440 /* Fall Through since DCA is disabled. */
441 case DCA_PROVIDER_REMOVE:
442 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
443 dca_remove_requester(dev);
444 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
445 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
446 }
447 break;
448 }
449
450 return 0;
451 }
452
453 #endif /* CONFIG_IXGBE_DCA */
454 /**
455 * ixgbe_receive_skb - Send a completed packet up the stack
456 * @adapter: board private structure
457 * @skb: packet to send up
458 * @status: hardware indication of status of receive
459 * @rx_ring: rx descriptor ring (for a specific queue) to setup
460 * @rx_desc: rx descriptor
461 **/
462 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
463 struct sk_buff *skb, u8 status,
464 struct ixgbe_ring *ring,
465 union ixgbe_adv_rx_desc *rx_desc)
466 {
467 struct ixgbe_adapter *adapter = q_vector->adapter;
468 struct napi_struct *napi = &q_vector->napi;
469 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
470 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
471
472 skb_record_rx_queue(skb, ring->queue_index);
473 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
474 if (adapter->vlgrp && is_vlan && (tag != 0))
475 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
476 else
477 napi_gro_receive(napi, skb);
478 } else {
479 if (adapter->vlgrp && is_vlan && (tag != 0))
480 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
481 else
482 netif_rx(skb);
483 }
484 }
485
486 /**
487 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
488 * @adapter: address of board private structure
489 * @status_err: hardware indication of status of receive
490 * @skb: skb currently being received and modified
491 **/
492 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
493 u32 status_err, struct sk_buff *skb)
494 {
495 skb->ip_summed = CHECKSUM_NONE;
496
497 /* Rx csum disabled */
498 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
499 return;
500
501 /* if IP and error */
502 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
503 (status_err & IXGBE_RXDADV_ERR_IPE)) {
504 adapter->hw_csum_rx_error++;
505 return;
506 }
507
508 if (!(status_err & IXGBE_RXD_STAT_L4CS))
509 return;
510
511 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
512 adapter->hw_csum_rx_error++;
513 return;
514 }
515
516 /* It must be a TCP or UDP packet with a valid checksum */
517 skb->ip_summed = CHECKSUM_UNNECESSARY;
518 adapter->hw_csum_rx_good++;
519 }
520
521 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
522 struct ixgbe_ring *rx_ring, u32 val)
523 {
524 /*
525 * Force memory writes to complete before letting h/w
526 * know there are new descriptors to fetch. (Only
527 * applicable for weak-ordered memory model archs,
528 * such as IA-64).
529 */
530 wmb();
531 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
532 }
533
534 /**
535 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
536 * @adapter: address of board private structure
537 **/
538 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
539 struct ixgbe_ring *rx_ring,
540 int cleaned_count)
541 {
542 struct pci_dev *pdev = adapter->pdev;
543 union ixgbe_adv_rx_desc *rx_desc;
544 struct ixgbe_rx_buffer *bi;
545 unsigned int i;
546 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
547
548 i = rx_ring->next_to_use;
549 bi = &rx_ring->rx_buffer_info[i];
550
551 while (cleaned_count--) {
552 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
553
554 if (!bi->page_dma &&
555 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
556 if (!bi->page) {
557 bi->page = alloc_page(GFP_ATOMIC);
558 if (!bi->page) {
559 adapter->alloc_rx_page_failed++;
560 goto no_buffers;
561 }
562 bi->page_offset = 0;
563 } else {
564 /* use a half page if we're re-using */
565 bi->page_offset ^= (PAGE_SIZE / 2);
566 }
567
568 bi->page_dma = pci_map_page(pdev, bi->page,
569 bi->page_offset,
570 (PAGE_SIZE / 2),
571 PCI_DMA_FROMDEVICE);
572 }
573
574 if (!bi->skb) {
575 struct sk_buff *skb;
576 skb = netdev_alloc_skb(adapter->netdev, bufsz);
577
578 if (!skb) {
579 adapter->alloc_rx_buff_failed++;
580 goto no_buffers;
581 }
582
583 /*
584 * Make buffer alignment 2 beyond a 16 byte boundary
585 * this will result in a 16 byte aligned IP header after
586 * the 14 byte MAC header is removed
587 */
588 skb_reserve(skb, NET_IP_ALIGN);
589
590 bi->skb = skb;
591 bi->dma = pci_map_single(pdev, skb->data, bufsz,
592 PCI_DMA_FROMDEVICE);
593 }
594 /* Refresh the desc even if buffer_addrs didn't change because
595 * each write-back erases this info. */
596 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
597 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
598 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
599 } else {
600 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
601 }
602
603 i++;
604 if (i == rx_ring->count)
605 i = 0;
606 bi = &rx_ring->rx_buffer_info[i];
607 }
608
609 no_buffers:
610 if (rx_ring->next_to_use != i) {
611 rx_ring->next_to_use = i;
612 if (i-- == 0)
613 i = (rx_ring->count - 1);
614
615 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
616 }
617 }
618
619 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
620 {
621 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
622 }
623
624 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
625 {
626 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
627 }
628
629 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
630 {
631 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
632 IXGBE_RXDADV_RSCCNT_MASK) >>
633 IXGBE_RXDADV_RSCCNT_SHIFT;
634 }
635
636 /**
637 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
638 * @skb: pointer to the last skb in the rsc queue
639 *
640 * This function changes a queue full of hw rsc buffers into a completed
641 * packet. It uses the ->prev pointers to find the first packet and then
642 * turns it into the frag list owner.
643 **/
644 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
645 {
646 unsigned int frag_list_size = 0;
647
648 while (skb->prev) {
649 struct sk_buff *prev = skb->prev;
650 frag_list_size += skb->len;
651 skb->prev = NULL;
652 skb = prev;
653 }
654
655 skb_shinfo(skb)->frag_list = skb->next;
656 skb->next = NULL;
657 skb->len += frag_list_size;
658 skb->data_len += frag_list_size;
659 skb->truesize += frag_list_size;
660 return skb;
661 }
662
663 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
664 struct ixgbe_ring *rx_ring,
665 int *work_done, int work_to_do)
666 {
667 struct ixgbe_adapter *adapter = q_vector->adapter;
668 struct pci_dev *pdev = adapter->pdev;
669 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
670 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
671 struct sk_buff *skb;
672 unsigned int i, rsc_count = 0;
673 u32 len, staterr;
674 u16 hdr_info;
675 bool cleaned = false;
676 int cleaned_count = 0;
677 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
678
679 i = rx_ring->next_to_clean;
680 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
681 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
682 rx_buffer_info = &rx_ring->rx_buffer_info[i];
683
684 while (staterr & IXGBE_RXD_STAT_DD) {
685 u32 upper_len = 0;
686 if (*work_done >= work_to_do)
687 break;
688 (*work_done)++;
689
690 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
691 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
692 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
693 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
694 if (hdr_info & IXGBE_RXDADV_SPH)
695 adapter->rx_hdr_split++;
696 if (len > IXGBE_RX_HDR_SIZE)
697 len = IXGBE_RX_HDR_SIZE;
698 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
699 } else {
700 len = le16_to_cpu(rx_desc->wb.upper.length);
701 }
702
703 cleaned = true;
704 skb = rx_buffer_info->skb;
705 prefetch(skb->data - NET_IP_ALIGN);
706 rx_buffer_info->skb = NULL;
707
708 if (len && !skb_shinfo(skb)->nr_frags) {
709 pci_unmap_single(pdev, rx_buffer_info->dma,
710 rx_ring->rx_buf_len,
711 PCI_DMA_FROMDEVICE);
712 skb_put(skb, len);
713 }
714
715 if (upper_len) {
716 pci_unmap_page(pdev, rx_buffer_info->page_dma,
717 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
718 rx_buffer_info->page_dma = 0;
719 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
720 rx_buffer_info->page,
721 rx_buffer_info->page_offset,
722 upper_len);
723
724 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
725 (page_count(rx_buffer_info->page) != 1))
726 rx_buffer_info->page = NULL;
727 else
728 get_page(rx_buffer_info->page);
729
730 skb->len += upper_len;
731 skb->data_len += upper_len;
732 skb->truesize += upper_len;
733 }
734
735 i++;
736 if (i == rx_ring->count)
737 i = 0;
738
739 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
740 prefetch(next_rxd);
741 cleaned_count++;
742
743 if (adapter->flags & IXGBE_FLAG_RSC_CAPABLE)
744 rsc_count = ixgbe_get_rsc_count(rx_desc);
745
746 if (rsc_count) {
747 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
748 IXGBE_RXDADV_NEXTP_SHIFT;
749 next_buffer = &rx_ring->rx_buffer_info[nextp];
750 rx_ring->rsc_count += (rsc_count - 1);
751 } else {
752 next_buffer = &rx_ring->rx_buffer_info[i];
753 }
754
755 if (staterr & IXGBE_RXD_STAT_EOP) {
756 if (skb->prev)
757 skb = ixgbe_transform_rsc_queue(skb);
758 rx_ring->stats.packets++;
759 rx_ring->stats.bytes += skb->len;
760 } else {
761 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
762 rx_buffer_info->skb = next_buffer->skb;
763 rx_buffer_info->dma = next_buffer->dma;
764 next_buffer->skb = skb;
765 next_buffer->dma = 0;
766 } else {
767 skb->next = next_buffer->skb;
768 skb->next->prev = skb;
769 }
770 adapter->non_eop_descs++;
771 goto next_desc;
772 }
773
774 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
775 dev_kfree_skb_irq(skb);
776 goto next_desc;
777 }
778
779 ixgbe_rx_checksum(adapter, staterr, skb);
780
781 /* probably a little skewed due to removing CRC */
782 total_rx_bytes += skb->len;
783 total_rx_packets++;
784
785 skb->protocol = eth_type_trans(skb, adapter->netdev);
786 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
787
788 next_desc:
789 rx_desc->wb.upper.status_error = 0;
790
791 /* return some buffers to hardware, one at a time is too slow */
792 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
793 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
794 cleaned_count = 0;
795 }
796
797 /* use prefetched values */
798 rx_desc = next_rxd;
799 rx_buffer_info = &rx_ring->rx_buffer_info[i];
800
801 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
802 }
803
804 rx_ring->next_to_clean = i;
805 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
806
807 if (cleaned_count)
808 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
809
810 rx_ring->total_packets += total_rx_packets;
811 rx_ring->total_bytes += total_rx_bytes;
812 adapter->net_stats.rx_bytes += total_rx_bytes;
813 adapter->net_stats.rx_packets += total_rx_packets;
814
815 return cleaned;
816 }
817
818 static int ixgbe_clean_rxonly(struct napi_struct *, int);
819 /**
820 * ixgbe_configure_msix - Configure MSI-X hardware
821 * @adapter: board private structure
822 *
823 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
824 * interrupts.
825 **/
826 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
827 {
828 struct ixgbe_q_vector *q_vector;
829 int i, j, q_vectors, v_idx, r_idx;
830 u32 mask;
831
832 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
833
834 /*
835 * Populate the IVAR table and set the ITR values to the
836 * corresponding register.
837 */
838 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
839 q_vector = adapter->q_vector[v_idx];
840 /* XXX for_each_bit(...) */
841 r_idx = find_first_bit(q_vector->rxr_idx,
842 adapter->num_rx_queues);
843
844 for (i = 0; i < q_vector->rxr_count; i++) {
845 j = adapter->rx_ring[r_idx].reg_idx;
846 ixgbe_set_ivar(adapter, 0, j, v_idx);
847 r_idx = find_next_bit(q_vector->rxr_idx,
848 adapter->num_rx_queues,
849 r_idx + 1);
850 }
851 r_idx = find_first_bit(q_vector->txr_idx,
852 adapter->num_tx_queues);
853
854 for (i = 0; i < q_vector->txr_count; i++) {
855 j = adapter->tx_ring[r_idx].reg_idx;
856 ixgbe_set_ivar(adapter, 1, j, v_idx);
857 r_idx = find_next_bit(q_vector->txr_idx,
858 adapter->num_tx_queues,
859 r_idx + 1);
860 }
861
862 /* if this is a tx only vector halve the interrupt rate */
863 if (q_vector->txr_count && !q_vector->rxr_count)
864 q_vector->eitr = (adapter->eitr_param >> 1);
865 else if (q_vector->rxr_count)
866 /* rx only */
867 q_vector->eitr = adapter->eitr_param;
868
869 /*
870 * since this is initial set up don't need to call
871 * ixgbe_write_eitr helper
872 */
873 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
874 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
875 }
876
877 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
878 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
879 v_idx);
880 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
881 ixgbe_set_ivar(adapter, -1, 1, v_idx);
882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
883
884 /* set up to autoclear timer, and the vectors */
885 mask = IXGBE_EIMS_ENABLE_MASK;
886 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
887 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
888 }
889
890 enum latency_range {
891 lowest_latency = 0,
892 low_latency = 1,
893 bulk_latency = 2,
894 latency_invalid = 255
895 };
896
897 /**
898 * ixgbe_update_itr - update the dynamic ITR value based on statistics
899 * @adapter: pointer to adapter
900 * @eitr: eitr setting (ints per sec) to give last timeslice
901 * @itr_setting: current throttle rate in ints/second
902 * @packets: the number of packets during this measurement interval
903 * @bytes: the number of bytes during this measurement interval
904 *
905 * Stores a new ITR value based on packets and byte
906 * counts during the last interrupt. The advantage of per interrupt
907 * computation is faster updates and more accurate ITR for the current
908 * traffic pattern. Constants in this function were computed
909 * based on theoretical maximum wire speed and thresholds were set based
910 * on testing data as well as attempting to minimize response time
911 * while increasing bulk throughput.
912 * this functionality is controlled by the InterruptThrottleRate module
913 * parameter (see ixgbe_param.c)
914 **/
915 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
916 u32 eitr, u8 itr_setting,
917 int packets, int bytes)
918 {
919 unsigned int retval = itr_setting;
920 u32 timepassed_us;
921 u64 bytes_perint;
922
923 if (packets == 0)
924 goto update_itr_done;
925
926
927 /* simple throttlerate management
928 * 0-20MB/s lowest (100000 ints/s)
929 * 20-100MB/s low (20000 ints/s)
930 * 100-1249MB/s bulk (8000 ints/s)
931 */
932 /* what was last interrupt timeslice? */
933 timepassed_us = 1000000/eitr;
934 bytes_perint = bytes / timepassed_us; /* bytes/usec */
935
936 switch (itr_setting) {
937 case lowest_latency:
938 if (bytes_perint > adapter->eitr_low)
939 retval = low_latency;
940 break;
941 case low_latency:
942 if (bytes_perint > adapter->eitr_high)
943 retval = bulk_latency;
944 else if (bytes_perint <= adapter->eitr_low)
945 retval = lowest_latency;
946 break;
947 case bulk_latency:
948 if (bytes_perint <= adapter->eitr_high)
949 retval = low_latency;
950 break;
951 }
952
953 update_itr_done:
954 return retval;
955 }
956
957 /**
958 * ixgbe_write_eitr - write EITR register in hardware specific way
959 * @adapter: pointer to adapter struct
960 * @v_idx: vector index into q_vector array
961 * @itr_reg: new value to be written in *register* format, not ints/s
962 *
963 * This function is made to be called by ethtool and by the driver
964 * when it needs to update EITR registers at runtime. Hardware
965 * specific quirks/differences are taken care of here.
966 */
967 void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg)
968 {
969 struct ixgbe_hw *hw = &adapter->hw;
970 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
971 /* must write high and low 16 bits to reset counter */
972 itr_reg |= (itr_reg << 16);
973 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
974 /*
975 * set the WDIS bit to not clear the timer bits and cause an
976 * immediate assertion of the interrupt
977 */
978 itr_reg |= IXGBE_EITR_CNT_WDIS;
979 }
980 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
981 }
982
983 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
984 {
985 struct ixgbe_adapter *adapter = q_vector->adapter;
986 u32 new_itr;
987 u8 current_itr, ret_itr;
988 int i, r_idx, v_idx = q_vector->v_idx;
989 struct ixgbe_ring *rx_ring, *tx_ring;
990
991 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
992 for (i = 0; i < q_vector->txr_count; i++) {
993 tx_ring = &(adapter->tx_ring[r_idx]);
994 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
995 q_vector->tx_itr,
996 tx_ring->total_packets,
997 tx_ring->total_bytes);
998 /* if the result for this queue would decrease interrupt
999 * rate for this vector then use that result */
1000 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1001 q_vector->tx_itr - 1 : ret_itr);
1002 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1003 r_idx + 1);
1004 }
1005
1006 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1007 for (i = 0; i < q_vector->rxr_count; i++) {
1008 rx_ring = &(adapter->rx_ring[r_idx]);
1009 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1010 q_vector->rx_itr,
1011 rx_ring->total_packets,
1012 rx_ring->total_bytes);
1013 /* if the result for this queue would decrease interrupt
1014 * rate for this vector then use that result */
1015 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1016 q_vector->rx_itr - 1 : ret_itr);
1017 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1018 r_idx + 1);
1019 }
1020
1021 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1022
1023 switch (current_itr) {
1024 /* counts and packets in update_itr are dependent on these numbers */
1025 case lowest_latency:
1026 new_itr = 100000;
1027 break;
1028 case low_latency:
1029 new_itr = 20000; /* aka hwitr = ~200 */
1030 break;
1031 case bulk_latency:
1032 default:
1033 new_itr = 8000;
1034 break;
1035 }
1036
1037 if (new_itr != q_vector->eitr) {
1038 u32 itr_reg;
1039
1040 /* save the algorithm value here, not the smoothed one */
1041 q_vector->eitr = new_itr;
1042 /* do an exponential smoothing */
1043 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1044 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1045 ixgbe_write_eitr(adapter, v_idx, itr_reg);
1046 }
1047
1048 return;
1049 }
1050
1051 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1052 {
1053 struct ixgbe_hw *hw = &adapter->hw;
1054
1055 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1056 (eicr & IXGBE_EICR_GPI_SDP1)) {
1057 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1058 /* write to clear the interrupt */
1059 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1060 }
1061 }
1062
1063 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1064 {
1065 struct ixgbe_hw *hw = &adapter->hw;
1066
1067 if (eicr & IXGBE_EICR_GPI_SDP1) {
1068 /* Clear the interrupt */
1069 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1070 schedule_work(&adapter->multispeed_fiber_task);
1071 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1072 /* Clear the interrupt */
1073 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1074 schedule_work(&adapter->sfp_config_module_task);
1075 } else {
1076 /* Interrupt isn't for us... */
1077 return;
1078 }
1079 }
1080
1081 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1082 {
1083 struct ixgbe_hw *hw = &adapter->hw;
1084
1085 adapter->lsc_int++;
1086 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1087 adapter->link_check_timeout = jiffies;
1088 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1089 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1090 schedule_work(&adapter->watchdog_task);
1091 }
1092 }
1093
1094 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1095 {
1096 struct net_device *netdev = data;
1097 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1098 struct ixgbe_hw *hw = &adapter->hw;
1099 u32 eicr;
1100
1101 /*
1102 * Workaround for Silicon errata. Use clear-by-write instead
1103 * of clear-by-read. Reading with EICS will return the
1104 * interrupt causes without clearing, which later be done
1105 * with the write to EICR.
1106 */
1107 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1108 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1109
1110 if (eicr & IXGBE_EICR_LSC)
1111 ixgbe_check_lsc(adapter);
1112
1113 if (hw->mac.type == ixgbe_mac_82598EB)
1114 ixgbe_check_fan_failure(adapter, eicr);
1115
1116 if (hw->mac.type == ixgbe_mac_82599EB)
1117 ixgbe_check_sfp_event(adapter, eicr);
1118 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1119 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1120
1121 return IRQ_HANDLED;
1122 }
1123
1124 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1125 {
1126 struct ixgbe_q_vector *q_vector = data;
1127 struct ixgbe_adapter *adapter = q_vector->adapter;
1128 struct ixgbe_ring *tx_ring;
1129 int i, r_idx;
1130
1131 if (!q_vector->txr_count)
1132 return IRQ_HANDLED;
1133
1134 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1135 for (i = 0; i < q_vector->txr_count; i++) {
1136 tx_ring = &(adapter->tx_ring[r_idx]);
1137 #ifdef CONFIG_IXGBE_DCA
1138 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1139 ixgbe_update_tx_dca(adapter, tx_ring);
1140 #endif
1141 tx_ring->total_bytes = 0;
1142 tx_ring->total_packets = 0;
1143 ixgbe_clean_tx_irq(adapter, tx_ring);
1144 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1145 r_idx + 1);
1146 }
1147
1148 return IRQ_HANDLED;
1149 }
1150
1151 /**
1152 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1153 * @irq: unused
1154 * @data: pointer to our q_vector struct for this interrupt vector
1155 **/
1156 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1157 {
1158 struct ixgbe_q_vector *q_vector = data;
1159 struct ixgbe_adapter *adapter = q_vector->adapter;
1160 struct ixgbe_ring *rx_ring;
1161 int r_idx;
1162 int i;
1163
1164 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1165 for (i = 0; i < q_vector->rxr_count; i++) {
1166 rx_ring = &(adapter->rx_ring[r_idx]);
1167 rx_ring->total_bytes = 0;
1168 rx_ring->total_packets = 0;
1169 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1170 r_idx + 1);
1171 }
1172
1173 if (!q_vector->rxr_count)
1174 return IRQ_HANDLED;
1175
1176 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1177 rx_ring = &(adapter->rx_ring[r_idx]);
1178 /* disable interrupts on this vector only */
1179 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1180 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
1181 else if (rx_ring->v_idx & 0xFFFFFFFF)
1182 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), rx_ring->v_idx);
1183 else
1184 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1),
1185 (rx_ring->v_idx >> 32));
1186 napi_schedule(&q_vector->napi);
1187
1188 return IRQ_HANDLED;
1189 }
1190
1191 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1192 {
1193 ixgbe_msix_clean_rx(irq, data);
1194 ixgbe_msix_clean_tx(irq, data);
1195
1196 return IRQ_HANDLED;
1197 }
1198
1199 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1200 u64 qmask)
1201 {
1202 u32 mask;
1203
1204 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1205 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1206 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1207 } else {
1208 mask = (qmask & 0xFFFFFFFF);
1209 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1210 mask = (qmask >> 32);
1211 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1212 }
1213 /* skip the flush */
1214 }
1215
1216 /**
1217 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1218 * @napi: napi struct with our devices info in it
1219 * @budget: amount of work driver is allowed to do this pass, in packets
1220 *
1221 * This function is optimized for cleaning one queue only on a single
1222 * q_vector!!!
1223 **/
1224 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1225 {
1226 struct ixgbe_q_vector *q_vector =
1227 container_of(napi, struct ixgbe_q_vector, napi);
1228 struct ixgbe_adapter *adapter = q_vector->adapter;
1229 struct ixgbe_ring *rx_ring = NULL;
1230 int work_done = 0;
1231 long r_idx;
1232
1233 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1234 rx_ring = &(adapter->rx_ring[r_idx]);
1235 #ifdef CONFIG_IXGBE_DCA
1236 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1237 ixgbe_update_rx_dca(adapter, rx_ring);
1238 #endif
1239
1240 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1241
1242 /* If all Rx work done, exit the polling mode */
1243 if (work_done < budget) {
1244 napi_complete(napi);
1245 if (adapter->itr_setting & 1)
1246 ixgbe_set_itr_msix(q_vector);
1247 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1248 ixgbe_irq_enable_queues(adapter, rx_ring->v_idx);
1249 }
1250
1251 return work_done;
1252 }
1253
1254 /**
1255 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1256 * @napi: napi struct with our devices info in it
1257 * @budget: amount of work driver is allowed to do this pass, in packets
1258 *
1259 * This function will clean more than one rx queue associated with a
1260 * q_vector.
1261 **/
1262 static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1263 {
1264 struct ixgbe_q_vector *q_vector =
1265 container_of(napi, struct ixgbe_q_vector, napi);
1266 struct ixgbe_adapter *adapter = q_vector->adapter;
1267 struct ixgbe_ring *rx_ring = NULL;
1268 int work_done = 0, i;
1269 long r_idx;
1270 u64 enable_mask = 0;
1271
1272 /* attempt to distribute budget to each queue fairly, but don't allow
1273 * the budget to go below 1 because we'll exit polling */
1274 budget /= (q_vector->rxr_count ?: 1);
1275 budget = max(budget, 1);
1276 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1277 for (i = 0; i < q_vector->rxr_count; i++) {
1278 rx_ring = &(adapter->rx_ring[r_idx]);
1279 #ifdef CONFIG_IXGBE_DCA
1280 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1281 ixgbe_update_rx_dca(adapter, rx_ring);
1282 #endif
1283 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1284 enable_mask |= rx_ring->v_idx;
1285 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1286 r_idx + 1);
1287 }
1288
1289 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1290 rx_ring = &(adapter->rx_ring[r_idx]);
1291 /* If all Rx work done, exit the polling mode */
1292 if (work_done < budget) {
1293 napi_complete(napi);
1294 if (adapter->itr_setting & 1)
1295 ixgbe_set_itr_msix(q_vector);
1296 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1297 ixgbe_irq_enable_queues(adapter, enable_mask);
1298 return 0;
1299 }
1300
1301 return work_done;
1302 }
1303 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1304 int r_idx)
1305 {
1306 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1307
1308 set_bit(r_idx, q_vector->rxr_idx);
1309 q_vector->rxr_count++;
1310 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1311 }
1312
1313 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1314 int t_idx)
1315 {
1316 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1317
1318 set_bit(t_idx, q_vector->txr_idx);
1319 q_vector->txr_count++;
1320 a->tx_ring[t_idx].v_idx = 1 << v_idx;
1321 }
1322
1323 /**
1324 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1325 * @adapter: board private structure to initialize
1326 * @vectors: allotted vector count for descriptor rings
1327 *
1328 * This function maps descriptor rings to the queue-specific vectors
1329 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1330 * one vector per ring/queue, but on a constrained vector budget, we
1331 * group the rings as "efficiently" as possible. You would add new
1332 * mapping configurations in here.
1333 **/
1334 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1335 int vectors)
1336 {
1337 int v_start = 0;
1338 int rxr_idx = 0, txr_idx = 0;
1339 int rxr_remaining = adapter->num_rx_queues;
1340 int txr_remaining = adapter->num_tx_queues;
1341 int i, j;
1342 int rqpv, tqpv;
1343 int err = 0;
1344
1345 /* No mapping required if MSI-X is disabled. */
1346 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1347 goto out;
1348
1349 /*
1350 * The ideal configuration...
1351 * We have enough vectors to map one per queue.
1352 */
1353 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1354 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1355 map_vector_to_rxq(adapter, v_start, rxr_idx);
1356
1357 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1358 map_vector_to_txq(adapter, v_start, txr_idx);
1359
1360 goto out;
1361 }
1362
1363 /*
1364 * If we don't have enough vectors for a 1-to-1
1365 * mapping, we'll have to group them so there are
1366 * multiple queues per vector.
1367 */
1368 /* Re-adjusting *qpv takes care of the remainder. */
1369 for (i = v_start; i < vectors; i++) {
1370 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1371 for (j = 0; j < rqpv; j++) {
1372 map_vector_to_rxq(adapter, i, rxr_idx);
1373 rxr_idx++;
1374 rxr_remaining--;
1375 }
1376 }
1377 for (i = v_start; i < vectors; i++) {
1378 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1379 for (j = 0; j < tqpv; j++) {
1380 map_vector_to_txq(adapter, i, txr_idx);
1381 txr_idx++;
1382 txr_remaining--;
1383 }
1384 }
1385
1386 out:
1387 return err;
1388 }
1389
1390 /**
1391 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1392 * @adapter: board private structure
1393 *
1394 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1395 * interrupts from the kernel.
1396 **/
1397 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1398 {
1399 struct net_device *netdev = adapter->netdev;
1400 irqreturn_t (*handler)(int, void *);
1401 int i, vector, q_vectors, err;
1402 int ri=0, ti=0;
1403
1404 /* Decrement for Other and TCP Timer vectors */
1405 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1406
1407 /* Map the Tx/Rx rings to the vectors we were allotted. */
1408 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1409 if (err)
1410 goto out;
1411
1412 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1413 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1414 &ixgbe_msix_clean_many)
1415 for (vector = 0; vector < q_vectors; vector++) {
1416 handler = SET_HANDLER(adapter->q_vector[vector]);
1417
1418 if(handler == &ixgbe_msix_clean_rx) {
1419 sprintf(adapter->name[vector], "%s-%s-%d",
1420 netdev->name, "rx", ri++);
1421 }
1422 else if(handler == &ixgbe_msix_clean_tx) {
1423 sprintf(adapter->name[vector], "%s-%s-%d",
1424 netdev->name, "tx", ti++);
1425 }
1426 else
1427 sprintf(adapter->name[vector], "%s-%s-%d",
1428 netdev->name, "TxRx", vector);
1429
1430 err = request_irq(adapter->msix_entries[vector].vector,
1431 handler, 0, adapter->name[vector],
1432 adapter->q_vector[vector]);
1433 if (err) {
1434 DPRINTK(PROBE, ERR,
1435 "request_irq failed for MSIX interrupt "
1436 "Error: %d\n", err);
1437 goto free_queue_irqs;
1438 }
1439 }
1440
1441 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1442 err = request_irq(adapter->msix_entries[vector].vector,
1443 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1444 if (err) {
1445 DPRINTK(PROBE, ERR,
1446 "request_irq for msix_lsc failed: %d\n", err);
1447 goto free_queue_irqs;
1448 }
1449
1450 return 0;
1451
1452 free_queue_irqs:
1453 for (i = vector - 1; i >= 0; i--)
1454 free_irq(adapter->msix_entries[--vector].vector,
1455 adapter->q_vector[i]);
1456 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1457 pci_disable_msix(adapter->pdev);
1458 kfree(adapter->msix_entries);
1459 adapter->msix_entries = NULL;
1460 out:
1461 return err;
1462 }
1463
1464 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1465 {
1466 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1467 u8 current_itr;
1468 u32 new_itr = q_vector->eitr;
1469 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1470 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1471
1472 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1473 q_vector->tx_itr,
1474 tx_ring->total_packets,
1475 tx_ring->total_bytes);
1476 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1477 q_vector->rx_itr,
1478 rx_ring->total_packets,
1479 rx_ring->total_bytes);
1480
1481 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1482
1483 switch (current_itr) {
1484 /* counts and packets in update_itr are dependent on these numbers */
1485 case lowest_latency:
1486 new_itr = 100000;
1487 break;
1488 case low_latency:
1489 new_itr = 20000; /* aka hwitr = ~200 */
1490 break;
1491 case bulk_latency:
1492 new_itr = 8000;
1493 break;
1494 default:
1495 break;
1496 }
1497
1498 if (new_itr != q_vector->eitr) {
1499 u32 itr_reg;
1500
1501 /* save the algorithm value here, not the smoothed one */
1502 q_vector->eitr = new_itr;
1503 /* do an exponential smoothing */
1504 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1505 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1506 ixgbe_write_eitr(adapter, 0, itr_reg);
1507 }
1508
1509 return;
1510 }
1511
1512 /**
1513 * ixgbe_irq_enable - Enable default interrupt generation settings
1514 * @adapter: board private structure
1515 **/
1516 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1517 {
1518 u32 mask;
1519
1520 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1521 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1522 mask |= IXGBE_EIMS_GPI_SDP1;
1523 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1524 mask |= IXGBE_EIMS_ECC;
1525 mask |= IXGBE_EIMS_GPI_SDP1;
1526 mask |= IXGBE_EIMS_GPI_SDP2;
1527 }
1528
1529 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1530 ixgbe_irq_enable_queues(adapter, ~0);
1531 IXGBE_WRITE_FLUSH(&adapter->hw);
1532 }
1533
1534 /**
1535 * ixgbe_intr - legacy mode Interrupt Handler
1536 * @irq: interrupt number
1537 * @data: pointer to a network interface device structure
1538 **/
1539 static irqreturn_t ixgbe_intr(int irq, void *data)
1540 {
1541 struct net_device *netdev = data;
1542 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1543 struct ixgbe_hw *hw = &adapter->hw;
1544 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1545 u32 eicr;
1546
1547 /*
1548 * Workaround for silicon errata. Mask the interrupts
1549 * before the read of EICR.
1550 */
1551 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1552
1553 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1554 * therefore no explict interrupt disable is necessary */
1555 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1556 if (!eicr) {
1557 /* shared interrupt alert!
1558 * make sure interrupts are enabled because the read will
1559 * have disabled interrupts due to EIAM */
1560 ixgbe_irq_enable(adapter);
1561 return IRQ_NONE; /* Not our interrupt */
1562 }
1563
1564 if (eicr & IXGBE_EICR_LSC)
1565 ixgbe_check_lsc(adapter);
1566
1567 if (hw->mac.type == ixgbe_mac_82599EB)
1568 ixgbe_check_sfp_event(adapter, eicr);
1569
1570 ixgbe_check_fan_failure(adapter, eicr);
1571
1572 if (napi_schedule_prep(&(q_vector->napi))) {
1573 adapter->tx_ring[0].total_packets = 0;
1574 adapter->tx_ring[0].total_bytes = 0;
1575 adapter->rx_ring[0].total_packets = 0;
1576 adapter->rx_ring[0].total_bytes = 0;
1577 /* would disable interrupts here but EIAM disabled it */
1578 __napi_schedule(&(q_vector->napi));
1579 }
1580
1581 return IRQ_HANDLED;
1582 }
1583
1584 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1585 {
1586 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1587
1588 for (i = 0; i < q_vectors; i++) {
1589 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1590 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1591 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1592 q_vector->rxr_count = 0;
1593 q_vector->txr_count = 0;
1594 }
1595 }
1596
1597 /**
1598 * ixgbe_request_irq - initialize interrupts
1599 * @adapter: board private structure
1600 *
1601 * Attempts to configure interrupts using the best available
1602 * capabilities of the hardware and kernel.
1603 **/
1604 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1605 {
1606 struct net_device *netdev = adapter->netdev;
1607 int err;
1608
1609 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1610 err = ixgbe_request_msix_irqs(adapter);
1611 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1612 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1613 netdev->name, netdev);
1614 } else {
1615 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1616 netdev->name, netdev);
1617 }
1618
1619 if (err)
1620 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1621
1622 return err;
1623 }
1624
1625 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1626 {
1627 struct net_device *netdev = adapter->netdev;
1628
1629 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1630 int i, q_vectors;
1631
1632 q_vectors = adapter->num_msix_vectors;
1633
1634 i = q_vectors - 1;
1635 free_irq(adapter->msix_entries[i].vector, netdev);
1636
1637 i--;
1638 for (; i >= 0; i--) {
1639 free_irq(adapter->msix_entries[i].vector,
1640 adapter->q_vector[i]);
1641 }
1642
1643 ixgbe_reset_q_vectors(adapter);
1644 } else {
1645 free_irq(adapter->pdev->irq, netdev);
1646 }
1647 }
1648
1649 /**
1650 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1651 * @adapter: board private structure
1652 **/
1653 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1654 {
1655 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1656 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1657 } else {
1658 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1659 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1660 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1661 }
1662 IXGBE_WRITE_FLUSH(&adapter->hw);
1663 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1664 int i;
1665 for (i = 0; i < adapter->num_msix_vectors; i++)
1666 synchronize_irq(adapter->msix_entries[i].vector);
1667 } else {
1668 synchronize_irq(adapter->pdev->irq);
1669 }
1670 }
1671
1672 /**
1673 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1674 *
1675 **/
1676 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1677 {
1678 struct ixgbe_hw *hw = &adapter->hw;
1679
1680 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1681 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1682
1683 ixgbe_set_ivar(adapter, 0, 0, 0);
1684 ixgbe_set_ivar(adapter, 1, 0, 0);
1685
1686 map_vector_to_rxq(adapter, 0, 0);
1687 map_vector_to_txq(adapter, 0, 0);
1688
1689 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1690 }
1691
1692 /**
1693 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1694 * @adapter: board private structure
1695 *
1696 * Configure the Tx unit of the MAC after a reset.
1697 **/
1698 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1699 {
1700 u64 tdba;
1701 struct ixgbe_hw *hw = &adapter->hw;
1702 u32 i, j, tdlen, txctrl;
1703
1704 /* Setup the HW Tx Head and Tail descriptor pointers */
1705 for (i = 0; i < adapter->num_tx_queues; i++) {
1706 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1707 j = ring->reg_idx;
1708 tdba = ring->dma;
1709 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1710 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1711 (tdba & DMA_BIT_MASK(32)));
1712 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1713 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1714 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1715 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1716 adapter->tx_ring[i].head = IXGBE_TDH(j);
1717 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1718 /* Disable Tx Head Writeback RO bit, since this hoses
1719 * bookkeeping if things aren't delivered in order.
1720 */
1721 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1722 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1723 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1724 }
1725 if (hw->mac.type == ixgbe_mac_82599EB) {
1726 /* We enable 8 traffic classes, DCB only */
1727 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1728 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1729 IXGBE_MTQC_8TC_8TQ));
1730 }
1731 }
1732
1733 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1734
1735 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1736 {
1737 struct ixgbe_ring *rx_ring;
1738 u32 srrctl;
1739 int queue0 = 0;
1740 unsigned long mask;
1741
1742 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1743 queue0 = index;
1744 } else {
1745 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1746 queue0 = index & mask;
1747 index = index & mask;
1748 }
1749
1750 rx_ring = &adapter->rx_ring[queue0];
1751
1752 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1753
1754 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1755 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1756
1757 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1758 IXGBE_SRRCTL_BSIZEHDR_MASK;
1759
1760 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1761 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1762 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1763 #else
1764 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1765 #endif
1766 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1767 } else {
1768 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1769 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1770 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1771 }
1772
1773 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1774 }
1775
1776 /**
1777 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1778 * @adapter: board private structure
1779 *
1780 * Configure the Rx unit of the MAC after a reset.
1781 **/
1782 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1783 {
1784 u64 rdba;
1785 struct ixgbe_hw *hw = &adapter->hw;
1786 struct net_device *netdev = adapter->netdev;
1787 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1788 int i, j;
1789 u32 rdlen, rxctrl, rxcsum;
1790 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1791 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1792 0x6A3E67EA, 0x14364D17, 0x3BED200D};
1793 u32 fctrl, hlreg0;
1794 u32 reta = 0, mrqc = 0;
1795 u32 rdrxctl;
1796 u32 rscctrl;
1797 int rx_buf_len;
1798
1799 /* Decide whether to use packet split mode or not */
1800 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1801
1802 /* Set the RX buffer length according to the mode */
1803 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1804 rx_buf_len = IXGBE_RX_HDR_SIZE;
1805 if (hw->mac.type == ixgbe_mac_82599EB) {
1806 /* PSRTYPE must be initialized in 82599 */
1807 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1808 IXGBE_PSRTYPE_UDPHDR |
1809 IXGBE_PSRTYPE_IPV4HDR |
1810 IXGBE_PSRTYPE_IPV6HDR;
1811 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
1812 }
1813 } else {
1814 if (!(adapter->flags & IXGBE_FLAG_RSC_ENABLED) &&
1815 (netdev->mtu <= ETH_DATA_LEN))
1816 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1817 else
1818 rx_buf_len = ALIGN(max_frame, 1024);
1819 }
1820
1821 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1822 fctrl |= IXGBE_FCTRL_BAM;
1823 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
1824 fctrl |= IXGBE_FCTRL_PMCF;
1825 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1826
1827 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1828 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1829 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1830 else
1831 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1832 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1833
1834 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1835 /* disable receives while setting up the descriptors */
1836 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1837 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1838
1839 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1840 * the Base and Length of the Rx Descriptor Ring */
1841 for (i = 0; i < adapter->num_rx_queues; i++) {
1842 rdba = adapter->rx_ring[i].dma;
1843 j = adapter->rx_ring[i].reg_idx;
1844 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
1845 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1846 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1847 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1848 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1849 adapter->rx_ring[i].head = IXGBE_RDH(j);
1850 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1851 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
1852
1853 ixgbe_configure_srrctl(adapter, j);
1854 }
1855
1856 if (hw->mac.type == ixgbe_mac_82598EB) {
1857 /*
1858 * For VMDq support of different descriptor types or
1859 * buffer sizes through the use of multiple SRRCTL
1860 * registers, RDRXCTL.MVMEN must be set to 1
1861 *
1862 * also, the manual doesn't mention it clearly but DCA hints
1863 * will only use queue 0's tags unless this bit is set. Side
1864 * effects of setting this bit are only that SRRCTL must be
1865 * fully programmed [0..15]
1866 */
1867 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1868 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1869 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1870 }
1871
1872 /* Program MRQC for the distribution of queues */
1873 if (hw->mac.type == ixgbe_mac_82599EB) {
1874 int mask = adapter->flags & (
1875 IXGBE_FLAG_RSS_ENABLED
1876 | IXGBE_FLAG_DCB_ENABLED
1877 );
1878
1879 switch (mask) {
1880 case (IXGBE_FLAG_RSS_ENABLED):
1881 mrqc = IXGBE_MRQC_RSSEN;
1882 break;
1883 case (IXGBE_FLAG_DCB_ENABLED):
1884 mrqc = IXGBE_MRQC_RT8TCEN;
1885 break;
1886 default:
1887 break;
1888 }
1889 }
1890 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
1891 /* Fill out redirection table */
1892 for (i = 0, j = 0; i < 128; i++, j++) {
1893 if (j == adapter->ring_feature[RING_F_RSS].indices)
1894 j = 0;
1895 /* reta = 4-byte sliding window of
1896 * 0x00..(indices-1)(indices-1)00..etc. */
1897 reta = (reta << 8) | (j * 0x11);
1898 if ((i & 3) == 3)
1899 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
1900 }
1901
1902 /* Fill out hash function seeds */
1903 for (i = 0; i < 10; i++)
1904 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
1905
1906 if (hw->mac.type == ixgbe_mac_82598EB)
1907 mrqc |= IXGBE_MRQC_RSSEN;
1908 /* Perform hash on these packet types */
1909 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
1910 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1911 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1912 | IXGBE_MRQC_RSS_FIELD_IPV6
1913 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1914 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
1915 }
1916 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
1917
1918 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1919
1920 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1921 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1922 /* Disable indicating checksum in descriptor, enables
1923 * RSS hash */
1924 rxcsum |= IXGBE_RXCSUM_PCSD;
1925 }
1926 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1927 /* Enable IPv4 payload checksum for UDP fragments
1928 * if PCSD is not set */
1929 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1930 }
1931
1932 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
1933
1934 if (hw->mac.type == ixgbe_mac_82599EB) {
1935 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1936 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
1937 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
1938 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1939 }
1940
1941 if (adapter->flags & IXGBE_FLAG_RSC_ENABLED) {
1942 /* Enable 82599 HW-RSC */
1943 for (i = 0; i < adapter->num_rx_queues; i++) {
1944 j = adapter->rx_ring[i].reg_idx;
1945 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
1946 rscctrl |= IXGBE_RSCCTL_RSCEN;
1947 /*
1948 * if packet split is enabled we can only support up
1949 * to max frags + 1 descriptors.
1950 */
1951 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
1952 #if (MAX_SKB_FRAGS < 3)
1953 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
1954 #elif (MAX_SKB_FRAGS < 7)
1955 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
1956 #elif (MAX_SKB_FRAGS < 15)
1957 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
1958 #else
1959 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
1960 #endif
1961 else
1962 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
1963 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
1964 }
1965 /* Disable RSC for ACK packets */
1966 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
1967 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
1968 }
1969 }
1970
1971 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1972 {
1973 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1974 struct ixgbe_hw *hw = &adapter->hw;
1975
1976 /* add VID to filter table */
1977 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1978 }
1979
1980 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1981 {
1982 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1983 struct ixgbe_hw *hw = &adapter->hw;
1984
1985 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1986 ixgbe_irq_disable(adapter);
1987
1988 vlan_group_set_device(adapter->vlgrp, vid, NULL);
1989
1990 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1991 ixgbe_irq_enable(adapter);
1992
1993 /* remove VID from filter table */
1994 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
1995 }
1996
1997 static void ixgbe_vlan_rx_register(struct net_device *netdev,
1998 struct vlan_group *grp)
1999 {
2000 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2001 u32 ctrl;
2002 int i, j;
2003
2004 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2005 ixgbe_irq_disable(adapter);
2006 adapter->vlgrp = grp;
2007
2008 /*
2009 * For a DCB driver, always enable VLAN tag stripping so we can
2010 * still receive traffic from a DCB-enabled host even if we're
2011 * not in DCB mode.
2012 */
2013 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2014 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2015 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2016 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2017 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2018 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2019 ctrl |= IXGBE_VLNCTRL_VFE;
2020 /* enable VLAN tag insert/strip */
2021 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2022 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2023 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2024 for (i = 0; i < adapter->num_rx_queues; i++) {
2025 j = adapter->rx_ring[i].reg_idx;
2026 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2027 ctrl |= IXGBE_RXDCTL_VME;
2028 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2029 }
2030 }
2031 ixgbe_vlan_rx_add_vid(netdev, 0);
2032
2033 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2034 ixgbe_irq_enable(adapter);
2035 }
2036
2037 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2038 {
2039 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2040
2041 if (adapter->vlgrp) {
2042 u16 vid;
2043 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2044 if (!vlan_group_get_device(adapter->vlgrp, vid))
2045 continue;
2046 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2047 }
2048 }
2049 }
2050
2051 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2052 {
2053 struct dev_mc_list *mc_ptr;
2054 u8 *addr = *mc_addr_ptr;
2055 *vmdq = 0;
2056
2057 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2058 if (mc_ptr->next)
2059 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2060 else
2061 *mc_addr_ptr = NULL;
2062
2063 return addr;
2064 }
2065
2066 /**
2067 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2068 * @netdev: network interface device structure
2069 *
2070 * The set_rx_method entry point is called whenever the unicast/multicast
2071 * address list or the network interface flags are updated. This routine is
2072 * responsible for configuring the hardware for proper unicast, multicast and
2073 * promiscuous mode.
2074 **/
2075 static void ixgbe_set_rx_mode(struct net_device *netdev)
2076 {
2077 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2078 struct ixgbe_hw *hw = &adapter->hw;
2079 u32 fctrl, vlnctrl;
2080 u8 *addr_list = NULL;
2081 int addr_count = 0;
2082
2083 /* Check for Promiscuous and All Multicast modes */
2084
2085 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2086 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2087
2088 if (netdev->flags & IFF_PROMISC) {
2089 hw->addr_ctrl.user_set_promisc = 1;
2090 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2091 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2092 } else {
2093 if (netdev->flags & IFF_ALLMULTI) {
2094 fctrl |= IXGBE_FCTRL_MPE;
2095 fctrl &= ~IXGBE_FCTRL_UPE;
2096 } else {
2097 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2098 }
2099 vlnctrl |= IXGBE_VLNCTRL_VFE;
2100 hw->addr_ctrl.user_set_promisc = 0;
2101 }
2102
2103 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2104 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2105
2106 /* reprogram secondary unicast list */
2107 addr_count = netdev->uc_count;
2108 if (addr_count)
2109 addr_list = netdev->uc_list->dmi_addr;
2110 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
2111 ixgbe_addr_list_itr);
2112
2113 /* reprogram multicast list */
2114 addr_count = netdev->mc_count;
2115 if (addr_count)
2116 addr_list = netdev->mc_list->dmi_addr;
2117 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2118 ixgbe_addr_list_itr);
2119 }
2120
2121 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2122 {
2123 int q_idx;
2124 struct ixgbe_q_vector *q_vector;
2125 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2126
2127 /* legacy and MSI only use one vector */
2128 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2129 q_vectors = 1;
2130
2131 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2132 struct napi_struct *napi;
2133 q_vector = adapter->q_vector[q_idx];
2134 if (!q_vector->rxr_count)
2135 continue;
2136 napi = &q_vector->napi;
2137 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
2138 (q_vector->rxr_count > 1))
2139 napi->poll = &ixgbe_clean_rxonly_many;
2140
2141 napi_enable(napi);
2142 }
2143 }
2144
2145 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2146 {
2147 int q_idx;
2148 struct ixgbe_q_vector *q_vector;
2149 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2150
2151 /* legacy and MSI only use one vector */
2152 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2153 q_vectors = 1;
2154
2155 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2156 q_vector = adapter->q_vector[q_idx];
2157 if (!q_vector->rxr_count)
2158 continue;
2159 napi_disable(&q_vector->napi);
2160 }
2161 }
2162
2163 #ifdef CONFIG_IXGBE_DCB
2164 /*
2165 * ixgbe_configure_dcb - Configure DCB hardware
2166 * @adapter: ixgbe adapter struct
2167 *
2168 * This is called by the driver on open to configure the DCB hardware.
2169 * This is also called by the gennetlink interface when reconfiguring
2170 * the DCB state.
2171 */
2172 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2173 {
2174 struct ixgbe_hw *hw = &adapter->hw;
2175 u32 txdctl, vlnctrl;
2176 int i, j;
2177
2178 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2179 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2180 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2181
2182 /* reconfigure the hardware */
2183 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2184
2185 for (i = 0; i < adapter->num_tx_queues; i++) {
2186 j = adapter->tx_ring[i].reg_idx;
2187 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2188 /* PThresh workaround for Tx hang with DFP enabled. */
2189 txdctl |= 32;
2190 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2191 }
2192 /* Enable VLAN tag insert/strip */
2193 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2194 if (hw->mac.type == ixgbe_mac_82598EB) {
2195 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2196 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2197 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2198 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2199 vlnctrl |= IXGBE_VLNCTRL_VFE;
2200 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2201 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2202 for (i = 0; i < adapter->num_rx_queues; i++) {
2203 j = adapter->rx_ring[i].reg_idx;
2204 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2205 vlnctrl |= IXGBE_RXDCTL_VME;
2206 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2207 }
2208 }
2209 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2210 }
2211
2212 #endif
2213 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2214 {
2215 struct net_device *netdev = adapter->netdev;
2216 int i;
2217
2218 ixgbe_set_rx_mode(netdev);
2219
2220 ixgbe_restore_vlan(adapter);
2221 #ifdef CONFIG_IXGBE_DCB
2222 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2223 netif_set_gso_max_size(netdev, 32768);
2224 ixgbe_configure_dcb(adapter);
2225 } else {
2226 netif_set_gso_max_size(netdev, 65536);
2227 }
2228 #else
2229 netif_set_gso_max_size(netdev, 65536);
2230 #endif
2231
2232 ixgbe_configure_tx(adapter);
2233 ixgbe_configure_rx(adapter);
2234 for (i = 0; i < adapter->num_rx_queues; i++)
2235 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2236 (adapter->rx_ring[i].count - 1));
2237 }
2238
2239 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2240 {
2241 switch (hw->phy.type) {
2242 case ixgbe_phy_sfp_avago:
2243 case ixgbe_phy_sfp_ftl:
2244 case ixgbe_phy_sfp_intel:
2245 case ixgbe_phy_sfp_unknown:
2246 case ixgbe_phy_tw_tyco:
2247 case ixgbe_phy_tw_unknown:
2248 return true;
2249 default:
2250 return false;
2251 }
2252 }
2253
2254 /**
2255 * ixgbe_sfp_link_config - set up SFP+ link
2256 * @adapter: pointer to private adapter struct
2257 **/
2258 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2259 {
2260 struct ixgbe_hw *hw = &adapter->hw;
2261
2262 if (hw->phy.multispeed_fiber) {
2263 /*
2264 * In multispeed fiber setups, the device may not have
2265 * had a physical connection when the driver loaded.
2266 * If that's the case, the initial link configuration
2267 * couldn't get the MAC into 10G or 1G mode, so we'll
2268 * never have a link status change interrupt fire.
2269 * We need to try and force an autonegotiation
2270 * session, then bring up link.
2271 */
2272 hw->mac.ops.setup_sfp(hw);
2273 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2274 schedule_work(&adapter->multispeed_fiber_task);
2275 } else {
2276 /*
2277 * Direct Attach Cu and non-multispeed fiber modules
2278 * still need to be configured properly prior to
2279 * attempting link.
2280 */
2281 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2282 schedule_work(&adapter->sfp_config_module_task);
2283 }
2284 }
2285
2286 /**
2287 * ixgbe_non_sfp_link_config - set up non-SFP+ link
2288 * @hw: pointer to private hardware struct
2289 *
2290 * Returns 0 on success, negative on failure
2291 **/
2292 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2293 {
2294 u32 autoneg;
2295 bool link_up = false;
2296 u32 ret = IXGBE_ERR_LINK_SETUP;
2297
2298 if (hw->mac.ops.check_link)
2299 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2300
2301 if (ret)
2302 goto link_cfg_out;
2303
2304 if (hw->mac.ops.get_link_capabilities)
2305 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2306 &hw->mac.autoneg);
2307 if (ret)
2308 goto link_cfg_out;
2309
2310 if (hw->mac.ops.setup_link_speed)
2311 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
2312 link_cfg_out:
2313 return ret;
2314 }
2315
2316 #define IXGBE_MAX_RX_DESC_POLL 10
2317 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2318 int rxr)
2319 {
2320 int j = adapter->rx_ring[rxr].reg_idx;
2321 int k;
2322
2323 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2324 if (IXGBE_READ_REG(&adapter->hw,
2325 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2326 break;
2327 else
2328 msleep(1);
2329 }
2330 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2331 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2332 "not set within the polling period\n", rxr);
2333 }
2334 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2335 (adapter->rx_ring[rxr].count - 1));
2336 }
2337
2338 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2339 {
2340 struct net_device *netdev = adapter->netdev;
2341 struct ixgbe_hw *hw = &adapter->hw;
2342 int i, j = 0;
2343 int num_rx_rings = adapter->num_rx_queues;
2344 int err;
2345 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2346 u32 txdctl, rxdctl, mhadd;
2347 u32 dmatxctl;
2348 u32 gpie;
2349
2350 ixgbe_get_hw_control(adapter);
2351
2352 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2353 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2354 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2355 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2356 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2357 } else {
2358 /* MSI only */
2359 gpie = 0;
2360 }
2361 /* XXX: to interrupt immediately for EICS writes, enable this */
2362 /* gpie |= IXGBE_GPIE_EIMEN; */
2363 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2364 }
2365
2366 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2367 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2368 * specifically only auto mask tx and rx interrupts */
2369 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2370 }
2371
2372 /* Enable fan failure interrupt if media type is copper */
2373 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2374 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2375 gpie |= IXGBE_SDP1_GPIEN;
2376 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2377 }
2378
2379 if (hw->mac.type == ixgbe_mac_82599EB) {
2380 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2381 gpie |= IXGBE_SDP1_GPIEN;
2382 gpie |= IXGBE_SDP2_GPIEN;
2383 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2384 }
2385
2386 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2387 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2388 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2389 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2390
2391 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2392 }
2393
2394 for (i = 0; i < adapter->num_tx_queues; i++) {
2395 j = adapter->tx_ring[i].reg_idx;
2396 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2397 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2398 txdctl |= (8 << 16);
2399 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2400 }
2401
2402 if (hw->mac.type == ixgbe_mac_82599EB) {
2403 /* DMATXCTL.EN must be set after all Tx queue config is done */
2404 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2405 dmatxctl |= IXGBE_DMATXCTL_TE;
2406 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2407 }
2408 for (i = 0; i < adapter->num_tx_queues; i++) {
2409 j = adapter->tx_ring[i].reg_idx;
2410 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2411 txdctl |= IXGBE_TXDCTL_ENABLE;
2412 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2413 }
2414
2415 for (i = 0; i < num_rx_rings; i++) {
2416 j = adapter->rx_ring[i].reg_idx;
2417 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2418 /* enable PTHRESH=32 descriptors (half the internal cache)
2419 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2420 * this also removes a pesky rx_no_buffer_count increment */
2421 rxdctl |= 0x0020;
2422 rxdctl |= IXGBE_RXDCTL_ENABLE;
2423 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2424 if (hw->mac.type == ixgbe_mac_82599EB)
2425 ixgbe_rx_desc_queue_enable(adapter, i);
2426 }
2427 /* enable all receives */
2428 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2429 if (hw->mac.type == ixgbe_mac_82598EB)
2430 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2431 else
2432 rxdctl |= IXGBE_RXCTRL_RXEN;
2433 hw->mac.ops.enable_rx_dma(hw, rxdctl);
2434
2435 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2436 ixgbe_configure_msix(adapter);
2437 else
2438 ixgbe_configure_msi_and_legacy(adapter);
2439
2440 clear_bit(__IXGBE_DOWN, &adapter->state);
2441 ixgbe_napi_enable_all(adapter);
2442
2443 /* clear any pending interrupts, may auto mask */
2444 IXGBE_READ_REG(hw, IXGBE_EICR);
2445
2446 ixgbe_irq_enable(adapter);
2447
2448 /*
2449 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2450 * arrived before interrupts were enabled. We need to kick off
2451 * the SFP+ module setup first, then try to bring up link.
2452 * If we're not hot-pluggable SFP+, we just need to configure link
2453 * and bring it up.
2454 */
2455 err = hw->phy.ops.identify(hw);
2456 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2457 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
2458 ixgbe_down(adapter);
2459 return err;
2460 }
2461
2462 if (ixgbe_is_sfp(hw)) {
2463 ixgbe_sfp_link_config(adapter);
2464 } else {
2465 err = ixgbe_non_sfp_link_config(hw);
2466 if (err)
2467 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2468 }
2469
2470 /* enable transmits */
2471 netif_tx_start_all_queues(netdev);
2472
2473 /* bring the link up in the watchdog, this could race with our first
2474 * link up interrupt but shouldn't be a problem */
2475 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2476 adapter->link_check_timeout = jiffies;
2477 mod_timer(&adapter->watchdog_timer, jiffies);
2478 return 0;
2479 }
2480
2481 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2482 {
2483 WARN_ON(in_interrupt());
2484 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2485 msleep(1);
2486 ixgbe_down(adapter);
2487 ixgbe_up(adapter);
2488 clear_bit(__IXGBE_RESETTING, &adapter->state);
2489 }
2490
2491 int ixgbe_up(struct ixgbe_adapter *adapter)
2492 {
2493 /* hardware has been reset, we need to reload some things */
2494 ixgbe_configure(adapter);
2495
2496 return ixgbe_up_complete(adapter);
2497 }
2498
2499 void ixgbe_reset(struct ixgbe_adapter *adapter)
2500 {
2501 struct ixgbe_hw *hw = &adapter->hw;
2502 if (hw->mac.ops.init_hw(hw))
2503 dev_err(&adapter->pdev->dev, "Hardware Error\n");
2504
2505 /* reprogram the RAR[0] in case user changed it. */
2506 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2507
2508 }
2509
2510 /**
2511 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2512 * @adapter: board private structure
2513 * @rx_ring: ring to free buffers from
2514 **/
2515 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2516 struct ixgbe_ring *rx_ring)
2517 {
2518 struct pci_dev *pdev = adapter->pdev;
2519 unsigned long size;
2520 unsigned int i;
2521
2522 /* Free all the Rx ring sk_buffs */
2523
2524 for (i = 0; i < rx_ring->count; i++) {
2525 struct ixgbe_rx_buffer *rx_buffer_info;
2526
2527 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2528 if (rx_buffer_info->dma) {
2529 pci_unmap_single(pdev, rx_buffer_info->dma,
2530 rx_ring->rx_buf_len,
2531 PCI_DMA_FROMDEVICE);
2532 rx_buffer_info->dma = 0;
2533 }
2534 if (rx_buffer_info->skb) {
2535 struct sk_buff *skb = rx_buffer_info->skb;
2536 rx_buffer_info->skb = NULL;
2537 do {
2538 struct sk_buff *this = skb;
2539 skb = skb->prev;
2540 dev_kfree_skb(this);
2541 } while (skb);
2542 }
2543 if (!rx_buffer_info->page)
2544 continue;
2545 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2546 PCI_DMA_FROMDEVICE);
2547 rx_buffer_info->page_dma = 0;
2548 put_page(rx_buffer_info->page);
2549 rx_buffer_info->page = NULL;
2550 rx_buffer_info->page_offset = 0;
2551 }
2552
2553 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2554 memset(rx_ring->rx_buffer_info, 0, size);
2555
2556 /* Zero out the descriptor ring */
2557 memset(rx_ring->desc, 0, rx_ring->size);
2558
2559 rx_ring->next_to_clean = 0;
2560 rx_ring->next_to_use = 0;
2561
2562 if (rx_ring->head)
2563 writel(0, adapter->hw.hw_addr + rx_ring->head);
2564 if (rx_ring->tail)
2565 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2566 }
2567
2568 /**
2569 * ixgbe_clean_tx_ring - Free Tx Buffers
2570 * @adapter: board private structure
2571 * @tx_ring: ring to be cleaned
2572 **/
2573 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2574 struct ixgbe_ring *tx_ring)
2575 {
2576 struct ixgbe_tx_buffer *tx_buffer_info;
2577 unsigned long size;
2578 unsigned int i;
2579
2580 /* Free all the Tx ring sk_buffs */
2581
2582 for (i = 0; i < tx_ring->count; i++) {
2583 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2584 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2585 }
2586
2587 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2588 memset(tx_ring->tx_buffer_info, 0, size);
2589
2590 /* Zero out the descriptor ring */
2591 memset(tx_ring->desc, 0, tx_ring->size);
2592
2593 tx_ring->next_to_use = 0;
2594 tx_ring->next_to_clean = 0;
2595
2596 if (tx_ring->head)
2597 writel(0, adapter->hw.hw_addr + tx_ring->head);
2598 if (tx_ring->tail)
2599 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2600 }
2601
2602 /**
2603 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2604 * @adapter: board private structure
2605 **/
2606 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2607 {
2608 int i;
2609
2610 for (i = 0; i < adapter->num_rx_queues; i++)
2611 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2612 }
2613
2614 /**
2615 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2616 * @adapter: board private structure
2617 **/
2618 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2619 {
2620 int i;
2621
2622 for (i = 0; i < adapter->num_tx_queues; i++)
2623 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2624 }
2625
2626 void ixgbe_down(struct ixgbe_adapter *adapter)
2627 {
2628 struct net_device *netdev = adapter->netdev;
2629 struct ixgbe_hw *hw = &adapter->hw;
2630 u32 rxctrl;
2631 u32 txdctl;
2632 int i, j;
2633
2634 /* signal that we are down to the interrupt handler */
2635 set_bit(__IXGBE_DOWN, &adapter->state);
2636
2637 /* disable receives */
2638 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2639 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2640
2641 netif_tx_disable(netdev);
2642
2643 IXGBE_WRITE_FLUSH(hw);
2644 msleep(10);
2645
2646 netif_tx_stop_all_queues(netdev);
2647
2648 ixgbe_irq_disable(adapter);
2649
2650 ixgbe_napi_disable_all(adapter);
2651
2652 del_timer_sync(&adapter->watchdog_timer);
2653 cancel_work_sync(&adapter->watchdog_task);
2654
2655 /* disable transmits in the hardware now that interrupts are off */
2656 for (i = 0; i < adapter->num_tx_queues; i++) {
2657 j = adapter->tx_ring[i].reg_idx;
2658 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2659 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2660 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2661 }
2662 /* Disable the Tx DMA engine on 82599 */
2663 if (hw->mac.type == ixgbe_mac_82599EB)
2664 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2665 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2666 ~IXGBE_DMATXCTL_TE));
2667
2668 netif_carrier_off(netdev);
2669
2670 #ifdef CONFIG_IXGBE_DCA
2671 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2672 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2673 dca_remove_requester(&adapter->pdev->dev);
2674 }
2675
2676 #endif
2677 if (!pci_channel_offline(adapter->pdev))
2678 ixgbe_reset(adapter);
2679 ixgbe_clean_all_tx_rings(adapter);
2680 ixgbe_clean_all_rx_rings(adapter);
2681
2682 #ifdef CONFIG_IXGBE_DCA
2683 /* since we reset the hardware DCA settings were cleared */
2684 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2685 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2686 /* always use CB2 mode, difference is masked
2687 * in the CB driver */
2688 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
2689 ixgbe_setup_dca(adapter);
2690 }
2691 #endif
2692 }
2693
2694 /**
2695 * ixgbe_poll - NAPI Rx polling callback
2696 * @napi: structure for representing this polling device
2697 * @budget: how many packets driver is allowed to clean
2698 *
2699 * This function is used for legacy and MSI, NAPI mode
2700 **/
2701 static int ixgbe_poll(struct napi_struct *napi, int budget)
2702 {
2703 struct ixgbe_q_vector *q_vector =
2704 container_of(napi, struct ixgbe_q_vector, napi);
2705 struct ixgbe_adapter *adapter = q_vector->adapter;
2706 int tx_clean_complete, work_done = 0;
2707
2708 #ifdef CONFIG_IXGBE_DCA
2709 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2710 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2711 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2712 }
2713 #endif
2714
2715 tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
2716 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
2717
2718 if (!tx_clean_complete)
2719 work_done = budget;
2720
2721 /* If budget not fully consumed, exit the polling mode */
2722 if (work_done < budget) {
2723 napi_complete(napi);
2724 if (adapter->itr_setting & 1)
2725 ixgbe_set_itr(adapter);
2726 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2727 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
2728 }
2729 return work_done;
2730 }
2731
2732 /**
2733 * ixgbe_tx_timeout - Respond to a Tx Hang
2734 * @netdev: network interface device structure
2735 **/
2736 static void ixgbe_tx_timeout(struct net_device *netdev)
2737 {
2738 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2739
2740 /* Do the reset outside of interrupt context */
2741 schedule_work(&adapter->reset_task);
2742 }
2743
2744 static void ixgbe_reset_task(struct work_struct *work)
2745 {
2746 struct ixgbe_adapter *adapter;
2747 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2748
2749 /* If we're already down or resetting, just bail */
2750 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2751 test_bit(__IXGBE_RESETTING, &adapter->state))
2752 return;
2753
2754 adapter->tx_timeout_count++;
2755
2756 ixgbe_reinit_locked(adapter);
2757 }
2758
2759 #ifdef CONFIG_IXGBE_DCB
2760 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
2761 {
2762 bool ret = false;
2763
2764 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2765 adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3;
2766 adapter->num_rx_queues =
2767 adapter->ring_feature[RING_F_DCB].indices;
2768 adapter->num_tx_queues =
2769 adapter->ring_feature[RING_F_DCB].indices;
2770 ret = true;
2771 } else {
2772 ret = false;
2773 }
2774
2775 return ret;
2776 }
2777 #endif
2778
2779 /**
2780 * ixgbe_set_rss_queues: Allocate queues for RSS
2781 * @adapter: board private structure to initialize
2782 *
2783 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
2784 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
2785 *
2786 **/
2787 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2788 {
2789 bool ret = false;
2790
2791 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2792 adapter->ring_feature[RING_F_RSS].mask = 0xF;
2793 adapter->num_rx_queues =
2794 adapter->ring_feature[RING_F_RSS].indices;
2795 adapter->num_tx_queues =
2796 adapter->ring_feature[RING_F_RSS].indices;
2797 ret = true;
2798 } else {
2799 ret = false;
2800 }
2801
2802 return ret;
2803 }
2804
2805 /*
2806 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
2807 * @adapter: board private structure to initialize
2808 *
2809 * This is the top level queue allocation routine. The order here is very
2810 * important, starting with the "most" number of features turned on at once,
2811 * and ending with the smallest set of features. This way large combinations
2812 * can be allocated if they're turned on, and smaller combinations are the
2813 * fallthrough conditions.
2814 *
2815 **/
2816 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2817 {
2818 #ifdef CONFIG_IXGBE_DCB
2819 if (ixgbe_set_dcb_queues(adapter))
2820 goto done;
2821
2822 #endif
2823 if (ixgbe_set_rss_queues(adapter))
2824 goto done;
2825
2826 /* fallback to base case */
2827 adapter->num_rx_queues = 1;
2828 adapter->num_tx_queues = 1;
2829
2830 done:
2831 /* Notify the stack of the (possibly) reduced Tx Queue count. */
2832 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
2833 }
2834
2835 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
2836 int vectors)
2837 {
2838 int err, vector_threshold;
2839
2840 /* We'll want at least 3 (vector_threshold):
2841 * 1) TxQ[0] Cleanup
2842 * 2) RxQ[0] Cleanup
2843 * 3) Other (Link Status Change, etc.)
2844 * 4) TCP Timer (optional)
2845 */
2846 vector_threshold = MIN_MSIX_COUNT;
2847
2848 /* The more we get, the more we will assign to Tx/Rx Cleanup
2849 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2850 * Right now, we simply care about how many we'll get; we'll
2851 * set them up later while requesting irq's.
2852 */
2853 while (vectors >= vector_threshold) {
2854 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
2855 vectors);
2856 if (!err) /* Success in acquiring all requested vectors. */
2857 break;
2858 else if (err < 0)
2859 vectors = 0; /* Nasty failure, quit now */
2860 else /* err == number of vectors we should try again with */
2861 vectors = err;
2862 }
2863
2864 if (vectors < vector_threshold) {
2865 /* Can't allocate enough MSI-X interrupts? Oh well.
2866 * This just means we'll go with either a single MSI
2867 * vector or fall back to legacy interrupts.
2868 */
2869 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2870 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2871 kfree(adapter->msix_entries);
2872 adapter->msix_entries = NULL;
2873 } else {
2874 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2875 /*
2876 * Adjust for only the vectors we'll use, which is minimum
2877 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
2878 * vectors we were allocated.
2879 */
2880 adapter->num_msix_vectors = min(vectors,
2881 adapter->max_msix_q_vectors + NON_Q_VECTORS);
2882 }
2883 }
2884
2885 /**
2886 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
2887 * @adapter: board private structure to initialize
2888 *
2889 * Cache the descriptor ring offsets for RSS to the assigned rings.
2890 *
2891 **/
2892 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
2893 {
2894 int i;
2895 bool ret = false;
2896
2897 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2898 for (i = 0; i < adapter->num_rx_queues; i++)
2899 adapter->rx_ring[i].reg_idx = i;
2900 for (i = 0; i < adapter->num_tx_queues; i++)
2901 adapter->tx_ring[i].reg_idx = i;
2902 ret = true;
2903 } else {
2904 ret = false;
2905 }
2906
2907 return ret;
2908 }
2909
2910 #ifdef CONFIG_IXGBE_DCB
2911 /**
2912 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
2913 * @adapter: board private structure to initialize
2914 *
2915 * Cache the descriptor ring offsets for DCB to the assigned rings.
2916 *
2917 **/
2918 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
2919 {
2920 int i;
2921 bool ret = false;
2922 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2923
2924 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2925 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2926 /* the number of queues is assumed to be symmetric */
2927 for (i = 0; i < dcb_i; i++) {
2928 adapter->rx_ring[i].reg_idx = i << 3;
2929 adapter->tx_ring[i].reg_idx = i << 2;
2930 }
2931 ret = true;
2932 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2933 if (dcb_i == 8) {
2934 /*
2935 * Tx TC0 starts at: descriptor queue 0
2936 * Tx TC1 starts at: descriptor queue 32
2937 * Tx TC2 starts at: descriptor queue 64
2938 * Tx TC3 starts at: descriptor queue 80
2939 * Tx TC4 starts at: descriptor queue 96
2940 * Tx TC5 starts at: descriptor queue 104
2941 * Tx TC6 starts at: descriptor queue 112
2942 * Tx TC7 starts at: descriptor queue 120
2943 *
2944 * Rx TC0-TC7 are offset by 16 queues each
2945 */
2946 for (i = 0; i < 3; i++) {
2947 adapter->tx_ring[i].reg_idx = i << 5;
2948 adapter->rx_ring[i].reg_idx = i << 4;
2949 }
2950 for ( ; i < 5; i++) {
2951 adapter->tx_ring[i].reg_idx =
2952 ((i + 2) << 4);
2953 adapter->rx_ring[i].reg_idx = i << 4;
2954 }
2955 for ( ; i < dcb_i; i++) {
2956 adapter->tx_ring[i].reg_idx =
2957 ((i + 8) << 3);
2958 adapter->rx_ring[i].reg_idx = i << 4;
2959 }
2960
2961 ret = true;
2962 } else if (dcb_i == 4) {
2963 /*
2964 * Tx TC0 starts at: descriptor queue 0
2965 * Tx TC1 starts at: descriptor queue 64
2966 * Tx TC2 starts at: descriptor queue 96
2967 * Tx TC3 starts at: descriptor queue 112
2968 *
2969 * Rx TC0-TC3 are offset by 32 queues each
2970 */
2971 adapter->tx_ring[0].reg_idx = 0;
2972 adapter->tx_ring[1].reg_idx = 64;
2973 adapter->tx_ring[2].reg_idx = 96;
2974 adapter->tx_ring[3].reg_idx = 112;
2975 for (i = 0 ; i < dcb_i; i++)
2976 adapter->rx_ring[i].reg_idx = i << 5;
2977
2978 ret = true;
2979 } else {
2980 ret = false;
2981 }
2982 } else {
2983 ret = false;
2984 }
2985 } else {
2986 ret = false;
2987 }
2988
2989 return ret;
2990 }
2991 #endif
2992
2993 /**
2994 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2995 * @adapter: board private structure to initialize
2996 *
2997 * Once we know the feature-set enabled for the device, we'll cache
2998 * the register offset the descriptor ring is assigned to.
2999 *
3000 * Note, the order the various feature calls is important. It must start with
3001 * the "most" features enabled at the same time, then trickle down to the
3002 * least amount of features turned on at once.
3003 **/
3004 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3005 {
3006 /* start with default case */
3007 adapter->rx_ring[0].reg_idx = 0;
3008 adapter->tx_ring[0].reg_idx = 0;
3009
3010 #ifdef CONFIG_IXGBE_DCB
3011 if (ixgbe_cache_ring_dcb(adapter))
3012 return;
3013
3014 #endif
3015 if (ixgbe_cache_ring_rss(adapter))
3016 return;
3017 }
3018
3019 /**
3020 * ixgbe_alloc_queues - Allocate memory for all rings
3021 * @adapter: board private structure to initialize
3022 *
3023 * We allocate one ring per queue at run-time since we don't know the
3024 * number of queues at compile-time. The polling_netdev array is
3025 * intended for Multiqueue, but should work fine with a single queue.
3026 **/
3027 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3028 {
3029 int i;
3030
3031 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3032 sizeof(struct ixgbe_ring), GFP_KERNEL);
3033 if (!adapter->tx_ring)
3034 goto err_tx_ring_allocation;
3035
3036 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3037 sizeof(struct ixgbe_ring), GFP_KERNEL);
3038 if (!adapter->rx_ring)
3039 goto err_rx_ring_allocation;
3040
3041 for (i = 0; i < adapter->num_tx_queues; i++) {
3042 adapter->tx_ring[i].count = adapter->tx_ring_count;
3043 adapter->tx_ring[i].queue_index = i;
3044 }
3045
3046 for (i = 0; i < adapter->num_rx_queues; i++) {
3047 adapter->rx_ring[i].count = adapter->rx_ring_count;
3048 adapter->rx_ring[i].queue_index = i;
3049 }
3050
3051 ixgbe_cache_ring_register(adapter);
3052
3053 return 0;
3054
3055 err_rx_ring_allocation:
3056 kfree(adapter->tx_ring);
3057 err_tx_ring_allocation:
3058 return -ENOMEM;
3059 }
3060
3061 /**
3062 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3063 * @adapter: board private structure to initialize
3064 *
3065 * Attempt to configure the interrupts using the best available
3066 * capabilities of the hardware and the kernel.
3067 **/
3068 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3069 {
3070 struct ixgbe_hw *hw = &adapter->hw;
3071 int err = 0;
3072 int vector, v_budget;
3073
3074 /*
3075 * It's easy to be greedy for MSI-X vectors, but it really
3076 * doesn't do us much good if we have a lot more vectors
3077 * than CPU's. So let's be conservative and only ask for
3078 * (roughly) twice the number of vectors as there are CPU's.
3079 */
3080 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3081 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3082
3083 /*
3084 * At the same time, hardware can only support a maximum of
3085 * hw.mac->max_msix_vectors vectors. With features
3086 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3087 * descriptor queues supported by our device. Thus, we cap it off in
3088 * those rare cases where the cpu count also exceeds our vector limit.
3089 */
3090 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3091
3092 /* A failure in MSI-X entry allocation isn't fatal, but it does
3093 * mean we disable MSI-X capabilities of the adapter. */
3094 adapter->msix_entries = kcalloc(v_budget,
3095 sizeof(struct msix_entry), GFP_KERNEL);
3096 if (adapter->msix_entries) {
3097 for (vector = 0; vector < v_budget; vector++)
3098 adapter->msix_entries[vector].entry = vector;
3099
3100 ixgbe_acquire_msix_vectors(adapter, v_budget);
3101
3102 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3103 goto out;
3104 }
3105
3106 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3107 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3108 ixgbe_set_num_queues(adapter);
3109
3110 err = pci_enable_msi(adapter->pdev);
3111 if (!err) {
3112 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3113 } else {
3114 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3115 "falling back to legacy. Error: %d\n", err);
3116 /* reset err */
3117 err = 0;
3118 }
3119
3120 out:
3121 return err;
3122 }
3123
3124 /**
3125 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3126 * @adapter: board private structure to initialize
3127 *
3128 * We allocate one q_vector per queue interrupt. If allocation fails we
3129 * return -ENOMEM.
3130 **/
3131 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3132 {
3133 int q_idx, num_q_vectors;
3134 struct ixgbe_q_vector *q_vector;
3135 int napi_vectors;
3136 int (*poll)(struct napi_struct *, int);
3137
3138 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3139 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3140 napi_vectors = adapter->num_rx_queues;
3141 poll = &ixgbe_clean_rxonly;
3142 } else {
3143 num_q_vectors = 1;
3144 napi_vectors = 1;
3145 poll = &ixgbe_poll;
3146 }
3147
3148 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3149 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3150 if (!q_vector)
3151 goto err_out;
3152 q_vector->adapter = adapter;
3153 q_vector->v_idx = q_idx;
3154 q_vector->eitr = adapter->eitr_param;
3155 if (q_idx < napi_vectors)
3156 netif_napi_add(adapter->netdev, &q_vector->napi,
3157 (*poll), 64);
3158 adapter->q_vector[q_idx] = q_vector;
3159 }
3160
3161 return 0;
3162
3163 err_out:
3164 while (q_idx) {
3165 q_idx--;
3166 q_vector = adapter->q_vector[q_idx];
3167 netif_napi_del(&q_vector->napi);
3168 kfree(q_vector);
3169 adapter->q_vector[q_idx] = NULL;
3170 }
3171 return -ENOMEM;
3172 }
3173
3174 /**
3175 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3176 * @adapter: board private structure to initialize
3177 *
3178 * This function frees the memory allocated to the q_vectors. In addition if
3179 * NAPI is enabled it will delete any references to the NAPI struct prior
3180 * to freeing the q_vector.
3181 **/
3182 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3183 {
3184 int q_idx, num_q_vectors;
3185 int napi_vectors;
3186
3187 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3188 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3189 napi_vectors = adapter->num_rx_queues;
3190 } else {
3191 num_q_vectors = 1;
3192 napi_vectors = 1;
3193 }
3194
3195 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3196 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3197
3198 adapter->q_vector[q_idx] = NULL;
3199 if (q_idx < napi_vectors)
3200 netif_napi_del(&q_vector->napi);
3201 kfree(q_vector);
3202 }
3203 }
3204
3205 void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3206 {
3207 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3208 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3209 pci_disable_msix(adapter->pdev);
3210 kfree(adapter->msix_entries);
3211 adapter->msix_entries = NULL;
3212 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3213 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3214 pci_disable_msi(adapter->pdev);
3215 }
3216 return;
3217 }
3218
3219 /**
3220 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3221 * @adapter: board private structure to initialize
3222 *
3223 * We determine which interrupt scheme to use based on...
3224 * - Kernel support (MSI, MSI-X)
3225 * - which can be user-defined (via MODULE_PARAM)
3226 * - Hardware queue count (num_*_queues)
3227 * - defined by miscellaneous hardware support/features (RSS, etc.)
3228 **/
3229 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3230 {
3231 int err;
3232
3233 /* Number of supported queues */
3234 ixgbe_set_num_queues(adapter);
3235
3236 err = ixgbe_set_interrupt_capability(adapter);
3237 if (err) {
3238 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3239 goto err_set_interrupt;
3240 }
3241
3242 err = ixgbe_alloc_q_vectors(adapter);
3243 if (err) {
3244 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3245 "vectors\n");
3246 goto err_alloc_q_vectors;
3247 }
3248
3249 err = ixgbe_alloc_queues(adapter);
3250 if (err) {
3251 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3252 goto err_alloc_queues;
3253 }
3254
3255 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3256 "Tx Queue count = %u\n",
3257 (adapter->num_rx_queues > 1) ? "Enabled" :
3258 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3259
3260 set_bit(__IXGBE_DOWN, &adapter->state);
3261
3262 return 0;
3263
3264 err_alloc_queues:
3265 ixgbe_free_q_vectors(adapter);
3266 err_alloc_q_vectors:
3267 ixgbe_reset_interrupt_capability(adapter);
3268 err_set_interrupt:
3269 return err;
3270 }
3271
3272 /**
3273 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3274 * @adapter: board private structure to clear interrupt scheme on
3275 *
3276 * We go through and clear interrupt specific resources and reset the structure
3277 * to pre-load conditions
3278 **/
3279 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3280 {
3281 kfree(adapter->tx_ring);
3282 kfree(adapter->rx_ring);
3283 adapter->tx_ring = NULL;
3284 adapter->rx_ring = NULL;
3285
3286 ixgbe_free_q_vectors(adapter);
3287 ixgbe_reset_interrupt_capability(adapter);
3288 }
3289
3290 /**
3291 * ixgbe_sfp_timer - worker thread to find a missing module
3292 * @data: pointer to our adapter struct
3293 **/
3294 static void ixgbe_sfp_timer(unsigned long data)
3295 {
3296 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3297
3298 /*
3299 * Do the sfp_timer outside of interrupt context due to the
3300 * delays that sfp+ detection requires
3301 */
3302 schedule_work(&adapter->sfp_task);
3303 }
3304
3305 /**
3306 * ixgbe_sfp_task - worker thread to find a missing module
3307 * @work: pointer to work_struct containing our data
3308 **/
3309 static void ixgbe_sfp_task(struct work_struct *work)
3310 {
3311 struct ixgbe_adapter *adapter = container_of(work,
3312 struct ixgbe_adapter,
3313 sfp_task);
3314 struct ixgbe_hw *hw = &adapter->hw;
3315
3316 if ((hw->phy.type == ixgbe_phy_nl) &&
3317 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3318 s32 ret = hw->phy.ops.identify_sfp(hw);
3319 if (ret)
3320 goto reschedule;
3321 ret = hw->phy.ops.reset(hw);
3322 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3323 DPRINTK(PROBE, ERR, "failed to initialize because an "
3324 "unsupported SFP+ module type was detected.\n"
3325 "Reload the driver after installing a "
3326 "supported module.\n");
3327 unregister_netdev(adapter->netdev);
3328 } else {
3329 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3330 hw->phy.sfp_type);
3331 }
3332 /* don't need this routine any more */
3333 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3334 }
3335 return;
3336 reschedule:
3337 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3338 mod_timer(&adapter->sfp_timer,
3339 round_jiffies(jiffies + (2 * HZ)));
3340 }
3341
3342 /**
3343 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3344 * @adapter: board private structure to initialize
3345 *
3346 * ixgbe_sw_init initializes the Adapter private data structure.
3347 * Fields are initialized based on PCI device information and
3348 * OS network device settings (MTU size).
3349 **/
3350 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3351 {
3352 struct ixgbe_hw *hw = &adapter->hw;
3353 struct pci_dev *pdev = adapter->pdev;
3354 unsigned int rss;
3355 #ifdef CONFIG_IXGBE_DCB
3356 int j;
3357 struct tc_configuration *tc;
3358 #endif
3359
3360 /* PCI config space info */
3361
3362 hw->vendor_id = pdev->vendor;
3363 hw->device_id = pdev->device;
3364 hw->revision_id = pdev->revision;
3365 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3366 hw->subsystem_device_id = pdev->subsystem_device;
3367
3368 /* Set capability flags */
3369 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3370 adapter->ring_feature[RING_F_RSS].indices = rss;
3371 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3372 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3373 if (hw->mac.type == ixgbe_mac_82598EB)
3374 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3375 else if (hw->mac.type == ixgbe_mac_82599EB) {
3376 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3377 adapter->flags |= IXGBE_FLAG_RSC_CAPABLE;
3378 adapter->flags |= IXGBE_FLAG_RSC_ENABLED;
3379 }
3380
3381 #ifdef CONFIG_IXGBE_DCB
3382 /* Configure DCB traffic classes */
3383 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3384 tc = &adapter->dcb_cfg.tc_config[j];
3385 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3386 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3387 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3388 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3389 tc->dcb_pfc = pfc_disabled;
3390 }
3391 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3392 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3393 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3394 adapter->dcb_cfg.round_robin_enable = false;
3395 adapter->dcb_set_bitmap = 0x00;
3396 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3397 adapter->ring_feature[RING_F_DCB].indices);
3398
3399 #endif
3400
3401 /* default flow control settings */
3402 hw->fc.requested_mode = ixgbe_fc_full;
3403 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
3404 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3405 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3406 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3407 hw->fc.send_xon = true;
3408 hw->fc.disable_fc_autoneg = false;
3409
3410 /* enable itr by default in dynamic mode */
3411 adapter->itr_setting = 1;
3412 adapter->eitr_param = 20000;
3413
3414 /* set defaults for eitr in MegaBytes */
3415 adapter->eitr_low = 10;
3416 adapter->eitr_high = 20;
3417
3418 /* set default ring sizes */
3419 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3420 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3421
3422 /* initialize eeprom parameters */
3423 if (ixgbe_init_eeprom_params_generic(hw)) {
3424 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3425 return -EIO;
3426 }
3427
3428 /* enable rx csum by default */
3429 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3430
3431 set_bit(__IXGBE_DOWN, &adapter->state);
3432
3433 return 0;
3434 }
3435
3436 /**
3437 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3438 * @adapter: board private structure
3439 * @tx_ring: tx descriptor ring (for a specific queue) to setup
3440 *
3441 * Return 0 on success, negative on failure
3442 **/
3443 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3444 struct ixgbe_ring *tx_ring)
3445 {
3446 struct pci_dev *pdev = adapter->pdev;
3447 int size;
3448
3449 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3450 tx_ring->tx_buffer_info = vmalloc(size);
3451 if (!tx_ring->tx_buffer_info)
3452 goto err;
3453 memset(tx_ring->tx_buffer_info, 0, size);
3454
3455 /* round up to nearest 4K */
3456 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3457 tx_ring->size = ALIGN(tx_ring->size, 4096);
3458
3459 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3460 &tx_ring->dma);
3461 if (!tx_ring->desc)
3462 goto err;
3463
3464 tx_ring->next_to_use = 0;
3465 tx_ring->next_to_clean = 0;
3466 tx_ring->work_limit = tx_ring->count;
3467 return 0;
3468
3469 err:
3470 vfree(tx_ring->tx_buffer_info);
3471 tx_ring->tx_buffer_info = NULL;
3472 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3473 "descriptor ring\n");
3474 return -ENOMEM;
3475 }
3476
3477 /**
3478 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3479 * @adapter: board private structure
3480 *
3481 * If this function returns with an error, then it's possible one or
3482 * more of the rings is populated (while the rest are not). It is the
3483 * callers duty to clean those orphaned rings.
3484 *
3485 * Return 0 on success, negative on failure
3486 **/
3487 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3488 {
3489 int i, err = 0;
3490
3491 for (i = 0; i < adapter->num_tx_queues; i++) {
3492 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3493 if (!err)
3494 continue;
3495 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3496 break;
3497 }
3498
3499 return err;
3500 }
3501
3502 /**
3503 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3504 * @adapter: board private structure
3505 * @rx_ring: rx descriptor ring (for a specific queue) to setup
3506 *
3507 * Returns 0 on success, negative on failure
3508 **/
3509 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
3510 struct ixgbe_ring *rx_ring)
3511 {
3512 struct pci_dev *pdev = adapter->pdev;
3513 int size;
3514
3515 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3516 rx_ring->rx_buffer_info = vmalloc(size);
3517 if (!rx_ring->rx_buffer_info) {
3518 DPRINTK(PROBE, ERR,
3519 "vmalloc allocation failed for the rx desc ring\n");
3520 goto alloc_failed;
3521 }
3522 memset(rx_ring->rx_buffer_info, 0, size);
3523
3524 /* Round up to nearest 4K */
3525 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3526 rx_ring->size = ALIGN(rx_ring->size, 4096);
3527
3528 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
3529
3530 if (!rx_ring->desc) {
3531 DPRINTK(PROBE, ERR,
3532 "Memory allocation failed for the rx desc ring\n");
3533 vfree(rx_ring->rx_buffer_info);
3534 goto alloc_failed;
3535 }
3536
3537 rx_ring->next_to_clean = 0;
3538 rx_ring->next_to_use = 0;
3539
3540 return 0;
3541
3542 alloc_failed:
3543 return -ENOMEM;
3544 }
3545
3546 /**
3547 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3548 * @adapter: board private structure
3549 *
3550 * If this function returns with an error, then it's possible one or
3551 * more of the rings is populated (while the rest are not). It is the
3552 * callers duty to clean those orphaned rings.
3553 *
3554 * Return 0 on success, negative on failure
3555 **/
3556
3557 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3558 {
3559 int i, err = 0;
3560
3561 for (i = 0; i < adapter->num_rx_queues; i++) {
3562 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3563 if (!err)
3564 continue;
3565 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3566 break;
3567 }
3568
3569 return err;
3570 }
3571
3572 /**
3573 * ixgbe_free_tx_resources - Free Tx Resources per Queue
3574 * @adapter: board private structure
3575 * @tx_ring: Tx descriptor ring for a specific queue
3576 *
3577 * Free all transmit software resources
3578 **/
3579 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3580 struct ixgbe_ring *tx_ring)
3581 {
3582 struct pci_dev *pdev = adapter->pdev;
3583
3584 ixgbe_clean_tx_ring(adapter, tx_ring);
3585
3586 vfree(tx_ring->tx_buffer_info);
3587 tx_ring->tx_buffer_info = NULL;
3588
3589 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3590
3591 tx_ring->desc = NULL;
3592 }
3593
3594 /**
3595 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3596 * @adapter: board private structure
3597 *
3598 * Free all transmit software resources
3599 **/
3600 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3601 {
3602 int i;
3603
3604 for (i = 0; i < adapter->num_tx_queues; i++)
3605 if (adapter->tx_ring[i].desc)
3606 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
3607 }
3608
3609 /**
3610 * ixgbe_free_rx_resources - Free Rx Resources
3611 * @adapter: board private structure
3612 * @rx_ring: ring to clean the resources from
3613 *
3614 * Free all receive software resources
3615 **/
3616 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3617 struct ixgbe_ring *rx_ring)
3618 {
3619 struct pci_dev *pdev = adapter->pdev;
3620
3621 ixgbe_clean_rx_ring(adapter, rx_ring);
3622
3623 vfree(rx_ring->rx_buffer_info);
3624 rx_ring->rx_buffer_info = NULL;
3625
3626 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3627
3628 rx_ring->desc = NULL;
3629 }
3630
3631 /**
3632 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3633 * @adapter: board private structure
3634 *
3635 * Free all receive software resources
3636 **/
3637 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3638 {
3639 int i;
3640
3641 for (i = 0; i < adapter->num_rx_queues; i++)
3642 if (adapter->rx_ring[i].desc)
3643 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
3644 }
3645
3646 /**
3647 * ixgbe_change_mtu - Change the Maximum Transfer Unit
3648 * @netdev: network interface device structure
3649 * @new_mtu: new value for maximum frame size
3650 *
3651 * Returns 0 on success, negative on failure
3652 **/
3653 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3654 {
3655 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3656 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3657
3658 /* MTU < 68 is an error and causes problems on some kernels */
3659 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
3660 return -EINVAL;
3661
3662 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
3663 netdev->mtu, new_mtu);
3664 /* must set new MTU before calling down or up */
3665 netdev->mtu = new_mtu;
3666
3667 if (netif_running(netdev))
3668 ixgbe_reinit_locked(adapter);
3669
3670 return 0;
3671 }
3672
3673 /**
3674 * ixgbe_open - Called when a network interface is made active
3675 * @netdev: network interface device structure
3676 *
3677 * Returns 0 on success, negative value on failure
3678 *
3679 * The open entry point is called when a network interface is made
3680 * active by the system (IFF_UP). At this point all resources needed
3681 * for transmit and receive operations are allocated, the interrupt
3682 * handler is registered with the OS, the watchdog timer is started,
3683 * and the stack is notified that the interface is ready.
3684 **/
3685 static int ixgbe_open(struct net_device *netdev)
3686 {
3687 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3688 int err;
3689
3690 /* disallow open during test */
3691 if (test_bit(__IXGBE_TESTING, &adapter->state))
3692 return -EBUSY;
3693
3694 netif_carrier_off(netdev);
3695
3696 /* allocate transmit descriptors */
3697 err = ixgbe_setup_all_tx_resources(adapter);
3698 if (err)
3699 goto err_setup_tx;
3700
3701 /* allocate receive descriptors */
3702 err = ixgbe_setup_all_rx_resources(adapter);
3703 if (err)
3704 goto err_setup_rx;
3705
3706 ixgbe_configure(adapter);
3707
3708 err = ixgbe_request_irq(adapter);
3709 if (err)
3710 goto err_req_irq;
3711
3712 err = ixgbe_up_complete(adapter);
3713 if (err)
3714 goto err_up;
3715
3716 netif_tx_start_all_queues(netdev);
3717
3718 return 0;
3719
3720 err_up:
3721 ixgbe_release_hw_control(adapter);
3722 ixgbe_free_irq(adapter);
3723 err_req_irq:
3724 err_setup_rx:
3725 ixgbe_free_all_rx_resources(adapter);
3726 err_setup_tx:
3727 ixgbe_free_all_tx_resources(adapter);
3728 ixgbe_reset(adapter);
3729
3730 return err;
3731 }
3732
3733 /**
3734 * ixgbe_close - Disables a network interface
3735 * @netdev: network interface device structure
3736 *
3737 * Returns 0, this is not allowed to fail
3738 *
3739 * The close entry point is called when an interface is de-activated
3740 * by the OS. The hardware is still under the drivers control, but
3741 * needs to be disabled. A global MAC reset is issued to stop the
3742 * hardware, and all transmit and receive resources are freed.
3743 **/
3744 static int ixgbe_close(struct net_device *netdev)
3745 {
3746 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3747
3748 ixgbe_down(adapter);
3749 ixgbe_free_irq(adapter);
3750
3751 ixgbe_free_all_tx_resources(adapter);
3752 ixgbe_free_all_rx_resources(adapter);
3753
3754 ixgbe_release_hw_control(adapter);
3755
3756 return 0;
3757 }
3758
3759 #ifdef CONFIG_PM
3760 static int ixgbe_resume(struct pci_dev *pdev)
3761 {
3762 struct net_device *netdev = pci_get_drvdata(pdev);
3763 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3764 u32 err;
3765
3766 pci_set_power_state(pdev, PCI_D0);
3767 pci_restore_state(pdev);
3768
3769 err = pci_enable_device_mem(pdev);
3770 if (err) {
3771 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
3772 "suspend\n");
3773 return err;
3774 }
3775 pci_set_master(pdev);
3776
3777 pci_wake_from_d3(pdev, false);
3778
3779 err = ixgbe_init_interrupt_scheme(adapter);
3780 if (err) {
3781 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3782 "device\n");
3783 return err;
3784 }
3785
3786 ixgbe_reset(adapter);
3787
3788 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
3789
3790 if (netif_running(netdev)) {
3791 err = ixgbe_open(adapter->netdev);
3792 if (err)
3793 return err;
3794 }
3795
3796 netif_device_attach(netdev);
3797
3798 return 0;
3799 }
3800 #endif /* CONFIG_PM */
3801
3802 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
3803 {
3804 struct net_device *netdev = pci_get_drvdata(pdev);
3805 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3806 struct ixgbe_hw *hw = &adapter->hw;
3807 u32 ctrl, fctrl;
3808 u32 wufc = adapter->wol;
3809 #ifdef CONFIG_PM
3810 int retval = 0;
3811 #endif
3812
3813 netif_device_detach(netdev);
3814
3815 if (netif_running(netdev)) {
3816 ixgbe_down(adapter);
3817 ixgbe_free_irq(adapter);
3818 ixgbe_free_all_tx_resources(adapter);
3819 ixgbe_free_all_rx_resources(adapter);
3820 }
3821 ixgbe_clear_interrupt_scheme(adapter);
3822
3823 #ifdef CONFIG_PM
3824 retval = pci_save_state(pdev);
3825 if (retval)
3826 return retval;
3827
3828 #endif
3829 if (wufc) {
3830 ixgbe_set_rx_mode(netdev);
3831
3832 /* turn on all-multi mode if wake on multicast is enabled */
3833 if (wufc & IXGBE_WUFC_MC) {
3834 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3835 fctrl |= IXGBE_FCTRL_MPE;
3836 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3837 }
3838
3839 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3840 ctrl |= IXGBE_CTRL_GIO_DIS;
3841 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3842
3843 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
3844 } else {
3845 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
3846 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
3847 }
3848
3849 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
3850 pci_wake_from_d3(pdev, true);
3851 else
3852 pci_wake_from_d3(pdev, false);
3853
3854 *enable_wake = !!wufc;
3855
3856 ixgbe_release_hw_control(adapter);
3857
3858 pci_disable_device(pdev);
3859
3860 return 0;
3861 }
3862
3863 #ifdef CONFIG_PM
3864 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3865 {
3866 int retval;
3867 bool wake;
3868
3869 retval = __ixgbe_shutdown(pdev, &wake);
3870 if (retval)
3871 return retval;
3872
3873 if (wake) {
3874 pci_prepare_to_sleep(pdev);
3875 } else {
3876 pci_wake_from_d3(pdev, false);
3877 pci_set_power_state(pdev, PCI_D3hot);
3878 }
3879
3880 return 0;
3881 }
3882 #endif /* CONFIG_PM */
3883
3884 static void ixgbe_shutdown(struct pci_dev *pdev)
3885 {
3886 bool wake;
3887
3888 __ixgbe_shutdown(pdev, &wake);
3889
3890 if (system_state == SYSTEM_POWER_OFF) {
3891 pci_wake_from_d3(pdev, wake);
3892 pci_set_power_state(pdev, PCI_D3hot);
3893 }
3894 }
3895
3896 /**
3897 * ixgbe_update_stats - Update the board statistics counters.
3898 * @adapter: board private structure
3899 **/
3900 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3901 {
3902 struct ixgbe_hw *hw = &adapter->hw;
3903 u64 total_mpc = 0;
3904 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
3905
3906 if (hw->mac.type == ixgbe_mac_82599EB) {
3907 u64 rsc_count = 0;
3908 for (i = 0; i < 16; i++)
3909 adapter->hw_rx_no_dma_resources +=
3910 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3911 for (i = 0; i < adapter->num_rx_queues; i++)
3912 rsc_count += adapter->rx_ring[i].rsc_count;
3913 adapter->rsc_count = rsc_count;
3914 }
3915
3916 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3917 for (i = 0; i < 8; i++) {
3918 /* for packet buffers not used, the register should read 0 */
3919 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3920 missed_rx += mpc;
3921 adapter->stats.mpc[i] += mpc;
3922 total_mpc += adapter->stats.mpc[i];
3923 if (hw->mac.type == ixgbe_mac_82598EB)
3924 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3925 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3926 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
3927 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3928 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
3929 if (hw->mac.type == ixgbe_mac_82599EB) {
3930 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3931 IXGBE_PXONRXCNT(i));
3932 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3933 IXGBE_PXOFFRXCNT(i));
3934 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3935 } else {
3936 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3937 IXGBE_PXONRXC(i));
3938 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3939 IXGBE_PXOFFRXC(i));
3940 }
3941 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
3942 IXGBE_PXONTXC(i));
3943 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
3944 IXGBE_PXOFFTXC(i));
3945 }
3946 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3947 /* work around hardware counting issue */
3948 adapter->stats.gprc -= missed_rx;
3949
3950 /* 82598 hardware only has a 32 bit counter in the high register */
3951 if (hw->mac.type == ixgbe_mac_82599EB) {
3952 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3953 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
3954 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3955 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
3956 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3957 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
3958 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3959 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3960 } else {
3961 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3962 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3963 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3964 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3965 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3966 }
3967 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3968 adapter->stats.bprc += bprc;
3969 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3970 if (hw->mac.type == ixgbe_mac_82598EB)
3971 adapter->stats.mprc -= bprc;
3972 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3973 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3974 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3975 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3976 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3977 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3978 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3979 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3980 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3981 adapter->stats.lxontxc += lxon;
3982 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3983 adapter->stats.lxofftxc += lxoff;
3984 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3985 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
3986 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3987 /*
3988 * 82598 errata - tx of flow control packets is included in tx counters
3989 */
3990 xon_off_tot = lxon + lxoff;
3991 adapter->stats.gptc -= xon_off_tot;
3992 adapter->stats.mptc -= xon_off_tot;
3993 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
3994 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3995 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3996 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3997 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3998 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3999 adapter->stats.ptc64 -= xon_off_tot;
4000 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4001 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4002 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4003 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4004 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4005 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4006
4007 /* Fill out the OS statistics structure */
4008 adapter->net_stats.multicast = adapter->stats.mprc;
4009
4010 /* Rx Errors */
4011 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
4012 adapter->stats.rlec;
4013 adapter->net_stats.rx_dropped = 0;
4014 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4015 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
4016 adapter->net_stats.rx_missed_errors = total_mpc;
4017 }
4018
4019 /**
4020 * ixgbe_watchdog - Timer Call-back
4021 * @data: pointer to adapter cast into an unsigned long
4022 **/
4023 static void ixgbe_watchdog(unsigned long data)
4024 {
4025 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4026 struct ixgbe_hw *hw = &adapter->hw;
4027
4028 /* Do the watchdog outside of interrupt context due to the lovely
4029 * delays that some of the newer hardware requires */
4030 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
4031 u64 eics = 0;
4032 int i;
4033
4034 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++)
4035 eics |= (1 << i);
4036
4037 /* Cause software interrupt to ensure rx rings are cleaned */
4038 switch (hw->mac.type) {
4039 case ixgbe_mac_82598EB:
4040 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4041 IXGBE_WRITE_REG(hw, IXGBE_EICS, (u32)eics);
4042 } else {
4043 /*
4044 * for legacy and MSI interrupts don't set any
4045 * bits that are enabled for EIAM, because this
4046 * operation would set *both* EIMS and EICS for
4047 * any bit in EIAM
4048 */
4049 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4050 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4051 }
4052 break;
4053 case ixgbe_mac_82599EB:
4054 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4055 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(0),
4056 (u32)(eics & 0xFFFFFFFF));
4057 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(1),
4058 (u32)(eics >> 32));
4059 } else {
4060 /*
4061 * for legacy and MSI interrupts don't set any
4062 * bits that are enabled for EIAM, because this
4063 * operation would set *both* EIMS and EICS for
4064 * any bit in EIAM
4065 */
4066 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4067 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4068 }
4069 break;
4070 default:
4071 break;
4072 }
4073 /* Reset the timer */
4074 mod_timer(&adapter->watchdog_timer,
4075 round_jiffies(jiffies + 2 * HZ));
4076 }
4077
4078 schedule_work(&adapter->watchdog_task);
4079 }
4080
4081 /**
4082 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4083 * @work: pointer to work_struct containing our data
4084 **/
4085 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4086 {
4087 struct ixgbe_adapter *adapter = container_of(work,
4088 struct ixgbe_adapter,
4089 multispeed_fiber_task);
4090 struct ixgbe_hw *hw = &adapter->hw;
4091 u32 autoneg;
4092
4093 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4094 if (hw->mac.ops.get_link_capabilities)
4095 hw->mac.ops.get_link_capabilities(hw, &autoneg,
4096 &hw->mac.autoneg);
4097 if (hw->mac.ops.setup_link_speed)
4098 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
4099 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4100 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4101 }
4102
4103 /**
4104 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4105 * @work: pointer to work_struct containing our data
4106 **/
4107 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4108 {
4109 struct ixgbe_adapter *adapter = container_of(work,
4110 struct ixgbe_adapter,
4111 sfp_config_module_task);
4112 struct ixgbe_hw *hw = &adapter->hw;
4113 u32 err;
4114
4115 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4116 err = hw->phy.ops.identify_sfp(hw);
4117 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4118 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
4119 ixgbe_down(adapter);
4120 return;
4121 }
4122 hw->mac.ops.setup_sfp(hw);
4123
4124 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4125 /* This will also work for DA Twinax connections */
4126 schedule_work(&adapter->multispeed_fiber_task);
4127 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4128 }
4129
4130 /**
4131 * ixgbe_watchdog_task - worker thread to bring link up
4132 * @work: pointer to work_struct containing our data
4133 **/
4134 static void ixgbe_watchdog_task(struct work_struct *work)
4135 {
4136 struct ixgbe_adapter *adapter = container_of(work,
4137 struct ixgbe_adapter,
4138 watchdog_task);
4139 struct net_device *netdev = adapter->netdev;
4140 struct ixgbe_hw *hw = &adapter->hw;
4141 u32 link_speed = adapter->link_speed;
4142 bool link_up = adapter->link_up;
4143 int i;
4144 struct ixgbe_ring *tx_ring;
4145 int some_tx_pending = 0;
4146
4147 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4148
4149 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4150 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4151 if (link_up ||
4152 time_after(jiffies, (adapter->link_check_timeout +
4153 IXGBE_TRY_LINK_TIMEOUT))) {
4154 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4155 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4156 }
4157 adapter->link_up = link_up;
4158 adapter->link_speed = link_speed;
4159 }
4160
4161 if (link_up) {
4162 if (!netif_carrier_ok(netdev)) {
4163 bool flow_rx, flow_tx;
4164
4165 if (hw->mac.type == ixgbe_mac_82599EB) {
4166 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4167 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4168 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
4169 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
4170 } else {
4171 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4172 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4173 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
4174 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
4175 }
4176
4177 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4178 "Flow Control: %s\n",
4179 netdev->name,
4180 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4181 "10 Gbps" :
4182 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4183 "1 Gbps" : "unknown speed")),
4184 ((flow_rx && flow_tx) ? "RX/TX" :
4185 (flow_rx ? "RX" :
4186 (flow_tx ? "TX" : "None"))));
4187
4188 netif_carrier_on(netdev);
4189 } else {
4190 /* Force detection of hung controller */
4191 adapter->detect_tx_hung = true;
4192 }
4193 } else {
4194 adapter->link_up = false;
4195 adapter->link_speed = 0;
4196 if (netif_carrier_ok(netdev)) {
4197 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4198 netdev->name);
4199 netif_carrier_off(netdev);
4200 }
4201 }
4202
4203 if (!netif_carrier_ok(netdev)) {
4204 for (i = 0; i < adapter->num_tx_queues; i++) {
4205 tx_ring = &adapter->tx_ring[i];
4206 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4207 some_tx_pending = 1;
4208 break;
4209 }
4210 }
4211
4212 if (some_tx_pending) {
4213 /* We've lost link, so the controller stops DMA,
4214 * but we've got queued Tx work that's never going
4215 * to get done, so reset controller to flush Tx.
4216 * (Do the reset outside of interrupt context).
4217 */
4218 schedule_work(&adapter->reset_task);
4219 }
4220 }
4221
4222 ixgbe_update_stats(adapter);
4223 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4224 }
4225
4226 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4227 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4228 u32 tx_flags, u8 *hdr_len)
4229 {
4230 struct ixgbe_adv_tx_context_desc *context_desc;
4231 unsigned int i;
4232 int err;
4233 struct ixgbe_tx_buffer *tx_buffer_info;
4234 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4235 u32 mss_l4len_idx, l4len;
4236
4237 if (skb_is_gso(skb)) {
4238 if (skb_header_cloned(skb)) {
4239 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4240 if (err)
4241 return err;
4242 }
4243 l4len = tcp_hdrlen(skb);
4244 *hdr_len += l4len;
4245
4246 if (skb->protocol == htons(ETH_P_IP)) {
4247 struct iphdr *iph = ip_hdr(skb);
4248 iph->tot_len = 0;
4249 iph->check = 0;
4250 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4251 iph->daddr, 0,
4252 IPPROTO_TCP,
4253 0);
4254 adapter->hw_tso_ctxt++;
4255 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4256 ipv6_hdr(skb)->payload_len = 0;
4257 tcp_hdr(skb)->check =
4258 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4259 &ipv6_hdr(skb)->daddr,
4260 0, IPPROTO_TCP, 0);
4261 adapter->hw_tso6_ctxt++;
4262 }
4263
4264 i = tx_ring->next_to_use;
4265
4266 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4267 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4268
4269 /* VLAN MACLEN IPLEN */
4270 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4271 vlan_macip_lens |=
4272 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4273 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4274 IXGBE_ADVTXD_MACLEN_SHIFT);
4275 *hdr_len += skb_network_offset(skb);
4276 vlan_macip_lens |=
4277 (skb_transport_header(skb) - skb_network_header(skb));
4278 *hdr_len +=
4279 (skb_transport_header(skb) - skb_network_header(skb));
4280 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4281 context_desc->seqnum_seed = 0;
4282
4283 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4284 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4285 IXGBE_ADVTXD_DTYP_CTXT);
4286
4287 if (skb->protocol == htons(ETH_P_IP))
4288 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4289 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4290 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4291
4292 /* MSS L4LEN IDX */
4293 mss_l4len_idx =
4294 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4295 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4296 /* use index 1 for TSO */
4297 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4298 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4299
4300 tx_buffer_info->time_stamp = jiffies;
4301 tx_buffer_info->next_to_watch = i;
4302
4303 i++;
4304 if (i == tx_ring->count)
4305 i = 0;
4306 tx_ring->next_to_use = i;
4307
4308 return true;
4309 }
4310 return false;
4311 }
4312
4313 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4314 struct ixgbe_ring *tx_ring,
4315 struct sk_buff *skb, u32 tx_flags)
4316 {
4317 struct ixgbe_adv_tx_context_desc *context_desc;
4318 unsigned int i;
4319 struct ixgbe_tx_buffer *tx_buffer_info;
4320 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4321
4322 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4323 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4324 i = tx_ring->next_to_use;
4325 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4326 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4327
4328 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4329 vlan_macip_lens |=
4330 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4331 vlan_macip_lens |= (skb_network_offset(skb) <<
4332 IXGBE_ADVTXD_MACLEN_SHIFT);
4333 if (skb->ip_summed == CHECKSUM_PARTIAL)
4334 vlan_macip_lens |= (skb_transport_header(skb) -
4335 skb_network_header(skb));
4336
4337 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4338 context_desc->seqnum_seed = 0;
4339
4340 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4341 IXGBE_ADVTXD_DTYP_CTXT);
4342
4343 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4344 switch (skb->protocol) {
4345 case cpu_to_be16(ETH_P_IP):
4346 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4347 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4348 type_tucmd_mlhl |=
4349 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4350 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4351 type_tucmd_mlhl |=
4352 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4353 break;
4354 case cpu_to_be16(ETH_P_IPV6):
4355 /* XXX what about other V6 headers?? */
4356 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4357 type_tucmd_mlhl |=
4358 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4359 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4360 type_tucmd_mlhl |=
4361 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4362 break;
4363 default:
4364 if (unlikely(net_ratelimit())) {
4365 DPRINTK(PROBE, WARNING,
4366 "partial checksum but proto=%x!\n",
4367 skb->protocol);
4368 }
4369 break;
4370 }
4371 }
4372
4373 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4374 /* use index zero for tx checksum offload */
4375 context_desc->mss_l4len_idx = 0;
4376
4377 tx_buffer_info->time_stamp = jiffies;
4378 tx_buffer_info->next_to_watch = i;
4379
4380 adapter->hw_csum_tx_good++;
4381 i++;
4382 if (i == tx_ring->count)
4383 i = 0;
4384 tx_ring->next_to_use = i;
4385
4386 return true;
4387 }
4388
4389 return false;
4390 }
4391
4392 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4393 struct ixgbe_ring *tx_ring,
4394 struct sk_buff *skb, unsigned int first)
4395 {
4396 struct ixgbe_tx_buffer *tx_buffer_info;
4397 unsigned int len = skb_headlen(skb);
4398 unsigned int offset = 0, size, count = 0, i;
4399 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4400 unsigned int f;
4401 dma_addr_t *map;
4402
4403 i = tx_ring->next_to_use;
4404
4405 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4406 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4407 return 0;
4408 }
4409
4410 map = skb_shinfo(skb)->dma_maps;
4411
4412 while (len) {
4413 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4414 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4415
4416 tx_buffer_info->length = size;
4417 tx_buffer_info->dma = map[0] + offset;
4418 tx_buffer_info->time_stamp = jiffies;
4419 tx_buffer_info->next_to_watch = i;
4420
4421 len -= size;
4422 offset += size;
4423 count++;
4424
4425 if (len) {
4426 i++;
4427 if (i == tx_ring->count)
4428 i = 0;
4429 }
4430 }
4431
4432 for (f = 0; f < nr_frags; f++) {
4433 struct skb_frag_struct *frag;
4434
4435 frag = &skb_shinfo(skb)->frags[f];
4436 len = frag->size;
4437 offset = 0;
4438
4439 while (len) {
4440 i++;
4441 if (i == tx_ring->count)
4442 i = 0;
4443
4444 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4445 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4446
4447 tx_buffer_info->length = size;
4448 tx_buffer_info->dma = map[f + 1] + offset;
4449 tx_buffer_info->time_stamp = jiffies;
4450 tx_buffer_info->next_to_watch = i;
4451
4452 len -= size;
4453 offset += size;
4454 count++;
4455 }
4456 }
4457
4458 tx_ring->tx_buffer_info[i].skb = skb;
4459 tx_ring->tx_buffer_info[first].next_to_watch = i;
4460
4461 return count;
4462 }
4463
4464 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
4465 struct ixgbe_ring *tx_ring,
4466 int tx_flags, int count, u32 paylen, u8 hdr_len)
4467 {
4468 union ixgbe_adv_tx_desc *tx_desc = NULL;
4469 struct ixgbe_tx_buffer *tx_buffer_info;
4470 u32 olinfo_status = 0, cmd_type_len = 0;
4471 unsigned int i;
4472 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4473
4474 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4475
4476 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4477
4478 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4479 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4480
4481 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4482 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4483
4484 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4485 IXGBE_ADVTXD_POPTS_SHIFT;
4486
4487 /* use index 1 context for tso */
4488 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4489 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4490 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
4491 IXGBE_ADVTXD_POPTS_SHIFT;
4492
4493 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4494 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4495 IXGBE_ADVTXD_POPTS_SHIFT;
4496
4497 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4498
4499 i = tx_ring->next_to_use;
4500 while (count--) {
4501 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4502 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4503 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4504 tx_desc->read.cmd_type_len =
4505 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
4506 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4507 i++;
4508 if (i == tx_ring->count)
4509 i = 0;
4510 }
4511
4512 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4513
4514 /*
4515 * Force memory writes to complete before letting h/w
4516 * know there are new descriptors to fetch. (Only
4517 * applicable for weak-ordered memory model archs,
4518 * such as IA-64).
4519 */
4520 wmb();
4521
4522 tx_ring->next_to_use = i;
4523 writel(i, adapter->hw.hw_addr + tx_ring->tail);
4524 }
4525
4526 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
4527 struct ixgbe_ring *tx_ring, int size)
4528 {
4529 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4530
4531 netif_stop_subqueue(netdev, tx_ring->queue_index);
4532 /* Herbert's original patch had:
4533 * smp_mb__after_netif_stop_queue();
4534 * but since that doesn't exist yet, just open code it. */
4535 smp_mb();
4536
4537 /* We need to check again in a case another CPU has just
4538 * made room available. */
4539 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
4540 return -EBUSY;
4541
4542 /* A reprieve! - use start_queue because it doesn't call schedule */
4543 netif_start_subqueue(netdev, tx_ring->queue_index);
4544 ++adapter->restart_queue;
4545 return 0;
4546 }
4547
4548 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
4549 struct ixgbe_ring *tx_ring, int size)
4550 {
4551 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
4552 return 0;
4553 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
4554 }
4555
4556 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
4557 {
4558 struct ixgbe_adapter *adapter = netdev_priv(dev);
4559
4560 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4561 return 0; /* All traffic should default to class 0 */
4562
4563 return skb_tx_hash(dev, skb);
4564 }
4565
4566 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
4567 {
4568 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4569 struct ixgbe_ring *tx_ring;
4570 unsigned int first;
4571 unsigned int tx_flags = 0;
4572 u8 hdr_len = 0;
4573 int r_idx = 0, tso;
4574 int count = 0;
4575 unsigned int f;
4576
4577 r_idx = skb->queue_mapping;
4578 tx_ring = &adapter->tx_ring[r_idx];
4579
4580 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
4581 tx_flags |= vlan_tx_tag_get(skb);
4582 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4583 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
4584 tx_flags |= (skb->queue_mapping << 13);
4585 }
4586 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4587 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4588 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4589 tx_flags |= (skb->queue_mapping << 13);
4590 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4591 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4592 }
4593 /* three things can cause us to need a context descriptor */
4594 if (skb_is_gso(skb) ||
4595 (skb->ip_summed == CHECKSUM_PARTIAL) ||
4596 (tx_flags & IXGBE_TX_FLAGS_VLAN))
4597 count++;
4598
4599 count += TXD_USE_COUNT(skb_headlen(skb));
4600 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4601 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4602
4603 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
4604 adapter->tx_busy++;
4605 return NETDEV_TX_BUSY;
4606 }
4607
4608 if (skb->protocol == htons(ETH_P_IP))
4609 tx_flags |= IXGBE_TX_FLAGS_IPV4;
4610 first = tx_ring->next_to_use;
4611 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4612 if (tso < 0) {
4613 dev_kfree_skb_any(skb);
4614 return NETDEV_TX_OK;
4615 }
4616
4617 if (tso)
4618 tx_flags |= IXGBE_TX_FLAGS_TSO;
4619 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
4620 (skb->ip_summed == CHECKSUM_PARTIAL))
4621 tx_flags |= IXGBE_TX_FLAGS_CSUM;
4622
4623 count = ixgbe_tx_map(adapter, tx_ring, skb, first);
4624
4625 if (count) {
4626 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
4627 hdr_len);
4628 netdev->trans_start = jiffies;
4629 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
4630
4631 } else {
4632 dev_kfree_skb_any(skb);
4633 tx_ring->tx_buffer_info[first].time_stamp = 0;
4634 tx_ring->next_to_use = first;
4635 }
4636
4637 return NETDEV_TX_OK;
4638 }
4639
4640 /**
4641 * ixgbe_get_stats - Get System Network Statistics
4642 * @netdev: network interface device structure
4643 *
4644 * Returns the address of the device statistics structure.
4645 * The statistics are actually updated from the timer callback.
4646 **/
4647 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
4648 {
4649 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4650
4651 /* only return the current stats */
4652 return &adapter->net_stats;
4653 }
4654
4655 /**
4656 * ixgbe_set_mac - Change the Ethernet Address of the NIC
4657 * @netdev: network interface device structure
4658 * @p: pointer to an address structure
4659 *
4660 * Returns 0 on success, negative on failure
4661 **/
4662 static int ixgbe_set_mac(struct net_device *netdev, void *p)
4663 {
4664 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4665 struct ixgbe_hw *hw = &adapter->hw;
4666 struct sockaddr *addr = p;
4667
4668 if (!is_valid_ether_addr(addr->sa_data))
4669 return -EADDRNOTAVAIL;
4670
4671 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4672 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
4673
4674 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
4675
4676 return 0;
4677 }
4678
4679 static int
4680 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
4681 {
4682 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4683 struct ixgbe_hw *hw = &adapter->hw;
4684 u16 value;
4685 int rc;
4686
4687 if (prtad != hw->phy.mdio.prtad)
4688 return -EINVAL;
4689 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
4690 if (!rc)
4691 rc = value;
4692 return rc;
4693 }
4694
4695 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
4696 u16 addr, u16 value)
4697 {
4698 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4699 struct ixgbe_hw *hw = &adapter->hw;
4700
4701 if (prtad != hw->phy.mdio.prtad)
4702 return -EINVAL;
4703 return hw->phy.ops.write_reg(hw, addr, devad, value);
4704 }
4705
4706 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
4707 {
4708 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4709
4710 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
4711 }
4712
4713 #ifdef CONFIG_NET_POLL_CONTROLLER
4714 /*
4715 * Polling 'interrupt' - used by things like netconsole to send skbs
4716 * without having to re-enable interrupts. It's not called while
4717 * the interrupt routine is executing.
4718 */
4719 static void ixgbe_netpoll(struct net_device *netdev)
4720 {
4721 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4722
4723 disable_irq(adapter->pdev->irq);
4724 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
4725 ixgbe_intr(adapter->pdev->irq, netdev);
4726 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
4727 enable_irq(adapter->pdev->irq);
4728 }
4729 #endif
4730
4731 static const struct net_device_ops ixgbe_netdev_ops = {
4732 .ndo_open = ixgbe_open,
4733 .ndo_stop = ixgbe_close,
4734 .ndo_start_xmit = ixgbe_xmit_frame,
4735 .ndo_select_queue = ixgbe_select_queue,
4736 .ndo_get_stats = ixgbe_get_stats,
4737 .ndo_set_rx_mode = ixgbe_set_rx_mode,
4738 .ndo_set_multicast_list = ixgbe_set_rx_mode,
4739 .ndo_validate_addr = eth_validate_addr,
4740 .ndo_set_mac_address = ixgbe_set_mac,
4741 .ndo_change_mtu = ixgbe_change_mtu,
4742 .ndo_tx_timeout = ixgbe_tx_timeout,
4743 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
4744 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
4745 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
4746 .ndo_do_ioctl = ixgbe_ioctl,
4747 #ifdef CONFIG_NET_POLL_CONTROLLER
4748 .ndo_poll_controller = ixgbe_netpoll,
4749 #endif
4750 };
4751
4752 /**
4753 * ixgbe_probe - Device Initialization Routine
4754 * @pdev: PCI device information struct
4755 * @ent: entry in ixgbe_pci_tbl
4756 *
4757 * Returns 0 on success, negative on failure
4758 *
4759 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
4760 * The OS initialization, configuring of the adapter private structure,
4761 * and a hardware reset occur.
4762 **/
4763 static int __devinit ixgbe_probe(struct pci_dev *pdev,
4764 const struct pci_device_id *ent)
4765 {
4766 struct net_device *netdev;
4767 struct ixgbe_adapter *adapter = NULL;
4768 struct ixgbe_hw *hw;
4769 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
4770 static int cards_found;
4771 int i, err, pci_using_dac;
4772 u32 part_num, eec;
4773
4774 err = pci_enable_device_mem(pdev);
4775 if (err)
4776 return err;
4777
4778 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
4779 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
4780 pci_using_dac = 1;
4781 } else {
4782 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4783 if (err) {
4784 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4785 if (err) {
4786 dev_err(&pdev->dev, "No usable DMA "
4787 "configuration, aborting\n");
4788 goto err_dma;
4789 }
4790 }
4791 pci_using_dac = 0;
4792 }
4793
4794 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
4795 IORESOURCE_MEM), ixgbe_driver_name);
4796 if (err) {
4797 dev_err(&pdev->dev,
4798 "pci_request_selected_regions failed 0x%x\n", err);
4799 goto err_pci_reg;
4800 }
4801
4802 err = pci_enable_pcie_error_reporting(pdev);
4803 if (err) {
4804 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
4805 "0x%x\n", err);
4806 /* non-fatal, continue */
4807 }
4808
4809 pci_set_master(pdev);
4810 pci_save_state(pdev);
4811
4812 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
4813 if (!netdev) {
4814 err = -ENOMEM;
4815 goto err_alloc_etherdev;
4816 }
4817
4818 SET_NETDEV_DEV(netdev, &pdev->dev);
4819
4820 pci_set_drvdata(pdev, netdev);
4821 adapter = netdev_priv(netdev);
4822
4823 adapter->netdev = netdev;
4824 adapter->pdev = pdev;
4825 hw = &adapter->hw;
4826 hw->back = adapter;
4827 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
4828
4829 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
4830 pci_resource_len(pdev, 0));
4831 if (!hw->hw_addr) {
4832 err = -EIO;
4833 goto err_ioremap;
4834 }
4835
4836 for (i = 1; i <= 5; i++) {
4837 if (pci_resource_len(pdev, i) == 0)
4838 continue;
4839 }
4840
4841 netdev->netdev_ops = &ixgbe_netdev_ops;
4842 ixgbe_set_ethtool_ops(netdev);
4843 netdev->watchdog_timeo = 5 * HZ;
4844 strcpy(netdev->name, pci_name(pdev));
4845
4846 adapter->bd_number = cards_found;
4847
4848 /* Setup hw api */
4849 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
4850 hw->mac.type = ii->mac;
4851
4852 /* EEPROM */
4853 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
4854 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
4855 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
4856 if (!(eec & (1 << 8)))
4857 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
4858
4859 /* PHY */
4860 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
4861 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
4862 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
4863 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
4864 hw->phy.mdio.mmds = 0;
4865 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
4866 hw->phy.mdio.dev = netdev;
4867 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
4868 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
4869
4870 /* set up this timer and work struct before calling get_invariants
4871 * which might start the timer
4872 */
4873 init_timer(&adapter->sfp_timer);
4874 adapter->sfp_timer.function = &ixgbe_sfp_timer;
4875 adapter->sfp_timer.data = (unsigned long) adapter;
4876
4877 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
4878
4879 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
4880 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
4881
4882 /* a new SFP+ module arrival, called from GPI SDP2 context */
4883 INIT_WORK(&adapter->sfp_config_module_task,
4884 ixgbe_sfp_config_module_task);
4885
4886 err = ii->get_invariants(hw);
4887 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
4888 /* start a kernel thread to watch for a module to arrive */
4889 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4890 mod_timer(&adapter->sfp_timer,
4891 round_jiffies(jiffies + (2 * HZ)));
4892 err = 0;
4893 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4894 DPRINTK(PROBE, ERR, "failed to load because an "
4895 "unsupported SFP+ module type was detected.\n");
4896 goto err_hw_init;
4897 } else if (err) {
4898 goto err_hw_init;
4899 }
4900
4901 /* setup the private structure */
4902 err = ixgbe_sw_init(adapter);
4903 if (err)
4904 goto err_sw_init;
4905
4906 /* reset_hw fills in the perm_addr as well */
4907 err = hw->mac.ops.reset_hw(hw);
4908 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4909 dev_err(&adapter->pdev->dev, "failed to load because an "
4910 "unsupported SFP+ module type was detected.\n");
4911 goto err_sw_init;
4912 } else if (err) {
4913 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
4914 goto err_sw_init;
4915 }
4916
4917 netdev->features = NETIF_F_SG |
4918 NETIF_F_IP_CSUM |
4919 NETIF_F_HW_VLAN_TX |
4920 NETIF_F_HW_VLAN_RX |
4921 NETIF_F_HW_VLAN_FILTER;
4922
4923 netdev->features |= NETIF_F_IPV6_CSUM;
4924 netdev->features |= NETIF_F_TSO;
4925 netdev->features |= NETIF_F_TSO6;
4926 netdev->features |= NETIF_F_GRO;
4927
4928 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
4929 netdev->features |= NETIF_F_SCTP_CSUM;
4930
4931 netdev->vlan_features |= NETIF_F_TSO;
4932 netdev->vlan_features |= NETIF_F_TSO6;
4933 netdev->vlan_features |= NETIF_F_IP_CSUM;
4934 netdev->vlan_features |= NETIF_F_SG;
4935
4936 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4937 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4938
4939 #ifdef CONFIG_IXGBE_DCB
4940 netdev->dcbnl_ops = &dcbnl_ops;
4941 #endif
4942
4943 if (pci_using_dac)
4944 netdev->features |= NETIF_F_HIGHDMA;
4945
4946 if (adapter->flags & IXGBE_FLAG_RSC_ENABLED)
4947 netdev->features |= NETIF_F_LRO;
4948
4949 /* make sure the EEPROM is good */
4950 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
4951 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
4952 err = -EIO;
4953 goto err_eeprom;
4954 }
4955
4956 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
4957 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
4958
4959 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
4960 dev_err(&pdev->dev, "invalid MAC address\n");
4961 err = -EIO;
4962 goto err_eeprom;
4963 }
4964
4965 init_timer(&adapter->watchdog_timer);
4966 adapter->watchdog_timer.function = &ixgbe_watchdog;
4967 adapter->watchdog_timer.data = (unsigned long)adapter;
4968
4969 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
4970 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
4971
4972 err = ixgbe_init_interrupt_scheme(adapter);
4973 if (err)
4974 goto err_sw_init;
4975
4976 switch (pdev->device) {
4977 case IXGBE_DEV_ID_82599_KX4:
4978 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
4979 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
4980 break;
4981 default:
4982 adapter->wol = 0;
4983 break;
4984 }
4985 device_init_wakeup(&adapter->pdev->dev, true);
4986 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
4987
4988 /* pick up the PCI bus settings for reporting later */
4989 hw->mac.ops.get_bus_info(hw);
4990
4991 /* print bus type/speed/width info */
4992 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
4993 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
4994 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
4995 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
4996 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
4997 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
4998 "Unknown"),
4999 netdev->dev_addr);
5000 ixgbe_read_pba_num_generic(hw, &part_num);
5001 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5002 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5003 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5004 (part_num >> 8), (part_num & 0xff));
5005 else
5006 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5007 hw->mac.type, hw->phy.type,
5008 (part_num >> 8), (part_num & 0xff));
5009
5010 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5011 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5012 "this card is not sufficient for optimal "
5013 "performance.\n");
5014 dev_warn(&pdev->dev, "For optimal performance a x8 "
5015 "PCI-Express slot is required.\n");
5016 }
5017
5018 /* save off EEPROM version number */
5019 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5020
5021 /* reset the hardware with the new settings */
5022 hw->mac.ops.start_hw(hw);
5023
5024 strcpy(netdev->name, "eth%d");
5025 err = register_netdev(netdev);
5026 if (err)
5027 goto err_register;
5028
5029 /* carrier off reporting is important to ethtool even BEFORE open */
5030 netif_carrier_off(netdev);
5031
5032 #ifdef CONFIG_IXGBE_DCA
5033 if (dca_add_requester(&pdev->dev) == 0) {
5034 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5035 /* always use CB2 mode, difference is masked
5036 * in the CB driver */
5037 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
5038 ixgbe_setup_dca(adapter);
5039 }
5040 #endif
5041
5042 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5043 cards_found++;
5044 return 0;
5045
5046 err_register:
5047 ixgbe_release_hw_control(adapter);
5048 err_hw_init:
5049 ixgbe_clear_interrupt_scheme(adapter);
5050 err_sw_init:
5051 err_eeprom:
5052 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5053 del_timer_sync(&adapter->sfp_timer);
5054 cancel_work_sync(&adapter->sfp_task);
5055 cancel_work_sync(&adapter->multispeed_fiber_task);
5056 cancel_work_sync(&adapter->sfp_config_module_task);
5057 iounmap(hw->hw_addr);
5058 err_ioremap:
5059 free_netdev(netdev);
5060 err_alloc_etherdev:
5061 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5062 IORESOURCE_MEM));
5063 err_pci_reg:
5064 err_dma:
5065 pci_disable_device(pdev);
5066 return err;
5067 }
5068
5069 /**
5070 * ixgbe_remove - Device Removal Routine
5071 * @pdev: PCI device information struct
5072 *
5073 * ixgbe_remove is called by the PCI subsystem to alert the driver
5074 * that it should release a PCI device. The could be caused by a
5075 * Hot-Plug event, or because the driver is going to be removed from
5076 * memory.
5077 **/
5078 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5079 {
5080 struct net_device *netdev = pci_get_drvdata(pdev);
5081 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5082 int err;
5083
5084 set_bit(__IXGBE_DOWN, &adapter->state);
5085 /* clear the module not found bit to make sure the worker won't
5086 * reschedule
5087 */
5088 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5089 del_timer_sync(&adapter->watchdog_timer);
5090
5091 del_timer_sync(&adapter->sfp_timer);
5092 cancel_work_sync(&adapter->watchdog_task);
5093 cancel_work_sync(&adapter->sfp_task);
5094 cancel_work_sync(&adapter->multispeed_fiber_task);
5095 cancel_work_sync(&adapter->sfp_config_module_task);
5096 flush_scheduled_work();
5097
5098 #ifdef CONFIG_IXGBE_DCA
5099 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5100 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5101 dca_remove_requester(&pdev->dev);
5102 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5103 }
5104
5105 #endif
5106 if (netdev->reg_state == NETREG_REGISTERED)
5107 unregister_netdev(netdev);
5108
5109 ixgbe_clear_interrupt_scheme(adapter);
5110
5111 ixgbe_release_hw_control(adapter);
5112
5113 iounmap(adapter->hw.hw_addr);
5114 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5115 IORESOURCE_MEM));
5116
5117 DPRINTK(PROBE, INFO, "complete\n");
5118
5119 free_netdev(netdev);
5120
5121 err = pci_disable_pcie_error_reporting(pdev);
5122 if (err)
5123 dev_err(&pdev->dev,
5124 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5125
5126 pci_disable_device(pdev);
5127 }
5128
5129 /**
5130 * ixgbe_io_error_detected - called when PCI error is detected
5131 * @pdev: Pointer to PCI device
5132 * @state: The current pci connection state
5133 *
5134 * This function is called after a PCI bus error affecting
5135 * this device has been detected.
5136 */
5137 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5138 pci_channel_state_t state)
5139 {
5140 struct net_device *netdev = pci_get_drvdata(pdev);
5141 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5142
5143 netif_device_detach(netdev);
5144
5145 if (state == pci_channel_io_perm_failure)
5146 return PCI_ERS_RESULT_DISCONNECT;
5147
5148 if (netif_running(netdev))
5149 ixgbe_down(adapter);
5150 pci_disable_device(pdev);
5151
5152 /* Request a slot reset. */
5153 return PCI_ERS_RESULT_NEED_RESET;
5154 }
5155
5156 /**
5157 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5158 * @pdev: Pointer to PCI device
5159 *
5160 * Restart the card from scratch, as if from a cold-boot.
5161 */
5162 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5163 {
5164 struct net_device *netdev = pci_get_drvdata(pdev);
5165 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5166 pci_ers_result_t result;
5167 int err;
5168
5169 if (pci_enable_device_mem(pdev)) {
5170 DPRINTK(PROBE, ERR,
5171 "Cannot re-enable PCI device after reset.\n");
5172 result = PCI_ERS_RESULT_DISCONNECT;
5173 } else {
5174 pci_set_master(pdev);
5175 pci_restore_state(pdev);
5176
5177 pci_wake_from_d3(pdev, false);
5178
5179 ixgbe_reset(adapter);
5180 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5181 result = PCI_ERS_RESULT_RECOVERED;
5182 }
5183
5184 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5185 if (err) {
5186 dev_err(&pdev->dev,
5187 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5188 /* non-fatal, continue */
5189 }
5190
5191 return result;
5192 }
5193
5194 /**
5195 * ixgbe_io_resume - called when traffic can start flowing again.
5196 * @pdev: Pointer to PCI device
5197 *
5198 * This callback is called when the error recovery driver tells us that
5199 * its OK to resume normal operation.
5200 */
5201 static void ixgbe_io_resume(struct pci_dev *pdev)
5202 {
5203 struct net_device *netdev = pci_get_drvdata(pdev);
5204 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5205
5206 if (netif_running(netdev)) {
5207 if (ixgbe_up(adapter)) {
5208 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5209 return;
5210 }
5211 }
5212
5213 netif_device_attach(netdev);
5214 }
5215
5216 static struct pci_error_handlers ixgbe_err_handler = {
5217 .error_detected = ixgbe_io_error_detected,
5218 .slot_reset = ixgbe_io_slot_reset,
5219 .resume = ixgbe_io_resume,
5220 };
5221
5222 static struct pci_driver ixgbe_driver = {
5223 .name = ixgbe_driver_name,
5224 .id_table = ixgbe_pci_tbl,
5225 .probe = ixgbe_probe,
5226 .remove = __devexit_p(ixgbe_remove),
5227 #ifdef CONFIG_PM
5228 .suspend = ixgbe_suspend,
5229 .resume = ixgbe_resume,
5230 #endif
5231 .shutdown = ixgbe_shutdown,
5232 .err_handler = &ixgbe_err_handler
5233 };
5234
5235 /**
5236 * ixgbe_init_module - Driver Registration Routine
5237 *
5238 * ixgbe_init_module is the first routine called when the driver is
5239 * loaded. All it does is register with the PCI subsystem.
5240 **/
5241 static int __init ixgbe_init_module(void)
5242 {
5243 int ret;
5244 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5245 ixgbe_driver_string, ixgbe_driver_version);
5246
5247 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5248
5249 #ifdef CONFIG_IXGBE_DCA
5250 dca_register_notify(&dca_notifier);
5251 #endif
5252
5253 ret = pci_register_driver(&ixgbe_driver);
5254 return ret;
5255 }
5256
5257 module_init(ixgbe_init_module);
5258
5259 /**
5260 * ixgbe_exit_module - Driver Exit Cleanup Routine
5261 *
5262 * ixgbe_exit_module is called just before the driver is removed
5263 * from memory.
5264 **/
5265 static void __exit ixgbe_exit_module(void)
5266 {
5267 #ifdef CONFIG_IXGBE_DCA
5268 dca_unregister_notify(&dca_notifier);
5269 #endif
5270 pci_unregister_driver(&ixgbe_driver);
5271 }
5272
5273 #ifdef CONFIG_IXGBE_DCA
5274 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
5275 void *p)
5276 {
5277 int ret_val;
5278
5279 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
5280 __ixgbe_notify_dca);
5281
5282 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5283 }
5284
5285 #endif /* CONFIG_IXGBE_DCA */
5286 #ifdef DEBUG
5287 /**
5288 * ixgbe_get_hw_dev_name - return device name string
5289 * used by hardware layer to print debugging information
5290 **/
5291 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5292 {
5293 struct ixgbe_adapter *adapter = hw->back;
5294 return adapter->netdev->name;
5295 }
5296
5297 #endif
5298 module_exit(ixgbe_exit_module);
5299
5300 /* ixgbe_main.c */
x86 "subsystem" repository