2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/usb.h>
24 #include <linux/pci.h>
29 * Allocates a generic ring segment from the ring pool, sets the dma address,
30 * initializes the segment to zero, and sets the private next pointer to NULL.
33 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
35 static struct xhci_segment
*xhci_segment_alloc(struct xhci_hcd
*xhci
, gfp_t flags
)
37 struct xhci_segment
*seg
;
40 seg
= kzalloc(sizeof *seg
, flags
);
43 xhci_dbg(xhci
, "Allocating priv segment structure at 0x%x\n",
46 seg
->trbs
= dma_pool_alloc(xhci
->segment_pool
, flags
, &dma
);
51 xhci_dbg(xhci
, "// Allocating segment at 0x%x (virtual) 0x%x (DMA)\n",
52 (unsigned int) seg
->trbs
, (u32
) dma
);
54 memset(seg
->trbs
, 0, SEGMENT_SIZE
);
61 static void xhci_segment_free(struct xhci_hcd
*xhci
, struct xhci_segment
*seg
)
66 xhci_dbg(xhci
, "Freeing DMA segment at 0x%x"
67 " (virtual) 0x%x (DMA)\n",
68 (unsigned int) seg
->trbs
, (u32
) seg
->dma
);
69 dma_pool_free(xhci
->segment_pool
, seg
->trbs
, seg
->dma
);
72 xhci_dbg(xhci
, "Freeing priv segment structure at 0x%x\n",
78 * Make the prev segment point to the next segment.
80 * Change the last TRB in the prev segment to be a Link TRB which points to the
81 * DMA address of the next segment. The caller needs to set any Link TRB
82 * related flags, such as End TRB, Toggle Cycle, and no snoop.
84 static void xhci_link_segments(struct xhci_hcd
*xhci
, struct xhci_segment
*prev
,
85 struct xhci_segment
*next
, bool link_trbs
)
93 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.segment_ptr
[0] = next
->dma
;
95 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
96 val
= prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
;
97 val
&= ~TRB_TYPE_BITMASK
;
98 val
|= TRB_TYPE(TRB_LINK
);
99 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
= val
;
101 xhci_dbg(xhci
, "Linking segment 0x%x to segment 0x%x (DMA)\n",
102 prev
->dma
, next
->dma
);
105 /* XXX: Do we need the hcd structure in all these functions? */
106 void xhci_ring_free(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
108 struct xhci_segment
*seg
;
109 struct xhci_segment
*first_seg
;
111 if (!ring
|| !ring
->first_seg
)
113 first_seg
= ring
->first_seg
;
114 seg
= first_seg
->next
;
115 xhci_dbg(xhci
, "Freeing ring at 0x%x\n", (unsigned int) ring
);
116 while (seg
!= first_seg
) {
117 struct xhci_segment
*next
= seg
->next
;
118 xhci_segment_free(xhci
, seg
);
121 xhci_segment_free(xhci
, first_seg
);
122 ring
->first_seg
= NULL
;
127 * Create a new ring with zero or more segments.
129 * Link each segment together into a ring.
130 * Set the end flag and the cycle toggle bit on the last segment.
131 * See section 4.9.1 and figures 15 and 16.
133 static struct xhci_ring
*xhci_ring_alloc(struct xhci_hcd
*xhci
,
134 unsigned int num_segs
, bool link_trbs
, gfp_t flags
)
136 struct xhci_ring
*ring
;
137 struct xhci_segment
*prev
;
139 ring
= kzalloc(sizeof *(ring
), flags
);
140 xhci_dbg(xhci
, "Allocating ring at 0x%x\n", (unsigned int) ring
);
144 INIT_LIST_HEAD(&ring
->td_list
);
145 INIT_LIST_HEAD(&ring
->cancelled_td_list
);
149 ring
->first_seg
= xhci_segment_alloc(xhci
, flags
);
150 if (!ring
->first_seg
)
154 prev
= ring
->first_seg
;
155 while (num_segs
> 0) {
156 struct xhci_segment
*next
;
158 next
= xhci_segment_alloc(xhci
, flags
);
161 xhci_link_segments(xhci
, prev
, next
, link_trbs
);
166 xhci_link_segments(xhci
, prev
, ring
->first_seg
, link_trbs
);
169 /* See section 4.9.2.1 and 6.4.4.1 */
170 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
|= (LINK_TOGGLE
);
171 xhci_dbg(xhci
, "Wrote link toggle flag to"
172 " segment 0x%x (virtual), 0x%x (DMA)\n",
173 (unsigned int) prev
, (u32
) prev
->dma
);
175 /* The ring is empty, so the enqueue pointer == dequeue pointer */
176 ring
->enqueue
= ring
->first_seg
->trbs
;
177 ring
->enq_seg
= ring
->first_seg
;
178 ring
->dequeue
= ring
->enqueue
;
179 ring
->deq_seg
= ring
->first_seg
;
180 /* The ring is initialized to 0. The producer must write 1 to the cycle
181 * bit to handover ownership of the TRB, so PCS = 1. The consumer must
182 * compare CCS to the cycle bit to check ownership, so CCS = 1.
184 ring
->cycle_state
= 1;
189 xhci_ring_free(xhci
, ring
);
193 /* All the xhci_tds in the ring's TD list should be freed at this point */
194 void xhci_free_virt_device(struct xhci_hcd
*xhci
, int slot_id
)
196 struct xhci_virt_device
*dev
;
199 /* Slot ID 0 is reserved */
200 if (slot_id
== 0 || !xhci
->devs
[slot_id
])
203 dev
= xhci
->devs
[slot_id
];
204 xhci
->dcbaa
->dev_context_ptrs
[2*slot_id
] = 0;
205 xhci
->dcbaa
->dev_context_ptrs
[2*slot_id
+ 1] = 0;
209 for (i
= 0; i
< 31; ++i
)
210 if (dev
->ep_rings
[i
])
211 xhci_ring_free(xhci
, dev
->ep_rings
[i
]);
214 dma_pool_free(xhci
->device_pool
,
215 dev
->in_ctx
, dev
->in_ctx_dma
);
217 dma_pool_free(xhci
->device_pool
,
218 dev
->out_ctx
, dev
->out_ctx_dma
);
219 kfree(xhci
->devs
[slot_id
]);
220 xhci
->devs
[slot_id
] = 0;
223 int xhci_alloc_virt_device(struct xhci_hcd
*xhci
, int slot_id
,
224 struct usb_device
*udev
, gfp_t flags
)
227 struct xhci_virt_device
*dev
;
229 /* Slot ID 0 is reserved */
230 if (slot_id
== 0 || xhci
->devs
[slot_id
]) {
231 xhci_warn(xhci
, "Bad Slot ID %d\n", slot_id
);
235 xhci
->devs
[slot_id
] = kzalloc(sizeof(*xhci
->devs
[slot_id
]), flags
);
236 if (!xhci
->devs
[slot_id
])
238 dev
= xhci
->devs
[slot_id
];
240 /* Allocate the (output) device context that will be used in the HC */
241 dev
->out_ctx
= dma_pool_alloc(xhci
->device_pool
, flags
, &dma
);
244 dev
->out_ctx_dma
= dma
;
245 xhci_dbg(xhci
, "Slot %d output ctx = 0x%x (dma)\n", slot_id
, dma
);
246 memset(dev
->out_ctx
, 0, sizeof(*dev
->out_ctx
));
248 /* Allocate the (input) device context for address device command */
249 dev
->in_ctx
= dma_pool_alloc(xhci
->device_pool
, flags
, &dma
);
252 dev
->in_ctx_dma
= dma
;
253 xhci_dbg(xhci
, "Slot %d input ctx = 0x%x (dma)\n", slot_id
, dma
);
254 memset(dev
->in_ctx
, 0, sizeof(*dev
->in_ctx
));
256 /* Allocate endpoint 0 ring */
257 dev
->ep_rings
[0] = xhci_ring_alloc(xhci
, 1, true, flags
);
258 if (!dev
->ep_rings
[0])
261 init_completion(&dev
->cmd_completion
);
264 * Point to output device context in dcbaa; skip the output control
265 * context, which is eight 32 bit fields (or 32 bytes long)
267 xhci
->dcbaa
->dev_context_ptrs
[2*slot_id
] =
268 (u32
) dev
->out_ctx_dma
+ (32);
269 xhci_dbg(xhci
, "Set slot id %d dcbaa entry 0x%x to 0x%x\n",
271 (unsigned int) &xhci
->dcbaa
->dev_context_ptrs
[2*slot_id
],
273 xhci
->dcbaa
->dev_context_ptrs
[2*slot_id
+ 1] = 0;
277 xhci_free_virt_device(xhci
, slot_id
);
281 /* Setup an xHCI virtual device for a Set Address command */
282 int xhci_setup_addressable_virt_dev(struct xhci_hcd
*xhci
, struct usb_device
*udev
)
284 struct xhci_virt_device
*dev
;
285 struct xhci_ep_ctx
*ep0_ctx
;
286 struct usb_device
*top_dev
;
288 dev
= xhci
->devs
[udev
->slot_id
];
289 /* Slot ID 0 is reserved */
290 if (udev
->slot_id
== 0 || !dev
) {
291 xhci_warn(xhci
, "Slot ID %d is not assigned to this device\n",
295 ep0_ctx
= &dev
->in_ctx
->ep
[0];
297 /* 2) New slot context and endpoint 0 context are valid*/
298 dev
->in_ctx
->add_flags
= SLOT_FLAG
| EP0_FLAG
;
300 /* 3) Only the control endpoint is valid - one endpoint context */
301 dev
->in_ctx
->slot
.dev_info
|= LAST_CTX(1);
303 switch (udev
->speed
) {
304 case USB_SPEED_SUPER
:
305 dev
->in_ctx
->slot
.dev_info
|= (u32
) udev
->route
;
306 dev
->in_ctx
->slot
.dev_info
|= (u32
) SLOT_SPEED_SS
;
309 dev
->in_ctx
->slot
.dev_info
|= (u32
) SLOT_SPEED_HS
;
312 dev
->in_ctx
->slot
.dev_info
|= (u32
) SLOT_SPEED_FS
;
315 dev
->in_ctx
->slot
.dev_info
|= (u32
) SLOT_SPEED_LS
;
317 case USB_SPEED_VARIABLE
:
318 xhci_dbg(xhci
, "FIXME xHCI doesn't support wireless speeds\n");
322 /* Speed was set earlier, this shouldn't happen. */
325 /* Find the root hub port this device is under */
326 for (top_dev
= udev
; top_dev
->parent
&& top_dev
->parent
->parent
;
327 top_dev
= top_dev
->parent
)
328 /* Found device below root hub */;
329 dev
->in_ctx
->slot
.dev_info2
|= (u32
) ROOT_HUB_PORT(top_dev
->portnum
);
330 xhci_dbg(xhci
, "Set root hub portnum to %d\n", top_dev
->portnum
);
332 /* Is this a LS/FS device under a HS hub? */
334 * FIXME: I don't think this is right, where does the TT info for the
335 * roothub or parent hub come from?
337 if ((udev
->speed
== USB_SPEED_LOW
|| udev
->speed
== USB_SPEED_FULL
) &&
339 dev
->in_ctx
->slot
.tt_info
= udev
->tt
->hub
->slot_id
;
340 dev
->in_ctx
->slot
.tt_info
|= udev
->ttport
<< 8;
342 xhci_dbg(xhci
, "udev->tt = 0x%x\n", (unsigned int) udev
->tt
);
343 xhci_dbg(xhci
, "udev->ttport = 0x%x\n", udev
->ttport
);
345 /* Step 4 - ring already allocated */
347 ep0_ctx
->ep_info2
= EP_TYPE(CTRL_EP
);
349 * See section 4.3 bullet 6:
350 * The default Max Packet size for ep0 is "8 bytes for a USB2
351 * LS/FS/HS device or 512 bytes for a USB3 SS device"
352 * XXX: Not sure about wireless USB devices.
354 if (udev
->speed
== USB_SPEED_SUPER
)
355 ep0_ctx
->ep_info2
|= MAX_PACKET(512);
357 ep0_ctx
->ep_info2
|= MAX_PACKET(8);
358 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
359 ep0_ctx
->ep_info2
|= MAX_BURST(0);
360 ep0_ctx
->ep_info2
|= ERROR_COUNT(3);
363 dev
->ep_rings
[0]->first_seg
->dma
;
364 ep0_ctx
->deq
[0] |= dev
->ep_rings
[0]->cycle_state
;
367 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
372 /* Return the polling or NAK interval.
374 * The polling interval is expressed in "microframes". If xHCI's Interval field
375 * is set to N, it will service the endpoint every 2^(Interval)*125us.
377 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
380 static inline unsigned int xhci_get_endpoint_interval(struct usb_device
*udev
,
381 struct usb_host_endpoint
*ep
)
383 unsigned int interval
= 0;
385 switch (udev
->speed
) {
388 if (usb_endpoint_xfer_control(&ep
->desc
) ||
389 usb_endpoint_xfer_bulk(&ep
->desc
))
390 interval
= ep
->desc
.bInterval
;
391 /* Fall through - SS and HS isoc/int have same decoding */
392 case USB_SPEED_SUPER
:
393 if (usb_endpoint_xfer_int(&ep
->desc
) ||
394 usb_endpoint_xfer_isoc(&ep
->desc
)) {
395 if (ep
->desc
.bInterval
== 0)
398 interval
= ep
->desc
.bInterval
- 1;
401 if (interval
!= ep
->desc
.bInterval
+ 1)
402 dev_warn(&udev
->dev
, "ep %#x - rounding interval to %d microframes\n",
403 ep
->desc
.bEndpointAddress
, 1 << interval
);
406 /* Convert bInterval (in 1-255 frames) to microframes and round down to
407 * nearest power of 2.
411 if (usb_endpoint_xfer_int(&ep
->desc
) ||
412 usb_endpoint_xfer_isoc(&ep
->desc
)) {
413 interval
= fls(8*ep
->desc
.bInterval
) - 1;
418 if ((1 << interval
) != 8*ep
->desc
.bInterval
)
419 dev_warn(&udev
->dev
, "ep %#x - rounding interval to %d microframes\n",
420 ep
->desc
.bEndpointAddress
, 1 << interval
);
426 return EP_INTERVAL(interval
);
429 static inline u32
xhci_get_endpoint_type(struct usb_device
*udev
,
430 struct usb_host_endpoint
*ep
)
435 in
= usb_endpoint_dir_in(&ep
->desc
);
436 if (usb_endpoint_xfer_control(&ep
->desc
)) {
437 type
= EP_TYPE(CTRL_EP
);
438 } else if (usb_endpoint_xfer_bulk(&ep
->desc
)) {
440 type
= EP_TYPE(BULK_IN_EP
);
442 type
= EP_TYPE(BULK_OUT_EP
);
443 } else if (usb_endpoint_xfer_isoc(&ep
->desc
)) {
445 type
= EP_TYPE(ISOC_IN_EP
);
447 type
= EP_TYPE(ISOC_OUT_EP
);
448 } else if (usb_endpoint_xfer_int(&ep
->desc
)) {
450 type
= EP_TYPE(INT_IN_EP
);
452 type
= EP_TYPE(INT_OUT_EP
);
459 int xhci_endpoint_init(struct xhci_hcd
*xhci
,
460 struct xhci_virt_device
*virt_dev
,
461 struct usb_device
*udev
,
462 struct usb_host_endpoint
*ep
)
464 unsigned int ep_index
;
465 struct xhci_ep_ctx
*ep_ctx
;
466 struct xhci_ring
*ep_ring
;
467 unsigned int max_packet
;
468 unsigned int max_burst
;
470 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
471 ep_ctx
= &virt_dev
->in_ctx
->ep
[ep_index
];
473 /* Set up the endpoint ring */
474 virt_dev
->new_ep_rings
[ep_index
] = xhci_ring_alloc(xhci
, 1, true, GFP_KERNEL
);
475 if (!virt_dev
->new_ep_rings
[ep_index
])
477 ep_ring
= virt_dev
->new_ep_rings
[ep_index
];
479 ep_ctx
->deq
[0] = ep_ring
->first_seg
->dma
| ep_ring
->cycle_state
;
481 ep_ctx
->ep_info
= xhci_get_endpoint_interval(udev
, ep
);
483 /* FIXME dig Mult and streams info out of ep companion desc */
485 /* Allow 3 retries for everything but isoc */
486 if (!usb_endpoint_xfer_isoc(&ep
->desc
))
487 ep_ctx
->ep_info2
= ERROR_COUNT(3);
489 ep_ctx
->ep_info2
= ERROR_COUNT(0);
491 ep_ctx
->ep_info2
|= xhci_get_endpoint_type(udev
, ep
);
493 /* Set the max packet size and max burst */
494 switch (udev
->speed
) {
495 case USB_SPEED_SUPER
:
496 max_packet
= ep
->desc
.wMaxPacketSize
;
497 ep_ctx
->ep_info2
|= MAX_PACKET(max_packet
);
498 /* dig out max burst from ep companion desc */
499 max_packet
= ep
->ep_comp
->desc
.bMaxBurst
;
500 ep_ctx
->ep_info2
|= MAX_BURST(max_packet
);
503 /* bits 11:12 specify the number of additional transaction
504 * opportunities per microframe (USB 2.0, section 9.6.6)
506 if (usb_endpoint_xfer_isoc(&ep
->desc
) ||
507 usb_endpoint_xfer_int(&ep
->desc
)) {
508 max_burst
= (ep
->desc
.wMaxPacketSize
& 0x1800) >> 11;
509 ep_ctx
->ep_info2
|= MAX_BURST(max_burst
);
514 max_packet
= ep
->desc
.wMaxPacketSize
& 0x3ff;
515 ep_ctx
->ep_info2
|= MAX_PACKET(max_packet
);
520 /* FIXME Debug endpoint context */
524 void xhci_endpoint_zero(struct xhci_hcd
*xhci
,
525 struct xhci_virt_device
*virt_dev
,
526 struct usb_host_endpoint
*ep
)
528 unsigned int ep_index
;
529 struct xhci_ep_ctx
*ep_ctx
;
531 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
532 ep_ctx
= &virt_dev
->in_ctx
->ep
[ep_index
];
535 ep_ctx
->ep_info2
= 0;
539 /* Don't free the endpoint ring until the set interface or configuration
544 void xhci_mem_cleanup(struct xhci_hcd
*xhci
)
546 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
550 /* Free the Event Ring Segment Table and the actual Event Ring */
551 xhci_writel(xhci
, 0, &xhci
->ir_set
->erst_size
);
552 xhci_writel(xhci
, 0, &xhci
->ir_set
->erst_base
[1]);
553 xhci_writel(xhci
, 0, &xhci
->ir_set
->erst_base
[0]);
554 xhci_writel(xhci
, 0, &xhci
->ir_set
->erst_dequeue
[1]);
555 xhci_writel(xhci
, 0, &xhci
->ir_set
->erst_dequeue
[0]);
556 size
= sizeof(struct xhci_erst_entry
)*(xhci
->erst
.num_entries
);
557 if (xhci
->erst
.entries
)
558 pci_free_consistent(pdev
, size
,
559 xhci
->erst
.entries
, xhci
->erst
.erst_dma_addr
);
560 xhci
->erst
.entries
= NULL
;
561 xhci_dbg(xhci
, "Freed ERST\n");
562 if (xhci
->event_ring
)
563 xhci_ring_free(xhci
, xhci
->event_ring
);
564 xhci
->event_ring
= NULL
;
565 xhci_dbg(xhci
, "Freed event ring\n");
567 xhci_writel(xhci
, 0, &xhci
->op_regs
->cmd_ring
[1]);
568 xhci_writel(xhci
, 0, &xhci
->op_regs
->cmd_ring
[0]);
570 xhci_ring_free(xhci
, xhci
->cmd_ring
);
571 xhci
->cmd_ring
= NULL
;
572 xhci_dbg(xhci
, "Freed command ring\n");
574 for (i
= 1; i
< MAX_HC_SLOTS
; ++i
)
575 xhci_free_virt_device(xhci
, i
);
577 if (xhci
->segment_pool
)
578 dma_pool_destroy(xhci
->segment_pool
);
579 xhci
->segment_pool
= NULL
;
580 xhci_dbg(xhci
, "Freed segment pool\n");
582 if (xhci
->device_pool
)
583 dma_pool_destroy(xhci
->device_pool
);
584 xhci
->device_pool
= NULL
;
585 xhci_dbg(xhci
, "Freed device context pool\n");
587 xhci_writel(xhci
, 0, &xhci
->op_regs
->dcbaa_ptr
[1]);
588 xhci_writel(xhci
, 0, &xhci
->op_regs
->dcbaa_ptr
[0]);
590 pci_free_consistent(pdev
, sizeof(*xhci
->dcbaa
),
591 xhci
->dcbaa
, xhci
->dcbaa
->dma
);
595 xhci
->page_shift
= 0;
598 int xhci_mem_init(struct xhci_hcd
*xhci
, gfp_t flags
)
601 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
602 unsigned int val
, val2
;
603 struct xhci_segment
*seg
;
607 page_size
= xhci_readl(xhci
, &xhci
->op_regs
->page_size
);
608 xhci_dbg(xhci
, "Supported page size register = 0x%x\n", page_size
);
609 for (i
= 0; i
< 16; i
++) {
610 if ((0x1 & page_size
) != 0)
612 page_size
= page_size
>> 1;
615 xhci_dbg(xhci
, "Supported page size of %iK\n", (1 << (i
+12)) / 1024);
617 xhci_warn(xhci
, "WARN: no supported page size\n");
618 /* Use 4K pages, since that's common and the minimum the HC supports */
619 xhci
->page_shift
= 12;
620 xhci
->page_size
= 1 << xhci
->page_shift
;
621 xhci_dbg(xhci
, "HCD page size set to %iK\n", xhci
->page_size
/ 1024);
624 * Program the Number of Device Slots Enabled field in the CONFIG
625 * register with the max value of slots the HC can handle.
627 val
= HCS_MAX_SLOTS(xhci_readl(xhci
, &xhci
->cap_regs
->hcs_params1
));
628 xhci_dbg(xhci
, "// xHC can handle at most %d device slots.\n",
630 val2
= xhci_readl(xhci
, &xhci
->op_regs
->config_reg
);
631 val
|= (val2
& ~HCS_SLOTS_MASK
);
632 xhci_dbg(xhci
, "// Setting Max device slots reg = 0x%x.\n",
634 xhci_writel(xhci
, val
, &xhci
->op_regs
->config_reg
);
637 * Section 5.4.8 - doorbell array must be
638 * "physically contiguous and 64-byte (cache line) aligned".
640 xhci
->dcbaa
= pci_alloc_consistent(to_pci_dev(dev
),
641 sizeof(*xhci
->dcbaa
), &dma
);
644 memset(xhci
->dcbaa
, 0, sizeof *(xhci
->dcbaa
));
645 xhci
->dcbaa
->dma
= dma
;
646 xhci_dbg(xhci
, "// Device context base array address = 0x%x (DMA), 0x%x (virt)\n",
647 xhci
->dcbaa
->dma
, (unsigned int) xhci
->dcbaa
);
648 xhci_writel(xhci
, (u32
) 0, &xhci
->op_regs
->dcbaa_ptr
[1]);
649 xhci_writel(xhci
, dma
, &xhci
->op_regs
->dcbaa_ptr
[0]);
652 * Initialize the ring segment pool. The ring must be a contiguous
653 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
654 * however, the command ring segment needs 64-byte aligned segments,
655 * so we pick the greater alignment need.
657 xhci
->segment_pool
= dma_pool_create("xHCI ring segments", dev
,
658 SEGMENT_SIZE
, 64, xhci
->page_size
);
659 /* See Table 46 and Note on Figure 55 */
660 /* FIXME support 64-byte contexts */
661 xhci
->device_pool
= dma_pool_create("xHCI input/output contexts", dev
,
662 sizeof(struct xhci_device_control
),
663 64, xhci
->page_size
);
664 if (!xhci
->segment_pool
|| !xhci
->device_pool
)
667 /* Set up the command ring to have one segments for now. */
668 xhci
->cmd_ring
= xhci_ring_alloc(xhci
, 1, true, flags
);
671 xhci_dbg(xhci
, "Allocated command ring at 0x%x\n", (unsigned int) xhci
->cmd_ring
);
672 xhci_dbg(xhci
, "First segment DMA is 0x%x\n", (unsigned int) xhci
->cmd_ring
->first_seg
->dma
);
674 /* Set the address in the Command Ring Control register */
675 val
= xhci_readl(xhci
, &xhci
->op_regs
->cmd_ring
[0]);
676 val
= (val
& ~CMD_RING_ADDR_MASK
) |
677 (xhci
->cmd_ring
->first_seg
->dma
& CMD_RING_ADDR_MASK
) |
678 xhci
->cmd_ring
->cycle_state
;
679 xhci_dbg(xhci
, "// Setting command ring address high bits to 0x0\n");
680 xhci_writel(xhci
, (u32
) 0, &xhci
->op_regs
->cmd_ring
[1]);
681 xhci_dbg(xhci
, "// Setting command ring address low bits to 0x%x\n", val
);
682 xhci_writel(xhci
, val
, &xhci
->op_regs
->cmd_ring
[0]);
683 xhci_dbg_cmd_ptrs(xhci
);
685 val
= xhci_readl(xhci
, &xhci
->cap_regs
->db_off
);
687 xhci_dbg(xhci
, "// Doorbell array is located at offset 0x%x"
688 " from cap regs base addr\n", val
);
689 xhci
->dba
= (void *) xhci
->cap_regs
+ val
;
691 xhci_print_run_regs(xhci
);
692 /* Set ir_set to interrupt register set 0 */
693 xhci
->ir_set
= (void *) xhci
->run_regs
->ir_set
;
696 * Event ring setup: Allocate a normal ring, but also setup
697 * the event ring segment table (ERST). Section 4.9.3.
699 xhci_dbg(xhci
, "// Allocating event ring\n");
700 xhci
->event_ring
= xhci_ring_alloc(xhci
, ERST_NUM_SEGS
, false, flags
);
701 if (!xhci
->event_ring
)
704 xhci
->erst
.entries
= pci_alloc_consistent(to_pci_dev(dev
),
705 sizeof(struct xhci_erst_entry
)*ERST_NUM_SEGS
, &dma
);
706 if (!xhci
->erst
.entries
)
708 xhci_dbg(xhci
, "// Allocated event ring segment table at 0x%x\n", dma
);
710 memset(xhci
->erst
.entries
, 0, sizeof(struct xhci_erst_entry
)*ERST_NUM_SEGS
);
711 xhci
->erst
.num_entries
= ERST_NUM_SEGS
;
712 xhci
->erst
.erst_dma_addr
= dma
;
713 xhci_dbg(xhci
, "Set ERST to 0; private num segs = %i, virt addr = 0x%x, dma addr = 0x%x\n",
714 xhci
->erst
.num_entries
,
715 (unsigned int) xhci
->erst
.entries
,
716 xhci
->erst
.erst_dma_addr
);
718 /* set ring base address and size for each segment table entry */
719 for (val
= 0, seg
= xhci
->event_ring
->first_seg
; val
< ERST_NUM_SEGS
; val
++) {
720 struct xhci_erst_entry
*entry
= &xhci
->erst
.entries
[val
];
721 entry
->seg_addr
[1] = 0;
722 entry
->seg_addr
[0] = seg
->dma
;
723 entry
->seg_size
= TRBS_PER_SEGMENT
;
728 /* set ERST count with the number of entries in the segment table */
729 val
= xhci_readl(xhci
, &xhci
->ir_set
->erst_size
);
730 val
&= ERST_SIZE_MASK
;
731 val
|= ERST_NUM_SEGS
;
732 xhci_dbg(xhci
, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
734 xhci_writel(xhci
, val
, &xhci
->ir_set
->erst_size
);
736 xhci_dbg(xhci
, "// Set ERST entries to point to event ring.\n");
737 /* set the segment table base address */
738 xhci_dbg(xhci
, "// Set ERST base address for ir_set 0 = 0x%x\n",
739 xhci
->erst
.erst_dma_addr
);
740 xhci_writel(xhci
, 0, &xhci
->ir_set
->erst_base
[1]);
741 val
= xhci_readl(xhci
, &xhci
->ir_set
->erst_base
[0]);
742 val
&= ERST_PTR_MASK
;
743 val
|= (xhci
->erst
.erst_dma_addr
& ~ERST_PTR_MASK
);
744 xhci_writel(xhci
, val
, &xhci
->ir_set
->erst_base
[0]);
746 /* Set the event ring dequeue address */
747 set_hc_event_deq(xhci
);
748 xhci_dbg(xhci
, "Wrote ERST address to ir_set 0.\n");
749 xhci_print_ir_set(xhci
, xhci
->ir_set
, 0);
752 * XXX: Might need to set the Interrupter Moderation Register to
753 * something other than the default (~1ms minimum between interrupts).
754 * See section 5.5.1.2.
756 init_completion(&xhci
->addr_dev
);
757 for (i
= 0; i
< MAX_HC_SLOTS
; ++i
)
762 xhci_warn(xhci
, "Couldn't initialize memory\n");
763 xhci_mem_cleanup(xhci
);