arch/arm/mach-at91/clock.c

   1 /*
   2  * linux/arch/arm/mach-at91/clock.c
   3  *
   4  * Copyright (C) 2005 David Brownell
   5  * Copyright (C) 2005 Ivan Kokshaysky
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/fs.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/seq_file.h>
  19 #include <linux/list.h>
  20 #include <linux/errno.h>
  21 #include <linux/err.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/delay.h>
  24 #include <linux/clk.h>
  25
  26 #include <asm/io.h>
  27
  28 #include <mach/hardware.h>
  29 #include <mach/at91_pmc.h>
  30 #include <mach/cpu.h>
  31
  32 #include "clock.h"
  33
  34
  35 /*
  36  * There's a lot more which can be done with clocks, including cpufreq
  37  * integration, slow clock mode support (for system suspend), letting
  38  * PLLB be used at other rates (on boards that don't need USB), etc.
  39  */
  40
  41 #define clk_is_primary(x)       ((x)->type & CLK_TYPE_PRIMARY)
  42 #define clk_is_programmable(x)  ((x)->type & CLK_TYPE_PROGRAMMABLE)
  43 #define clk_is_peripheral(x)    ((x)->type & CLK_TYPE_PERIPHERAL)
  44 #define clk_is_sys(x)           ((x)->type & CLK_TYPE_SYSTEM)
  45
  46
  47 static LIST_HEAD(clocks);
  48 static DEFINE_SPINLOCK(clk_lock);
  49
  50 static u32 at91_pllb_usb_init;
  51
  52 /*
  53  * Four primary clock sources:  two crystal oscillators (32K, main), and
  54  * two PLLs.  PLLA usually runs the master clock; and PLLB must run at
  55  * 48 MHz (unless no USB function clocks are needed).  The main clock and
  56  * both PLLs are turned off to run in "slow clock mode" (system suspend).
  57  */
  58 static struct clk clk32k = {
  59         .name           = "clk32k",
  60         .rate_hz        = AT91_SLOW_CLOCK,
  61         .users          = 1,            /* always on */
  62         .id             = 0,
  63         .type           = CLK_TYPE_PRIMARY,
  64 };
  65 static struct clk main_clk = {
  66         .name           = "main",
  67         .pmc_mask       = AT91_PMC_MOSCS,       /* in PMC_SR */
  68         .id             = 1,
  69         .type           = CLK_TYPE_PRIMARY,
  70 };
  71 static struct clk plla = {
  72         .name           = "plla",
  73         .parent         = &main_clk,
  74         .pmc_mask       = AT91_PMC_LOCKA,       /* in PMC_SR */
  75         .id             = 2,
  76         .type           = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
  77 };
  78
  79 static void pllb_mode(struct clk *clk, int is_on)
  80 {
  81         u32     value;
  82
  83         if (is_on) {
  84                 is_on = AT91_PMC_LOCKB;
  85                 value = at91_pllb_usb_init;
  86         } else
  87                 value = 0;
  88
  89         // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
  90         at91_sys_write(AT91_CKGR_PLLBR, value);
  91
  92         do {
  93                 cpu_relax();
  94         } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
  95 }
  96
  97 static struct clk pllb = {
  98         .name           = "pllb",
  99         .parent         = &main_clk,
 100         .pmc_mask       = AT91_PMC_LOCKB,       /* in PMC_SR */
 101         .mode           = pllb_mode,
 102         .id             = 3,
 103         .type           = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
 104 };
 105
 106 static void pmc_sys_mode(struct clk *clk, int is_on)
 107 {
 108         if (is_on)
 109                 at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
 110         else
 111                 at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
 112 }
 113
 114 static void pmc_uckr_mode(struct clk *clk, int is_on)
 115 {
 116         unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
 117
 118         if (is_on) {
 119                 is_on = AT91_PMC_LOCKU;
 120                 at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
 121         } else
 122                 at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
 123
 124         do {
 125                 cpu_relax();
 126         } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
 127 }
 128
 129 /* USB function clocks (PLLB must be 48 MHz) */
 130 static struct clk udpck = {
 131         .name           = "udpck",
 132         .parent         = &pllb,
 133         .mode           = pmc_sys_mode,
 134 };
 135 static struct clk utmi_clk = {
 136         .name           = "utmi_clk",
 137         .parent         = &main_clk,
 138         .pmc_mask       = AT91_PMC_UPLLEN,      /* in CKGR_UCKR */
 139         .mode           = pmc_uckr_mode,
 140         .type           = CLK_TYPE_PLL,
 141 };
 142 static struct clk uhpck = {
 143         .name           = "uhpck",
 144         .parent         = &pllb,
 145         .mode           = pmc_sys_mode,
 146 };
 147
 148
 149 /*
 150  * The master clock is divided from the CPU clock (by 1-4).  It's used for
 151  * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
 152  * (e.g baud rate generation).  It's sourced from one of the primary clocks.
 153  */
 154 static struct clk mck = {
 155         .name           = "mck",
 156         .pmc_mask       = AT91_PMC_MCKRDY,      /* in PMC_SR */
 157 };
 158
 159 static void pmc_periph_mode(struct clk *clk, int is_on)
 160 {
 161         if (is_on)
 162                 at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
 163         else
 164                 at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
 165 }
 166
 167 static struct clk __init *at91_css_to_clk(unsigned long css)
 168 {
 169         switch (css) {
 170                 case AT91_PMC_CSS_SLOW:
 171                         return &clk32k;
 172                 case AT91_PMC_CSS_MAIN:
 173                         return &main_clk;
 174                 case AT91_PMC_CSS_PLLA:
 175                         return &plla;
 176                 case AT91_PMC_CSS_PLLB:
 177                         return &pllb;
 178         }
 179
 180         return NULL;
 181 }
 182
 183 /*
 184  * Associate a particular clock with a function (eg, "uart") and device.
 185  * The drivers can then request the same 'function' with several different
 186  * devices and not care about which clock name to use.
 187  */
 188 void __init at91_clock_associate(const char *id, struct device *dev, const char *func)
 189 {
 190         struct clk *clk = clk_get(NULL, id);
 191
 192         if (!dev || !clk || !IS_ERR(clk_get(dev, func)))
 193                 return;
 194
 195         clk->function = func;
 196         clk->dev = dev;
 197 }
 198
 199 /* clocks cannot be de-registered no refcounting necessary */
 200 struct clk *clk_get(struct device *dev, const char *id)
 201 {
 202         struct clk *clk;
 203
 204         list_for_each_entry(clk, &clocks, node) {
 205                 if (strcmp(id, clk->name) == 0)
 206                         return clk;
 207                 if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0)
 208                         return clk;
 209         }
 210
 211         return ERR_PTR(-ENOENT);
 212 }
 213 EXPORT_SYMBOL(clk_get);
 214
 215 void clk_put(struct clk *clk)
 216 {
 217 }
 218 EXPORT_SYMBOL(clk_put);
 219
 220 static void __clk_enable(struct clk *clk)
 221 {
 222         if (clk->parent)
 223                 __clk_enable(clk->parent);
 224         if (clk->users++ == 0 && clk->mode)
 225                 clk->mode(clk, 1);
 226 }
 227
 228 int clk_enable(struct clk *clk)
 229 {
 230         unsigned long   flags;
 231
 232         spin_lock_irqsave(&clk_lock, flags);
 233         __clk_enable(clk);
 234         spin_unlock_irqrestore(&clk_lock, flags);
 235         return 0;
 236 }
 237 EXPORT_SYMBOL(clk_enable);
 238
 239 static void __clk_disable(struct clk *clk)
 240 {
 241         BUG_ON(clk->users == 0);
 242         if (--clk->users == 0 && clk->mode)
 243                 clk->mode(clk, 0);
 244         if (clk->parent)
 245                 __clk_disable(clk->parent);
 246 }
 247
 248 void clk_disable(struct clk *clk)
 249 {
 250         unsigned long   flags;
 251
 252         spin_lock_irqsave(&clk_lock, flags);
 253         __clk_disable(clk);
 254         spin_unlock_irqrestore(&clk_lock, flags);
 255 }
 256 EXPORT_SYMBOL(clk_disable);
 257
 258 unsigned long clk_get_rate(struct clk *clk)
 259 {
 260         unsigned long   flags;
 261         unsigned long   rate;
 262
 263         spin_lock_irqsave(&clk_lock, flags);
 264         for (;;) {
 265                 rate = clk->rate_hz;
 266                 if (rate || !clk->parent)
 267                         break;
 268                 clk = clk->parent;
 269         }
 270         spin_unlock_irqrestore(&clk_lock, flags);
 271         return rate;
 272 }
 273 EXPORT_SYMBOL(clk_get_rate);
 274
 275 /*------------------------------------------------------------------------*/
 276
 277 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
 278
 279 /*
 280  * For now, only the programmable clocks support reparenting (MCK could
 281  * do this too, with care) or rate changing (the PLLs could do this too,
 282  * ditto MCK but that's more for cpufreq).  Drivers may reparent to get
 283  * a better rate match; we don't.
 284  */
 285
 286 long clk_round_rate(struct clk *clk, unsigned long rate)
 287 {
 288         unsigned long   flags;
 289         unsigned        prescale;
 290         unsigned long   actual;
 291
 292         if (!clk_is_programmable(clk))
 293                 return -EINVAL;
 294         spin_lock_irqsave(&clk_lock, flags);
 295
 296         actual = clk->parent->rate_hz;
 297         for (prescale = 0; prescale < 7; prescale++) {
 298                 if (actual && actual <= rate)
 299                         break;
 300                 actual >>= 1;
 301         }
 302
 303         spin_unlock_irqrestore(&clk_lock, flags);
 304         return (prescale < 7) ? actual : -ENOENT;
 305 }
 306 EXPORT_SYMBOL(clk_round_rate);
 307
 308 int clk_set_rate(struct clk *clk, unsigned long rate)
 309 {
 310         unsigned long   flags;
 311         unsigned        prescale;
 312         unsigned long   actual;
 313
 314         if (!clk_is_programmable(clk))
 315                 return -EINVAL;
 316         if (clk->users)
 317                 return -EBUSY;
 318         spin_lock_irqsave(&clk_lock, flags);
 319
 320         actual = clk->parent->rate_hz;
 321         for (prescale = 0; prescale < 7; prescale++) {
 322                 if (actual && actual <= rate) {
 323                         u32     pckr;
 324
 325                         pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
 326                         pckr &= AT91_PMC_CSS_PLLB;      /* clock selection */
 327                         pckr |= prescale << 2;
 328                         at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
 329                         clk->rate_hz = actual;
 330                         break;
 331                 }
 332                 actual >>= 1;
 333         }
 334
 335         spin_unlock_irqrestore(&clk_lock, flags);
 336         return (prescale < 7) ? actual : -ENOENT;
 337 }
 338 EXPORT_SYMBOL(clk_set_rate);
 339
 340 struct clk *clk_get_parent(struct clk *clk)
 341 {
 342         return clk->parent;
 343 }
 344 EXPORT_SYMBOL(clk_get_parent);
 345
 346 int clk_set_parent(struct clk *clk, struct clk *parent)
 347 {
 348         unsigned long   flags;
 349
 350         if (clk->users)
 351                 return -EBUSY;
 352         if (!clk_is_primary(parent) || !clk_is_programmable(clk))
 353                 return -EINVAL;
 354         spin_lock_irqsave(&clk_lock, flags);
 355
 356         clk->rate_hz = parent->rate_hz;
 357         clk->parent = parent;
 358         at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
 359
 360         spin_unlock_irqrestore(&clk_lock, flags);
 361         return 0;
 362 }
 363 EXPORT_SYMBOL(clk_set_parent);
 364
 365 /* establish PCK0..PCK3 parentage and rate */
 366 static void __init init_programmable_clock(struct clk *clk)
 367 {
 368         struct clk      *parent;
 369         u32             pckr;
 370
 371         pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
 372         parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
 373         clk->parent = parent;
 374         clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
 375 }
 376
 377 #endif  /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
 378
 379 /*------------------------------------------------------------------------*/
 380
 381 #ifdef CONFIG_DEBUG_FS
 382
 383 static int at91_clk_show(struct seq_file *s, void *unused)
 384 {
 385         u32             scsr, pcsr, uckr = 0, sr;
 386         struct clk      *clk;
 387
 388         seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
 389         seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
 390         seq_printf(s, "MOR  = %8x\n", at91_sys_read(AT91_CKGR_MOR));
 391         seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
 392         seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
 393         if (!cpu_is_at91sam9rl())
 394                 seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
 395         if (cpu_is_at91cap9() || cpu_is_at91sam9rl())
 396                 seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
 397         seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
 398         seq_printf(s, "SR   = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
 399
 400         seq_printf(s, "\n");
 401
 402         list_for_each_entry(clk, &clocks, node) {
 403                 char    *state;
 404
 405                 if (clk->mode == pmc_sys_mode)
 406                         state = (scsr & clk->pmc_mask) ? "on" : "off";
 407                 else if (clk->mode == pmc_periph_mode)
 408                         state = (pcsr & clk->pmc_mask) ? "on" : "off";
 409                 else if (clk->mode == pmc_uckr_mode)
 410                         state = (uckr & clk->pmc_mask) ? "on" : "off";
 411                 else if (clk->pmc_mask)
 412                         state = (sr & clk->pmc_mask) ? "on" : "off";
 413                 else if (clk == &clk32k || clk == &main_clk)
 414                         state = "on";
 415                 else
 416                         state = "";
 417
 418                 seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
 419                         clk->name, clk->users, state, clk_get_rate(clk),
 420                         clk->parent ? clk->parent->name : "");
 421         }
 422         return 0;
 423 }
 424
 425 static int at91_clk_open(struct inode *inode, struct file *file)
 426 {
 427         return single_open(file, at91_clk_show, NULL);
 428 }
 429
 430 static const struct file_operations at91_clk_operations = {
 431         .open           = at91_clk_open,
 432         .read           = seq_read,
 433         .llseek         = seq_lseek,
 434         .release        = single_release,
 435 };
 436
 437 static int __init at91_clk_debugfs_init(void)
 438 {
 439         /* /sys/kernel/debug/at91_clk */
 440         (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
 441
 442         return 0;
 443 }
 444 postcore_initcall(at91_clk_debugfs_init);
 445
 446 #endif
 447
 448 /*------------------------------------------------------------------------*/
 449
 450 /* Register a new clock */
 451 int __init clk_register(struct clk *clk)
 452 {
 453         if (clk_is_peripheral(clk)) {
 454                 clk->parent = &mck;
 455                 clk->mode = pmc_periph_mode;
 456                 list_add_tail(&clk->node, &clocks);
 457         }
 458         else if (clk_is_sys(clk)) {
 459                 clk->parent = &mck;
 460                 clk->mode = pmc_sys_mode;
 461
 462                 list_add_tail(&clk->node, &clocks);
 463         }
 464 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
 465         else if (clk_is_programmable(clk)) {
 466                 clk->mode = pmc_sys_mode;
 467                 init_programmable_clock(clk);
 468                 list_add_tail(&clk->node, &clocks);
 469         }
 470 #endif
 471
 472         return 0;
 473 }
 474
 475
 476 /*------------------------------------------------------------------------*/
 477
 478 static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
 479 {
 480         unsigned mul, div;
 481
 482         div = reg & 0xff;
 483         mul = (reg >> 16) & 0x7ff;
 484         if (div && mul) {
 485                 freq /= div;
 486                 freq *= mul + 1;
 487         } else
 488                 freq = 0;
 489
 490         return freq;
 491 }
 492
 493 static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
 494 {
 495         if (pll == &pllb && (reg & AT91_PMC_USB96M))
 496                 return freq / 2;
 497         else
 498                 return freq;
 499 }
 500
 501 static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
 502 {
 503         unsigned i, div = 0, mul = 0, diff = 1 << 30;
 504         unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
 505
 506         /* PLL output max 240 MHz (or 180 MHz per errata) */
 507         if (out_freq > 240000000)
 508                 goto fail;
 509
 510         for (i = 1; i < 256; i++) {
 511                 int diff1;
 512                 unsigned input, mul1;
 513
 514                 /*
 515                  * PLL input between 1MHz and 32MHz per spec, but lower
 516                  * frequences seem necessary in some cases so allow 100K.
 517                  * Warning: some newer products need 2MHz min.
 518                  */
 519                 input = main_freq / i;
 520                 if (cpu_is_at91sam9g20() && input < 2000000)
 521                         continue;
 522                 if (input < 100000)
 523                         continue;
 524                 if (input > 32000000)
 525                         continue;
 526
 527                 mul1 = out_freq / input;
 528                 if (cpu_is_at91sam9g20() && mul > 63)
 529                         continue;
 530                 if (mul1 > 2048)
 531                         continue;
 532                 if (mul1 < 2)
 533                         goto fail;
 534
 535                 diff1 = out_freq - input * mul1;
 536                 if (diff1 < 0)
 537                         diff1 = -diff1;
 538                 if (diff > diff1) {
 539                         diff = diff1;
 540                         div = i;
 541                         mul = mul1;
 542                         if (diff == 0)
 543                                 break;
 544                 }
 545         }
 546         if (i == 256 && diff > (out_freq >> 5))
 547                 goto fail;
 548         return ret | ((mul - 1) << 16) | div;
 549 fail:
 550         return 0;
 551 }
 552
 553 static struct clk *const standard_pmc_clocks[] __initdata = {
 554         /* four primary clocks */
 555         &clk32k,
 556         &main_clk,
 557         &plla,
 558         &pllb,
 559
 560         /* PLLB children (USB) */
 561         &udpck,
 562         &uhpck,
 563
 564         /* MCK */
 565         &mck
 566 };
 567
 568 int __init at91_clock_init(unsigned long main_clock)
 569 {
 570         unsigned tmp, freq, mckr;
 571         int i;
 572
 573         /*
 574          * When the bootloader initialized the main oscillator correctly,
 575          * there's no problem using the cycle counter.  But if it didn't,
 576          * or when using oscillator bypass mode, we must be told the speed
 577          * of the main clock.
 578          */
 579         if (!main_clock) {
 580                 do {
 581                         tmp = at91_sys_read(AT91_CKGR_MCFR);
 582                 } while (!(tmp & AT91_PMC_MAINRDY));
 583                 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
 584         }
 585         main_clk.rate_hz = main_clock;
 586
 587         /* report if PLLA is more than mildly overclocked */
 588         plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
 589         if ((!cpu_is_at91sam9g20() && plla.rate_hz > 209000000)
 590            || (cpu_is_at91sam9g20() && plla.rate_hz > 800000000))
 591                 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
 592
 593         /*
 594          * USB clock init:  choose 48 MHz PLLB value,
 595          * disable 48MHz clock during usb peripheral suspend.
 596          *
 597          * REVISIT:  assumes MCK doesn't derive from PLLB!
 598          */
 599         at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
 600         pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
 601         if (cpu_is_at91rm9200()) {
 602                 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
 603                 udpck.pmc_mask = AT91RM9200_PMC_UDP;
 604                 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
 605         } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) {
 606                 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
 607                 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
 608         } else if (cpu_is_at91cap9()) {
 609                 uhpck.pmc_mask = AT91CAP9_PMC_UHP;
 610         }
 611         at91_sys_write(AT91_CKGR_PLLBR, 0);
 612
 613         udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
 614         uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
 615
 616         /*
 617          * USB HS clock init
 618          */
 619         if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) {
 620                 /*
 621                  * multiplier is hard-wired to 40
 622                  * (obtain the USB High Speed 480 MHz when input is 12 MHz)
 623                  */
 624                 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
 625         }
 626
 627         /*
 628          * MCK and CPU derive from one of those primary clocks.
 629          * For now, assume this parentage won't change.
 630          */
 631         mckr = at91_sys_read(AT91_PMC_MCKR);
 632         mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
 633         freq = mck.parent->rate_hz;
 634         freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));                           /* prescale */
 635         if (cpu_is_at91rm9200())
 636                 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));       /* mdiv */
 637         else if (cpu_is_at91sam9g20()) {
 638                 mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
 639                         freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;    /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
 640                 if (mckr & AT91_PMC_PDIV)
 641                         freq /= 2;              /* processor clock division */
 642         } else
 643                 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */
 644
 645         /* Register the PMC's standard clocks */
 646         for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
 647                 list_add_tail(&standard_pmc_clocks[i]->node, &clocks);
 648
 649         if (cpu_is_at91cap9() || cpu_is_at91sam9rl())
 650                 list_add_tail(&utmi_clk.node, &clocks);
 651
 652         /* MCK and CPU clock are "always on" */
 653         clk_enable(&mck);
 654
 655         printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
 656                 freq / 1000000, (unsigned) mck.rate_hz / 1000000,
 657                 (unsigned) main_clock / 1000000,
 658                 ((unsigned) main_clock % 1000000) / 1000);
 659
 660         return 0;
 661 }
 662
 663 /*
 664  * Several unused clocks may be active.  Turn them off.
 665  */
 666 static int __init at91_clock_reset(void)
 667 {
 668         unsigned long pcdr = 0;
 669         unsigned long scdr = 0;
 670         struct clk *clk;
 671
 672         list_for_each_entry(clk, &clocks, node) {
 673                 if (clk->users > 0)
 674                         continue;
 675
 676                 if (clk->mode == pmc_periph_mode)
 677                         pcdr |= clk->pmc_mask;
 678
 679                 if (clk->mode == pmc_sys_mode)
 680                         scdr |= clk->pmc_mask;
 681
 682                 pr_debug("Clocks: disable unused %s\n", clk->name);
 683         }
 684
 685         at91_sys_write(AT91_PMC_PCDR, pcdr);
 686         at91_sys_write(AT91_PMC_SCDR, scdr);
 687
 688         return 0;
 689 }
 690 late_initcall(at91_clock_reset);