arch/powerpc/boot/cuboot-pq2.c

   1 /*
   2  * Old U-boot compatibility for PowerQUICC II
   3  * (a.k.a. 82xx with CPM, not the 8240 family of chips)
   4  *
   5  * Author: Scott Wood <scottwood@freescale.com>
   6  *
   7  * Copyright (c) 2007 Freescale Semiconductor, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License version 2 as published
  11  * by the Free Software Foundation.
  12  */
  13
  14 #include "ops.h"
  15 #include "stdio.h"
  16 #include "cuboot.h"
  17 #include "io.h"
  18 #include "fsl-soc.h"
  19
  20 #define TARGET_CPM2
  21 #define TARGET_HAS_ETH1
  22 #include "ppcboot.h"
  23
  24 static bd_t bd;
  25
  26 struct cs_range {
  27         u32 csnum;
  28         u32 base; /* must be zero */
  29         u32 addr;
  30         u32 size;
  31 };
  32
  33 struct pci_range {
  34         u32 flags;
  35         u32 pci_addr[2];
  36         u32 phys_addr;
  37         u32 size[2];
  38 };
  39
  40 struct cs_range cs_ranges_buf[MAX_PROP_LEN / sizeof(struct cs_range)];
  41 struct pci_range pci_ranges_buf[MAX_PROP_LEN / sizeof(struct pci_range)];
  42
  43 /* Different versions of u-boot put the BCSR in different places, and
  44  * some don't set up the PCI PIC at all, so we assume the device tree is
  45  * sane and update the BRx registers appropriately.
  46  *
  47  * For any node defined as compatible with fsl,pq2-chipselect,
  48  * #address/#size must be 2/1 for chipselect bus, 1/1 for parent bus,
  49  * and ranges must be for whole chip selects.
  50  */
  51 static void update_cs_ranges(void)
  52 {
  53         u32 ctrl_ph;
  54         void *ctrl_node, *bus_node, *parent_node;
  55         u32 *ctrl_addr;
  56         unsigned long ctrl_size;
  57         u32 naddr, nsize;
  58         int len;
  59         int i;
  60
  61         bus_node = finddevice("/chipselect");
  62         if (!bus_node || !dt_is_compatible(bus_node, "fsl,pq2-chipselect"))
  63                 return;
  64
  65         dt_get_reg_format(bus_node, &naddr, &nsize);
  66         if (naddr != 2 || nsize != 1)
  67                 goto err;
  68
  69         parent_node = get_parent(bus_node);
  70         if (!parent_node)
  71                 goto err;
  72
  73         dt_get_reg_format(parent_node, &naddr, &nsize);
  74         if (naddr != 1 || nsize != 1)
  75                 goto err;
  76
  77         len = getprop(bus_node, "fsl,ctrl", &ctrl_ph, 4);
  78         if (len != 4)
  79                 goto err;
  80
  81         ctrl_node = find_node_by_prop_value(NULL, "linux,phandle",
  82                                             (char *)&ctrl_ph, 4);
  83         if (!ctrl_node)
  84                 goto err;
  85
  86         if (!dt_is_compatible(ctrl_node, "fsl,pq2-chipselect-ctrl"))
  87                 goto err;
  88
  89         if (!dt_xlate_reg(ctrl_node, 0, (unsigned long *)&ctrl_addr,
  90                           &ctrl_size))
  91                 goto err;
  92
  93         len = getprop(bus_node, "ranges", cs_ranges_buf, sizeof(cs_ranges_buf));
  94
  95         for (i = 0; i < len / sizeof(struct cs_range); i++) {
  96                 u32 base, option;
  97                 int cs = cs_ranges_buf[i].csnum;
  98                 if (cs >= ctrl_size / 8)
  99                         goto err;
 100
 101                 if (cs_ranges_buf[i].base != 0)
 102                         goto err;
 103
 104                 base = in_be32(&ctrl_addr[cs * 2]);
 105
 106                 /* If CS is already valid, use the existing flags.
 107                  * Otherwise, guess a sane default.
 108                  */
 109                 if (base & 1) {
 110                         base &= 0x7fff;
 111                         option = in_be32(&ctrl_addr[cs * 2 + 1]) & 0x7fff;
 112                 } else {
 113                         base = 0x1801;
 114                         option = 0x10;
 115                 }
 116
 117                 out_be32(&ctrl_addr[cs * 2], 0);
 118                 out_be32(&ctrl_addr[cs * 2 + 1],
 119                          option | ~(cs_ranges_buf[i].size - 1));
 120                 out_be32(&ctrl_addr[cs * 2], base | cs_ranges_buf[i].addr);
 121         }
 122
 123         return;
 124
 125 err:
 126         printf("Bad /chipselect or fsl,pq2-chipselect-ctrl node\r\n");
 127 }
 128
 129 /* Older u-boots don't set PCI up properly.  Update the hardware to match
 130  * the device tree.  The prefetch mem region and non-prefetch mem region
 131  * must be contiguous in the host bus.  As required by the PCI binding,
 132  * PCI #addr/#size must be 3/2.  The parent bus must be 1/1.  Only
 133  * 32-bit PCI is supported.  All three region types (prefetchable mem,
 134  * non-prefetchable mem, and I/O) must be present.
 135  */
 136 static void fixup_pci(void)
 137 {
 138         struct pci_range *mem = NULL, *mmio = NULL,
 139                          *io = NULL, *mem_base = NULL;
 140         u32 *pci_regs[3];
 141         u8 *soc_regs;
 142         int i, len;
 143         void *node, *parent_node;
 144         u32 naddr, nsize, mem_log2;
 145
 146         node = finddevice("/pci");
 147         if (!node || !dt_is_compatible(node, "fsl,pq2-pci"))
 148                 return;
 149
 150         for (i = 0; i < 3; i++)
 151                 if (!dt_xlate_reg(node, i,
 152                                   (unsigned long *)&pci_regs[i], NULL))
 153                         goto err;
 154
 155         soc_regs = (u8 *)fsl_get_immr();
 156         if (!soc_regs)
 157                 goto err;
 158
 159         dt_get_reg_format(node, &naddr, &nsize);
 160         if (naddr != 3 || nsize != 2)
 161                 goto err;
 162
 163         parent_node = get_parent(node);
 164         if (!parent_node)
 165                 goto err;
 166
 167         dt_get_reg_format(parent_node, &naddr, &nsize);
 168         if (naddr != 1 || nsize != 1)
 169                 goto err;
 170
 171         len = getprop(node, "ranges", pci_ranges_buf,
 172                       sizeof(pci_ranges_buf));
 173
 174         for (i = 0; i < len / sizeof(struct pci_range); i++) {
 175                 u32 flags = pci_ranges_buf[i].flags & 0x43000000;
 176
 177                 if (flags == 0x42000000)
 178                         mem = &pci_ranges_buf[i];
 179                 else if (flags == 0x02000000)
 180                         mmio = &pci_ranges_buf[i];
 181                 else if (flags == 0x01000000)
 182                         io = &pci_ranges_buf[i];
 183         }
 184
 185         if (!mem || !mmio || !io)
 186                 goto err;
 187
 188         if (mem->phys_addr + mem->size[1] == mmio->phys_addr)
 189                 mem_base = mem;
 190         else if (mmio->phys_addr + mmio->size[1] == mem->phys_addr)
 191                 mem_base = mmio;
 192         else
 193                 goto err;
 194
 195         out_be32(&pci_regs[1][0], mem_base->phys_addr | 1);
 196         out_be32(&pci_regs[2][0], ~(mem->size[1] + mmio->size[1] - 1));
 197
 198         out_be32(&pci_regs[1][1], io->phys_addr | 1);
 199         out_be32(&pci_regs[2][1], ~(io->size[1] - 1));
 200
 201         out_le32(&pci_regs[0][0], mem->pci_addr[1] >> 12);
 202         out_le32(&pci_regs[0][2], mem->phys_addr >> 12);
 203         out_le32(&pci_regs[0][4], (~(mem->size[1] - 1) >> 12) | 0xa0000000);
 204
 205         out_le32(&pci_regs[0][6], mmio->pci_addr[1] >> 12);
 206         out_le32(&pci_regs[0][8], mmio->phys_addr >> 12);
 207         out_le32(&pci_regs[0][10], (~(mmio->size[1] - 1) >> 12) | 0x80000000);
 208
 209         out_le32(&pci_regs[0][12], io->pci_addr[1] >> 12);
 210         out_le32(&pci_regs[0][14], io->phys_addr >> 12);
 211         out_le32(&pci_regs[0][16], (~(io->size[1] - 1) >> 12) | 0xc0000000);
 212
 213         /* Inbound translation */
 214         out_le32(&pci_regs[0][58], 0);
 215         out_le32(&pci_regs[0][60], 0);
 216
 217         mem_log2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1);
 218         out_le32(&pci_regs[0][62], 0xa0000000 | ~((1 << (mem_log2 - 12)) - 1));
 219
 220         /* If PCI is disabled, drive RST high to enable. */
 221         if (!(in_le32(&pci_regs[0][32]) & 1)) {
 222                  /* Tpvrh (Power valid to RST# high) 100 ms */
 223                 udelay(100000);
 224
 225                 out_le32(&pci_regs[0][32], 1);
 226
 227                 /* Trhfa (RST# high to first cfg access) 2^25 clocks */
 228                 udelay(1020000);
 229         }
 230
 231         /* Enable bus master and memory access */
 232         out_le32(&pci_regs[0][64], 0x80000004);
 233         out_le32(&pci_regs[0][65], in_le32(&pci_regs[0][65]) | 6);
 234
 235         /* Park the bus on PCI, and elevate PCI's arbitration priority,
 236          * as required by section 9.6 of the user's manual.
 237          */
 238         out_8(&soc_regs[0x10028], 3);
 239         out_be32((u32 *)&soc_regs[0x1002c], 0x01236745);
 240
 241         return;
 242
 243 err:
 244         printf("Bad PCI node\r\n");
 245 }
 246
 247 static void pq2_platform_fixups(void)
 248 {
 249         void *node;
 250
 251         dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
 252         dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
 253         dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
 254
 255         node = finddevice("/soc/cpm");
 256         if (node)
 257                 setprop(node, "clock-frequency", &bd.bi_cpmfreq, 4);
 258
 259         node = finddevice("/soc/cpm/brg");
 260         if (node)
 261                 setprop(node, "clock-frequency",  &bd.bi_brgfreq, 4);
 262
 263         update_cs_ranges();
 264         fixup_pci();
 265 }
 266
 267 void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 268                    unsigned long r6, unsigned long r7)
 269 {
 270         CUBOOT_INIT();
 271         ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
 272         serial_console_init();
 273         platform_ops.fixups = pq2_platform_fixups;
 274 }