arch/powerpc/platforms/pseries/xics.c

   1 /*
   2  * arch/powerpc/platforms/pseries/xics.c
   3  *
   4  * Copyright 2000 IBM Corporation.
   5  *
   6  *  This program is free software; you can redistribute it and/or
   7  *  modify it under the terms of the GNU General Public License
   8  *  as published by the Free Software Foundation; either version
   9  *  2 of the License, or (at your option) any later version.
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/types.h>
  15 #include <linux/threads.h>
  16 #include <linux/kernel.h>
  17 #include <linux/irq.h>
  18 #include <linux/smp.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/signal.h>
  21 #include <linux/init.h>
  22 #include <linux/gfp.h>
  23 #include <linux/radix-tree.h>
  24 #include <linux/cpu.h>
  25
  26 #include <asm/firmware.h>
  27 #include <asm/prom.h>
  28 #include <asm/io.h>
  29 #include <asm/pgtable.h>
  30 #include <asm/smp.h>
  31 #include <asm/rtas.h>
  32 #include <asm/hvcall.h>
  33 #include <asm/machdep.h>
  34 #include <asm/i8259.h>
  35
  36 #include "xics.h"
  37 #include "plpar_wrappers.h"
  38
  39 #define XICS_IPI                2
  40 #define XICS_IRQ_SPURIOUS       0
  41
  42 /* Want a priority other than 0.  Various HW issues require this. */
  43 #define DEFAULT_PRIORITY        5
  44
  45 /*
  46  * Mark IPIs as higher priority so we can take them inside interrupts that
  47  * arent marked IRQF_DISABLED
  48  */
  49 #define IPI_PRIORITY            4
  50
  51 struct xics_ipl {
  52         union {
  53                 u32 word;
  54                 u8 bytes[4];
  55         } xirr_poll;
  56         union {
  57                 u32 word;
  58                 u8 bytes[4];
  59         } xirr;
  60         u32 dummy;
  61         union {
  62                 u32 word;
  63                 u8 bytes[4];
  64         } qirr;
  65 };
  66
  67 static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS];
  68
  69 static unsigned int default_server = 0xFF;
  70 static unsigned int default_distrib_server = 0;
  71 static unsigned int interrupt_server_size = 8;
  72
  73 static struct irq_host *xics_host;
  74
  75 /*
  76  * XICS only has a single IPI, so encode the messages per CPU
  77  */
  78 struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned;
  79
  80 /* RTAS service tokens */
  81 static int ibm_get_xive;
  82 static int ibm_set_xive;
  83 static int ibm_int_on;
  84 static int ibm_int_off;
  85
  86
  87 /* Direct HW low level accessors */
  88
  89
  90 static inline unsigned int direct_xirr_info_get(int n_cpu)
  91 {
  92         return in_be32(&xics_per_cpu[n_cpu]->xirr.word);
  93 }
  94
  95 static inline void direct_xirr_info_set(int n_cpu, int value)
  96 {
  97         out_be32(&xics_per_cpu[n_cpu]->xirr.word, value);
  98 }
  99
 100 static inline void direct_cppr_info(int n_cpu, u8 value)
 101 {
 102         out_8(&xics_per_cpu[n_cpu]->xirr.bytes[0], value);
 103 }
 104
 105 static inline void direct_qirr_info(int n_cpu, u8 value)
 106 {
 107         out_8(&xics_per_cpu[n_cpu]->qirr.bytes[0], value);
 108 }
 109
 110
 111 /* LPAR low level accessors */
 112
 113
 114 static inline unsigned int lpar_xirr_info_get(int n_cpu)
 115 {
 116         unsigned long lpar_rc;
 117         unsigned long return_value;
 118
 119         lpar_rc = plpar_xirr(&return_value);
 120         if (lpar_rc != H_SUCCESS)
 121                 panic(" bad return code xirr - rc = %lx \n", lpar_rc);
 122         return (unsigned int)return_value;
 123 }
 124
 125 static inline void lpar_xirr_info_set(int n_cpu, int value)
 126 {
 127         unsigned long lpar_rc;
 128         unsigned long val64 = value & 0xffffffff;
 129
 130         lpar_rc = plpar_eoi(val64);
 131         if (lpar_rc != H_SUCCESS)
 132                 panic("bad return code EOI - rc = %ld, value=%lx\n", lpar_rc,
 133                       val64);
 134 }
 135
 136 static inline void lpar_cppr_info(int n_cpu, u8 value)
 137 {
 138         unsigned long lpar_rc;
 139
 140         lpar_rc = plpar_cppr(value);
 141         if (lpar_rc != H_SUCCESS)
 142                 panic("bad return code cppr - rc = %lx\n", lpar_rc);
 143 }
 144
 145 static inline void lpar_qirr_info(int n_cpu , u8 value)
 146 {
 147         unsigned long lpar_rc;
 148
 149         lpar_rc = plpar_ipi(get_hard_smp_processor_id(n_cpu), value);
 150         if (lpar_rc != H_SUCCESS)
 151                 panic("bad return code qirr - rc = %lx\n", lpar_rc);
 152 }
 153
 154
 155 /* High level handlers and init code */
 156
 157
 158 #ifdef CONFIG_SMP
 159 static int get_irq_server(unsigned int virq)
 160 {
 161         unsigned int server;
 162         /* For the moment only implement delivery to all cpus or one cpu */
 163         cpumask_t cpumask = irq_desc[virq].affinity;
 164         cpumask_t tmp = CPU_MASK_NONE;
 165
 166         if (!distribute_irqs)
 167                 return default_server;
 168
 169         if (cpus_equal(cpumask, CPU_MASK_ALL)) {
 170                 server = default_distrib_server;
 171         } else {
 172                 cpus_and(tmp, cpu_online_map, cpumask);
 173
 174                 if (cpus_empty(tmp))
 175                         server = default_distrib_server;
 176                 else
 177                         server = get_hard_smp_processor_id(first_cpu(tmp));
 178         }
 179
 180         return server;
 181
 182 }
 183 #else
 184 static int get_irq_server(unsigned int virq)
 185 {
 186         return default_server;
 187 }
 188 #endif
 189
 190
 191 static void xics_unmask_irq(unsigned int virq)
 192 {
 193         unsigned int irq;
 194         int call_status;
 195         unsigned int server;
 196
 197         pr_debug("xics: unmask virq %d\n", virq);
 198
 199         irq = (unsigned int)irq_map[virq].hwirq;
 200         pr_debug(" -> map to hwirq 0x%x\n", irq);
 201         if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
 202                 return;
 203
 204         server = get_irq_server(virq);
 205
 206         call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server,
 207                                 DEFAULT_PRIORITY);
 208         if (call_status != 0) {
 209                 printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_set_xive "
 210                        "returned %d\n", irq, call_status);
 211                 printk("set_xive %x, server %x\n", ibm_set_xive, server);
 212                 return;
 213         }
 214
 215         /* Now unmask the interrupt (often a no-op) */
 216         call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq);
 217         if (call_status != 0) {
 218                 printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_int_on "
 219                        "returned %d\n", irq, call_status);
 220                 return;
 221         }
 222 }
 223
 224 static void xics_mask_real_irq(unsigned int irq)
 225 {
 226         int call_status;
 227
 228         if (irq == XICS_IPI)
 229                 return;
 230
 231         call_status = rtas_call(ibm_int_off, 1, 1, NULL, irq);
 232         if (call_status != 0) {
 233                 printk(KERN_ERR "xics_disable_real_irq: irq=%u: "
 234                        "ibm_int_off returned %d\n", irq, call_status);
 235                 return;
 236         }
 237
 238         /* Have to set XIVE to 0xff to be able to remove a slot */
 239         call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq,
 240                                 default_server, 0xff);
 241         if (call_status != 0) {
 242                 printk(KERN_ERR "xics_disable_irq: irq=%u: ibm_set_xive(0xff)"
 243                        " returned %d\n", irq, call_status);
 244                 return;
 245         }
 246 }
 247
 248 static void xics_mask_irq(unsigned int virq)
 249 {
 250         unsigned int irq;
 251
 252         pr_debug("xics: mask virq %d\n", virq);
 253
 254         irq = (unsigned int)irq_map[virq].hwirq;
 255         if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
 256                 return;
 257         xics_mask_real_irq(irq);
 258 }
 259
 260 static unsigned int xics_startup(unsigned int virq)
 261 {
 262         unsigned int irq;
 263
 264         /* force a reverse mapping of the interrupt so it gets in the cache */
 265         irq = (unsigned int)irq_map[virq].hwirq;
 266         irq_radix_revmap(xics_host, irq);
 267
 268         /* unmask it */
 269         xics_unmask_irq(virq);
 270         return 0;
 271 }
 272
 273 static void xics_eoi_direct(unsigned int virq)
 274 {
 275         int cpu = smp_processor_id();
 276         unsigned int irq = (unsigned int)irq_map[virq].hwirq;
 277
 278         iosync();
 279         direct_xirr_info_set(cpu, (0xff << 24) | irq);
 280 }
 281
 282
 283 static void xics_eoi_lpar(unsigned int virq)
 284 {
 285         int cpu = smp_processor_id();
 286         unsigned int irq = (unsigned int)irq_map[virq].hwirq;
 287
 288         iosync();
 289         lpar_xirr_info_set(cpu, (0xff << 24) | irq);
 290 }
 291
 292 static inline unsigned int xics_remap_irq(unsigned int vec)
 293 {
 294         unsigned int irq;
 295
 296         vec &= 0x00ffffff;
 297
 298         if (vec == XICS_IRQ_SPURIOUS)
 299                 return NO_IRQ;
 300         irq = irq_radix_revmap(xics_host, vec);
 301         if (likely(irq != NO_IRQ))
 302                 return irq;
 303
 304         printk(KERN_ERR "Interrupt %u (real) is invalid,"
 305                " disabling it.\n", vec);
 306         xics_mask_real_irq(vec);
 307         return NO_IRQ;
 308 }
 309
 310 static unsigned int xics_get_irq_direct(void)
 311 {
 312         unsigned int cpu = smp_processor_id();
 313
 314         return xics_remap_irq(direct_xirr_info_get(cpu));
 315 }
 316
 317 static unsigned int xics_get_irq_lpar(void)
 318 {
 319         unsigned int cpu = smp_processor_id();
 320
 321         return xics_remap_irq(lpar_xirr_info_get(cpu));
 322 }
 323
 324 #ifdef CONFIG_SMP
 325
 326 static irqreturn_t xics_ipi_dispatch(int cpu)
 327 {
 328         WARN_ON(cpu_is_offline(cpu));
 329
 330         while (xics_ipi_message[cpu].value) {
 331                 if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION,
 332                                        &xics_ipi_message[cpu].value)) {
 333                         mb();
 334                         smp_message_recv(PPC_MSG_CALL_FUNCTION);
 335                 }
 336                 if (test_and_clear_bit(PPC_MSG_RESCHEDULE,
 337                                        &xics_ipi_message[cpu].value)) {
 338                         mb();
 339                         smp_message_recv(PPC_MSG_RESCHEDULE);
 340                 }
 341 #if 0
 342                 if (test_and_clear_bit(PPC_MSG_MIGRATE_TASK,
 343                                        &xics_ipi_message[cpu].value)) {
 344                         mb();
 345                         smp_message_recv(PPC_MSG_MIGRATE_TASK);
 346                 }
 347 #endif
 348 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
 349                 if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK,
 350                                        &xics_ipi_message[cpu].value)) {
 351                         mb();
 352                         smp_message_recv(PPC_MSG_DEBUGGER_BREAK);
 353                 }
 354 #endif
 355         }
 356         return IRQ_HANDLED;
 357 }
 358
 359 static irqreturn_t xics_ipi_action_direct(int irq, void *dev_id)
 360 {
 361         int cpu = smp_processor_id();
 362
 363         direct_qirr_info(cpu, 0xff);
 364
 365         return xics_ipi_dispatch(cpu);
 366 }
 367
 368 static irqreturn_t xics_ipi_action_lpar(int irq, void *dev_id)
 369 {
 370         int cpu = smp_processor_id();
 371
 372         lpar_qirr_info(cpu, 0xff);
 373
 374         return xics_ipi_dispatch(cpu);
 375 }
 376
 377 void xics_cause_IPI(int cpu)
 378 {
 379         if (firmware_has_feature(FW_FEATURE_LPAR))
 380                 lpar_qirr_info(cpu, IPI_PRIORITY);
 381         else
 382                 direct_qirr_info(cpu, IPI_PRIORITY);
 383 }
 384
 385 #endif /* CONFIG_SMP */
 386
 387 static void xics_set_cpu_priority(int cpu, unsigned char cppr)
 388 {
 389         if (firmware_has_feature(FW_FEATURE_LPAR))
 390                 lpar_cppr_info(cpu, cppr);
 391         else
 392                 direct_cppr_info(cpu, cppr);
 393         iosync();
 394 }
 395
 396 static void xics_set_affinity(unsigned int virq, cpumask_t cpumask)
 397 {
 398         unsigned int irq;
 399         int status;
 400         int xics_status[2];
 401         unsigned long newmask;
 402         cpumask_t tmp = CPU_MASK_NONE;
 403
 404         irq = (unsigned int)irq_map[virq].hwirq;
 405         if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
 406                 return;
 407
 408         status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
 409
 410         if (status) {
 411                 printk(KERN_ERR "xics_set_affinity: irq=%u ibm,get-xive "
 412                        "returns %d\n", irq, status);
 413                 return;
 414         }
 415
 416         /* For the moment only implement delivery to all cpus or one cpu */
 417         if (cpus_equal(cpumask, CPU_MASK_ALL)) {
 418                 newmask = default_distrib_server;
 419         } else {
 420                 cpus_and(tmp, cpu_online_map, cpumask);
 421                 if (cpus_empty(tmp))
 422                         return;
 423                 newmask = get_hard_smp_processor_id(first_cpu(tmp));
 424         }
 425
 426         status = rtas_call(ibm_set_xive, 3, 1, NULL,
 427                                 irq, newmask, xics_status[1]);
 428
 429         if (status) {
 430                 printk(KERN_ERR "xics_set_affinity: irq=%u ibm,set-xive "
 431                        "returns %d\n", irq, status);
 432                 return;
 433         }
 434 }
 435
 436 void xics_setup_cpu(void)
 437 {
 438         int cpu = smp_processor_id();
 439
 440         xics_set_cpu_priority(cpu, 0xff);
 441
 442         /*
 443          * Put the calling processor into the GIQ.  This is really only
 444          * necessary from a secondary thread as the OF start-cpu interface
 445          * performs this function for us on primary threads.
 446          *
 447          * XXX: undo of teardown on kexec needs this too, as may hotplug
 448          */
 449         rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
 450                 (1UL << interrupt_server_size) - 1 - default_distrib_server, 1);
 451 }
 452
 453
 454 static struct irq_chip xics_pic_direct = {
 455         .typename = " XICS     ",
 456         .startup = xics_startup,
 457         .mask = xics_mask_irq,
 458         .unmask = xics_unmask_irq,
 459         .eoi = xics_eoi_direct,
 460         .set_affinity = xics_set_affinity
 461 };
 462
 463
 464 static struct irq_chip xics_pic_lpar = {
 465         .typename = " XICS     ",
 466         .startup = xics_startup,
 467         .mask = xics_mask_irq,
 468         .unmask = xics_unmask_irq,
 469         .eoi = xics_eoi_lpar,
 470         .set_affinity = xics_set_affinity
 471 };
 472
 473
 474 static int xics_host_match(struct irq_host *h, struct device_node *node)
 475 {
 476         /* IBM machines have interrupt parents of various funky types for things
 477          * like vdevices, events, etc... The trick we use here is to match
 478          * everything here except the legacy 8259 which is compatible "chrp,iic"
 479          */
 480         return !device_is_compatible(node, "chrp,iic");
 481 }
 482
 483 static int xics_host_map_direct(struct irq_host *h, unsigned int virq,
 484                                 irq_hw_number_t hw)
 485 {
 486         pr_debug("xics: map_direct virq %d, hwirq 0x%lx\n", virq, hw);
 487
 488         get_irq_desc(virq)->status |= IRQ_LEVEL;
 489         set_irq_chip_and_handler(virq, &xics_pic_direct, handle_fasteoi_irq);
 490         return 0;
 491 }
 492
 493 static int xics_host_map_lpar(struct irq_host *h, unsigned int virq,
 494                               irq_hw_number_t hw)
 495 {
 496         pr_debug("xics: map_direct virq %d, hwirq 0x%lx\n", virq, hw);
 497
 498         get_irq_desc(virq)->status |= IRQ_LEVEL;
 499         set_irq_chip_and_handler(virq, &xics_pic_lpar, handle_fasteoi_irq);
 500         return 0;
 501 }
 502
 503 static int xics_host_xlate(struct irq_host *h, struct device_node *ct,
 504                            u32 *intspec, unsigned int intsize,
 505                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 506
 507 {
 508         /* Current xics implementation translates everything
 509          * to level. It is not technically right for MSIs but this
 510          * is irrelevant at this point. We might get smarter in the future
 511          */
 512         *out_hwirq = intspec[0];
 513         *out_flags = IRQ_TYPE_LEVEL_LOW;
 514
 515         return 0;
 516 }
 517
 518 static struct irq_host_ops xics_host_direct_ops = {
 519         .match = xics_host_match,
 520         .map = xics_host_map_direct,
 521         .xlate = xics_host_xlate,
 522 };
 523
 524 static struct irq_host_ops xics_host_lpar_ops = {
 525         .match = xics_host_match,
 526         .map = xics_host_map_lpar,
 527         .xlate = xics_host_xlate,
 528 };
 529
 530 static void __init xics_init_host(void)
 531 {
 532         struct irq_host_ops *ops;
 533
 534         if (firmware_has_feature(FW_FEATURE_LPAR))
 535                 ops = &xics_host_lpar_ops;
 536         else
 537                 ops = &xics_host_direct_ops;
 538         xics_host = irq_alloc_host(IRQ_HOST_MAP_TREE, 0, ops,
 539                                    XICS_IRQ_SPURIOUS);
 540         BUG_ON(xics_host == NULL);
 541         irq_set_default_host(xics_host);
 542 }
 543
 544 static void __init xics_map_one_cpu(int hw_id, unsigned long addr,
 545                                      unsigned long size)
 546 {
 547 #ifdef CONFIG_SMP
 548         int i;
 549
 550         /* This may look gross but it's good enough for now, we don't quite
 551          * have a hard -> linux processor id matching.
 552          */
 553         for_each_possible_cpu(i) {
 554                 if (!cpu_present(i))
 555                         continue;
 556                 if (hw_id == get_hard_smp_processor_id(i)) {
 557                         xics_per_cpu[i] = ioremap(addr, size);
 558                         return;
 559                 }
 560         }
 561 #else
 562         if (hw_id != 0)
 563                 return;
 564         xics_per_cpu[0] = ioremap(addr, size);
 565 #endif /* CONFIG_SMP */
 566 }
 567
 568 static void __init xics_init_one_node(struct device_node *np,
 569                                       unsigned int *indx)
 570 {
 571         unsigned int ilen;
 572         const u32 *ireg;
 573
 574         /* This code does the theorically broken assumption that the interrupt
 575          * server numbers are the same as the hard CPU numbers.
 576          * This happens to be the case so far but we are playing with fire...
 577          * should be fixed one of these days. -BenH.
 578          */
 579         ireg = get_property(np, "ibm,interrupt-server-ranges", NULL);
 580
 581         /* Do that ever happen ? we'll know soon enough... but even good'old
 582          * f80 does have that property ..
 583          */
 584         WARN_ON(ireg == NULL);
 585         if (ireg) {
 586                 /*
 587                  * set node starting index for this node
 588                  */
 589                 *indx = *ireg;
 590         }
 591         ireg = get_property(np, "reg", &ilen);
 592         if (!ireg)
 593                 panic("xics_init_IRQ: can't find interrupt reg property");
 594
 595         while (ilen >= (4 * sizeof(u32))) {
 596                 unsigned long addr, size;
 597
 598                 /* XXX Use proper OF parsing code here !!! */
 599                 addr = (unsigned long)*ireg++ << 32;
 600                 ilen -= sizeof(u32);
 601                 addr |= *ireg++;
 602                 ilen -= sizeof(u32);
 603                 size = (unsigned long)*ireg++ << 32;
 604                 ilen -= sizeof(u32);
 605                 size |= *ireg++;
 606                 ilen -= sizeof(u32);
 607                 xics_map_one_cpu(*indx, addr, size);
 608                 (*indx)++;
 609         }
 610 }
 611
 612
 613 static void __init xics_setup_8259_cascade(void)
 614 {
 615         struct device_node *np, *old, *found = NULL;
 616         int cascade, naddr;
 617         const u32 *addrp;
 618         unsigned long intack = 0;
 619
 620         for_each_node_by_type(np, "interrupt-controller")
 621                 if (device_is_compatible(np, "chrp,iic")) {
 622                         found = np;
 623                         break;
 624                 }
 625         if (found == NULL) {
 626                 printk(KERN_DEBUG "xics: no ISA interrupt controller\n");
 627                 return;
 628         }
 629         cascade = irq_of_parse_and_map(found, 0);
 630         if (cascade == NO_IRQ) {
 631                 printk(KERN_ERR "xics: failed to map cascade interrupt");
 632                 return;
 633         }
 634         pr_debug("xics: cascade mapped to irq %d\n", cascade);
 635
 636         for (old = of_node_get(found); old != NULL ; old = np) {
 637                 np = of_get_parent(old);
 638                 of_node_put(old);
 639                 if (np == NULL)
 640                         break;
 641                 if (strcmp(np->name, "pci") != 0)
 642                         continue;
 643                 addrp = get_property(np, "8259-interrupt-acknowledge", NULL);
 644                 if (addrp == NULL)
 645                         continue;
 646                 naddr = of_n_addr_cells(np);
 647                 intack = addrp[naddr-1];
 648                 if (naddr > 1)
 649                         intack |= ((unsigned long)addrp[naddr-2]) << 32;
 650         }
 651         if (intack)
 652                 printk(KERN_DEBUG "xics: PCI 8259 intack at 0x%016lx\n", intack);
 653         i8259_init(found, intack);
 654         of_node_put(found);
 655         set_irq_chained_handler(cascade, pseries_8259_cascade);
 656 }
 657
 658 static struct device_node *cpuid_to_of_node(int cpu)
 659 {
 660         struct device_node *np;
 661         u32 hcpuid = get_hard_smp_processor_id(cpu);
 662
 663         for_each_node_by_type(np, "cpu") {
 664                 int i, len;
 665                 const u32 *intserv;
 666
 667                 intserv = get_property(np, "ibm,ppc-interrupt-server#s", &len);
 668
 669                 if (!intserv)
 670                         intserv = get_property(np, "reg", &len);
 671
 672                 i = len / sizeof(u32);
 673
 674                 while (i--)
 675                         if (intserv[i] == hcpuid)
 676                                 return np;
 677         }
 678
 679         return NULL;
 680 }
 681
 682 void __init xics_init_IRQ(void)
 683 {
 684         int i, j;
 685         struct device_node *np;
 686         u32 ilen, indx = 0;
 687         const u32 *ireg, *isize;
 688         int found = 0;
 689         u32 hcpuid;
 690
 691         ppc64_boot_msg(0x20, "XICS Init");
 692
 693         ibm_get_xive = rtas_token("ibm,get-xive");
 694         ibm_set_xive = rtas_token("ibm,set-xive");
 695         ibm_int_on  = rtas_token("ibm,int-on");
 696         ibm_int_off = rtas_token("ibm,int-off");
 697
 698         for_each_node_by_type(np, "PowerPC-External-Interrupt-Presentation") {
 699                 found = 1;
 700                 if (firmware_has_feature(FW_FEATURE_LPAR))
 701                         break;
 702                 xics_init_one_node(np, &indx);
 703         }
 704         if (found == 0)
 705                 return;
 706
 707         xics_init_host();
 708
 709         /* Find the server numbers for the boot cpu. */
 710         np = cpuid_to_of_node(boot_cpuid);
 711         BUG_ON(!np);
 712         ireg = get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
 713         if (!ireg)
 714                 goto skip_gserver_check;
 715         i = ilen / sizeof(int);
 716         hcpuid = get_hard_smp_processor_id(boot_cpuid);
 717
 718         /* Global interrupt distribution server is specified in the last
 719          * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
 720          * entry fom this property for current boot cpu id and use it as
 721          * default distribution server
 722          */
 723         for (j = 0; j < i; j += 2) {
 724                 if (ireg[j] == hcpuid) {
 725                         default_server = hcpuid;
 726                         default_distrib_server = ireg[j+1];
 727
 728                         isize = get_property(np,
 729                                         "ibm,interrupt-server#-size", NULL);
 730                         if (isize)
 731                                 interrupt_server_size = *isize;
 732                 }
 733         }
 734 skip_gserver_check:
 735         of_node_put(np);
 736
 737         if (firmware_has_feature(FW_FEATURE_LPAR))
 738                 ppc_md.get_irq = xics_get_irq_lpar;
 739         else
 740                 ppc_md.get_irq = xics_get_irq_direct;
 741
 742         xics_setup_cpu();
 743
 744         xics_setup_8259_cascade();
 745
 746         ppc64_boot_msg(0x21, "XICS Done");
 747 }
 748
 749
 750 #ifdef CONFIG_SMP
 751 void xics_request_IPIs(void)
 752 {
 753         unsigned int ipi;
 754
 755         ipi = irq_create_mapping(xics_host, XICS_IPI);
 756         BUG_ON(ipi == NO_IRQ);
 757
 758         /*
 759          * IPIs are marked IRQF_DISABLED as they must run with irqs
 760          * disabled
 761          */
 762         set_irq_handler(ipi, handle_percpu_irq);
 763         if (firmware_has_feature(FW_FEATURE_LPAR))
 764                 request_irq(ipi, xics_ipi_action_lpar, IRQF_DISABLED,
 765                             "IPI", NULL);
 766         else
 767                 request_irq(ipi, xics_ipi_action_direct, IRQF_DISABLED,
 768                             "IPI", NULL);
 769 }
 770 #endif /* CONFIG_SMP */
 771
 772 void xics_teardown_cpu(int secondary)
 773 {
 774         int cpu = smp_processor_id();
 775         unsigned int ipi;
 776         struct irq_desc *desc;
 777
 778         xics_set_cpu_priority(cpu, 0);
 779
 780         /*
 781          * Clear IPI
 782          */
 783         if (firmware_has_feature(FW_FEATURE_LPAR))
 784                 lpar_qirr_info(cpu, 0xff);
 785         else
 786                 direct_qirr_info(cpu, 0xff);
 787
 788         /*
 789          * we need to EOI the IPI if we got here from kexec down IPI
 790          *
 791          * probably need to check all the other interrupts too
 792          * should we be flagging idle loop instead?
 793          * or creating some task to be scheduled?
 794          */
 795
 796         ipi = irq_find_mapping(xics_host, XICS_IPI);
 797         if (ipi == XICS_IRQ_SPURIOUS)
 798                 return;
 799         desc = get_irq_desc(ipi);
 800         if (desc->chip && desc->chip->eoi)
 801                 desc->chip->eoi(ipi);
 802
 803         /*
 804          * Some machines need to have at least one cpu in the GIQ,
 805          * so leave the master cpu in the group.
 806          */
 807         if (secondary)
 808                 rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
 809                                    (1UL << interrupt_server_size) - 1 -
 810                                    default_distrib_server, 0);
 811 }
 812
 813 #ifdef CONFIG_HOTPLUG_CPU
 814
 815 /* Interrupts are disabled. */
 816 void xics_migrate_irqs_away(void)
 817 {
 818         int status;
 819         unsigned int irq, virq, cpu = smp_processor_id();
 820
 821         /* Reject any interrupt that was queued to us... */
 822         xics_set_cpu_priority(cpu, 0);
 823
 824         /* remove ourselves from the global interrupt queue */
 825         status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
 826                 (1UL << interrupt_server_size) - 1 - default_distrib_server, 0);
 827         WARN_ON(status < 0);
 828
 829         /* Allow IPIs again... */
 830         xics_set_cpu_priority(cpu, DEFAULT_PRIORITY);
 831
 832         for_each_irq(virq) {
 833                 struct irq_desc *desc;
 834                 int xics_status[2];
 835                 unsigned long flags;
 836
 837                 /* We cant set affinity on ISA interrupts */
 838                 if (virq < NUM_ISA_INTERRUPTS)
 839                         continue;
 840                 if (irq_map[virq].host != xics_host)
 841                         continue;
 842                 irq = (unsigned int)irq_map[virq].hwirq;
 843                 /* We need to get IPIs still. */
 844                 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
 845                         continue;
 846                 desc = get_irq_desc(virq);
 847
 848                 /* We only need to migrate enabled IRQS */
 849                 if (desc == NULL || desc->chip == NULL
 850                     || desc->action == NULL
 851                     || desc->chip->set_affinity == NULL)
 852                         continue;
 853
 854                 spin_lock_irqsave(&desc->lock, flags);
 855
 856                 status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
 857                 if (status) {
 858                         printk(KERN_ERR "migrate_irqs_away: irq=%u "
 859                                         "ibm,get-xive returns %d\n",
 860                                         virq, status);
 861                         goto unlock;
 862                 }
 863
 864                 /*
 865                  * We only support delivery to all cpus or to one cpu.
 866                  * The irq has to be migrated only in the single cpu
 867                  * case.
 868                  */
 869                 if (xics_status[0] != get_hard_smp_processor_id(cpu))
 870                         goto unlock;
 871
 872                 printk(KERN_WARNING "IRQ %u affinity broken off cpu %u\n",
 873                        virq, cpu);
 874
 875                 /* Reset affinity to all cpus */
 876                 desc->chip->set_affinity(virq, CPU_MASK_ALL);
 877                 irq_desc[irq].affinity = CPU_MASK_ALL;
 878 unlock:
 879                 spin_unlock_irqrestore(&desc->lock, flags);
 880         }
 881 }
 882 #endif