arch/x86/kernel/suspend_64.c

   1 /*
   2  * Suspend support specific for i386.
   3  *
   4  * Distribute under GPLv2
   5  *
   6  * Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
   7  * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
   8  */
   9
  10 #include <linux/smp.h>
  11 #include <linux/suspend.h>
  12 #include <asm/proto.h>
  13 #include <asm/page.h>
  14 #include <asm/pgtable.h>
  15 #include <asm/mtrr.h>
  16
  17 /* References to section boundaries */
  18 extern const void __nosave_begin, __nosave_end;
  19
  20 struct saved_context saved_context;
  21
  22 void __save_processor_state(struct saved_context *ctxt)
  23 {
  24         kernel_fpu_begin();
  25
  26         /*
  27          * descriptor tables
  28          */
  29         store_gdt((struct desc_ptr *)&ctxt->gdt_limit);
  30         store_idt((struct desc_ptr *)&ctxt->idt_limit);
  31         store_tr(ctxt->tr);
  32
  33         /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
  34         /*
  35          * segment registers
  36          */
  37         asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
  38         asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
  39         asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
  40         asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
  41         asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
  42
  43         rdmsrl(MSR_FS_BASE, ctxt->fs_base);
  44         rdmsrl(MSR_GS_BASE, ctxt->gs_base);
  45         rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
  46         mtrr_save_fixed_ranges(NULL);
  47
  48         /*
  49          * control registers
  50          */
  51         rdmsrl(MSR_EFER, ctxt->efer);
  52         ctxt->cr0 = read_cr0();
  53         ctxt->cr2 = read_cr2();
  54         ctxt->cr3 = read_cr3();
  55         ctxt->cr4 = read_cr4();
  56         ctxt->cr8 = read_cr8();
  57 }
  58
  59 void save_processor_state(void)
  60 {
  61         __save_processor_state(&saved_context);
  62 }
  63
  64 static void do_fpu_end(void)
  65 {
  66         /*
  67          * Restore FPU regs if necessary
  68          */
  69         kernel_fpu_end();
  70 }
  71
  72 void __restore_processor_state(struct saved_context *ctxt)
  73 {
  74         /*
  75          * control registers
  76          */
  77         wrmsrl(MSR_EFER, ctxt->efer);
  78         write_cr8(ctxt->cr8);
  79         write_cr4(ctxt->cr4);
  80         write_cr3(ctxt->cr3);
  81         write_cr2(ctxt->cr2);
  82         write_cr0(ctxt->cr0);
  83
  84         /*
  85          * now restore the descriptor tables to their proper values
  86          * ltr is done i fix_processor_context().
  87          */
  88         load_gdt((const struct desc_ptr *)&ctxt->gdt_limit);
  89         load_idt((const struct desc_ptr *)&ctxt->idt_limit);
  90
  91
  92         /*
  93          * segment registers
  94          */
  95         asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
  96         asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
  97         asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
  98         load_gs_index(ctxt->gs);
  99         asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
 100
 101         wrmsrl(MSR_FS_BASE, ctxt->fs_base);
 102         wrmsrl(MSR_GS_BASE, ctxt->gs_base);
 103         wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
 104
 105         fix_processor_context();
 106
 107         do_fpu_end();
 108         mtrr_ap_init();
 109 }
 110
 111 void restore_processor_state(void)
 112 {
 113         __restore_processor_state(&saved_context);
 114 }
 115
 116 void fix_processor_context(void)
 117 {
 118         int cpu = smp_processor_id();
 119         struct tss_struct *t = &per_cpu(init_tss, cpu);
 120
 121         set_tss_desc(cpu,t);    /* This just modifies memory; should not be necessary. But... This is necessary, because 386 hardware has concept of busy TSS or some similar stupidity. */
 122
 123         cpu_gdt(cpu)[GDT_ENTRY_TSS].type = 9;
 124
 125         syscall_init();                         /* This sets MSR_*STAR and related */
 126         load_TR_desc();                         /* This does ltr */
 127         load_LDT(&current->active_mm->context); /* This does lldt */
 128
 129         /*
 130          * Now maybe reload the debug registers
 131          */
 132         if (current->thread.debugreg7){
 133                 loaddebug(&current->thread, 0);
 134                 loaddebug(&current->thread, 1);
 135                 loaddebug(&current->thread, 2);
 136                 loaddebug(&current->thread, 3);
 137                 /* no 4 and 5 */
 138                 loaddebug(&current->thread, 6);
 139                 loaddebug(&current->thread, 7);
 140         }
 141
 142 }
 143
 144 #ifdef CONFIG_HIBERNATION
 145 /* Defined in arch/x86_64/kernel/suspend_asm.S */
 146 extern int restore_image(void);
 147
 148 /*
 149  * Address to jump to in the last phase of restore in order to get to the image
 150  * kernel's text (this value is passed in the image header).
 151  */
 152 unsigned long restore_jump_address;
 153
 154 /*
 155  * Value of the cr3 register from before the hibernation (this value is passed
 156  * in the image header).
 157  */
 158 unsigned long restore_cr3;
 159
 160 pgd_t *temp_level4_pgt;
 161
 162 void *relocated_restore_code;
 163
 164 static int res_phys_pud_init(pud_t *pud, unsigned long address, unsigned long end)
 165 {
 166         long i, j;
 167
 168         i = pud_index(address);
 169         pud = pud + i;
 170         for (; i < PTRS_PER_PUD; pud++, i++) {
 171                 unsigned long paddr;
 172                 pmd_t *pmd;
 173
 174                 paddr = address + i*PUD_SIZE;
 175                 if (paddr >= end)
 176                         break;
 177
 178                 pmd = (pmd_t *)get_safe_page(GFP_ATOMIC);
 179                 if (!pmd)
 180                         return -ENOMEM;
 181                 set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE));
 182                 for (j = 0; j < PTRS_PER_PMD; pmd++, j++, paddr += PMD_SIZE) {
 183                         unsigned long pe;
 184
 185                         if (paddr >= end)
 186                                 break;
 187                         pe = __PAGE_KERNEL_LARGE_EXEC | paddr;
 188                         pe &= __supported_pte_mask;
 189                         set_pmd(pmd, __pmd(pe));
 190                 }
 191         }
 192         return 0;
 193 }
 194
 195 static int set_up_temporary_mappings(void)
 196 {
 197         unsigned long start, end, next;
 198         int error;
 199
 200         temp_level4_pgt = (pgd_t *)get_safe_page(GFP_ATOMIC);
 201         if (!temp_level4_pgt)
 202                 return -ENOMEM;
 203
 204         /* It is safe to reuse the original kernel mapping */
 205         set_pgd(temp_level4_pgt + pgd_index(__START_KERNEL_map),
 206                 init_level4_pgt[pgd_index(__START_KERNEL_map)]);
 207
 208         /* Set up the direct mapping from scratch */
 209         start = (unsigned long)pfn_to_kaddr(0);
 210         end = (unsigned long)pfn_to_kaddr(end_pfn);
 211
 212         for (; start < end; start = next) {
 213                 pud_t *pud = (pud_t *)get_safe_page(GFP_ATOMIC);
 214                 if (!pud)
 215                         return -ENOMEM;
 216                 next = start + PGDIR_SIZE;
 217                 if (next > end)
 218                         next = end;
 219                 if ((error = res_phys_pud_init(pud, __pa(start), __pa(next))))
 220                         return error;
 221                 set_pgd(temp_level4_pgt + pgd_index(start),
 222                         mk_kernel_pgd(__pa(pud)));
 223         }
 224         return 0;
 225 }
 226
 227 int swsusp_arch_resume(void)
 228 {
 229         int error;
 230
 231         /* We have got enough memory and from now on we cannot recover */
 232         if ((error = set_up_temporary_mappings()))
 233                 return error;
 234
 235         relocated_restore_code = (void *)get_safe_page(GFP_ATOMIC);
 236         if (!relocated_restore_code)
 237                 return -ENOMEM;
 238         memcpy(relocated_restore_code, &core_restore_code,
 239                &restore_registers - &core_restore_code);
 240
 241         restore_image();
 242         return 0;
 243 }
 244
 245 /*
 246  *      pfn_is_nosave - check if given pfn is in the 'nosave' section
 247  */
 248
 249 int pfn_is_nosave(unsigned long pfn)
 250 {
 251         unsigned long nosave_begin_pfn = __pa_symbol(&__nosave_begin) >> PAGE_SHIFT;
 252         unsigned long nosave_end_pfn = PAGE_ALIGN(__pa_symbol(&__nosave_end)) >> PAGE_SHIFT;
 253         return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn);
 254 }
 255
 256 struct restore_data_record {
 257         unsigned long jump_address;
 258         unsigned long cr3;
 259         unsigned long magic;
 260 };
 261
 262 #define RESTORE_MAGIC   0x0123456789ABCDEFUL
 263
 264 /**
 265  *      arch_hibernation_header_save - populate the architecture specific part
 266  *              of a hibernation image header
 267  *      @addr: address to save the data at
 268  */
 269 int arch_hibernation_header_save(void *addr, unsigned int max_size)
 270 {
 271         struct restore_data_record *rdr = addr;
 272
 273         if (max_size < sizeof(struct restore_data_record))
 274                 return -EOVERFLOW;
 275         rdr->jump_address = restore_jump_address;
 276         rdr->cr3 = restore_cr3;
 277         rdr->magic = RESTORE_MAGIC;
 278         return 0;
 279 }
 280
 281 /**
 282  *      arch_hibernation_header_restore - read the architecture specific data
 283  *              from the hibernation image header
 284  *      @addr: address to read the data from
 285  */
 286 int arch_hibernation_header_restore(void *addr)
 287 {
 288         struct restore_data_record *rdr = addr;
 289
 290         restore_jump_address = rdr->jump_address;
 291         restore_cr3 = rdr->cr3;
 292         return (rdr->magic == RESTORE_MAGIC) ? 0 : -EINVAL;
 293 }
 294 #endif /* CONFIG_HIBERNATION */