drivers/scsi/qla2xxx/qla_dbg.h

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2011 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7
   8 #include "qla_def.h"
   9
  10 /*
  11  * Driver debug definitions.
  12  */
  13 /* #define QL_DEBUG_LEVEL_1  */ /* Output register accesses to COM1 */
  14 /* #define QL_DEBUG_LEVEL_2  */ /* Output error msgs to COM1 */
  15 /* #define QL_DEBUG_LEVEL_3  */ /* Output function trace msgs to COM1 */
  16 /* #define QL_DEBUG_LEVEL_4  */ /* Output NVRAM trace msgs to COM1 */
  17 /* #define QL_DEBUG_LEVEL_5  */ /* Output ring trace msgs to COM1 */
  18 /* #define QL_DEBUG_LEVEL_6  */ /* Output WATCHDOG timer trace to COM1 */
  19 /* #define QL_DEBUG_LEVEL_7  */ /* Output RISC load trace msgs to COM1 */
  20 /* #define QL_DEBUG_LEVEL_8  */ /* Output ring saturation msgs to COM1 */
  21 /* #define QL_DEBUG_LEVEL_9  */ /* Output IOCTL trace msgs */
  22 /* #define QL_DEBUG_LEVEL_10 */ /* Output IOCTL error msgs */
  23 /* #define QL_DEBUG_LEVEL_11 */ /* Output Mbx Cmd trace msgs */
  24 /* #define QL_DEBUG_LEVEL_12 */ /* Output IP trace msgs */
  25 /* #define QL_DEBUG_LEVEL_13 */ /* Output fdmi function trace msgs */
  26 /* #define QL_DEBUG_LEVEL_14 */ /* Output RSCN trace msgs */
  27 /* #define QL_DEBUG_LEVEL_15 */ /* Output NPIV trace msgs */
  28 /* #define QL_DEBUG_LEVEL_16 */ /* Output ISP84XX trace msgs */
  29 /* #define QL_DEBUG_LEVEL_17 */ /* Output EEH trace messages */
  30 /* #define QL_DEBUG_LEVEL_18 */ /* Output T10 CRC trace messages */
  31
  32 /*
  33 * Macros use for debugging the driver.
  34 */
  35
  36 #define DEBUG(x)        do { if (ql2xextended_error_logging) { x; } } while (0)
  37
  38 #if defined(QL_DEBUG_LEVEL_1)
  39 #define DEBUG1(x)       do {x;} while (0)
  40 #else
  41 #define DEBUG1(x)       do {} while (0)
  42 #endif
  43
  44 #define DEBUG2(x)       do { if (ql2xextended_error_logging) { x; } } while (0)
  45 #define DEBUG2_3(x)     do { if (ql2xextended_error_logging) { x; } } while (0)
  46 #define DEBUG2_3_11(x)  do { if (ql2xextended_error_logging) { x; } } while (0)
  47 #define DEBUG2_9_10(x)  do { if (ql2xextended_error_logging) { x; } } while (0)
  48 #define DEBUG2_11(x)    do { if (ql2xextended_error_logging) { x; } } while (0)
  49 #define DEBUG2_13(x)    do { if (ql2xextended_error_logging) { x; } } while (0)
  50 #define DEBUG2_16(x)    do { if (ql2xextended_error_logging) { x; } } while (0)
  51 #define DEBUG2_17(x)    do { if (ql2xextended_error_logging) { x; } } while (0)
  52
  53 #if defined(QL_DEBUG_LEVEL_3)
  54 #define DEBUG3(x)       do {x;} while (0)
  55 #define DEBUG3_11(x)    do {x;} while (0)
  56 #else
  57 #define DEBUG3(x)       do {} while (0)
  58 #endif
  59
  60 #if defined(QL_DEBUG_LEVEL_4)
  61 #define DEBUG4(x)       do {x;} while (0)
  62 #else
  63 #define DEBUG4(x)       do {} while (0)
  64 #endif
  65
  66 #if defined(QL_DEBUG_LEVEL_5)
  67 #define DEBUG5(x)          do {x;} while (0)
  68 #else
  69 #define DEBUG5(x)       do {} while (0)
  70 #endif
  71
  72 #if defined(QL_DEBUG_LEVEL_7)
  73 #define DEBUG7(x)          do {x;} while (0)
  74 #else
  75 #define DEBUG7(x)          do {} while (0)
  76 #endif
  77
  78 #if defined(QL_DEBUG_LEVEL_9)
  79 #define DEBUG9(x)       do {x;} while (0)
  80 #define DEBUG9_10(x)    do {x;} while (0)
  81 #else
  82 #define DEBUG9(x)       do {} while (0)
  83 #endif
  84
  85 #if defined(QL_DEBUG_LEVEL_10)
  86 #define DEBUG10(x)      do {x;} while (0)
  87 #define DEBUG9_10(x)    do {x;} while (0)
  88 #else
  89 #define DEBUG10(x)      do {} while (0)
  90   #if !defined(DEBUG9_10)
  91   #define DEBUG9_10(x)  do {} while (0)
  92   #endif
  93 #endif
  94
  95 #if defined(QL_DEBUG_LEVEL_11)
  96 #define DEBUG11(x)      do{x;} while(0)
  97 #if !defined(DEBUG3_11)
  98 #define DEBUG3_11(x)    do{x;} while(0)
  99 #endif
 100 #else
 101 #define DEBUG11(x)      do{} while(0)
 102   #if !defined(QL_DEBUG_LEVEL_3)
 103   #define DEBUG3_11(x)  do{} while(0)
 104   #endif
 105 #endif
 106
 107 #if defined(QL_DEBUG_LEVEL_12)
 108 #define DEBUG12(x)      do {x;} while (0)
 109 #else
 110 #define DEBUG12(x)      do {} while (0)
 111 #endif
 112
 113 #if defined(QL_DEBUG_LEVEL_13)
 114 #define DEBUG13(x)      do {x;} while (0)
 115 #else
 116 #define DEBUG13(x)      do {} while (0)
 117 #endif
 118
 119 #if defined(QL_DEBUG_LEVEL_14)
 120 #define DEBUG14(x)      do {x;} while (0)
 121 #else
 122 #define DEBUG14(x)      do {} while (0)
 123 #endif
 124
 125 #if defined(QL_DEBUG_LEVEL_15)
 126 #define DEBUG15(x)      do {x;} while (0)
 127 #else
 128 #define DEBUG15(x)      do {} while (0)
 129 #endif
 130
 131 #if defined(QL_DEBUG_LEVEL_16)
 132 #define DEBUG16(x)      do {x;} while (0)
 133 #else
 134 #define DEBUG16(x)      do {} while (0)
 135 #endif
 136
 137 #if defined(QL_DEBUG_LEVEL_17)
 138 #define DEBUG17(x)      do {x;} while (0)
 139 #else
 140 #define DEBUG17(x)      do {} while (0)
 141 #endif
 142
 143 #if defined(QL_DEBUG_LEVEL_18)
 144 #define DEBUG18(x)      do {if (ql2xextended_error_logging) x; } while (0)
 145 #else
 146 #define DEBUG18(x)      do {} while (0)
 147 #endif
 148
 149
 150 /*
 151  * Firmware Dump structure definition
 152  */
 153
 154 struct qla2300_fw_dump {
 155         uint16_t hccr;
 156         uint16_t pbiu_reg[8];
 157         uint16_t risc_host_reg[8];
 158         uint16_t mailbox_reg[32];
 159         uint16_t resp_dma_reg[32];
 160         uint16_t dma_reg[48];
 161         uint16_t risc_hdw_reg[16];
 162         uint16_t risc_gp0_reg[16];
 163         uint16_t risc_gp1_reg[16];
 164         uint16_t risc_gp2_reg[16];
 165         uint16_t risc_gp3_reg[16];
 166         uint16_t risc_gp4_reg[16];
 167         uint16_t risc_gp5_reg[16];
 168         uint16_t risc_gp6_reg[16];
 169         uint16_t risc_gp7_reg[16];
 170         uint16_t frame_buf_hdw_reg[64];
 171         uint16_t fpm_b0_reg[64];
 172         uint16_t fpm_b1_reg[64];
 173         uint16_t risc_ram[0xf800];
 174         uint16_t stack_ram[0x1000];
 175         uint16_t data_ram[1];
 176 };
 177
 178 struct qla2100_fw_dump {
 179         uint16_t hccr;
 180         uint16_t pbiu_reg[8];
 181         uint16_t mailbox_reg[32];
 182         uint16_t dma_reg[48];
 183         uint16_t risc_hdw_reg[16];
 184         uint16_t risc_gp0_reg[16];
 185         uint16_t risc_gp1_reg[16];
 186         uint16_t risc_gp2_reg[16];
 187         uint16_t risc_gp3_reg[16];
 188         uint16_t risc_gp4_reg[16];
 189         uint16_t risc_gp5_reg[16];
 190         uint16_t risc_gp6_reg[16];
 191         uint16_t risc_gp7_reg[16];
 192         uint16_t frame_buf_hdw_reg[16];
 193         uint16_t fpm_b0_reg[64];
 194         uint16_t fpm_b1_reg[64];
 195         uint16_t risc_ram[0xf000];
 196 };
 197
 198 struct qla24xx_fw_dump {
 199         uint32_t host_status;
 200         uint32_t host_reg[32];
 201         uint32_t shadow_reg[7];
 202         uint16_t mailbox_reg[32];
 203         uint32_t xseq_gp_reg[128];
 204         uint32_t xseq_0_reg[16];
 205         uint32_t xseq_1_reg[16];
 206         uint32_t rseq_gp_reg[128];
 207         uint32_t rseq_0_reg[16];
 208         uint32_t rseq_1_reg[16];
 209         uint32_t rseq_2_reg[16];
 210         uint32_t cmd_dma_reg[16];
 211         uint32_t req0_dma_reg[15];
 212         uint32_t resp0_dma_reg[15];
 213         uint32_t req1_dma_reg[15];
 214         uint32_t xmt0_dma_reg[32];
 215         uint32_t xmt1_dma_reg[32];
 216         uint32_t xmt2_dma_reg[32];
 217         uint32_t xmt3_dma_reg[32];
 218         uint32_t xmt4_dma_reg[32];
 219         uint32_t xmt_data_dma_reg[16];
 220         uint32_t rcvt0_data_dma_reg[32];
 221         uint32_t rcvt1_data_dma_reg[32];
 222         uint32_t risc_gp_reg[128];
 223         uint32_t lmc_reg[112];
 224         uint32_t fpm_hdw_reg[192];
 225         uint32_t fb_hdw_reg[176];
 226         uint32_t code_ram[0x2000];
 227         uint32_t ext_mem[1];
 228 };
 229
 230 struct qla25xx_fw_dump {
 231         uint32_t host_status;
 232         uint32_t host_risc_reg[32];
 233         uint32_t pcie_regs[4];
 234         uint32_t host_reg[32];
 235         uint32_t shadow_reg[11];
 236         uint32_t risc_io_reg;
 237         uint16_t mailbox_reg[32];
 238         uint32_t xseq_gp_reg[128];
 239         uint32_t xseq_0_reg[48];
 240         uint32_t xseq_1_reg[16];
 241         uint32_t rseq_gp_reg[128];
 242         uint32_t rseq_0_reg[32];
 243         uint32_t rseq_1_reg[16];
 244         uint32_t rseq_2_reg[16];
 245         uint32_t aseq_gp_reg[128];
 246         uint32_t aseq_0_reg[32];
 247         uint32_t aseq_1_reg[16];
 248         uint32_t aseq_2_reg[16];
 249         uint32_t cmd_dma_reg[16];
 250         uint32_t req0_dma_reg[15];
 251         uint32_t resp0_dma_reg[15];
 252         uint32_t req1_dma_reg[15];
 253         uint32_t xmt0_dma_reg[32];
 254         uint32_t xmt1_dma_reg[32];
 255         uint32_t xmt2_dma_reg[32];
 256         uint32_t xmt3_dma_reg[32];
 257         uint32_t xmt4_dma_reg[32];
 258         uint32_t xmt_data_dma_reg[16];
 259         uint32_t rcvt0_data_dma_reg[32];
 260         uint32_t rcvt1_data_dma_reg[32];
 261         uint32_t risc_gp_reg[128];
 262         uint32_t lmc_reg[128];
 263         uint32_t fpm_hdw_reg[192];
 264         uint32_t fb_hdw_reg[192];
 265         uint32_t code_ram[0x2000];
 266         uint32_t ext_mem[1];
 267 };
 268
 269 struct qla81xx_fw_dump {
 270         uint32_t host_status;
 271         uint32_t host_risc_reg[32];
 272         uint32_t pcie_regs[4];
 273         uint32_t host_reg[32];
 274         uint32_t shadow_reg[11];
 275         uint32_t risc_io_reg;
 276         uint16_t mailbox_reg[32];
 277         uint32_t xseq_gp_reg[128];
 278         uint32_t xseq_0_reg[48];
 279         uint32_t xseq_1_reg[16];
 280         uint32_t rseq_gp_reg[128];
 281         uint32_t rseq_0_reg[32];
 282         uint32_t rseq_1_reg[16];
 283         uint32_t rseq_2_reg[16];
 284         uint32_t aseq_gp_reg[128];
 285         uint32_t aseq_0_reg[32];
 286         uint32_t aseq_1_reg[16];
 287         uint32_t aseq_2_reg[16];
 288         uint32_t cmd_dma_reg[16];
 289         uint32_t req0_dma_reg[15];
 290         uint32_t resp0_dma_reg[15];
 291         uint32_t req1_dma_reg[15];
 292         uint32_t xmt0_dma_reg[32];
 293         uint32_t xmt1_dma_reg[32];
 294         uint32_t xmt2_dma_reg[32];
 295         uint32_t xmt3_dma_reg[32];
 296         uint32_t xmt4_dma_reg[32];
 297         uint32_t xmt_data_dma_reg[16];
 298         uint32_t rcvt0_data_dma_reg[32];
 299         uint32_t rcvt1_data_dma_reg[32];
 300         uint32_t risc_gp_reg[128];
 301         uint32_t lmc_reg[128];
 302         uint32_t fpm_hdw_reg[224];
 303         uint32_t fb_hdw_reg[208];
 304         uint32_t code_ram[0x2000];
 305         uint32_t ext_mem[1];
 306 };
 307
 308 #define EFT_NUM_BUFFERS         4
 309 #define EFT_BYTES_PER_BUFFER    0x4000
 310 #define EFT_SIZE                ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))
 311
 312 #define FCE_NUM_BUFFERS         64
 313 #define FCE_BYTES_PER_BUFFER    0x400
 314 #define FCE_SIZE                ((FCE_BYTES_PER_BUFFER) * (FCE_NUM_BUFFERS))
 315 #define fce_calc_size(b)        ((FCE_BYTES_PER_BUFFER) * (b))
 316
 317 struct qla2xxx_fce_chain {
 318         uint32_t type;
 319         uint32_t chain_size;
 320
 321         uint32_t size;
 322         uint32_t addr_l;
 323         uint32_t addr_h;
 324         uint32_t eregs[8];
 325 };
 326
 327 struct qla2xxx_mq_chain {
 328         uint32_t type;
 329         uint32_t chain_size;
 330
 331         uint32_t count;
 332         uint32_t qregs[4 * QLA_MQ_SIZE];
 333 };
 334
 335 #define DUMP_CHAIN_VARIANT      0x80000000
 336 #define DUMP_CHAIN_FCE          0x7FFFFAF0
 337 #define DUMP_CHAIN_MQ           0x7FFFFAF1
 338 #define DUMP_CHAIN_LAST         0x80000000
 339
 340 struct qla2xxx_fw_dump {
 341         uint8_t signature[4];
 342         uint32_t version;
 343
 344         uint32_t fw_major_version;
 345         uint32_t fw_minor_version;
 346         uint32_t fw_subminor_version;
 347         uint32_t fw_attributes;
 348
 349         uint32_t vendor;
 350         uint32_t device;
 351         uint32_t subsystem_vendor;
 352         uint32_t subsystem_device;
 353
 354         uint32_t fixed_size;
 355         uint32_t mem_size;
 356         uint32_t req_q_size;
 357         uint32_t rsp_q_size;
 358
 359         uint32_t eft_size;
 360         uint32_t eft_addr_l;
 361         uint32_t eft_addr_h;
 362
 363         uint32_t header_size;
 364
 365         union {
 366                 struct qla2100_fw_dump isp21;
 367                 struct qla2300_fw_dump isp23;
 368                 struct qla24xx_fw_dump isp24;
 369                 struct qla25xx_fw_dump isp25;
 370                 struct qla81xx_fw_dump isp81;
 371         } isp;
 372 };