arch/x86/pci/mmconfig-shared.c

   1 /*
   2  * mmconfig-shared.c - Low-level direct PCI config space access via
   3  *                     MMCONFIG - common code between i386 and x86-64.
   4  *
   5  * This code does:
   6  * - known chipset handling
   7  * - ACPI decoding and validation
   8  *
   9  * Per-architecture code takes care of the mappings and accesses
  10  * themselves.
  11  */
  12
  13 #include <linux/pci.h>
  14 #include <linux/init.h>
  15 #include <linux/acpi.h>
  16 #include <linux/sfi_acpi.h>
  17 #include <linux/bitmap.h>
  18 #include <linux/dmi.h>
  19 #include <linux/sort.h>
  20 #include <asm/e820.h>
  21 #include <asm/pci_x86.h>
  22 #include <asm/acpi.h>
  23
  24 #define PREFIX "PCI: "
  25
  26 /* Indicate if the mmcfg resources have been placed into the resource table. */
  27 static int __initdata pci_mmcfg_resources_inserted;
  28
  29 static __init void free_all_mmcfg(void)
  30 {
  31         int i;
  32         struct pci_mmcfg_region *cfg;
  33
  34         pci_mmcfg_arch_free();
  35         for (i = 0; i < pci_mmcfg_config_num; i++) {
  36                 cfg = &pci_mmcfg_config[i];
  37                 if (cfg->res.parent)
  38                         release_resource(&cfg->res);
  39         }
  40         pci_mmcfg_config_num = 0;
  41         kfree(pci_mmcfg_config);
  42         pci_mmcfg_config = NULL;
  43 }
  44
  45 static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
  46                                                         int end, u64 addr)
  47 {
  48         struct pci_mmcfg_region *new;
  49         int new_num = pci_mmcfg_config_num + 1;
  50         int i = pci_mmcfg_config_num;
  51         int num_buses;
  52         struct resource *res;
  53
  54         if (addr == 0)
  55                 return NULL;
  56
  57         new = kzalloc(sizeof(pci_mmcfg_config[0]) * new_num, GFP_KERNEL);
  58         if (!new)
  59                 return NULL;
  60
  61         if (pci_mmcfg_config) {
  62                 memcpy(new, pci_mmcfg_config,
  63                          sizeof(pci_mmcfg_config[0]) * new_num);
  64                 kfree(pci_mmcfg_config);
  65         }
  66         pci_mmcfg_config = new;
  67         pci_mmcfg_config_num++;
  68
  69         new = &pci_mmcfg_config[i];
  70
  71         new->address = addr;
  72         new->segment = segment;
  73         new->start_bus = start;
  74         new->end_bus = end;
  75
  76         num_buses = end - start + 1;
  77         res = &new->res;
  78         res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
  79         res->end = addr + PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
  80         res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
  81         snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
  82                  "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
  83         res->name = new->name;
  84
  85         return &pci_mmcfg_config[i];
  86 }
  87
  88 static const char __init *pci_mmcfg_e7520(void)
  89 {
  90         u32 win;
  91         raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
  92
  93         win = win & 0xf000;
  94         if (win == 0x0000 || win == 0xf000)
  95                 return NULL;
  96
  97         if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
  98                 return NULL;
  99
 100         return "Intel Corporation E7520 Memory Controller Hub";
 101 }
 102
 103 static const char __init *pci_mmcfg_intel_945(void)
 104 {
 105         u32 pciexbar, mask = 0, len = 0;
 106
 107         raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
 108
 109         /* Enable bit */
 110         if (!(pciexbar & 1))
 111                 return NULL;
 112
 113         /* Size bits */
 114         switch ((pciexbar >> 1) & 3) {
 115         case 0:
 116                 mask = 0xf0000000U;
 117                 len  = 0x10000000U;
 118                 break;
 119         case 1:
 120                 mask = 0xf8000000U;
 121                 len  = 0x08000000U;
 122                 break;
 123         case 2:
 124                 mask = 0xfc000000U;
 125                 len  = 0x04000000U;
 126                 break;
 127         default:
 128                 return NULL;
 129         }
 130
 131         /* Errata #2, things break when not aligned on a 256Mb boundary */
 132         /* Can only happen in 64M/128M mode */
 133
 134         if ((pciexbar & mask) & 0x0fffffffU)
 135                 return NULL;
 136
 137         /* Don't hit the APIC registers and their friends */
 138         if ((pciexbar & mask) >= 0xf0000000U)
 139                 return NULL;
 140
 141         if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
 142                 return NULL;
 143
 144         return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
 145 }
 146
 147 static const char __init *pci_mmcfg_amd_fam10h(void)
 148 {
 149         u32 low, high, address;
 150         u64 base, msr;
 151         int i;
 152         unsigned segnbits = 0, busnbits, end_bus;
 153
 154         if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
 155                 return NULL;
 156
 157         address = MSR_FAM10H_MMIO_CONF_BASE;
 158         if (rdmsr_safe(address, &low, &high))
 159                 return NULL;
 160
 161         msr = high;
 162         msr <<= 32;
 163         msr |= low;
 164
 165         /* mmconfig is not enable */
 166         if (!(msr & FAM10H_MMIO_CONF_ENABLE))
 167                 return NULL;
 168
 169         base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
 170
 171         busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
 172                          FAM10H_MMIO_CONF_BUSRANGE_MASK;
 173
 174         /*
 175          * only handle bus 0 ?
 176          * need to skip it
 177          */
 178         if (!busnbits)
 179                 return NULL;
 180
 181         if (busnbits > 8) {
 182                 segnbits = busnbits - 8;
 183                 busnbits = 8;
 184         }
 185
 186         end_bus = (1 << busnbits) - 1;
 187         for (i = 0; i < (1 << segnbits); i++)
 188                 if (pci_mmconfig_add(i, 0, end_bus,
 189                                      base + (1<<28) * i) == NULL) {
 190                         free_all_mmcfg();
 191                         return NULL;
 192                 }
 193
 194         return "AMD Family 10h NB";
 195 }
 196
 197 static bool __initdata mcp55_checked;
 198 static const char __init *pci_mmcfg_nvidia_mcp55(void)
 199 {
 200         int bus;
 201         int mcp55_mmconf_found = 0;
 202
 203         static const u32 extcfg_regnum          = 0x90;
 204         static const u32 extcfg_regsize         = 4;
 205         static const u32 extcfg_enable_mask     = 1<<31;
 206         static const u32 extcfg_start_mask      = 0xff<<16;
 207         static const int extcfg_start_shift     = 16;
 208         static const u32 extcfg_size_mask       = 0x3<<28;
 209         static const int extcfg_size_shift      = 28;
 210         static const int extcfg_sizebus[]       = {0x100, 0x80, 0x40, 0x20};
 211         static const u32 extcfg_base_mask[]     = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
 212         static const int extcfg_base_lshift     = 25;
 213
 214         /*
 215          * do check if amd fam10h already took over
 216          */
 217         if (!acpi_disabled || pci_mmcfg_config_num || mcp55_checked)
 218                 return NULL;
 219
 220         mcp55_checked = true;
 221         for (bus = 0; bus < 256; bus++) {
 222                 u64 base;
 223                 u32 l, extcfg;
 224                 u16 vendor, device;
 225                 int start, size_index, end;
 226
 227                 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
 228                 vendor = l & 0xffff;
 229                 device = (l >> 16) & 0xffff;
 230
 231                 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
 232                         continue;
 233
 234                 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
 235                                   extcfg_regsize, &extcfg);
 236
 237                 if (!(extcfg & extcfg_enable_mask))
 238                         continue;
 239
 240                 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
 241                 base = extcfg & extcfg_base_mask[size_index];
 242                 /* base could > 4G */
 243                 base <<= extcfg_base_lshift;
 244                 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
 245                 end = start + extcfg_sizebus[size_index] - 1;
 246                 if (pci_mmconfig_add(0, start, end, base) == NULL)
 247                         continue;
 248                 mcp55_mmconf_found++;
 249         }
 250
 251         if (!mcp55_mmconf_found)
 252                 return NULL;
 253
 254         return "nVidia MCP55";
 255 }
 256
 257 struct pci_mmcfg_hostbridge_probe {
 258         u32 bus;
 259         u32 devfn;
 260         u32 vendor;
 261         u32 device;
 262         const char *(*probe)(void);
 263 };
 264
 265 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
 266         { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
 267           PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
 268         { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
 269           PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
 270         { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
 271           0x1200, pci_mmcfg_amd_fam10h },
 272         { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
 273           0x1200, pci_mmcfg_amd_fam10h },
 274         { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
 275           0x0369, pci_mmcfg_nvidia_mcp55 },
 276 };
 277
 278 static int __init cmp_mmcfg(const void *x1, const void *x2)
 279 {
 280         const struct pci_mmcfg_region *m1 = x1;
 281         const struct pci_mmcfg_region *m2 = x2;
 282         int start1, start2;
 283
 284         start1 = m1->start_bus;
 285         start2 = m2->start_bus;
 286
 287         return start1 - start2;
 288 }
 289
 290 static void __init pci_mmcfg_check_end_bus_number(void)
 291 {
 292         int i;
 293         struct pci_mmcfg_region *cfg, *cfgx;
 294
 295         /* sort them at first */
 296         sort(pci_mmcfg_config, pci_mmcfg_config_num,
 297                  sizeof(pci_mmcfg_config[0]), cmp_mmcfg, NULL);
 298
 299         /* last one*/
 300         if (pci_mmcfg_config_num > 0) {
 301                 i = pci_mmcfg_config_num - 1;
 302                 cfg = &pci_mmcfg_config[i];
 303                 if (cfg->end_bus < cfg->start_bus)
 304                         cfg->end_bus = 255;
 305         }
 306
 307         /* don't overlap please */
 308         for (i = 0; i < pci_mmcfg_config_num - 1; i++) {
 309                 cfg = &pci_mmcfg_config[i];
 310                 cfgx = &pci_mmcfg_config[i+1];
 311
 312                 if (cfg->end_bus < cfg->start_bus)
 313                         cfg->end_bus = 255;
 314
 315                 if (cfg->end_bus >= cfgx->start_bus)
 316                         cfg->end_bus = cfgx->start_bus - 1;
 317         }
 318 }
 319
 320 static int __init pci_mmcfg_check_hostbridge(void)
 321 {
 322         u32 l;
 323         u32 bus, devfn;
 324         u16 vendor, device;
 325         int i;
 326         const char *name;
 327
 328         if (!raw_pci_ops)
 329                 return 0;
 330
 331         free_all_mmcfg();
 332
 333         for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
 334                 bus =  pci_mmcfg_probes[i].bus;
 335                 devfn = pci_mmcfg_probes[i].devfn;
 336                 raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
 337                 vendor = l & 0xffff;
 338                 device = (l >> 16) & 0xffff;
 339
 340                 name = NULL;
 341                 if (pci_mmcfg_probes[i].vendor == vendor &&
 342                     pci_mmcfg_probes[i].device == device)
 343                         name = pci_mmcfg_probes[i].probe();
 344
 345                 if (name)
 346                         printk(KERN_INFO "PCI: Found %s with MMCONFIG support.\n",
 347                                name);
 348         }
 349
 350         /* some end_bus_number is crazy, fix it */
 351         pci_mmcfg_check_end_bus_number();
 352
 353         return pci_mmcfg_config_num != 0;
 354 }
 355
 356 static void __init pci_mmcfg_insert_resources(void)
 357 {
 358         int i;
 359         struct pci_mmcfg_region *cfg;
 360
 361         for (i = 0; i < pci_mmcfg_config_num; i++) {
 362                 cfg = &pci_mmcfg_config[i];
 363                 insert_resource(&iomem_resource, &cfg->res);
 364         }
 365
 366         /* Mark that the resources have been inserted. */
 367         pci_mmcfg_resources_inserted = 1;
 368 }
 369
 370 static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
 371                                               void *data)
 372 {
 373         struct resource *mcfg_res = data;
 374         struct acpi_resource_address64 address;
 375         acpi_status status;
 376
 377         if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
 378                 struct acpi_resource_fixed_memory32 *fixmem32 =
 379                         &res->data.fixed_memory32;
 380                 if (!fixmem32)
 381                         return AE_OK;
 382                 if ((mcfg_res->start >= fixmem32->address) &&
 383                     (mcfg_res->end < (fixmem32->address +
 384                                       fixmem32->address_length))) {
 385                         mcfg_res->flags = 1;
 386                         return AE_CTRL_TERMINATE;
 387                 }
 388         }
 389         if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
 390             (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
 391                 return AE_OK;
 392
 393         status = acpi_resource_to_address64(res, &address);
 394         if (ACPI_FAILURE(status) ||
 395            (address.address_length <= 0) ||
 396            (address.resource_type != ACPI_MEMORY_RANGE))
 397                 return AE_OK;
 398
 399         if ((mcfg_res->start >= address.minimum) &&
 400             (mcfg_res->end < (address.minimum + address.address_length))) {
 401                 mcfg_res->flags = 1;
 402                 return AE_CTRL_TERMINATE;
 403         }
 404         return AE_OK;
 405 }
 406
 407 static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
 408                 void *context, void **rv)
 409 {
 410         struct resource *mcfg_res = context;
 411
 412         acpi_walk_resources(handle, METHOD_NAME__CRS,
 413                             check_mcfg_resource, context);
 414
 415         if (mcfg_res->flags)
 416                 return AE_CTRL_TERMINATE;
 417
 418         return AE_OK;
 419 }
 420
 421 static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
 422 {
 423         struct resource mcfg_res;
 424
 425         mcfg_res.start = start;
 426         mcfg_res.end = end - 1;
 427         mcfg_res.flags = 0;
 428
 429         acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
 430
 431         if (!mcfg_res.flags)
 432                 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
 433                                  NULL);
 434
 435         return mcfg_res.flags;
 436 }
 437
 438 typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
 439
 440 static int __init is_mmconf_reserved(check_reserved_t is_reserved,
 441                 int i, struct pci_mmcfg_region *cfg, int with_e820)
 442 {
 443         u64 addr = cfg->res.start;
 444         u64 size = resource_size(&cfg->res);
 445         u64 old_size = size;
 446         int valid = 0, num_buses;
 447
 448         while (!is_reserved(addr, addr + size, E820_RESERVED)) {
 449                 size >>= 1;
 450                 if (size < (16UL<<20))
 451                         break;
 452         }
 453
 454         if (size >= (16UL<<20) || size == old_size) {
 455                 printk(KERN_NOTICE
 456                        "PCI: MCFG area at %Lx reserved in %s\n",
 457                         addr, with_e820?"E820":"ACPI motherboard resources");
 458                 valid = 1;
 459
 460                 if (old_size != size) {
 461                         /* update end_bus */
 462                         cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
 463                         num_buses = cfg->end_bus - cfg->start_bus + 1;
 464                         cfg->res.end = cfg->res.start +
 465                             PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
 466                         snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
 467                                  "PCI MMCONFIG %04x [bus %02x-%02x]",
 468                                  cfg->segment, cfg->start_bus, cfg->end_bus);
 469                         printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx "
 470                                "segment %hu buses %u - %u\n",
 471                                i, (unsigned long)cfg->address, cfg->segment,
 472                                (unsigned int)cfg->start_bus,
 473                                (unsigned int)cfg->end_bus);
 474                 }
 475         }
 476
 477         return valid;
 478 }
 479
 480 static void __init pci_mmcfg_reject_broken(int early)
 481 {
 482         struct pci_mmcfg_region *cfg;
 483         int i;
 484
 485         if (pci_mmcfg_config_num == 0)
 486                 return;
 487
 488         for (i = 0; i < pci_mmcfg_config_num; i++) {
 489                 int valid = 0;
 490
 491                 cfg = &pci_mmcfg_config[i];
 492                 printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
 493                        "segment %hu buses %u - %u\n",
 494                        i, (unsigned long)cfg->address, cfg->segment,
 495                        (unsigned int)cfg->start_bus,
 496                        (unsigned int)cfg->end_bus);
 497
 498                 if (!early && !acpi_disabled)
 499                         valid = is_mmconf_reserved(is_acpi_reserved, i, cfg, 0);
 500
 501                 if (valid)
 502                         continue;
 503
 504                 if (!early)
 505                         printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
 506                                " reserved in ACPI motherboard resources\n",
 507                                cfg->address);
 508
 509                 /* Don't try to do this check unless configuration
 510                    type 1 is available. how about type 2 ?*/
 511                 if (raw_pci_ops)
 512                         valid = is_mmconf_reserved(e820_all_mapped, i, cfg, 1);
 513
 514                 if (!valid)
 515                         goto reject;
 516         }
 517
 518         return;
 519
 520 reject:
 521         printk(KERN_INFO "PCI: Not using MMCONFIG.\n");
 522         free_all_mmcfg();
 523 }
 524
 525 static int __initdata known_bridge;
 526
 527 /* The physical address of the MMCONFIG aperture.  Set from ACPI tables. */
 528 struct pci_mmcfg_region *pci_mmcfg_config;
 529 int pci_mmcfg_config_num;
 530
 531 static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
 532                                         struct acpi_mcfg_allocation *cfg)
 533 {
 534         int year;
 535
 536         if (cfg->address < 0xFFFFFFFF)
 537                 return 0;
 538
 539         if (!strcmp(mcfg->header.oem_id, "SGI"))
 540                 return 0;
 541
 542         if (mcfg->header.revision >= 1) {
 543                 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
 544                     year >= 2010)
 545                         return 0;
 546         }
 547
 548         printk(KERN_ERR PREFIX "MCFG region for %04x:%02x-%02x at %#llx "
 549                "is above 4GB, ignored\n", cfg->pci_segment,
 550                cfg->start_bus_number, cfg->end_bus_number, cfg->address);
 551         return -EINVAL;
 552 }
 553
 554 static int __init pci_parse_mcfg(struct acpi_table_header *header)
 555 {
 556         struct acpi_table_mcfg *mcfg;
 557         struct acpi_mcfg_allocation *cfg_table, *cfg;
 558         unsigned long i;
 559         int entries;
 560
 561         if (!header)
 562                 return -EINVAL;
 563
 564         mcfg = (struct acpi_table_mcfg *)header;
 565
 566         /* how many config structures do we have */
 567         free_all_mmcfg();
 568         entries = 0;
 569         i = header->length - sizeof(struct acpi_table_mcfg);
 570         while (i >= sizeof(struct acpi_mcfg_allocation)) {
 571                 entries++;
 572                 i -= sizeof(struct acpi_mcfg_allocation);
 573         };
 574         if (entries == 0) {
 575                 printk(KERN_ERR PREFIX "MMCONFIG has no entries\n");
 576                 return -ENODEV;
 577         }
 578
 579         cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1];
 580         for (i = 0; i < entries; i++) {
 581                 cfg = &cfg_table[i];
 582                 if (acpi_mcfg_check_entry(mcfg, cfg)) {
 583                         free_all_mmcfg();
 584                         return -ENODEV;
 585                 }
 586
 587                 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
 588                                    cfg->end_bus_number, cfg->address) == NULL) {
 589                         printk(KERN_WARNING PREFIX
 590                                "no memory for MCFG entries\n");
 591                         free_all_mmcfg();
 592                         return -ENOMEM;
 593                 }
 594         }
 595
 596         return 0;
 597 }
 598
 599 static void __init __pci_mmcfg_init(int early)
 600 {
 601         /* MMCONFIG disabled */
 602         if ((pci_probe & PCI_PROBE_MMCONF) == 0)
 603                 return;
 604
 605         /* MMCONFIG already enabled */
 606         if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
 607                 return;
 608
 609         /* for late to exit */
 610         if (known_bridge)
 611                 return;
 612
 613         if (early) {
 614                 if (pci_mmcfg_check_hostbridge())
 615                         known_bridge = 1;
 616         }
 617
 618         if (!known_bridge)
 619                 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
 620
 621         pci_mmcfg_reject_broken(early);
 622
 623         if (pci_mmcfg_config_num == 0)
 624                 return;
 625
 626         if (pci_mmcfg_arch_init())
 627                 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
 628         else {
 629                 /*
 630                  * Signal not to attempt to insert mmcfg resources because
 631                  * the architecture mmcfg setup could not initialize.
 632                  */
 633                 pci_mmcfg_resources_inserted = 1;
 634         }
 635 }
 636
 637 void __init pci_mmcfg_early_init(void)
 638 {
 639         __pci_mmcfg_init(1);
 640 }
 641
 642 void __init pci_mmcfg_late_init(void)
 643 {
 644         __pci_mmcfg_init(0);
 645 }
 646
 647 static int __init pci_mmcfg_late_insert_resources(void)
 648 {
 649         /*
 650          * If resources are already inserted or we are not using MMCONFIG,
 651          * don't insert the resources.
 652          */
 653         if ((pci_mmcfg_resources_inserted == 1) ||
 654             (pci_probe & PCI_PROBE_MMCONF) == 0 ||
 655             (pci_mmcfg_config_num == 0))
 656                 return 1;
 657
 658         /*
 659          * Attempt to insert the mmcfg resources but not with the busy flag
 660          * marked so it won't cause request errors when __request_region is
 661          * called.
 662          */
 663         pci_mmcfg_insert_resources();
 664
 665         return 0;
 666 }
 667
 668 /*
 669  * Perform MMCONFIG resource insertion after PCI initialization to allow for
 670  * misprogrammed MCFG tables that state larger sizes but actually conflict
 671  * with other system resources.
 672  */
 673 late_initcall(pci_mmcfg_late_insert_resources);