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IB/ipath: add new minor device to allow sending of diag packets
[linux-2.6/x86.git] / drivers / net / 8139too.c
blobe4f4eaff76792292abe07865d7fcdbae34ac59de
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.27"
94
95
96 #include <linux/module.h>
97 #include <linux/kernel.h>
98 #include <linux/compiler.h>
99 #include <linux/pci.h>
100 #include <linux/init.h>
101 #include <linux/ioport.h>
102 #include <linux/netdevice.h>
103 #include <linux/etherdevice.h>
104 #include <linux/rtnetlink.h>
105 #include <linux/delay.h>
106 #include <linux/ethtool.h>
107 #include <linux/mii.h>
108 #include <linux/completion.h>
109 #include <linux/crc32.h>
110 #include <asm/io.h>
111 #include <asm/uaccess.h>
112 #include <asm/irq.h>
113
114 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
115 #define PFX DRV_NAME ": "
116
117 /* Default Message level */
118 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
119 NETIF_MSG_PROBE | \
120 NETIF_MSG_LINK)
121
122
123 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
124 #ifdef CONFIG_8139TOO_PIO
125 #define USE_IO_OPS 1
126 #endif
127
128 /* define to 1, 2 or 3 to enable copious debugging info */
129 #define RTL8139_DEBUG 0
130
131 /* define to 1 to disable lightweight runtime debugging checks */
132 #undef RTL8139_NDEBUG
133
134
135 #if RTL8139_DEBUG
136 /* note: prints function name for you */
137 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
138 #else
139 # define DPRINTK(fmt, args...)
140 #endif
141
142 #ifdef RTL8139_NDEBUG
143 # define assert(expr) do {} while (0)
144 #else
145 # define assert(expr) \
146 if(unlikely(!(expr))) { \
147 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
148 #expr,__FILE__,__FUNCTION__,__LINE__); \
149 }
150 #endif
151
152
153 /* A few user-configurable values. */
154 /* media options */
155 #define MAX_UNITS 8
156 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
157 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
158
159 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
160 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
161 static int multicast_filter_limit = 32;
162
163 /* bitmapped message enable number */
164 static int debug = -1;
165
166 /*
167 * Receive ring size
168 * Warning: 64K ring has hardware issues and may lock up.
169 */
170 #if defined(CONFIG_SH_DREAMCAST)
171 #define RX_BUF_IDX 1 /* 16K ring */
172 #else
173 #define RX_BUF_IDX 2 /* 32K ring */
174 #endif
175 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
176 #define RX_BUF_PAD 16
177 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
178
179 #if RX_BUF_LEN == 65536
180 #define RX_BUF_TOT_LEN RX_BUF_LEN
181 #else
182 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
183 #endif
184
185 /* Number of Tx descriptor registers. */
186 #define NUM_TX_DESC 4
187
188 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
189 #define MAX_ETH_FRAME_SIZE 1536
190
191 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
192 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
193 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
194
195 /* PCI Tuning Parameters
196 Threshold is bytes transferred to chip before transmission starts. */
197 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
198
199 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
200 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
201 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
202 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
203 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
204
205 /* Operational parameters that usually are not changed. */
206 /* Time in jiffies before concluding the transmitter is hung. */
207 #define TX_TIMEOUT (6*HZ)
208
209
210 enum {
211 HAS_MII_XCVR = 0x010000,
212 HAS_CHIP_XCVR = 0x020000,
213 HAS_LNK_CHNG = 0x040000,
214 };
215
216 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
217 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
218 #define RTL_MIN_IO_SIZE 0x80
219 #define RTL8139B_IO_SIZE 256
220
221 #define RTL8129_CAPS HAS_MII_XCVR
222 #define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
223
224 typedef enum {
225 RTL8139 = 0,
226 RTL8129,
227 } board_t;
228
229
230 /* indexed by board_t, above */
231 static const struct {
232 const char *name;
233 u32 hw_flags;
234 } board_info[] __devinitdata = {
235 { "RealTek RTL8139", RTL8139_CAPS },
236 { "RealTek RTL8129", RTL8129_CAPS },
237 };
238
239
240 static struct pci_device_id rtl8139_pci_tbl[] = {
241 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
242 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260
261 #ifdef CONFIG_SH_SECUREEDGE5410
262 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
263 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
264 #endif
265 #ifdef CONFIG_8139TOO_8129
266 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
267 #endif
268
269 /* some crazy cards report invalid vendor ids like
270 * 0x0001 here. The other ids are valid and constant,
271 * so we simply don't match on the main vendor id.
272 */
273 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
274 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
275 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
276
277 {0,}
278 };
279 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
280
281 static struct {
282 const char str[ETH_GSTRING_LEN];
283 } ethtool_stats_keys[] = {
284 { "early_rx" },
285 { "tx_buf_mapped" },
286 { "tx_timeouts" },
287 { "rx_lost_in_ring" },
288 };
289
290 /* The rest of these values should never change. */
291
292 /* Symbolic offsets to registers. */
293 enum RTL8139_registers {
294 MAC0 = 0, /* Ethernet hardware address. */
295 MAR0 = 8, /* Multicast filter. */
296 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
297 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
298 RxBuf = 0x30,
299 ChipCmd = 0x37,
300 RxBufPtr = 0x38,
301 RxBufAddr = 0x3A,
302 IntrMask = 0x3C,
303 IntrStatus = 0x3E,
304 TxConfig = 0x40,
305 RxConfig = 0x44,
306 Timer = 0x48, /* A general-purpose counter. */
307 RxMissed = 0x4C, /* 24 bits valid, write clears. */
308 Cfg9346 = 0x50,
309 Config0 = 0x51,
310 Config1 = 0x52,
311 FlashReg = 0x54,
312 MediaStatus = 0x58,
313 Config3 = 0x59,
314 Config4 = 0x5A, /* absent on RTL-8139A */
315 HltClk = 0x5B,
316 MultiIntr = 0x5C,
317 TxSummary = 0x60,
318 BasicModeCtrl = 0x62,
319 BasicModeStatus = 0x64,
320 NWayAdvert = 0x66,
321 NWayLPAR = 0x68,
322 NWayExpansion = 0x6A,
323 /* Undocumented registers, but required for proper operation. */
324 FIFOTMS = 0x70, /* FIFO Control and test. */
325 CSCR = 0x74, /* Chip Status and Configuration Register. */
326 PARA78 = 0x78,
327 PARA7c = 0x7c, /* Magic transceiver parameter register. */
328 Config5 = 0xD8, /* absent on RTL-8139A */
329 };
330
331 enum ClearBitMasks {
332 MultiIntrClear = 0xF000,
333 ChipCmdClear = 0xE2,
334 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
335 };
336
337 enum ChipCmdBits {
338 CmdReset = 0x10,
339 CmdRxEnb = 0x08,
340 CmdTxEnb = 0x04,
341 RxBufEmpty = 0x01,
342 };
343
344 /* Interrupt register bits, using my own meaningful names. */
345 enum IntrStatusBits {
346 PCIErr = 0x8000,
347 PCSTimeout = 0x4000,
348 RxFIFOOver = 0x40,
349 RxUnderrun = 0x20,
350 RxOverflow = 0x10,
351 TxErr = 0x08,
352 TxOK = 0x04,
353 RxErr = 0x02,
354 RxOK = 0x01,
355
356 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
357 };
358
359 enum TxStatusBits {
360 TxHostOwns = 0x2000,
361 TxUnderrun = 0x4000,
362 TxStatOK = 0x8000,
363 TxOutOfWindow = 0x20000000,
364 TxAborted = 0x40000000,
365 TxCarrierLost = 0x80000000,
366 };
367 enum RxStatusBits {
368 RxMulticast = 0x8000,
369 RxPhysical = 0x4000,
370 RxBroadcast = 0x2000,
371 RxBadSymbol = 0x0020,
372 RxRunt = 0x0010,
373 RxTooLong = 0x0008,
374 RxCRCErr = 0x0004,
375 RxBadAlign = 0x0002,
376 RxStatusOK = 0x0001,
377 };
378
379 /* Bits in RxConfig. */
380 enum rx_mode_bits {
381 AcceptErr = 0x20,
382 AcceptRunt = 0x10,
383 AcceptBroadcast = 0x08,
384 AcceptMulticast = 0x04,
385 AcceptMyPhys = 0x02,
386 AcceptAllPhys = 0x01,
387 };
388
389 /* Bits in TxConfig. */
390 enum tx_config_bits {
391
392 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
393 TxIFGShift = 24,
394 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
395 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
396 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
397 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
398
399 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
400 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
401 TxClearAbt = (1 << 0), /* Clear abort (WO) */
402 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
403 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
404
405 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
406 };
407
408 /* Bits in Config1 */
409 enum Config1Bits {
410 Cfg1_PM_Enable = 0x01,
411 Cfg1_VPD_Enable = 0x02,
412 Cfg1_PIO = 0x04,
413 Cfg1_MMIO = 0x08,
414 LWAKE = 0x10, /* not on 8139, 8139A */
415 Cfg1_Driver_Load = 0x20,
416 Cfg1_LED0 = 0x40,
417 Cfg1_LED1 = 0x80,
418 SLEEP = (1 << 1), /* only on 8139, 8139A */
419 PWRDN = (1 << 0), /* only on 8139, 8139A */
420 };
421
422 /* Bits in Config3 */
423 enum Config3Bits {
424 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
425 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
426 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
427 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
428 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
429 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
430 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
431 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
432 };
433
434 /* Bits in Config4 */
435 enum Config4Bits {
436 LWPTN = (1 << 2), /* not on 8139, 8139A */
437 };
438
439 /* Bits in Config5 */
440 enum Config5Bits {
441 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
442 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
443 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
444 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
445 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
446 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
447 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
448 };
449
450 enum RxConfigBits {
451 /* rx fifo threshold */
452 RxCfgFIFOShift = 13,
453 RxCfgFIFONone = (7 << RxCfgFIFOShift),
454
455 /* Max DMA burst */
456 RxCfgDMAShift = 8,
457 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
458
459 /* rx ring buffer length */
460 RxCfgRcv8K = 0,
461 RxCfgRcv16K = (1 << 11),
462 RxCfgRcv32K = (1 << 12),
463 RxCfgRcv64K = (1 << 11) | (1 << 12),
464
465 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
466 RxNoWrap = (1 << 7),
467 };
468
469 /* Twister tuning parameters from RealTek.
470 Completely undocumented, but required to tune bad links on some boards. */
471 enum CSCRBits {
472 CSCR_LinkOKBit = 0x0400,
473 CSCR_LinkChangeBit = 0x0800,
474 CSCR_LinkStatusBits = 0x0f000,
475 CSCR_LinkDownOffCmd = 0x003c0,
476 CSCR_LinkDownCmd = 0x0f3c0,
477 };
478
479 enum Cfg9346Bits {
480 Cfg9346_Lock = 0x00,
481 Cfg9346_Unlock = 0xC0,
482 };
483
484 typedef enum {
485 CH_8139 = 0,
486 CH_8139_K,
487 CH_8139A,
488 CH_8139A_G,
489 CH_8139B,
490 CH_8130,
491 CH_8139C,
492 CH_8100,
493 CH_8100B_8139D,
494 CH_8101,
495 } chip_t;
496
497 enum chip_flags {
498 HasHltClk = (1 << 0),
499 HasLWake = (1 << 1),
500 };
501
502 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
503 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
504 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
505
506 /* directly indexed by chip_t, above */
507 static const struct {
508 const char *name;
509 u32 version; /* from RTL8139C/RTL8139D docs */
510 u32 flags;
511 } rtl_chip_info[] = {
512 { "RTL-8139",
513 HW_REVID(1, 0, 0, 0, 0, 0, 0),
514 HasHltClk,
515 },
516
517 { "RTL-8139 rev K",
518 HW_REVID(1, 1, 0, 0, 0, 0, 0),
519 HasHltClk,
520 },
521
522 { "RTL-8139A",
523 HW_REVID(1, 1, 1, 0, 0, 0, 0),
524 HasHltClk, /* XXX undocumented? */
525 },
526
527 { "RTL-8139A rev G",
528 HW_REVID(1, 1, 1, 0, 0, 1, 0),
529 HasHltClk, /* XXX undocumented? */
530 },
531
532 { "RTL-8139B",
533 HW_REVID(1, 1, 1, 1, 0, 0, 0),
534 HasLWake,
535 },
536
537 { "RTL-8130",
538 HW_REVID(1, 1, 1, 1, 1, 0, 0),
539 HasLWake,
540 },
541
542 { "RTL-8139C",
543 HW_REVID(1, 1, 1, 0, 1, 0, 0),
544 HasLWake,
545 },
546
547 { "RTL-8100",
548 HW_REVID(1, 1, 1, 1, 0, 1, 0),
549 HasLWake,
550 },
551
552 { "RTL-8100B/8139D",
553 HW_REVID(1, 1, 1, 0, 1, 0, 1),
554 HasHltClk /* XXX undocumented? */
555 | HasLWake,
556 },
557
558 { "RTL-8101",
559 HW_REVID(1, 1, 1, 0, 1, 1, 1),
560 HasLWake,
561 },
562 };
563
564 struct rtl_extra_stats {
565 unsigned long early_rx;
566 unsigned long tx_buf_mapped;
567 unsigned long tx_timeouts;
568 unsigned long rx_lost_in_ring;
569 };
570
571 struct rtl8139_private {
572 void __iomem *mmio_addr;
573 int drv_flags;
574 struct pci_dev *pci_dev;
575 u32 msg_enable;
576 struct net_device_stats stats;
577 unsigned char *rx_ring;
578 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
579 unsigned int tx_flag;
580 unsigned long cur_tx;
581 unsigned long dirty_tx;
582 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
583 unsigned char *tx_bufs; /* Tx bounce buffer region. */
584 dma_addr_t rx_ring_dma;
585 dma_addr_t tx_bufs_dma;
586 signed char phys[4]; /* MII device addresses. */
587 char twistie, twist_row, twist_col; /* Twister tune state. */
588 unsigned int watchdog_fired : 1;
589 unsigned int default_port : 4; /* Last dev->if_port value. */
590 unsigned int have_thread : 1;
591 spinlock_t lock;
592 spinlock_t rx_lock;
593 chip_t chipset;
594 u32 rx_config;
595 struct rtl_extra_stats xstats;
596
597 struct work_struct thread;
598
599 struct mii_if_info mii;
600 unsigned int regs_len;
601 unsigned long fifo_copy_timeout;
602 };
603
604 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
605 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
606 MODULE_LICENSE("GPL");
607 MODULE_VERSION(DRV_VERSION);
608
609 module_param(multicast_filter_limit, int, 0);
610 module_param_array(media, int, NULL, 0);
611 module_param_array(full_duplex, int, NULL, 0);
612 module_param(debug, int, 0);
613 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
614 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
615 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
616 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
617
618 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
619 static int rtl8139_open (struct net_device *dev);
620 static int mdio_read (struct net_device *dev, int phy_id, int location);
621 static void mdio_write (struct net_device *dev, int phy_id, int location,
622 int val);
623 static void rtl8139_start_thread(struct rtl8139_private *tp);
624 static void rtl8139_tx_timeout (struct net_device *dev);
625 static void rtl8139_init_ring (struct net_device *dev);
626 static int rtl8139_start_xmit (struct sk_buff *skb,
627 struct net_device *dev);
628 static int rtl8139_poll(struct net_device *dev, int *budget);
629 #ifdef CONFIG_NET_POLL_CONTROLLER
630 static void rtl8139_poll_controller(struct net_device *dev);
631 #endif
632 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
633 struct pt_regs *regs);
634 static int rtl8139_close (struct net_device *dev);
635 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
636 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
637 static void rtl8139_set_rx_mode (struct net_device *dev);
638 static void __set_rx_mode (struct net_device *dev);
639 static void rtl8139_hw_start (struct net_device *dev);
640 static void rtl8139_thread (void *_data);
641 static void rtl8139_tx_timeout_task(void *_data);
642 static struct ethtool_ops rtl8139_ethtool_ops;
643
644 /* write MMIO register, with flush */
645 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
646 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
647 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
648 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
649
650
651 #define MMIO_FLUSH_AUDIT_COMPLETE 1
652 #if MMIO_FLUSH_AUDIT_COMPLETE
653
654 /* write MMIO register */
655 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
656 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
657 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
658
659 #else
660
661 /* write MMIO register, then flush */
662 #define RTL_W8 RTL_W8_F
663 #define RTL_W16 RTL_W16_F
664 #define RTL_W32 RTL_W32_F
665
666 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
667
668 /* read MMIO register */
669 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
670 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
671 #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
672
673
674 static const u16 rtl8139_intr_mask =
675 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
676 TxErr | TxOK | RxErr | RxOK;
677
678 static const u16 rtl8139_norx_intr_mask =
679 PCIErr | PCSTimeout | RxUnderrun |
680 TxErr | TxOK | RxErr ;
681
682 #if RX_BUF_IDX == 0
683 static const unsigned int rtl8139_rx_config =
684 RxCfgRcv8K | RxNoWrap |
685 (RX_FIFO_THRESH << RxCfgFIFOShift) |
686 (RX_DMA_BURST << RxCfgDMAShift);
687 #elif RX_BUF_IDX == 1
688 static const unsigned int rtl8139_rx_config =
689 RxCfgRcv16K | RxNoWrap |
690 (RX_FIFO_THRESH << RxCfgFIFOShift) |
691 (RX_DMA_BURST << RxCfgDMAShift);
692 #elif RX_BUF_IDX == 2
693 static const unsigned int rtl8139_rx_config =
694 RxCfgRcv32K | RxNoWrap |
695 (RX_FIFO_THRESH << RxCfgFIFOShift) |
696 (RX_DMA_BURST << RxCfgDMAShift);
697 #elif RX_BUF_IDX == 3
698 static const unsigned int rtl8139_rx_config =
699 RxCfgRcv64K |
700 (RX_FIFO_THRESH << RxCfgFIFOShift) |
701 (RX_DMA_BURST << RxCfgDMAShift);
702 #else
703 #error "Invalid configuration for 8139_RXBUF_IDX"
704 #endif
705
706 static const unsigned int rtl8139_tx_config =
707 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
708
709 static void __rtl8139_cleanup_dev (struct net_device *dev)
710 {
711 struct rtl8139_private *tp = netdev_priv(dev);
712 struct pci_dev *pdev;
713
714 assert (dev != NULL);
715 assert (tp->pci_dev != NULL);
716 pdev = tp->pci_dev;
717
718 #ifdef USE_IO_OPS
719 if (tp->mmio_addr)
720 ioport_unmap (tp->mmio_addr);
721 #else
722 if (tp->mmio_addr)
723 pci_iounmap (pdev, tp->mmio_addr);
724 #endif /* USE_IO_OPS */
725
726 /* it's ok to call this even if we have no regions to free */
727 pci_release_regions (pdev);
728
729 free_netdev(dev);
730 pci_set_drvdata (pdev, NULL);
731 }
732
733
734 static void rtl8139_chip_reset (void __iomem *ioaddr)
735 {
736 int i;
737
738 /* Soft reset the chip. */
739 RTL_W8 (ChipCmd, CmdReset);
740
741 /* Check that the chip has finished the reset. */
742 for (i = 1000; i > 0; i--) {
743 barrier();
744 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
745 break;
746 udelay (10);
747 }
748 }
749
750
751 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
752 struct net_device **dev_out)
753 {
754 void __iomem *ioaddr;
755 struct net_device *dev;
756 struct rtl8139_private *tp;
757 u8 tmp8;
758 int rc, disable_dev_on_err = 0;
759 unsigned int i;
760 unsigned long pio_start, pio_end, pio_flags, pio_len;
761 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
762 u32 version;
763
764 assert (pdev != NULL);
765
766 *dev_out = NULL;
767
768 /* dev and priv zeroed in alloc_etherdev */
769 dev = alloc_etherdev (sizeof (*tp));
770 if (dev == NULL) {
771 dev_err(&pdev->dev, "Unable to alloc new net device\n");
772 return -ENOMEM;
773 }
774 SET_MODULE_OWNER(dev);
775 SET_NETDEV_DEV(dev, &pdev->dev);
776
777 tp = netdev_priv(dev);
778 tp->pci_dev = pdev;
779
780 /* enable device (incl. PCI PM wakeup and hotplug setup) */
781 rc = pci_enable_device (pdev);
782 if (rc)
783 goto err_out;
784
785 pio_start = pci_resource_start (pdev, 0);
786 pio_end = pci_resource_end (pdev, 0);
787 pio_flags = pci_resource_flags (pdev, 0);
788 pio_len = pci_resource_len (pdev, 0);
789
790 mmio_start = pci_resource_start (pdev, 1);
791 mmio_end = pci_resource_end (pdev, 1);
792 mmio_flags = pci_resource_flags (pdev, 1);
793 mmio_len = pci_resource_len (pdev, 1);
794
795 /* set this immediately, we need to know before
796 * we talk to the chip directly */
797 DPRINTK("PIO region size == 0x%02X\n", pio_len);
798 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
799
800 #ifdef USE_IO_OPS
801 /* make sure PCI base addr 0 is PIO */
802 if (!(pio_flags & IORESOURCE_IO)) {
803 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
804 rc = -ENODEV;
805 goto err_out;
806 }
807 /* check for weird/broken PCI region reporting */
808 if (pio_len < RTL_MIN_IO_SIZE) {
809 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");
810 rc = -ENODEV;
811 goto err_out;
812 }
813 #else
814 /* make sure PCI base addr 1 is MMIO */
815 if (!(mmio_flags & IORESOURCE_MEM)) {
816 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
817 rc = -ENODEV;
818 goto err_out;
819 }
820 if (mmio_len < RTL_MIN_IO_SIZE) {
821 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");
822 rc = -ENODEV;
823 goto err_out;
824 }
825 #endif
826
827 rc = pci_request_regions (pdev, DRV_NAME);
828 if (rc)
829 goto err_out;
830 disable_dev_on_err = 1;
831
832 /* enable PCI bus-mastering */
833 pci_set_master (pdev);
834
835 #ifdef USE_IO_OPS
836 ioaddr = ioport_map(pio_start, pio_len);
837 if (!ioaddr) {
838 dev_err(&pdev->dev, "cannot map PIO, aborting\n");
839 rc = -EIO;
840 goto err_out;
841 }
842 dev->base_addr = pio_start;
843 tp->mmio_addr = ioaddr;
844 tp->regs_len = pio_len;
845 #else
846 /* ioremap MMIO region */
847 ioaddr = pci_iomap(pdev, 1, 0);
848 if (ioaddr == NULL) {
849 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
850 rc = -EIO;
851 goto err_out;
852 }
853 dev->base_addr = (long) ioaddr;
854 tp->mmio_addr = ioaddr;
855 tp->regs_len = mmio_len;
856 #endif /* USE_IO_OPS */
857
858 /* Bring old chips out of low-power mode. */
859 RTL_W8 (HltClk, 'R');
860
861 /* check for missing/broken hardware */
862 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
863 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
864 rc = -EIO;
865 goto err_out;
866 }
867
868 /* identify chip attached to board */
869 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
870 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
871 if (version == rtl_chip_info[i].version) {
872 tp->chipset = i;
873 goto match;
874 }
875
876 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
877 dev_printk (KERN_DEBUG, &pdev->dev,
878 "unknown chip version, assuming RTL-8139\n");
879 dev_printk (KERN_DEBUG, &pdev->dev,
880 "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));
881 tp->chipset = 0;
882
883 match:
884 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
885 version, i, rtl_chip_info[i].name);
886
887 if (tp->chipset >= CH_8139B) {
888 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
889 DPRINTK("PCI PM wakeup\n");
890 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
891 (tmp8 & LWAKE))
892 new_tmp8 &= ~LWAKE;
893 new_tmp8 |= Cfg1_PM_Enable;
894 if (new_tmp8 != tmp8) {
895 RTL_W8 (Cfg9346, Cfg9346_Unlock);
896 RTL_W8 (Config1, tmp8);
897 RTL_W8 (Cfg9346, Cfg9346_Lock);
898 }
899 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
900 tmp8 = RTL_R8 (Config4);
901 if (tmp8 & LWPTN) {
902 RTL_W8 (Cfg9346, Cfg9346_Unlock);
903 RTL_W8 (Config4, tmp8 & ~LWPTN);
904 RTL_W8 (Cfg9346, Cfg9346_Lock);
905 }
906 }
907 } else {
908 DPRINTK("Old chip wakeup\n");
909 tmp8 = RTL_R8 (Config1);
910 tmp8 &= ~(SLEEP | PWRDN);
911 RTL_W8 (Config1, tmp8);
912 }
913
914 rtl8139_chip_reset (ioaddr);
915
916 *dev_out = dev;
917 return 0;
918
919 err_out:
920 __rtl8139_cleanup_dev (dev);
921 if (disable_dev_on_err)
922 pci_disable_device (pdev);
923 return rc;
924 }
925
926
927 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
928 const struct pci_device_id *ent)
929 {
930 struct net_device *dev = NULL;
931 struct rtl8139_private *tp;
932 int i, addr_len, option;
933 void __iomem *ioaddr;
934 static int board_idx = -1;
935 u8 pci_rev;
936
937 assert (pdev != NULL);
938 assert (ent != NULL);
939
940 board_idx++;
941
942 /* when we're built into the kernel, the driver version message
943 * is only printed if at least one 8139 board has been found
944 */
945 #ifndef MODULE
946 {
947 static int printed_version;
948 if (!printed_version++)
949 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
950 }
951 #endif
952
953 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
954
955 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
956 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {
957 dev_info(&pdev->dev,
958 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
959 pdev->vendor, pdev->device, pci_rev);
960 dev_info(&pdev->dev,
961 "Use the \"8139cp\" driver for improved performance and stability.\n");
962 }
963
964 i = rtl8139_init_board (pdev, &dev);
965 if (i < 0)
966 return i;
967
968 assert (dev != NULL);
969 tp = netdev_priv(dev);
970
971 ioaddr = tp->mmio_addr;
972 assert (ioaddr != NULL);
973
974 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
975 for (i = 0; i < 3; i++)
976 ((u16 *) (dev->dev_addr))[i] =
977 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
978 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
979
980 /* The Rtl8139-specific entries in the device structure. */
981 dev->open = rtl8139_open;
982 dev->hard_start_xmit = rtl8139_start_xmit;
983 dev->poll = rtl8139_poll;
984 dev->weight = 64;
985 dev->stop = rtl8139_close;
986 dev->get_stats = rtl8139_get_stats;
987 dev->set_multicast_list = rtl8139_set_rx_mode;
988 dev->do_ioctl = netdev_ioctl;
989 dev->ethtool_ops = &rtl8139_ethtool_ops;
990 dev->tx_timeout = rtl8139_tx_timeout;
991 dev->watchdog_timeo = TX_TIMEOUT;
992 #ifdef CONFIG_NET_POLL_CONTROLLER
993 dev->poll_controller = rtl8139_poll_controller;
994 #endif
995
996 /* note: the hardware is not capable of sg/csum/highdma, however
997 * through the use of skb_copy_and_csum_dev we enable these
998 * features
999 */
1000 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1001
1002 dev->irq = pdev->irq;
1003
1004 /* tp zeroed and aligned in alloc_etherdev */
1005 tp = netdev_priv(dev);
1006
1007 /* note: tp->chipset set in rtl8139_init_board */
1008 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1009 tp->mmio_addr = ioaddr;
1010 tp->msg_enable =
1011 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1012 spin_lock_init (&tp->lock);
1013 spin_lock_init (&tp->rx_lock);
1014 INIT_WORK(&tp->thread, rtl8139_thread, dev);
1015 tp->mii.dev = dev;
1016 tp->mii.mdio_read = mdio_read;
1017 tp->mii.mdio_write = mdio_write;
1018 tp->mii.phy_id_mask = 0x3f;
1019 tp->mii.reg_num_mask = 0x1f;
1020
1021 /* dev is fully set up and ready to use now */
1022 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1023 i = register_netdev (dev);
1024 if (i) goto err_out;
1025
1026 pci_set_drvdata (pdev, dev);
1027
1028 printk (KERN_INFO "%s: %s at 0x%lx, "
1029 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1030 "IRQ %d\n",
1031 dev->name,
1032 board_info[ent->driver_data].name,
1033 dev->base_addr,
1034 dev->dev_addr[0], dev->dev_addr[1],
1035 dev->dev_addr[2], dev->dev_addr[3],
1036 dev->dev_addr[4], dev->dev_addr[5],
1037 dev->irq);
1038
1039 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1040 dev->name, rtl_chip_info[tp->chipset].name);
1041
1042 /* Find the connected MII xcvrs.
1043 Doing this in open() would allow detecting external xcvrs later, but
1044 takes too much time. */
1045 #ifdef CONFIG_8139TOO_8129
1046 if (tp->drv_flags & HAS_MII_XCVR) {
1047 int phy, phy_idx = 0;
1048 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1049 int mii_status = mdio_read(dev, phy, 1);
1050 if (mii_status != 0xffff && mii_status != 0x0000) {
1051 u16 advertising = mdio_read(dev, phy, 4);
1052 tp->phys[phy_idx++] = phy;
1053 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1054 "advertising %4.4x.\n",
1055 dev->name, phy, mii_status, advertising);
1056 }
1057 }
1058 if (phy_idx == 0) {
1059 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1060 "transceiver.\n",
1061 dev->name);
1062 tp->phys[0] = 32;
1063 }
1064 } else
1065 #endif
1066 tp->phys[0] = 32;
1067 tp->mii.phy_id = tp->phys[0];
1068
1069 /* The lower four bits are the media type. */
1070 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1071 if (option > 0) {
1072 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1073 tp->default_port = option & 0xFF;
1074 if (tp->default_port)
1075 tp->mii.force_media = 1;
1076 }
1077 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1078 tp->mii.full_duplex = full_duplex[board_idx];
1079 if (tp->mii.full_duplex) {
1080 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1081 /* Changing the MII-advertised media because might prevent
1082 re-connection. */
1083 tp->mii.force_media = 1;
1084 }
1085 if (tp->default_port) {
1086 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1087 (option & 0x20 ? 100 : 10),
1088 (option & 0x10 ? "full" : "half"));
1089 mdio_write(dev, tp->phys[0], 0,
1090 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1091 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1092 }
1093
1094 /* Put the chip into low-power mode. */
1095 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1096 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1097
1098 return 0;
1099
1100 err_out:
1101 __rtl8139_cleanup_dev (dev);
1102 pci_disable_device (pdev);
1103 return i;
1104 }
1105
1106
1107 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1108 {
1109 struct net_device *dev = pci_get_drvdata (pdev);
1110
1111 assert (dev != NULL);
1112
1113 unregister_netdev (dev);
1114
1115 __rtl8139_cleanup_dev (dev);
1116 pci_disable_device (pdev);
1117 }
1118
1119
1120 /* Serial EEPROM section. */
1121
1122 /* EEPROM_Ctrl bits. */
1123 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1124 #define EE_CS 0x08 /* EEPROM chip select. */
1125 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1126 #define EE_WRITE_0 0x00
1127 #define EE_WRITE_1 0x02
1128 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1129 #define EE_ENB (0x80 | EE_CS)
1130
1131 /* Delay between EEPROM clock transitions.
1132 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1133 */
1134
1135 #define eeprom_delay() (void)RTL_R32(Cfg9346)
1136
1137 /* The EEPROM commands include the alway-set leading bit. */
1138 #define EE_WRITE_CMD (5)
1139 #define EE_READ_CMD (6)
1140 #define EE_ERASE_CMD (7)
1141
1142 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1143 {
1144 int i;
1145 unsigned retval = 0;
1146 int read_cmd = location | (EE_READ_CMD << addr_len);
1147
1148 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1149 RTL_W8 (Cfg9346, EE_ENB);
1150 eeprom_delay ();
1151
1152 /* Shift the read command bits out. */
1153 for (i = 4 + addr_len; i >= 0; i--) {
1154 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1155 RTL_W8 (Cfg9346, EE_ENB | dataval);
1156 eeprom_delay ();
1157 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1158 eeprom_delay ();
1159 }
1160 RTL_W8 (Cfg9346, EE_ENB);
1161 eeprom_delay ();
1162
1163 for (i = 16; i > 0; i--) {
1164 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1165 eeprom_delay ();
1166 retval =
1167 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1168 0);
1169 RTL_W8 (Cfg9346, EE_ENB);
1170 eeprom_delay ();
1171 }
1172
1173 /* Terminate the EEPROM access. */
1174 RTL_W8 (Cfg9346, ~EE_CS);
1175 eeprom_delay ();
1176
1177 return retval;
1178 }
1179
1180 /* MII serial management: mostly bogus for now. */
1181 /* Read and write the MII management registers using software-generated
1182 serial MDIO protocol.
1183 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1184 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1185 "overclocking" issues. */
1186 #define MDIO_DIR 0x80
1187 #define MDIO_DATA_OUT 0x04
1188 #define MDIO_DATA_IN 0x02
1189 #define MDIO_CLK 0x01
1190 #define MDIO_WRITE0 (MDIO_DIR)
1191 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1192
1193 #define mdio_delay() RTL_R8(Config4)
1194
1195
1196 static const char mii_2_8139_map[8] = {
1197 BasicModeCtrl,
1198 BasicModeStatus,
1199 0,
1200 0,
1201 NWayAdvert,
1202 NWayLPAR,
1203 NWayExpansion,
1204 0
1205 };
1206
1207
1208 #ifdef CONFIG_8139TOO_8129
1209 /* Syncronize the MII management interface by shifting 32 one bits out. */
1210 static void mdio_sync (void __iomem *ioaddr)
1211 {
1212 int i;
1213
1214 for (i = 32; i >= 0; i--) {
1215 RTL_W8 (Config4, MDIO_WRITE1);
1216 mdio_delay ();
1217 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1218 mdio_delay ();
1219 }
1220 }
1221 #endif
1222
1223 static int mdio_read (struct net_device *dev, int phy_id, int location)
1224 {
1225 struct rtl8139_private *tp = netdev_priv(dev);
1226 int retval = 0;
1227 #ifdef CONFIG_8139TOO_8129
1228 void __iomem *ioaddr = tp->mmio_addr;
1229 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1230 int i;
1231 #endif
1232
1233 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1234 void __iomem *ioaddr = tp->mmio_addr;
1235 return location < 8 && mii_2_8139_map[location] ?
1236 RTL_R16 (mii_2_8139_map[location]) : 0;
1237 }
1238
1239 #ifdef CONFIG_8139TOO_8129
1240 mdio_sync (ioaddr);
1241 /* Shift the read command bits out. */
1242 for (i = 15; i >= 0; i--) {
1243 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1244
1245 RTL_W8 (Config4, MDIO_DIR | dataval);
1246 mdio_delay ();
1247 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1248 mdio_delay ();
1249 }
1250
1251 /* Read the two transition, 16 data, and wire-idle bits. */
1252 for (i = 19; i > 0; i--) {
1253 RTL_W8 (Config4, 0);
1254 mdio_delay ();
1255 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1256 RTL_W8 (Config4, MDIO_CLK);
1257 mdio_delay ();
1258 }
1259 #endif
1260
1261 return (retval >> 1) & 0xffff;
1262 }
1263
1264
1265 static void mdio_write (struct net_device *dev, int phy_id, int location,
1266 int value)
1267 {
1268 struct rtl8139_private *tp = netdev_priv(dev);
1269 #ifdef CONFIG_8139TOO_8129
1270 void __iomem *ioaddr = tp->mmio_addr;
1271 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1272 int i;
1273 #endif
1274
1275 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1276 void __iomem *ioaddr = tp->mmio_addr;
1277 if (location == 0) {
1278 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1279 RTL_W16 (BasicModeCtrl, value);
1280 RTL_W8 (Cfg9346, Cfg9346_Lock);
1281 } else if (location < 8 && mii_2_8139_map[location])
1282 RTL_W16 (mii_2_8139_map[location], value);
1283 return;
1284 }
1285
1286 #ifdef CONFIG_8139TOO_8129
1287 mdio_sync (ioaddr);
1288
1289 /* Shift the command bits out. */
1290 for (i = 31; i >= 0; i--) {
1291 int dataval =
1292 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1293 RTL_W8 (Config4, dataval);
1294 mdio_delay ();
1295 RTL_W8 (Config4, dataval | MDIO_CLK);
1296 mdio_delay ();
1297 }
1298 /* Clear out extra bits. */
1299 for (i = 2; i > 0; i--) {
1300 RTL_W8 (Config4, 0);
1301 mdio_delay ();
1302 RTL_W8 (Config4, MDIO_CLK);
1303 mdio_delay ();
1304 }
1305 #endif
1306 }
1307
1308
1309 static int rtl8139_open (struct net_device *dev)
1310 {
1311 struct rtl8139_private *tp = netdev_priv(dev);
1312 int retval;
1313 void __iomem *ioaddr = tp->mmio_addr;
1314
1315 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1316 if (retval)
1317 return retval;
1318
1319 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1320 &tp->tx_bufs_dma);
1321 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1322 &tp->rx_ring_dma);
1323 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1324 free_irq(dev->irq, dev);
1325
1326 if (tp->tx_bufs)
1327 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1328 tp->tx_bufs, tp->tx_bufs_dma);
1329 if (tp->rx_ring)
1330 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1331 tp->rx_ring, tp->rx_ring_dma);
1332
1333 return -ENOMEM;
1334
1335 }
1336
1337 tp->mii.full_duplex = tp->mii.force_media;
1338 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1339
1340 rtl8139_init_ring (dev);
1341 rtl8139_hw_start (dev);
1342 netif_start_queue (dev);
1343
1344 if (netif_msg_ifup(tp))
1345 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#llx IRQ %d"
1346 " GP Pins %2.2x %s-duplex.\n", dev->name,
1347 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1348 dev->irq, RTL_R8 (MediaStatus),
1349 tp->mii.full_duplex ? "full" : "half");
1350
1351 rtl8139_start_thread(tp);
1352
1353 return 0;
1354 }
1355
1356
1357 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1358 {
1359 struct rtl8139_private *tp = netdev_priv(dev);
1360
1361 if (tp->phys[0] >= 0) {
1362 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1363 }
1364 }
1365
1366 /* Start the hardware at open or resume. */
1367 static void rtl8139_hw_start (struct net_device *dev)
1368 {
1369 struct rtl8139_private *tp = netdev_priv(dev);
1370 void __iomem *ioaddr = tp->mmio_addr;
1371 u32 i;
1372 u8 tmp;
1373
1374 /* Bring old chips out of low-power mode. */
1375 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1376 RTL_W8 (HltClk, 'R');
1377
1378 rtl8139_chip_reset (ioaddr);
1379
1380 /* unlock Config[01234] and BMCR register writes */
1381 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1382 /* Restore our idea of the MAC address. */
1383 RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1384 RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1385
1386 /* Must enable Tx/Rx before setting transfer thresholds! */
1387 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1388
1389 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1390 RTL_W32 (RxConfig, tp->rx_config);
1391 RTL_W32 (TxConfig, rtl8139_tx_config);
1392
1393 tp->cur_rx = 0;
1394
1395 rtl_check_media (dev, 1);
1396
1397 if (tp->chipset >= CH_8139B) {
1398 /* Disable magic packet scanning, which is enabled
1399 * when PM is enabled in Config1. It can be reenabled
1400 * via ETHTOOL_SWOL if desired. */
1401 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1402 }
1403
1404 DPRINTK("init buffer addresses\n");
1405
1406 /* Lock Config[01234] and BMCR register writes */
1407 RTL_W8 (Cfg9346, Cfg9346_Lock);
1408
1409 /* init Rx ring buffer DMA address */
1410 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1411
1412 /* init Tx buffer DMA addresses */
1413 for (i = 0; i < NUM_TX_DESC; i++)
1414 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1415
1416 RTL_W32 (RxMissed, 0);
1417
1418 rtl8139_set_rx_mode (dev);
1419
1420 /* no early-rx interrupts */
1421 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1422
1423 /* make sure RxTx has started */
1424 tmp = RTL_R8 (ChipCmd);
1425 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1426 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1427
1428 /* Enable all known interrupts by setting the interrupt mask. */
1429 RTL_W16 (IntrMask, rtl8139_intr_mask);
1430 }
1431
1432
1433 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1434 static void rtl8139_init_ring (struct net_device *dev)
1435 {
1436 struct rtl8139_private *tp = netdev_priv(dev);
1437 int i;
1438
1439 tp->cur_rx = 0;
1440 tp->cur_tx = 0;
1441 tp->dirty_tx = 0;
1442
1443 for (i = 0; i < NUM_TX_DESC; i++)
1444 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1445 }
1446
1447
1448 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1449 static int next_tick = 3 * HZ;
1450
1451 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1452 static inline void rtl8139_tune_twister (struct net_device *dev,
1453 struct rtl8139_private *tp) {}
1454 #else
1455 enum TwisterParamVals {
1456 PARA78_default = 0x78fa8388,
1457 PARA7c_default = 0xcb38de43, /* param[0][3] */
1458 PARA7c_xxx = 0xcb38de43,
1459 };
1460
1461 static const unsigned long param[4][4] = {
1462 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1463 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1464 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1465 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1466 };
1467
1468 static void rtl8139_tune_twister (struct net_device *dev,
1469 struct rtl8139_private *tp)
1470 {
1471 int linkcase;
1472 void __iomem *ioaddr = tp->mmio_addr;
1473
1474 /* This is a complicated state machine to configure the "twister" for
1475 impedance/echos based on the cable length.
1476 All of this is magic and undocumented.
1477 */
1478 switch (tp->twistie) {
1479 case 1:
1480 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1481 /* We have link beat, let us tune the twister. */
1482 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1483 tp->twistie = 2; /* Change to state 2. */
1484 next_tick = HZ / 10;
1485 } else {
1486 /* Just put in some reasonable defaults for when beat returns. */
1487 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1488 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1489 RTL_W32 (PARA78, PARA78_default);
1490 RTL_W32 (PARA7c, PARA7c_default);
1491 tp->twistie = 0; /* Bail from future actions. */
1492 }
1493 break;
1494 case 2:
1495 /* Read how long it took to hear the echo. */
1496 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1497 if (linkcase == 0x7000)
1498 tp->twist_row = 3;
1499 else if (linkcase == 0x3000)
1500 tp->twist_row = 2;
1501 else if (linkcase == 0x1000)
1502 tp->twist_row = 1;
1503 else
1504 tp->twist_row = 0;
1505 tp->twist_col = 0;
1506 tp->twistie = 3; /* Change to state 2. */
1507 next_tick = HZ / 10;
1508 break;
1509 case 3:
1510 /* Put out four tuning parameters, one per 100msec. */
1511 if (tp->twist_col == 0)
1512 RTL_W16 (FIFOTMS, 0);
1513 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1514 [(int) tp->twist_col]);
1515 next_tick = HZ / 10;
1516 if (++tp->twist_col >= 4) {
1517 /* For short cables we are done.
1518 For long cables (row == 3) check for mistune. */
1519 tp->twistie =
1520 (tp->twist_row == 3) ? 4 : 0;
1521 }
1522 break;
1523 case 4:
1524 /* Special case for long cables: check for mistune. */
1525 if ((RTL_R16 (CSCR) &
1526 CSCR_LinkStatusBits) == 0x7000) {
1527 tp->twistie = 0;
1528 break;
1529 } else {
1530 RTL_W32 (PARA7c, 0xfb38de03);
1531 tp->twistie = 5;
1532 next_tick = HZ / 10;
1533 }
1534 break;
1535 case 5:
1536 /* Retune for shorter cable (column 2). */
1537 RTL_W32 (FIFOTMS, 0x20);
1538 RTL_W32 (PARA78, PARA78_default);
1539 RTL_W32 (PARA7c, PARA7c_default);
1540 RTL_W32 (FIFOTMS, 0x00);
1541 tp->twist_row = 2;
1542 tp->twist_col = 0;
1543 tp->twistie = 3;
1544 next_tick = HZ / 10;
1545 break;
1546
1547 default:
1548 /* do nothing */
1549 break;
1550 }
1551 }
1552 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1553
1554 static inline void rtl8139_thread_iter (struct net_device *dev,
1555 struct rtl8139_private *tp,
1556 void __iomem *ioaddr)
1557 {
1558 int mii_lpa;
1559
1560 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1561
1562 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1563 int duplex = (mii_lpa & LPA_100FULL)
1564 || (mii_lpa & 0x01C0) == 0x0040;
1565 if (tp->mii.full_duplex != duplex) {
1566 tp->mii.full_duplex = duplex;
1567
1568 if (mii_lpa) {
1569 printk (KERN_INFO
1570 "%s: Setting %s-duplex based on MII #%d link"
1571 " partner ability of %4.4x.\n",
1572 dev->name,
1573 tp->mii.full_duplex ? "full" : "half",
1574 tp->phys[0], mii_lpa);
1575 } else {
1576 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1577 dev->name);
1578 }
1579 #if 0
1580 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1581 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1582 RTL_W8 (Cfg9346, Cfg9346_Lock);
1583 #endif
1584 }
1585 }
1586
1587 next_tick = HZ * 60;
1588
1589 rtl8139_tune_twister (dev, tp);
1590
1591 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1592 dev->name, RTL_R16 (NWayLPAR));
1593 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1594 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1595 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1596 dev->name, RTL_R8 (Config0),
1597 RTL_R8 (Config1));
1598 }
1599
1600 static void rtl8139_thread (void *_data)
1601 {
1602 struct net_device *dev = _data;
1603 struct rtl8139_private *tp = netdev_priv(dev);
1604 unsigned long thr_delay = next_tick;
1605
1606 if (tp->watchdog_fired) {
1607 tp->watchdog_fired = 0;
1608 rtl8139_tx_timeout_task(_data);
1609 } else if (rtnl_trylock()) {
1610 rtl8139_thread_iter (dev, tp, tp->mmio_addr);
1611 rtnl_unlock ();
1612 } else {
1613 /* unlikely race. mitigate with fast poll. */
1614 thr_delay = HZ / 2;
1615 }
1616
1617 schedule_delayed_work(&tp->thread, thr_delay);
1618 }
1619
1620 static void rtl8139_start_thread(struct rtl8139_private *tp)
1621 {
1622 tp->twistie = 0;
1623 if (tp->chipset == CH_8139_K)
1624 tp->twistie = 1;
1625 else if (tp->drv_flags & HAS_LNK_CHNG)
1626 return;
1627
1628 tp->have_thread = 1;
1629
1630 schedule_delayed_work(&tp->thread, next_tick);
1631 }
1632
1633 static void rtl8139_stop_thread(struct rtl8139_private *tp)
1634 {
1635 if (tp->have_thread) {
1636 cancel_rearming_delayed_work(&tp->thread);
1637 tp->have_thread = 0;
1638 } else
1639 flush_scheduled_work();
1640 }
1641
1642 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1643 {
1644 tp->cur_tx = 0;
1645 tp->dirty_tx = 0;
1646
1647 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1648 }
1649
1650 static void rtl8139_tx_timeout_task (void *_data)
1651 {
1652 struct net_device *dev = _data;
1653 struct rtl8139_private *tp = netdev_priv(dev);
1654 void __iomem *ioaddr = tp->mmio_addr;
1655 int i;
1656 u8 tmp8;
1657
1658 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1659 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1660 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1661 /* Emit info to figure out what went wrong. */
1662 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1663 dev->name, tp->cur_tx, tp->dirty_tx);
1664 for (i = 0; i < NUM_TX_DESC; i++)
1665 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1666 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1667 i == tp->dirty_tx % NUM_TX_DESC ?
1668 " (queue head)" : "");
1669
1670 tp->xstats.tx_timeouts++;
1671
1672 /* disable Tx ASAP, if not already */
1673 tmp8 = RTL_R8 (ChipCmd);
1674 if (tmp8 & CmdTxEnb)
1675 RTL_W8 (ChipCmd, CmdRxEnb);
1676
1677 spin_lock_bh(&tp->rx_lock);
1678 /* Disable interrupts by clearing the interrupt mask. */
1679 RTL_W16 (IntrMask, 0x0000);
1680
1681 /* Stop a shared interrupt from scavenging while we are. */
1682 spin_lock_irq(&tp->lock);
1683 rtl8139_tx_clear (tp);
1684 spin_unlock_irq(&tp->lock);
1685
1686 /* ...and finally, reset everything */
1687 if (netif_running(dev)) {
1688 rtl8139_hw_start (dev);
1689 netif_wake_queue (dev);
1690 }
1691 spin_unlock_bh(&tp->rx_lock);
1692 }
1693
1694 static void rtl8139_tx_timeout (struct net_device *dev)
1695 {
1696 struct rtl8139_private *tp = netdev_priv(dev);
1697
1698 if (!tp->have_thread) {
1699 INIT_WORK(&tp->thread, rtl8139_tx_timeout_task, dev);
1700 schedule_delayed_work(&tp->thread, next_tick);
1701 } else
1702 tp->watchdog_fired = 1;
1703
1704 }
1705
1706 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1707 {
1708 struct rtl8139_private *tp = netdev_priv(dev);
1709 void __iomem *ioaddr = tp->mmio_addr;
1710 unsigned int entry;
1711 unsigned int len = skb->len;
1712 unsigned long flags;
1713
1714 /* Calculate the next Tx descriptor entry. */
1715 entry = tp->cur_tx % NUM_TX_DESC;
1716
1717 /* Note: the chip doesn't have auto-pad! */
1718 if (likely(len < TX_BUF_SIZE)) {
1719 if (len < ETH_ZLEN)
1720 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1721 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1722 dev_kfree_skb(skb);
1723 } else {
1724 dev_kfree_skb(skb);
1725 tp->stats.tx_dropped++;
1726 return 0;
1727 }
1728
1729 spin_lock_irqsave(&tp->lock, flags);
1730 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1731 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1732
1733 dev->trans_start = jiffies;
1734
1735 tp->cur_tx++;
1736 wmb();
1737
1738 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1739 netif_stop_queue (dev);
1740 spin_unlock_irqrestore(&tp->lock, flags);
1741
1742 if (netif_msg_tx_queued(tp))
1743 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1744 dev->name, len, entry);
1745
1746 return 0;
1747 }
1748
1749
1750 static void rtl8139_tx_interrupt (struct net_device *dev,
1751 struct rtl8139_private *tp,
1752 void __iomem *ioaddr)
1753 {
1754 unsigned long dirty_tx, tx_left;
1755
1756 assert (dev != NULL);
1757 assert (ioaddr != NULL);
1758
1759 dirty_tx = tp->dirty_tx;
1760 tx_left = tp->cur_tx - dirty_tx;
1761 while (tx_left > 0) {
1762 int entry = dirty_tx % NUM_TX_DESC;
1763 int txstatus;
1764
1765 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1766
1767 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1768 break; /* It still hasn't been Txed */
1769
1770 /* Note: TxCarrierLost is always asserted at 100mbps. */
1771 if (txstatus & (TxOutOfWindow | TxAborted)) {
1772 /* There was an major error, log it. */
1773 if (netif_msg_tx_err(tp))
1774 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1775 dev->name, txstatus);
1776 tp->stats.tx_errors++;
1777 if (txstatus & TxAborted) {
1778 tp->stats.tx_aborted_errors++;
1779 RTL_W32 (TxConfig, TxClearAbt);
1780 RTL_W16 (IntrStatus, TxErr);
1781 wmb();
1782 }
1783 if (txstatus & TxCarrierLost)
1784 tp->stats.tx_carrier_errors++;
1785 if (txstatus & TxOutOfWindow)
1786 tp->stats.tx_window_errors++;
1787 } else {
1788 if (txstatus & TxUnderrun) {
1789 /* Add 64 to the Tx FIFO threshold. */
1790 if (tp->tx_flag < 0x00300000)
1791 tp->tx_flag += 0x00020000;
1792 tp->stats.tx_fifo_errors++;
1793 }
1794 tp->stats.collisions += (txstatus >> 24) & 15;
1795 tp->stats.tx_bytes += txstatus & 0x7ff;
1796 tp->stats.tx_packets++;
1797 }
1798
1799 dirty_tx++;
1800 tx_left--;
1801 }
1802
1803 #ifndef RTL8139_NDEBUG
1804 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1805 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1806 dev->name, dirty_tx, tp->cur_tx);
1807 dirty_tx += NUM_TX_DESC;
1808 }
1809 #endif /* RTL8139_NDEBUG */
1810
1811 /* only wake the queue if we did work, and the queue is stopped */
1812 if (tp->dirty_tx != dirty_tx) {
1813 tp->dirty_tx = dirty_tx;
1814 mb();
1815 netif_wake_queue (dev);
1816 }
1817 }
1818
1819
1820 /* TODO: clean this up! Rx reset need not be this intensive */
1821 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1822 struct rtl8139_private *tp, void __iomem *ioaddr)
1823 {
1824 u8 tmp8;
1825 #ifdef CONFIG_8139_OLD_RX_RESET
1826 int tmp_work;
1827 #endif
1828
1829 if (netif_msg_rx_err (tp))
1830 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1831 dev->name, rx_status);
1832 tp->stats.rx_errors++;
1833 if (!(rx_status & RxStatusOK)) {
1834 if (rx_status & RxTooLong) {
1835 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1836 dev->name, rx_status);
1837 /* A.C.: The chip hangs here. */
1838 }
1839 if (rx_status & (RxBadSymbol | RxBadAlign))
1840 tp->stats.rx_frame_errors++;
1841 if (rx_status & (RxRunt | RxTooLong))
1842 tp->stats.rx_length_errors++;
1843 if (rx_status & RxCRCErr)
1844 tp->stats.rx_crc_errors++;
1845 } else {
1846 tp->xstats.rx_lost_in_ring++;
1847 }
1848
1849 #ifndef CONFIG_8139_OLD_RX_RESET
1850 tmp8 = RTL_R8 (ChipCmd);
1851 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1852 RTL_W8 (ChipCmd, tmp8);
1853 RTL_W32 (RxConfig, tp->rx_config);
1854 tp->cur_rx = 0;
1855 #else
1856 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1857
1858 /* disable receive */
1859 RTL_W8_F (ChipCmd, CmdTxEnb);
1860 tmp_work = 200;
1861 while (--tmp_work > 0) {
1862 udelay(1);
1863 tmp8 = RTL_R8 (ChipCmd);
1864 if (!(tmp8 & CmdRxEnb))
1865 break;
1866 }
1867 if (tmp_work <= 0)
1868 printk (KERN_WARNING PFX "rx stop wait too long\n");
1869 /* restart receive */
1870 tmp_work = 200;
1871 while (--tmp_work > 0) {
1872 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1873 udelay(1);
1874 tmp8 = RTL_R8 (ChipCmd);
1875 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1876 break;
1877 }
1878 if (tmp_work <= 0)
1879 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1880
1881 /* and reinitialize all rx related registers */
1882 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1883 /* Must enable Tx/Rx before setting transfer thresholds! */
1884 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1885
1886 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1887 RTL_W32 (RxConfig, tp->rx_config);
1888 tp->cur_rx = 0;
1889
1890 DPRINTK("init buffer addresses\n");
1891
1892 /* Lock Config[01234] and BMCR register writes */
1893 RTL_W8 (Cfg9346, Cfg9346_Lock);
1894
1895 /* init Rx ring buffer DMA address */
1896 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1897
1898 /* A.C.: Reset the multicast list. */
1899 __set_rx_mode (dev);
1900 #endif
1901 }
1902
1903 #if RX_BUF_IDX == 3
1904 static __inline__ void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1905 u32 offset, unsigned int size)
1906 {
1907 u32 left = RX_BUF_LEN - offset;
1908
1909 if (size > left) {
1910 memcpy(skb->data, ring + offset, left);
1911 memcpy(skb->data+left, ring, size - left);
1912 } else
1913 memcpy(skb->data, ring + offset, size);
1914 }
1915 #endif
1916
1917 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1918 {
1919 void __iomem *ioaddr = tp->mmio_addr;
1920 u16 status;
1921
1922 status = RTL_R16 (IntrStatus) & RxAckBits;
1923
1924 /* Clear out errors and receive interrupts */
1925 if (likely(status != 0)) {
1926 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1927 tp->stats.rx_errors++;
1928 if (status & RxFIFOOver)
1929 tp->stats.rx_fifo_errors++;
1930 }
1931 RTL_W16_F (IntrStatus, RxAckBits);
1932 }
1933 }
1934
1935 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1936 int budget)
1937 {
1938 void __iomem *ioaddr = tp->mmio_addr;
1939 int received = 0;
1940 unsigned char *rx_ring = tp->rx_ring;
1941 unsigned int cur_rx = tp->cur_rx;
1942 unsigned int rx_size = 0;
1943
1944 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1945 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1946 RTL_R16 (RxBufAddr),
1947 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1948
1949 while (netif_running(dev) && received < budget
1950 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1951 u32 ring_offset = cur_rx % RX_BUF_LEN;
1952 u32 rx_status;
1953 unsigned int pkt_size;
1954 struct sk_buff *skb;
1955
1956 rmb();
1957
1958 /* read size+status of next frame from DMA ring buffer */
1959 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1960 rx_size = rx_status >> 16;
1961 pkt_size = rx_size - 4;
1962
1963 if (netif_msg_rx_status(tp))
1964 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1965 " cur %4.4x.\n", dev->name, rx_status,
1966 rx_size, cur_rx);
1967 #if RTL8139_DEBUG > 2
1968 {
1969 int i;
1970 DPRINTK ("%s: Frame contents ", dev->name);
1971 for (i = 0; i < 70; i++)
1972 printk (" %2.2x",
1973 rx_ring[ring_offset + i]);
1974 printk (".\n");
1975 }
1976 #endif
1977
1978 /* Packet copy from FIFO still in progress.
1979 * Theoretically, this should never happen
1980 * since EarlyRx is disabled.
1981 */
1982 if (unlikely(rx_size == 0xfff0)) {
1983 if (!tp->fifo_copy_timeout)
1984 tp->fifo_copy_timeout = jiffies + 2;
1985 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1986 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
1987 rx_size = 0;
1988 goto no_early_rx;
1989 }
1990 if (netif_msg_intr(tp)) {
1991 printk(KERN_DEBUG "%s: fifo copy in progress.",
1992 dev->name);
1993 }
1994 tp->xstats.early_rx++;
1995 break;
1996 }
1997
1998 no_early_rx:
1999 tp->fifo_copy_timeout = 0;
2000
2001 /* If Rx err or invalid rx_size/rx_status received
2002 * (which happens if we get lost in the ring),
2003 * Rx process gets reset, so we abort any further
2004 * Rx processing.
2005 */
2006 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
2007 (rx_size < 8) ||
2008 (!(rx_status & RxStatusOK)))) {
2009 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2010 received = -1;
2011 goto out;
2012 }
2013
2014 /* Malloc up new buffer, compatible with net-2e. */
2015 /* Omit the four octet CRC from the length. */
2016
2017 skb = dev_alloc_skb (pkt_size + 2);
2018 if (likely(skb)) {
2019 skb->dev = dev;
2020 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
2021 #if RX_BUF_IDX == 3
2022 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2023 #else
2024 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
2025 #endif
2026 skb_put (skb, pkt_size);
2027
2028 skb->protocol = eth_type_trans (skb, dev);
2029
2030 dev->last_rx = jiffies;
2031 tp->stats.rx_bytes += pkt_size;
2032 tp->stats.rx_packets++;
2033
2034 netif_receive_skb (skb);
2035 } else {
2036 if (net_ratelimit())
2037 printk (KERN_WARNING
2038 "%s: Memory squeeze, dropping packet.\n",
2039 dev->name);
2040 tp->stats.rx_dropped++;
2041 }
2042 received++;
2043
2044 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2045 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2046
2047 rtl8139_isr_ack(tp);
2048 }
2049
2050 if (unlikely(!received || rx_size == 0xfff0))
2051 rtl8139_isr_ack(tp);
2052
2053 #if RTL8139_DEBUG > 1
2054 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2055 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2056 RTL_R16 (RxBufAddr),
2057 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2058 #endif
2059
2060 tp->cur_rx = cur_rx;
2061
2062 /*
2063 * The receive buffer should be mostly empty.
2064 * Tell NAPI to reenable the Rx irq.
2065 */
2066 if (tp->fifo_copy_timeout)
2067 received = budget;
2068
2069 out:
2070 return received;
2071 }
2072
2073
2074 static void rtl8139_weird_interrupt (struct net_device *dev,
2075 struct rtl8139_private *tp,
2076 void __iomem *ioaddr,
2077 int status, int link_changed)
2078 {
2079 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2080 dev->name, status);
2081
2082 assert (dev != NULL);
2083 assert (tp != NULL);
2084 assert (ioaddr != NULL);
2085
2086 /* Update the error count. */
2087 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2088 RTL_W32 (RxMissed, 0);
2089
2090 if ((status & RxUnderrun) && link_changed &&
2091 (tp->drv_flags & HAS_LNK_CHNG)) {
2092 rtl_check_media(dev, 0);
2093 status &= ~RxUnderrun;
2094 }
2095
2096 if (status & (RxUnderrun | RxErr))
2097 tp->stats.rx_errors++;
2098
2099 if (status & PCSTimeout)
2100 tp->stats.rx_length_errors++;
2101 if (status & RxUnderrun)
2102 tp->stats.rx_fifo_errors++;
2103 if (status & PCIErr) {
2104 u16 pci_cmd_status;
2105 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2106 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2107
2108 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2109 dev->name, pci_cmd_status);
2110 }
2111 }
2112
2113 static int rtl8139_poll(struct net_device *dev, int *budget)
2114 {
2115 struct rtl8139_private *tp = netdev_priv(dev);
2116 void __iomem *ioaddr = tp->mmio_addr;
2117 int orig_budget = min(*budget, dev->quota);
2118 int done = 1;
2119
2120 spin_lock(&tp->rx_lock);
2121 if (likely(RTL_R16(IntrStatus) & RxAckBits)) {
2122 int work_done;
2123
2124 work_done = rtl8139_rx(dev, tp, orig_budget);
2125 if (likely(work_done > 0)) {
2126 *budget -= work_done;
2127 dev->quota -= work_done;
2128 done = (work_done < orig_budget);
2129 }
2130 }
2131
2132 if (done) {
2133 /*
2134 * Order is important since data can get interrupted
2135 * again when we think we are done.
2136 */
2137 local_irq_disable();
2138 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2139 __netif_rx_complete(dev);
2140 local_irq_enable();
2141 }
2142 spin_unlock(&tp->rx_lock);
2143
2144 return !done;
2145 }
2146
2147 /* The interrupt handler does all of the Rx thread work and cleans up
2148 after the Tx thread. */
2149 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
2150 struct pt_regs *regs)
2151 {
2152 struct net_device *dev = (struct net_device *) dev_instance;
2153 struct rtl8139_private *tp = netdev_priv(dev);
2154 void __iomem *ioaddr = tp->mmio_addr;
2155 u16 status, ackstat;
2156 int link_changed = 0; /* avoid bogus "uninit" warning */
2157 int handled = 0;
2158
2159 spin_lock (&tp->lock);
2160 status = RTL_R16 (IntrStatus);
2161
2162 /* shared irq? */
2163 if (unlikely((status & rtl8139_intr_mask) == 0))
2164 goto out;
2165
2166 handled = 1;
2167
2168 /* h/w no longer present (hotplug?) or major error, bail */
2169 if (unlikely(status == 0xFFFF))
2170 goto out;
2171
2172 /* close possible race's with dev_close */
2173 if (unlikely(!netif_running(dev))) {
2174 RTL_W16 (IntrMask, 0);
2175 goto out;
2176 }
2177
2178 /* Acknowledge all of the current interrupt sources ASAP, but
2179 an first get an additional status bit from CSCR. */
2180 if (unlikely(status & RxUnderrun))
2181 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2182
2183 ackstat = status & ~(RxAckBits | TxErr);
2184 if (ackstat)
2185 RTL_W16 (IntrStatus, ackstat);
2186
2187 /* Receive packets are processed by poll routine.
2188 If not running start it now. */
2189 if (status & RxAckBits){
2190 if (netif_rx_schedule_prep(dev)) {
2191 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2192 __netif_rx_schedule (dev);
2193 }
2194 }
2195
2196 /* Check uncommon events with one test. */
2197 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2198 rtl8139_weird_interrupt (dev, tp, ioaddr,
2199 status, link_changed);
2200
2201 if (status & (TxOK | TxErr)) {
2202 rtl8139_tx_interrupt (dev, tp, ioaddr);
2203 if (status & TxErr)
2204 RTL_W16 (IntrStatus, TxErr);
2205 }
2206 out:
2207 spin_unlock (&tp->lock);
2208
2209 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2210 dev->name, RTL_R16 (IntrStatus));
2211 return IRQ_RETVAL(handled);
2212 }
2213
2214 #ifdef CONFIG_NET_POLL_CONTROLLER
2215 /*
2216 * Polling receive - used by netconsole and other diagnostic tools
2217 * to allow network i/o with interrupts disabled.
2218 */
2219 static void rtl8139_poll_controller(struct net_device *dev)
2220 {
2221 disable_irq(dev->irq);
2222 rtl8139_interrupt(dev->irq, dev, NULL);
2223 enable_irq(dev->irq);
2224 }
2225 #endif
2226
2227 static int rtl8139_close (struct net_device *dev)
2228 {
2229 struct rtl8139_private *tp = netdev_priv(dev);
2230 void __iomem *ioaddr = tp->mmio_addr;
2231 unsigned long flags;
2232
2233 netif_stop_queue (dev);
2234
2235 rtl8139_stop_thread(tp);
2236
2237 if (netif_msg_ifdown(tp))
2238 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2239 dev->name, RTL_R16 (IntrStatus));
2240
2241 spin_lock_irqsave (&tp->lock, flags);
2242
2243 /* Stop the chip's Tx and Rx DMA processes. */
2244 RTL_W8 (ChipCmd, 0);
2245
2246 /* Disable interrupts by clearing the interrupt mask. */
2247 RTL_W16 (IntrMask, 0);
2248
2249 /* Update the error counts. */
2250 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2251 RTL_W32 (RxMissed, 0);
2252
2253 spin_unlock_irqrestore (&tp->lock, flags);
2254
2255 synchronize_irq (dev->irq); /* racy, but that's ok here */
2256 free_irq (dev->irq, dev);
2257
2258 rtl8139_tx_clear (tp);
2259
2260 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
2261 tp->rx_ring, tp->rx_ring_dma);
2262 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
2263 tp->tx_bufs, tp->tx_bufs_dma);
2264 tp->rx_ring = NULL;
2265 tp->tx_bufs = NULL;
2266
2267 /* Green! Put the chip in low-power mode. */
2268 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2269
2270 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2271 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2272
2273 return 0;
2274 }
2275
2276
2277 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2278 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2279 other threads or interrupts aren't messing with the 8139. */
2280 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2281 {
2282 struct rtl8139_private *np = netdev_priv(dev);
2283 void __iomem *ioaddr = np->mmio_addr;
2284
2285 spin_lock_irq(&np->lock);
2286 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2287 u8 cfg3 = RTL_R8 (Config3);
2288 u8 cfg5 = RTL_R8 (Config5);
2289
2290 wol->supported = WAKE_PHY | WAKE_MAGIC
2291 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2292
2293 wol->wolopts = 0;
2294 if (cfg3 & Cfg3_LinkUp)
2295 wol->wolopts |= WAKE_PHY;
2296 if (cfg3 & Cfg3_Magic)
2297 wol->wolopts |= WAKE_MAGIC;
2298 /* (KON)FIXME: See how netdev_set_wol() handles the
2299 following constants. */
2300 if (cfg5 & Cfg5_UWF)
2301 wol->wolopts |= WAKE_UCAST;
2302 if (cfg5 & Cfg5_MWF)
2303 wol->wolopts |= WAKE_MCAST;
2304 if (cfg5 & Cfg5_BWF)
2305 wol->wolopts |= WAKE_BCAST;
2306 }
2307 spin_unlock_irq(&np->lock);
2308 }
2309
2310
2311 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2312 that wol points to kernel memory and other threads or interrupts
2313 aren't messing with the 8139. */
2314 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2315 {
2316 struct rtl8139_private *np = netdev_priv(dev);
2317 void __iomem *ioaddr = np->mmio_addr;
2318 u32 support;
2319 u8 cfg3, cfg5;
2320
2321 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2322 ? (WAKE_PHY | WAKE_MAGIC
2323 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2324 : 0);
2325 if (wol->wolopts & ~support)
2326 return -EINVAL;
2327
2328 spin_lock_irq(&np->lock);
2329 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2330 if (wol->wolopts & WAKE_PHY)
2331 cfg3 |= Cfg3_LinkUp;
2332 if (wol->wolopts & WAKE_MAGIC)
2333 cfg3 |= Cfg3_Magic;
2334 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2335 RTL_W8 (Config3, cfg3);
2336 RTL_W8 (Cfg9346, Cfg9346_Lock);
2337
2338 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2339 /* (KON)FIXME: These are untested. We may have to set the
2340 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2341 documentation. */
2342 if (wol->wolopts & WAKE_UCAST)
2343 cfg5 |= Cfg5_UWF;
2344 if (wol->wolopts & WAKE_MCAST)
2345 cfg5 |= Cfg5_MWF;
2346 if (wol->wolopts & WAKE_BCAST)
2347 cfg5 |= Cfg5_BWF;
2348 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2349 spin_unlock_irq(&np->lock);
2350
2351 return 0;
2352 }
2353
2354 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2355 {
2356 struct rtl8139_private *np = netdev_priv(dev);
2357 strcpy(info->driver, DRV_NAME);
2358 strcpy(info->version, DRV_VERSION);
2359 strcpy(info->bus_info, pci_name(np->pci_dev));
2360 info->regdump_len = np->regs_len;
2361 }
2362
2363 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2364 {
2365 struct rtl8139_private *np = netdev_priv(dev);
2366 spin_lock_irq(&np->lock);
2367 mii_ethtool_gset(&np->mii, cmd);
2368 spin_unlock_irq(&np->lock);
2369 return 0;
2370 }
2371
2372 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2373 {
2374 struct rtl8139_private *np = netdev_priv(dev);
2375 int rc;
2376 spin_lock_irq(&np->lock);
2377 rc = mii_ethtool_sset(&np->mii, cmd);
2378 spin_unlock_irq(&np->lock);
2379 return rc;
2380 }
2381
2382 static int rtl8139_nway_reset(struct net_device *dev)
2383 {
2384 struct rtl8139_private *np = netdev_priv(dev);
2385 return mii_nway_restart(&np->mii);
2386 }
2387
2388 static u32 rtl8139_get_link(struct net_device *dev)
2389 {
2390 struct rtl8139_private *np = netdev_priv(dev);
2391 return mii_link_ok(&np->mii);
2392 }
2393
2394 static u32 rtl8139_get_msglevel(struct net_device *dev)
2395 {
2396 struct rtl8139_private *np = netdev_priv(dev);
2397 return np->msg_enable;
2398 }
2399
2400 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2401 {
2402 struct rtl8139_private *np = netdev_priv(dev);
2403 np->msg_enable = datum;
2404 }
2405
2406 /* TODO: we are too slack to do reg dumping for pio, for now */
2407 #ifdef CONFIG_8139TOO_PIO
2408 #define rtl8139_get_regs_len NULL
2409 #define rtl8139_get_regs NULL
2410 #else
2411 static int rtl8139_get_regs_len(struct net_device *dev)
2412 {
2413 struct rtl8139_private *np = netdev_priv(dev);
2414 return np->regs_len;
2415 }
2416
2417 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2418 {
2419 struct rtl8139_private *np = netdev_priv(dev);
2420
2421 regs->version = RTL_REGS_VER;
2422
2423 spin_lock_irq(&np->lock);
2424 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2425 spin_unlock_irq(&np->lock);
2426 }
2427 #endif /* CONFIG_8139TOO_MMIO */
2428
2429 static int rtl8139_get_stats_count(struct net_device *dev)
2430 {
2431 return RTL_NUM_STATS;
2432 }
2433
2434 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2435 {
2436 struct rtl8139_private *np = netdev_priv(dev);
2437
2438 data[0] = np->xstats.early_rx;
2439 data[1] = np->xstats.tx_buf_mapped;
2440 data[2] = np->xstats.tx_timeouts;
2441 data[3] = np->xstats.rx_lost_in_ring;
2442 }
2443
2444 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2445 {
2446 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2447 }
2448
2449 static struct ethtool_ops rtl8139_ethtool_ops = {
2450 .get_drvinfo = rtl8139_get_drvinfo,
2451 .get_settings = rtl8139_get_settings,
2452 .set_settings = rtl8139_set_settings,
2453 .get_regs_len = rtl8139_get_regs_len,
2454 .get_regs = rtl8139_get_regs,
2455 .nway_reset = rtl8139_nway_reset,
2456 .get_link = rtl8139_get_link,
2457 .get_msglevel = rtl8139_get_msglevel,
2458 .set_msglevel = rtl8139_set_msglevel,
2459 .get_wol = rtl8139_get_wol,
2460 .set_wol = rtl8139_set_wol,
2461 .get_strings = rtl8139_get_strings,
2462 .get_stats_count = rtl8139_get_stats_count,
2463 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2464 .get_perm_addr = ethtool_op_get_perm_addr,
2465 };
2466
2467 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2468 {
2469 struct rtl8139_private *np = netdev_priv(dev);
2470 int rc;
2471
2472 if (!netif_running(dev))
2473 return -EINVAL;
2474
2475 spin_lock_irq(&np->lock);
2476 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2477 spin_unlock_irq(&np->lock);
2478
2479 return rc;
2480 }
2481
2482
2483 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2484 {
2485 struct rtl8139_private *tp = netdev_priv(dev);
2486 void __iomem *ioaddr = tp->mmio_addr;
2487 unsigned long flags;
2488
2489 if (netif_running(dev)) {
2490 spin_lock_irqsave (&tp->lock, flags);
2491 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2492 RTL_W32 (RxMissed, 0);
2493 spin_unlock_irqrestore (&tp->lock, flags);
2494 }
2495
2496 return &tp->stats;
2497 }
2498
2499 /* Set or clear the multicast filter for this adaptor.
2500 This routine is not state sensitive and need not be SMP locked. */
2501
2502 static void __set_rx_mode (struct net_device *dev)
2503 {
2504 struct rtl8139_private *tp = netdev_priv(dev);
2505 void __iomem *ioaddr = tp->mmio_addr;
2506 u32 mc_filter[2]; /* Multicast hash filter */
2507 int i, rx_mode;
2508 u32 tmp;
2509
2510 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2511 dev->name, dev->flags, RTL_R32 (RxConfig));
2512
2513 /* Note: do not reorder, GCC is clever about common statements. */
2514 if (dev->flags & IFF_PROMISC) {
2515 /* Unconditionally log net taps. */
2516 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2517 dev->name);
2518 rx_mode =
2519 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2520 AcceptAllPhys;
2521 mc_filter[1] = mc_filter[0] = 0xffffffff;
2522 } else if ((dev->mc_count > multicast_filter_limit)
2523 || (dev->flags & IFF_ALLMULTI)) {
2524 /* Too many to filter perfectly -- accept all multicasts. */
2525 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2526 mc_filter[1] = mc_filter[0] = 0xffffffff;
2527 } else {
2528 struct dev_mc_list *mclist;
2529 rx_mode = AcceptBroadcast | AcceptMyPhys;
2530 mc_filter[1] = mc_filter[0] = 0;
2531 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2532 i++, mclist = mclist->next) {
2533 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2534
2535 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2536 rx_mode |= AcceptMulticast;
2537 }
2538 }
2539
2540 /* We can safely update without stopping the chip. */
2541 tmp = rtl8139_rx_config | rx_mode;
2542 if (tp->rx_config != tmp) {
2543 RTL_W32_F (RxConfig, tmp);
2544 tp->rx_config = tmp;
2545 }
2546 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2547 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2548 }
2549
2550 static void rtl8139_set_rx_mode (struct net_device *dev)
2551 {
2552 unsigned long flags;
2553 struct rtl8139_private *tp = netdev_priv(dev);
2554
2555 spin_lock_irqsave (&tp->lock, flags);
2556 __set_rx_mode(dev);
2557 spin_unlock_irqrestore (&tp->lock, flags);
2558 }
2559
2560 #ifdef CONFIG_PM
2561
2562 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2563 {
2564 struct net_device *dev = pci_get_drvdata (pdev);
2565 struct rtl8139_private *tp = netdev_priv(dev);
2566 void __iomem *ioaddr = tp->mmio_addr;
2567 unsigned long flags;
2568
2569 pci_save_state (pdev);
2570
2571 if (!netif_running (dev))
2572 return 0;
2573
2574 netif_device_detach (dev);
2575
2576 spin_lock_irqsave (&tp->lock, flags);
2577
2578 /* Disable interrupts, stop Tx and Rx. */
2579 RTL_W16 (IntrMask, 0);
2580 RTL_W8 (ChipCmd, 0);
2581
2582 /* Update the error counts. */
2583 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2584 RTL_W32 (RxMissed, 0);
2585
2586 spin_unlock_irqrestore (&tp->lock, flags);
2587
2588 pci_set_power_state (pdev, PCI_D3hot);
2589
2590 return 0;
2591 }
2592
2593
2594 static int rtl8139_resume (struct pci_dev *pdev)
2595 {
2596 struct net_device *dev = pci_get_drvdata (pdev);
2597
2598 pci_restore_state (pdev);
2599 if (!netif_running (dev))
2600 return 0;
2601 pci_set_power_state (pdev, PCI_D0);
2602 rtl8139_init_ring (dev);
2603 rtl8139_hw_start (dev);
2604 netif_device_attach (dev);
2605 return 0;
2606 }
2607
2608 #endif /* CONFIG_PM */
2609
2610
2611 static struct pci_driver rtl8139_pci_driver = {
2612 .name = DRV_NAME,
2613 .id_table = rtl8139_pci_tbl,
2614 .probe = rtl8139_init_one,
2615 .remove = __devexit_p(rtl8139_remove_one),
2616 #ifdef CONFIG_PM
2617 .suspend = rtl8139_suspend,
2618 .resume = rtl8139_resume,
2619 #endif /* CONFIG_PM */
2620 };
2621
2622
2623 static int __init rtl8139_init_module (void)
2624 {
2625 /* when we're a module, we always print a version message,
2626 * even if no 8139 board is found.
2627 */
2628 #ifdef MODULE
2629 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2630 #endif
2631
2632 return pci_module_init (&rtl8139_pci_driver);
2633 }
2634
2635
2636 static void __exit rtl8139_cleanup_module (void)
2637 {
2638 pci_unregister_driver (&rtl8139_pci_driver);
2639 }
2640
2641
2642 module_init(rtl8139_init_module);
2643 module_exit(rtl8139_cleanup_module);
x86 "subsystem" repository