drivers/ide/legacy/q40ide.c

   1 /*
   2  *  Q40 I/O port IDE Driver
   3  *
   4  *     (c) Richard Zidlicky
   5  *
   6  *  This file is subject to the terms and conditions of the GNU General Public
   7  *  License.  See the file COPYING in the main directory of this archive for
   8  *  more details.
   9  *
  10  *
  11  */
  12
  13 #include <linux/types.h>
  14 #include <linux/mm.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/blkdev.h>
  17 #include <linux/hdreg.h>
  18
  19 #include <linux/ide.h>
  20
  21     /*
  22      *  Bases of the IDE interfaces
  23      */
  24
  25 #define Q40IDE_NUM_HWIFS        2
  26
  27 #define PCIDE_BASE1     0x1f0
  28 #define PCIDE_BASE2     0x170
  29 #define PCIDE_BASE3     0x1e8
  30 #define PCIDE_BASE4     0x168
  31 #define PCIDE_BASE5     0x1e0
  32 #define PCIDE_BASE6     0x160
  33
  34 static const unsigned long pcide_bases[Q40IDE_NUM_HWIFS] = {
  35     PCIDE_BASE1, PCIDE_BASE2, /* PCIDE_BASE3, PCIDE_BASE4  , PCIDE_BASE5,
  36     PCIDE_BASE6 */
  37 };
  38
  39 static int q40ide_default_irq(unsigned long base)
  40 {
  41            switch (base) {
  42                     case 0x1f0: return 14;
  43                     case 0x170: return 15;
  44                     case 0x1e8: return 11;
  45                     default:
  46                         return 0;
  47            }
  48 }
  49
  50
  51 /*
  52  * Addresses are pretranslated for Q40 ISA access.
  53  */
  54 static void q40_ide_setup_ports(hw_regs_t *hw, unsigned long base,
  55                         ide_ack_intr_t *ack_intr,
  56                         int irq)
  57 {
  58         memset(hw, 0, sizeof(hw_regs_t));
  59         /* BIG FAT WARNING:
  60            assumption: only DATA port is ever used in 16 bit mode */
  61         hw->io_ports.data_addr = Q40_ISA_IO_W(base);
  62         hw->io_ports.error_addr = Q40_ISA_IO_B(base + 1);
  63         hw->io_ports.nsect_addr = Q40_ISA_IO_B(base + 2);
  64         hw->io_ports.lbal_addr = Q40_ISA_IO_B(base + 3);
  65         hw->io_ports.lbam_addr = Q40_ISA_IO_B(base + 4);
  66         hw->io_ports.lbah_addr = Q40_ISA_IO_B(base + 5);
  67         hw->io_ports.device_addr = Q40_ISA_IO_B(base + 6);
  68         hw->io_ports.status_addr = Q40_ISA_IO_B(base + 7);
  69         hw->io_ports.ctl_addr = Q40_ISA_IO_B(base + 0x206);
  70
  71         hw->irq = irq;
  72         hw->ack_intr = ack_intr;
  73 }
  74
  75 static void q40ide_atapi_input_bytes(ide_drive_t *drive, void *buf,
  76                                      unsigned int len)
  77 {
  78         insw_swapw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
  79 }
  80
  81 static void q40ide_atapi_output_bytes(ide_drive_t *drive, void *buf,
  82                                       unsigned int len)
  83 {
  84         outsw_swapw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
  85 }
  86
  87 static void q40ide_ata_input_data(ide_drive_t *drive, struct request *rq,
  88                                   void *buf, unsigned int wcount)
  89 {
  90         if (drive->media == ide_disk && rq && rq->cmd_type == REQ_TYPE_FS)
  91                 return insw(drive->hwif->io_ports.data_addr, buf, wcount * 2);
  92
  93         q40ide_atapi_input_bytes(drive, buf, wcount * 4);
  94 }
  95
  96 static void q40ide_ata_output_data(ide_drive_t *drive, struct request *rq,
  97                                    void *buf, unsigned int wcount)
  98 {
  99         if (drive->media == ide_disk && rq && rq->cmd_type == REQ_TYPE_FS)
 100                 return outsw(drive->hwif->io_ports.data_addr, buf, wcount * 2);
 101
 102         q40ide_atapi_output_bytes(drive, buf, wcount * 4);
 103 }
 104
 105 /*
 106  * the static array is needed to have the name reported in /proc/ioports,
 107  * hwif->name unfortunately isn't available yet
 108  */
 109 static const char *q40_ide_names[Q40IDE_NUM_HWIFS]={
 110         "ide0", "ide1"
 111 };
 112
 113 /*
 114  *  Probe for Q40 IDE interfaces
 115  */
 116
 117 static int __init q40ide_init(void)
 118 {
 119     int i;
 120     ide_hwif_t *hwif;
 121     const char *name;
 122     u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
 123
 124     if (!MACH_IS_Q40)
 125       return -ENODEV;
 126
 127     printk(KERN_INFO "ide: Q40 IDE controller\n");
 128
 129     for (i = 0; i < Q40IDE_NUM_HWIFS; i++) {
 130         hw_regs_t hw;
 131
 132         name = q40_ide_names[i];
 133         if (!request_region(pcide_bases[i], 8, name)) {
 134                 printk("could not reserve ports %lx-%lx for %s\n",
 135                        pcide_bases[i],pcide_bases[i]+8,name);
 136                 continue;
 137         }
 138         if (!request_region(pcide_bases[i]+0x206, 1, name)) {
 139                 printk("could not reserve port %lx for %s\n",
 140                        pcide_bases[i]+0x206,name);
 141                 release_region(pcide_bases[i], 8);
 142                 continue;
 143         }
 144         q40_ide_setup_ports(&hw, pcide_bases[i],
 145                         NULL,
 146 //                      m68kide_iops,
 147                         q40ide_default_irq(pcide_bases[i]));
 148
 149         hwif = ide_find_port();
 150         if (hwif) {
 151                 ide_init_port_data(hwif, hwif->index);
 152                 ide_init_port_hw(hwif, &hw);
 153
 154                 /* Q40 has a byte-swapped IDE interface */
 155                 hwif->atapi_input_bytes  = q40ide_atapi_input_bytes;
 156                 hwif->atapi_output_bytes = q40ide_atapi_output_bytes;
 157                 hwif->ata_input_data     = q40ide_ata_input_data;
 158                 hwif->ata_output_data    = q40ide_ata_output_data;
 159
 160                 idx[i] = hwif->index;
 161         }
 162     }
 163
 164     ide_device_add(idx, NULL);
 165
 166     return 0;
 167 }
 168
 169 module_init(q40ide_init);
 170
 171 MODULE_LICENSE("GPL");