2 * FCC driver for Motorola MPC82xx (PQ2).
4 * Copyright (c) 2003 Intracom S.A.
5 * by Pantelis Antoniou <panto@intracom.gr>
7 * 2005 (c) MontaVista Software, Inc.
8 * Vitaly Bordug <vbordug@ru.mvista.com>
10 * This file is licensed under the terms of the GNU General Public License
11 * version 2. This program is licensed "as is" without any warranty of any
12 * kind, whether express or implied.
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/string.h>
19 #include <linux/ptrace.h>
20 #include <linux/errno.h>
21 #include <linux/ioport.h>
22 #include <linux/slab.h>
23 #include <linux/interrupt.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/netdevice.h>
27 #include <linux/etherdevice.h>
28 #include <linux/skbuff.h>
29 #include <linux/spinlock.h>
30 #include <linux/mii.h>
31 #include <linux/ethtool.h>
32 #include <linux/bitops.h>
34 #include <linux/platform_device.h>
35 #include <linux/phy.h>
37 #include <asm/immap_cpm2.h>
38 #include <asm/mpc8260.h>
41 #include <asm/pgtable.h>
43 #include <asm/uaccess.h>
47 /*************************************************/
49 /* FCC access macros */
51 #define __fcc_out32(addr, x) out_be32((unsigned *)addr, x)
52 #define __fcc_out16(addr, x) out_be16((unsigned short *)addr, x)
53 #define __fcc_out8(addr, x) out_8((unsigned char *)addr, x)
54 #define __fcc_in32(addr) in_be32((unsigned *)addr)
55 #define __fcc_in16(addr) in_be16((unsigned short *)addr)
56 #define __fcc_in8(addr) in_8((unsigned char *)addr)
60 /* write, read, set bits, clear bits */
61 #define W32(_p, _m, _v) __fcc_out32(&(_p)->_m, (_v))
62 #define R32(_p, _m) __fcc_in32(&(_p)->_m)
63 #define S32(_p, _m, _v) W32(_p, _m, R32(_p, _m) | (_v))
64 #define C32(_p, _m, _v) W32(_p, _m, R32(_p, _m) & ~(_v))
66 #define W16(_p, _m, _v) __fcc_out16(&(_p)->_m, (_v))
67 #define R16(_p, _m) __fcc_in16(&(_p)->_m)
68 #define S16(_p, _m, _v) W16(_p, _m, R16(_p, _m) | (_v))
69 #define C16(_p, _m, _v) W16(_p, _m, R16(_p, _m) & ~(_v))
71 #define W8(_p, _m, _v) __fcc_out8(&(_p)->_m, (_v))
72 #define R8(_p, _m) __fcc_in8(&(_p)->_m)
73 #define S8(_p, _m, _v) W8(_p, _m, R8(_p, _m) | (_v))
74 #define C8(_p, _m, _v) W8(_p, _m, R8(_p, _m) & ~(_v))
76 /*************************************************/
78 #define FCC_MAX_MULTICAST_ADDRS 64
80 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
81 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
84 #define MAX_CR_CMD_LOOPS 10000
86 static inline int fcc_cr_cmd(struct fs_enet_private
*fep
, u32 mcn
, u32 op
)
88 const struct fs_platform_info
*fpi
= fep
->fpi
;
90 cpm2_map_t
*immap
= fs_enet_immap
;
91 cpm_cpm2_t
*cpmp
= &immap
->im_cpm
;
95 /* Currently I don't know what feature call will look like. But
96 I guess there'd be something like do_cpm_cmd() which will require page & sblock */
97 v
= mk_cr_cmd(fpi
->cp_page
, fpi
->cp_block
, mcn
, op
);
98 W32(cpmp
, cp_cpcr
, v
| CPM_CR_FLG
);
99 for (i
= 0; i
< MAX_CR_CMD_LOOPS
; i
++)
100 if ((R32(cpmp
, cp_cpcr
) & CPM_CR_FLG
) == 0)
103 if (i
>= MAX_CR_CMD_LOOPS
) {
104 printk(KERN_ERR
"%s(): Not able to issue CPM command\n",
112 static int do_pd_setup(struct fs_enet_private
*fep
)
114 struct platform_device
*pdev
= to_platform_device(fep
->dev
);
117 /* Fill out IRQ field */
118 fep
->interrupt
= platform_get_irq(pdev
, 0);
119 if (fep
->interrupt
< 0)
122 /* Attach the memory for the FCC Parameter RAM */
123 r
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "fcc_pram");
124 fep
->fcc
.ep
= (void *)ioremap(r
->start
, r
->end
- r
->start
+ 1);
125 if (fep
->fcc
.ep
== NULL
)
128 r
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "fcc_regs");
129 fep
->fcc
.fccp
= (void *)ioremap(r
->start
, r
->end
- r
->start
+ 1);
130 if (fep
->fcc
.fccp
== NULL
)
133 if (fep
->fpi
->fcc_regs_c
) {
135 fep
->fcc
.fcccp
= (void *)fep
->fpi
->fcc_regs_c
;
137 r
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
,
139 fep
->fcc
.fcccp
= (void *)ioremap(r
->start
,
140 r
->end
- r
->start
+ 1);
143 if (fep
->fcc
.fcccp
== NULL
)
146 fep
->fcc
.mem
= (void *)fep
->fpi
->mem_offset
;
147 if (fep
->fcc
.mem
== NULL
)
153 #define FCC_NAPI_RX_EVENT_MSK (FCC_ENET_RXF | FCC_ENET_RXB)
154 #define FCC_RX_EVENT (FCC_ENET_RXF)
155 #define FCC_TX_EVENT (FCC_ENET_TXB)
156 #define FCC_ERR_EVENT_MSK (FCC_ENET_TXE | FCC_ENET_BSY)
158 static int setup_data(struct net_device
*dev
)
160 struct fs_enet_private
*fep
= netdev_priv(dev
);
161 const struct fs_platform_info
*fpi
= fep
->fpi
;
163 fep
->fcc
.idx
= fs_get_fcc_index(fpi
->fs_no
);
164 if ((unsigned int)fep
->fcc
.idx
>= 3) /* max 3 FCCs */
167 if (do_pd_setup(fep
) != 0)
170 fep
->ev_napi_rx
= FCC_NAPI_RX_EVENT_MSK
;
171 fep
->ev_rx
= FCC_RX_EVENT
;
172 fep
->ev_tx
= FCC_TX_EVENT
;
173 fep
->ev_err
= FCC_ERR_EVENT_MSK
;
178 static int allocate_bd(struct net_device
*dev
)
180 struct fs_enet_private
*fep
= netdev_priv(dev
);
181 const struct fs_platform_info
*fpi
= fep
->fpi
;
183 fep
->ring_base
= dma_alloc_coherent(fep
->dev
,
184 (fpi
->tx_ring
+ fpi
->rx_ring
) *
185 sizeof(cbd_t
), &fep
->ring_mem_addr
,
187 if (fep
->ring_base
== NULL
)
193 static void free_bd(struct net_device
*dev
)
195 struct fs_enet_private
*fep
= netdev_priv(dev
);
196 const struct fs_platform_info
*fpi
= fep
->fpi
;
199 dma_free_coherent(fep
->dev
,
200 (fpi
->tx_ring
+ fpi
->rx_ring
) * sizeof(cbd_t
),
201 fep
->ring_base
, fep
->ring_mem_addr
);
204 static void cleanup_data(struct net_device
*dev
)
209 static void set_promiscuous_mode(struct net_device
*dev
)
211 struct fs_enet_private
*fep
= netdev_priv(dev
);
212 fcc_t
*fccp
= fep
->fcc
.fccp
;
214 S32(fccp
, fcc_fpsmr
, FCC_PSMR_PRO
);
217 static void set_multicast_start(struct net_device
*dev
)
219 struct fs_enet_private
*fep
= netdev_priv(dev
);
220 fcc_enet_t
*ep
= fep
->fcc
.ep
;
222 W32(ep
, fen_gaddrh
, 0);
223 W32(ep
, fen_gaddrl
, 0);
226 static void set_multicast_one(struct net_device
*dev
, const u8
*mac
)
228 struct fs_enet_private
*fep
= netdev_priv(dev
);
229 fcc_enet_t
*ep
= fep
->fcc
.ep
;
230 u16 taddrh
, taddrm
, taddrl
;
232 taddrh
= ((u16
)mac
[5] << 8) | mac
[4];
233 taddrm
= ((u16
)mac
[3] << 8) | mac
[2];
234 taddrl
= ((u16
)mac
[1] << 8) | mac
[0];
236 W16(ep
, fen_taddrh
, taddrh
);
237 W16(ep
, fen_taddrm
, taddrm
);
238 W16(ep
, fen_taddrl
, taddrl
);
239 fcc_cr_cmd(fep
, 0x0C, CPM_CR_SET_GADDR
);
242 static void set_multicast_finish(struct net_device
*dev
)
244 struct fs_enet_private
*fep
= netdev_priv(dev
);
245 fcc_t
*fccp
= fep
->fcc
.fccp
;
246 fcc_enet_t
*ep
= fep
->fcc
.ep
;
248 /* clear promiscuous always */
249 C32(fccp
, fcc_fpsmr
, FCC_PSMR_PRO
);
251 /* if all multi or too many multicasts; just enable all */
252 if ((dev
->flags
& IFF_ALLMULTI
) != 0 ||
253 dev
->mc_count
> FCC_MAX_MULTICAST_ADDRS
) {
255 W32(ep
, fen_gaddrh
, 0xffffffff);
256 W32(ep
, fen_gaddrl
, 0xffffffff);
260 fep
->fcc
.gaddrh
= R32(ep
, fen_gaddrh
);
261 fep
->fcc
.gaddrl
= R32(ep
, fen_gaddrl
);
264 static void set_multicast_list(struct net_device
*dev
)
266 struct dev_mc_list
*pmc
;
268 if ((dev
->flags
& IFF_PROMISC
) == 0) {
269 set_multicast_start(dev
);
270 for (pmc
= dev
->mc_list
; pmc
!= NULL
; pmc
= pmc
->next
)
271 set_multicast_one(dev
, pmc
->dmi_addr
);
272 set_multicast_finish(dev
);
274 set_promiscuous_mode(dev
);
277 static void restart(struct net_device
*dev
)
279 struct fs_enet_private
*fep
= netdev_priv(dev
);
280 const struct fs_platform_info
*fpi
= fep
->fpi
;
281 fcc_t
*fccp
= fep
->fcc
.fccp
;
282 fcc_c_t
*fcccp
= fep
->fcc
.fcccp
;
283 fcc_enet_t
*ep
= fep
->fcc
.ep
;
284 dma_addr_t rx_bd_base_phys
, tx_bd_base_phys
;
285 u16 paddrh
, paddrm
, paddrl
;
287 const unsigned char *mac
;
290 C32(fccp
, fcc_gfmr
, FCC_GFMR_ENR
| FCC_GFMR_ENT
);
292 /* clear everything (slow & steady does it) */
293 for (i
= 0; i
< sizeof(*ep
); i
++)
294 __fcc_out8((char *)ep
+ i
, 0);
296 /* get physical address */
297 rx_bd_base_phys
= fep
->ring_mem_addr
;
298 tx_bd_base_phys
= rx_bd_base_phys
+ sizeof(cbd_t
) * fpi
->rx_ring
;
301 W32(ep
, fen_genfcc
.fcc_rbase
, rx_bd_base_phys
);
302 W32(ep
, fen_genfcc
.fcc_tbase
, tx_bd_base_phys
);
304 /* Set maximum bytes per receive buffer.
305 * It must be a multiple of 32.
307 W16(ep
, fen_genfcc
.fcc_mrblr
, PKT_MAXBLR_SIZE
);
309 W32(ep
, fen_genfcc
.fcc_rstate
, (CPMFCR_GBL
| CPMFCR_EB
) << 24);
310 W32(ep
, fen_genfcc
.fcc_tstate
, (CPMFCR_GBL
| CPMFCR_EB
) << 24);
312 /* Allocate space in the reserved FCC area of DPRAM for the
313 * internal buffers. No one uses this space (yet), so we
314 * can do this. Later, we will add resource management for
318 mem_addr
= (u32
) fep
->fcc
.mem
; /* de-fixup dpram offset */
320 W16(ep
, fen_genfcc
.fcc_riptr
, (mem_addr
& 0xffff));
321 W16(ep
, fen_genfcc
.fcc_tiptr
, ((mem_addr
+ 32) & 0xffff));
322 W16(ep
, fen_padptr
, mem_addr
+ 64);
324 /* fill with special symbol... */
325 memset(fep
->fcc
.mem
+ fpi
->dpram_offset
+ 64, 0x88, 32);
327 W32(ep
, fen_genfcc
.fcc_rbptr
, 0);
328 W32(ep
, fen_genfcc
.fcc_tbptr
, 0);
329 W32(ep
, fen_genfcc
.fcc_rcrc
, 0);
330 W32(ep
, fen_genfcc
.fcc_tcrc
, 0);
331 W16(ep
, fen_genfcc
.fcc_res1
, 0);
332 W32(ep
, fen_genfcc
.fcc_res2
, 0);
335 W32(ep
, fen_camptr
, 0);
337 /* Set CRC preset and mask */
338 W32(ep
, fen_cmask
, 0xdebb20e3);
339 W32(ep
, fen_cpres
, 0xffffffff);
341 W32(ep
, fen_crcec
, 0); /* CRC Error counter */
342 W32(ep
, fen_alec
, 0); /* alignment error counter */
343 W32(ep
, fen_disfc
, 0); /* discard frame counter */
344 W16(ep
, fen_retlim
, 15); /* Retry limit threshold */
345 W16(ep
, fen_pper
, 0); /* Normal persistence */
347 /* set group address */
348 W32(ep
, fen_gaddrh
, fep
->fcc
.gaddrh
);
349 W32(ep
, fen_gaddrl
, fep
->fcc
.gaddrh
);
351 /* Clear hash filter tables */
352 W32(ep
, fen_iaddrh
, 0);
353 W32(ep
, fen_iaddrl
, 0);
355 /* Clear the Out-of-sequence TxBD */
356 W16(ep
, fen_tfcstat
, 0);
357 W16(ep
, fen_tfclen
, 0);
358 W32(ep
, fen_tfcptr
, 0);
360 W16(ep
, fen_mflr
, PKT_MAXBUF_SIZE
); /* maximum frame length register */
361 W16(ep
, fen_minflr
, PKT_MINBUF_SIZE
); /* minimum frame length register */
365 paddrh
= ((u16
)mac
[5] << 8) | mac
[4];
366 paddrm
= ((u16
)mac
[3] << 8) | mac
[2];
367 paddrl
= ((u16
)mac
[1] << 8) | mac
[0];
369 W16(ep
, fen_paddrh
, paddrh
);
370 W16(ep
, fen_paddrm
, paddrm
);
371 W16(ep
, fen_paddrl
, paddrl
);
373 W16(ep
, fen_taddrh
, 0);
374 W16(ep
, fen_taddrm
, 0);
375 W16(ep
, fen_taddrl
, 0);
377 W16(ep
, fen_maxd1
, 1520); /* maximum DMA1 length */
378 W16(ep
, fen_maxd2
, 1520); /* maximum DMA2 length */
380 /* Clear stat counters, in case we ever enable RMON */
381 W32(ep
, fen_octc
, 0);
382 W32(ep
, fen_colc
, 0);
383 W32(ep
, fen_broc
, 0);
384 W32(ep
, fen_mulc
, 0);
385 W32(ep
, fen_uspc
, 0);
386 W32(ep
, fen_frgc
, 0);
387 W32(ep
, fen_ospc
, 0);
388 W32(ep
, fen_jbrc
, 0);
389 W32(ep
, fen_p64c
, 0);
390 W32(ep
, fen_p65c
, 0);
391 W32(ep
, fen_p128c
, 0);
392 W32(ep
, fen_p256c
, 0);
393 W32(ep
, fen_p512c
, 0);
394 W32(ep
, fen_p1024c
, 0);
396 W16(ep
, fen_rfthr
, 0); /* Suggested by manual */
397 W16(ep
, fen_rfcnt
, 0);
398 W16(ep
, fen_cftype
, 0);
402 /* adjust to speed (for RMII mode) */
404 if (fep
->phydev
->speed
== 100)
405 C8(fcccp
, fcc_gfemr
, 0x20);
407 S8(fcccp
, fcc_gfemr
, 0x20);
410 fcc_cr_cmd(fep
, 0x0c, CPM_CR_INIT_TRX
);
413 W16(fccp
, fcc_fcce
, 0xffff);
415 /* Enable interrupts we wish to service */
416 W16(fccp
, fcc_fccm
, FCC_ENET_TXE
| FCC_ENET_RXF
| FCC_ENET_TXB
);
418 /* Set GFMR to enable Ethernet operating mode */
419 W32(fccp
, fcc_gfmr
, FCC_GFMR_TCI
| FCC_GFMR_MODE_ENET
);
421 /* set sync/delimiters */
422 W16(fccp
, fcc_fdsr
, 0xd555);
424 W32(fccp
, fcc_fpsmr
, FCC_PSMR_ENCRC
);
427 S32(fccp
, fcc_fpsmr
, FCC_PSMR_RMII
);
429 /* adjust to duplex mode */
430 if (fep
->phydev
->duplex
)
431 S32(fccp
, fcc_fpsmr
, FCC_PSMR_FDE
| FCC_PSMR_LPB
);
433 C32(fccp
, fcc_fpsmr
, FCC_PSMR_FDE
| FCC_PSMR_LPB
);
435 S32(fccp
, fcc_gfmr
, FCC_GFMR_ENR
| FCC_GFMR_ENT
);
438 static void stop(struct net_device
*dev
)
440 struct fs_enet_private
*fep
= netdev_priv(dev
);
441 fcc_t
*fccp
= fep
->fcc
.fccp
;
444 C32(fccp
, fcc_gfmr
, FCC_GFMR_ENR
| FCC_GFMR_ENT
);
447 W16(fccp
, fcc_fcce
, 0xffff);
449 /* clear interrupt mask */
450 W16(fccp
, fcc_fccm
, 0);
455 static void pre_request_irq(struct net_device
*dev
, int irq
)
460 static void post_free_irq(struct net_device
*dev
, int irq
)
465 static void napi_clear_rx_event(struct net_device
*dev
)
467 struct fs_enet_private
*fep
= netdev_priv(dev
);
468 fcc_t
*fccp
= fep
->fcc
.fccp
;
470 W16(fccp
, fcc_fcce
, FCC_NAPI_RX_EVENT_MSK
);
473 static void napi_enable_rx(struct net_device
*dev
)
475 struct fs_enet_private
*fep
= netdev_priv(dev
);
476 fcc_t
*fccp
= fep
->fcc
.fccp
;
478 S16(fccp
, fcc_fccm
, FCC_NAPI_RX_EVENT_MSK
);
481 static void napi_disable_rx(struct net_device
*dev
)
483 struct fs_enet_private
*fep
= netdev_priv(dev
);
484 fcc_t
*fccp
= fep
->fcc
.fccp
;
486 C16(fccp
, fcc_fccm
, FCC_NAPI_RX_EVENT_MSK
);
489 static void rx_bd_done(struct net_device
*dev
)
494 static void tx_kickstart(struct net_device
*dev
)
496 struct fs_enet_private
*fep
= netdev_priv(dev
);
497 fcc_t
*fccp
= fep
->fcc
.fccp
;
499 S32(fccp
, fcc_ftodr
, 0x80);
502 static u32
get_int_events(struct net_device
*dev
)
504 struct fs_enet_private
*fep
= netdev_priv(dev
);
505 fcc_t
*fccp
= fep
->fcc
.fccp
;
507 return (u32
)R16(fccp
, fcc_fcce
);
510 static void clear_int_events(struct net_device
*dev
, u32 int_events
)
512 struct fs_enet_private
*fep
= netdev_priv(dev
);
513 fcc_t
*fccp
= fep
->fcc
.fccp
;
515 W16(fccp
, fcc_fcce
, int_events
& 0xffff);
518 static void ev_error(struct net_device
*dev
, u32 int_events
)
520 printk(KERN_WARNING DRV_MODULE_NAME
521 ": %s FS_ENET ERROR(s) 0x%x\n", dev
->name
, int_events
);
524 int get_regs(struct net_device
*dev
, void *p
, int *sizep
)
526 struct fs_enet_private
*fep
= netdev_priv(dev
);
528 if (*sizep
< sizeof(fcc_t
) + sizeof(fcc_c_t
) + sizeof(fcc_enet_t
))
531 memcpy_fromio(p
, fep
->fcc
.fccp
, sizeof(fcc_t
));
532 p
= (char *)p
+ sizeof(fcc_t
);
534 memcpy_fromio(p
, fep
->fcc
.fcccp
, sizeof(fcc_c_t
));
535 p
= (char *)p
+ sizeof(fcc_c_t
);
537 memcpy_fromio(p
, fep
->fcc
.ep
, sizeof(fcc_enet_t
));
542 int get_regs_len(struct net_device
*dev
)
544 return sizeof(fcc_t
) + sizeof(fcc_c_t
) + sizeof(fcc_enet_t
);
547 /* Some transmit errors cause the transmitter to shut
548 * down. We now issue a restart transmit. Since the
549 * errors close the BD and update the pointers, the restart
550 * _should_ pick up without having to reset any of our
551 * pointers either. Also, To workaround 8260 device erratum
552 * CPM37, we must disable and then re-enable the transmitter
553 * following a Late Collision, Underrun, or Retry Limit error.
555 void tx_restart(struct net_device
*dev
)
557 struct fs_enet_private
*fep
= netdev_priv(dev
);
558 fcc_t
*fccp
= fep
->fcc
.fccp
;
560 C32(fccp
, fcc_gfmr
, FCC_GFMR_ENT
);
562 S32(fccp
, fcc_gfmr
, FCC_GFMR_ENT
);
564 fcc_cr_cmd(fep
, 0x0C, CPM_CR_RESTART_TX
);
567 /*************************************************************************/
569 const struct fs_ops fs_fcc_ops
= {
570 .setup_data
= setup_data
,
571 .cleanup_data
= cleanup_data
,
572 .set_multicast_list
= set_multicast_list
,
575 .pre_request_irq
= pre_request_irq
,
576 .post_free_irq
= post_free_irq
,
577 .napi_clear_rx_event
= napi_clear_rx_event
,
578 .napi_enable_rx
= napi_enable_rx
,
579 .napi_disable_rx
= napi_disable_rx
,
580 .rx_bd_done
= rx_bd_done
,
581 .tx_kickstart
= tx_kickstart
,
582 .get_int_events
= get_int_events
,
583 .clear_int_events
= clear_int_events
,
584 .ev_error
= ev_error
,
585 .get_regs
= get_regs
,
586 .get_regs_len
= get_regs_len
,
587 .tx_restart
= tx_restart
,
588 .allocate_bd
= allocate_bd
,