drivers/infiniband/hw/ipath/ipath_iba6120.c

   1 /*
   2  * Copyright (c) 2006 QLogic, Inc. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33 /*
  34  * This file contains all of the code that is specific to the
  35  * InfiniPath PCIe chip.
  36  */
  37
  38 #include <linux/interrupt.h>
  39 #include <linux/pci.h>
  40 #include <linux/delay.h>
  41
  42
  43 #include "ipath_kernel.h"
  44 #include "ipath_registers.h"
  45
  46 /*
  47  * This file contains all the chip-specific register information and
  48  * access functions for the QLogic InfiniPath PCI-Express chip.
  49  *
  50  * This lists the InfiniPath registers, in the actual chip layout.
  51  * This structure should never be directly accessed.
  52  */
  53 struct _infinipath_do_not_use_kernel_regs {
  54         unsigned long long Revision;
  55         unsigned long long Control;
  56         unsigned long long PageAlign;
  57         unsigned long long PortCnt;
  58         unsigned long long DebugPortSelect;
  59         unsigned long long Reserved0;
  60         unsigned long long SendRegBase;
  61         unsigned long long UserRegBase;
  62         unsigned long long CounterRegBase;
  63         unsigned long long Scratch;
  64         unsigned long long Reserved1;
  65         unsigned long long Reserved2;
  66         unsigned long long IntBlocked;
  67         unsigned long long IntMask;
  68         unsigned long long IntStatus;
  69         unsigned long long IntClear;
  70         unsigned long long ErrorMask;
  71         unsigned long long ErrorStatus;
  72         unsigned long long ErrorClear;
  73         unsigned long long HwErrMask;
  74         unsigned long long HwErrStatus;
  75         unsigned long long HwErrClear;
  76         unsigned long long HwDiagCtrl;
  77         unsigned long long MDIO;
  78         unsigned long long IBCStatus;
  79         unsigned long long IBCCtrl;
  80         unsigned long long ExtStatus;
  81         unsigned long long ExtCtrl;
  82         unsigned long long GPIOOut;
  83         unsigned long long GPIOMask;
  84         unsigned long long GPIOStatus;
  85         unsigned long long GPIOClear;
  86         unsigned long long RcvCtrl;
  87         unsigned long long RcvBTHQP;
  88         unsigned long long RcvHdrSize;
  89         unsigned long long RcvHdrCnt;
  90         unsigned long long RcvHdrEntSize;
  91         unsigned long long RcvTIDBase;
  92         unsigned long long RcvTIDCnt;
  93         unsigned long long RcvEgrBase;
  94         unsigned long long RcvEgrCnt;
  95         unsigned long long RcvBufBase;
  96         unsigned long long RcvBufSize;
  97         unsigned long long RxIntMemBase;
  98         unsigned long long RxIntMemSize;
  99         unsigned long long RcvPartitionKey;
 100         unsigned long long Reserved3;
 101         unsigned long long RcvPktLEDCnt;
 102         unsigned long long Reserved4[8];
 103         unsigned long long SendCtrl;
 104         unsigned long long SendPIOBufBase;
 105         unsigned long long SendPIOSize;
 106         unsigned long long SendPIOBufCnt;
 107         unsigned long long SendPIOAvailAddr;
 108         unsigned long long TxIntMemBase;
 109         unsigned long long TxIntMemSize;
 110         unsigned long long Reserved5;
 111         unsigned long long PCIeRBufTestReg0;
 112         unsigned long long PCIeRBufTestReg1;
 113         unsigned long long Reserved51[6];
 114         unsigned long long SendBufferError;
 115         unsigned long long SendBufferErrorCONT1;
 116         unsigned long long Reserved6SBE[6];
 117         unsigned long long RcvHdrAddr0;
 118         unsigned long long RcvHdrAddr1;
 119         unsigned long long RcvHdrAddr2;
 120         unsigned long long RcvHdrAddr3;
 121         unsigned long long RcvHdrAddr4;
 122         unsigned long long Reserved7RHA[11];
 123         unsigned long long RcvHdrTailAddr0;
 124         unsigned long long RcvHdrTailAddr1;
 125         unsigned long long RcvHdrTailAddr2;
 126         unsigned long long RcvHdrTailAddr3;
 127         unsigned long long RcvHdrTailAddr4;
 128         unsigned long long Reserved8RHTA[11];
 129         unsigned long long Reserved9SW[8];
 130         unsigned long long SerdesConfig0;
 131         unsigned long long SerdesConfig1;
 132         unsigned long long SerdesStatus;
 133         unsigned long long XGXSConfig;
 134         unsigned long long IBPLLCfg;
 135         unsigned long long Reserved10SW2[3];
 136         unsigned long long PCIEQ0SerdesConfig0;
 137         unsigned long long PCIEQ0SerdesConfig1;
 138         unsigned long long PCIEQ0SerdesStatus;
 139         unsigned long long Reserved11;
 140         unsigned long long PCIEQ1SerdesConfig0;
 141         unsigned long long PCIEQ1SerdesConfig1;
 142         unsigned long long PCIEQ1SerdesStatus;
 143         unsigned long long Reserved12;
 144 };
 145
 146 #define IPATH_KREG_OFFSET(field) (offsetof(struct \
 147     _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
 148 #define IPATH_CREG_OFFSET(field) (offsetof( \
 149     struct infinipath_counters, field) / sizeof(u64))
 150
 151 static const struct ipath_kregs ipath_pe_kregs = {
 152         .kr_control = IPATH_KREG_OFFSET(Control),
 153         .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
 154         .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
 155         .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
 156         .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
 157         .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
 158         .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
 159         .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
 160         .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
 161         .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
 162         .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
 163         .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
 164         .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
 165         .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
 166         .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
 167         .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
 168         .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
 169         .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
 170         .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
 171         .kr_intclear = IPATH_KREG_OFFSET(IntClear),
 172         .kr_intmask = IPATH_KREG_OFFSET(IntMask),
 173         .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
 174         .kr_mdio = IPATH_KREG_OFFSET(MDIO),
 175         .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
 176         .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
 177         .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
 178         .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
 179         .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
 180         .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
 181         .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
 182         .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
 183         .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
 184         .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
 185         .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
 186         .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
 187         .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
 188         .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
 189         .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
 190         .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
 191         .kr_revision = IPATH_KREG_OFFSET(Revision),
 192         .kr_scratch = IPATH_KREG_OFFSET(Scratch),
 193         .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
 194         .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
 195         .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
 196         .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
 197         .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
 198         .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
 199         .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
 200         .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
 201         .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
 202         .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
 203         .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
 204         .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
 205         .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
 206         .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
 207         .kr_ibpllcfg = IPATH_KREG_OFFSET(IBPLLCfg),
 208
 209         /*
 210          * These should not be used directly via ipath_read_kreg64(),
 211          * use them with ipath_read_kreg64_port()
 212          */
 213         .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
 214         .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0),
 215
 216         /* The rcvpktled register controls one of the debug port signals, so
 217          * a packet activity LED can be connected to it. */
 218         .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt),
 219         .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0),
 220         .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1),
 221         .kr_pcieq0serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig0),
 222         .kr_pcieq0serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig1),
 223         .kr_pcieq0serdesstatus = IPATH_KREG_OFFSET(PCIEQ0SerdesStatus),
 224         .kr_pcieq1serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig0),
 225         .kr_pcieq1serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig1),
 226         .kr_pcieq1serdesstatus = IPATH_KREG_OFFSET(PCIEQ1SerdesStatus)
 227 };
 228
 229 static const struct ipath_cregs ipath_pe_cregs = {
 230         .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
 231         .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
 232         .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
 233         .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
 234         .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
 235         .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
 236         .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
 237         .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
 238         .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
 239         .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
 240         .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
 241         .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
 242         .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
 243         .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
 244         .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
 245         .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
 246         .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
 247         .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
 248         .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
 249         .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
 250         .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
 251         .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
 252         .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
 253         .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
 254         .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
 255         .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
 256         .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
 257         .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
 258         .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
 259         .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
 260         .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
 261         .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
 262         .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
 263 };
 264
 265 /* kr_intstatus, kr_intclear, kr_intmask bits */
 266 #define INFINIPATH_I_RCVURG_MASK 0x1F
 267 #define INFINIPATH_I_RCVAVAIL_MASK 0x1F
 268
 269 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
 270 #define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK  0x000000000000003fULL
 271 #define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
 272 #define INFINIPATH_HWE_PCIEPOISONEDTLP      0x0000000010000000ULL
 273 #define INFINIPATH_HWE_PCIECPLTIMEOUT       0x0000000020000000ULL
 274 #define INFINIPATH_HWE_PCIEBUSPARITYXTLH    0x0000000040000000ULL
 275 #define INFINIPATH_HWE_PCIEBUSPARITYXADM    0x0000000080000000ULL
 276 #define INFINIPATH_HWE_PCIEBUSPARITYRADM    0x0000000100000000ULL
 277 #define INFINIPATH_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
 278 #define INFINIPATH_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
 279 #define INFINIPATH_HWE_PCIE1PLLFAILED       0x0400000000000000ULL
 280 #define INFINIPATH_HWE_PCIE0PLLFAILED       0x0800000000000000ULL
 281 #define INFINIPATH_HWE_SERDESPLLFAILED      0x1000000000000000ULL
 282
 283 /* kr_extstatus bits */
 284 #define INFINIPATH_EXTS_FREQSEL 0x2
 285 #define INFINIPATH_EXTS_SERDESSEL 0x4
 286 #define INFINIPATH_EXTS_MEMBIST_ENDTEST     0x0000000000004000
 287 #define INFINIPATH_EXTS_MEMBIST_FOUND       0x0000000000008000
 288
 289 #define _IPATH_GPIO_SDA_NUM 1
 290 #define _IPATH_GPIO_SCL_NUM 0
 291
 292 #define IPATH_GPIO_SDA (1ULL << \
 293         (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 294 #define IPATH_GPIO_SCL (1ULL << \
 295         (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 296
 297 /*
 298  * Rev2 silicon allows suppressing check for ArmLaunch errors.
 299  * this can speed up short packet sends on systems that do
 300  * not guaranteee write-order.
 301  */
 302 #define INFINIPATH_XGXS_SUPPRESS_ARMLAUNCH_ERR (1ULL<<63)
 303
 304 /* 6120 specific hardware errors... */
 305 static const struct ipath_hwerror_msgs ipath_6120_hwerror_msgs[] = {
 306         INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
 307         INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
 308         /*
 309          * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
 310          * parity or memory parity error failures, because most likely we
 311          * won't be able to talk to the core of the chip.  Nonetheless, we
 312          * might see them, if they are in parts of the PCIe core that aren't
 313          * essential.
 314          */
 315         INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
 316         INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
 317         INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
 318         INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
 319         INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
 320         INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
 321         INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
 322 };
 323
 324 /**
 325  * ipath_pe_handle_hwerrors - display hardware errors.
 326  * @dd: the infinipath device
 327  * @msg: the output buffer
 328  * @msgl: the size of the output buffer
 329  *
 330  * Use same msg buffer as regular errors to avoid excessive stack
 331  * use.  Most hardware errors are catastrophic, but for right now,
 332  * we'll print them and continue.  We reuse the same message buffer as
 333  * ipath_handle_errors() to avoid excessive stack usage.
 334  */
 335 static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
 336                                      size_t msgl)
 337 {
 338         ipath_err_t hwerrs;
 339         u32 bits, ctrl;
 340         int isfatal = 0;
 341         char bitsmsg[64];
 342
 343         hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
 344         if (!hwerrs) {
 345                 /*
 346                  * better than printing cofusing messages
 347                  * This seems to be related to clearing the crc error, or
 348                  * the pll error during init.
 349                  */
 350                 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
 351                 return;
 352         } else if (hwerrs == ~0ULL) {
 353                 ipath_dev_err(dd, "Read of hardware error status failed "
 354                               "(all bits set); ignoring\n");
 355                 return;
 356         }
 357         ipath_stats.sps_hwerrs++;
 358
 359         /* Always clear the error status register, except MEMBISTFAIL,
 360          * regardless of whether we continue or stop using the chip.
 361          * We want that set so we know it failed, even across driver reload.
 362          * We'll still ignore it in the hwerrmask.  We do this partly for
 363          * diagnostics, but also for support */
 364         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 365                          hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
 366
 367         hwerrs &= dd->ipath_hwerrmask;
 368
 369         /*
 370          * make sure we get this much out, unless told to be quiet,
 371          * or it's occurred within the last 5 seconds
 372          */
 373         if ((hwerrs & ~dd->ipath_lasthwerror) ||
 374             (ipath_debug & __IPATH_VERBDBG))
 375                 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
 376                          "(cleared)\n", (unsigned long long) hwerrs);
 377         dd->ipath_lasthwerror |= hwerrs;
 378
 379         if (hwerrs & ~infinipath_hwe_bitsextant)
 380                 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
 381                               "%llx set\n", (unsigned long long)
 382                               (hwerrs & ~infinipath_hwe_bitsextant));
 383
 384         ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
 385         if (ctrl & INFINIPATH_C_FREEZEMODE) {
 386                 if (hwerrs) {
 387                         /*
 388                          * if any set that we aren't ignoring only make the
 389                          * complaint once, in case it's stuck or recurring,
 390                          * and we get here multiple times
 391                          */
 392                         if (dd->ipath_flags & IPATH_INITTED) {
 393                                 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
 394                                               "mode), no longer usable, SN %.16s\n",
 395                                                   dd->ipath_serial);
 396                                 isfatal = 1;
 397                         }
 398                         /*
 399                          * Mark as having had an error for driver, and also
 400                          * for /sys and status word mapped to user programs.
 401                          * This marks unit as not usable, until reset
 402                          */
 403                         *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
 404                         *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 405                         dd->ipath_flags &= ~IPATH_INITTED;
 406                 } else {
 407                         ipath_dbg("Clearing freezemode on ignored hardware "
 408                                   "error\n");
 409                         ctrl &= ~INFINIPATH_C_FREEZEMODE;
 410                         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 411                                          ctrl);
 412                 }
 413         }
 414
 415         *msg = '\0';
 416
 417         if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
 418                 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
 419                         msgl);
 420                 /* ignore from now on, so disable until driver reloaded */
 421                 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 422                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
 423                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 424                                  dd->ipath_hwerrmask);
 425         }
 426
 427         ipath_format_hwerrors(hwerrs,
 428                               ipath_6120_hwerror_msgs,
 429                               sizeof(ipath_6120_hwerror_msgs)/
 430                               sizeof(ipath_6120_hwerror_msgs[0]),
 431                               msg, msgl);
 432
 433         if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
 434                       << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
 435                 bits = (u32) ((hwerrs >>
 436                                INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) &
 437                               INFINIPATH_HWE_PCIEMEMPARITYERR_MASK);
 438                 snprintf(bitsmsg, sizeof bitsmsg,
 439                          "[PCIe Mem Parity Errs %x] ", bits);
 440                 strlcat(msg, bitsmsg, msgl);
 441         }
 442
 443 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP |        \
 444                          INFINIPATH_HWE_COREPLL_RFSLIP )
 445
 446         if (hwerrs & _IPATH_PLL_FAIL) {
 447                 snprintf(bitsmsg, sizeof bitsmsg,
 448                          "[PLL failed (%llx), InfiniPath hardware unusable]",
 449                          (unsigned long long) hwerrs & _IPATH_PLL_FAIL);
 450                 strlcat(msg, bitsmsg, msgl);
 451                 /* ignore from now on, so disable until driver reloaded */
 452                 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
 453                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 454                                  dd->ipath_hwerrmask);
 455         }
 456
 457         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
 458                 /*
 459                  * If it occurs, it is left masked since the eternal
 460                  * interface is unused
 461                  */
 462                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 463                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 464                                  dd->ipath_hwerrmask);
 465         }
 466
 467         ipath_dev_err(dd, "%s hardware error\n", msg);
 468         if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) {
 469                 /*
 470                  * for /sys status file ; if no trailing } is copied, we'll
 471                  * know it was truncated.
 472                  */
 473                 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
 474                          "{%s}", msg);
 475         }
 476 }
 477
 478 /**
 479  * ipath_pe_boardname - fill in the board name
 480  * @dd: the infinipath device
 481  * @name: the output buffer
 482  * @namelen: the size of the output buffer
 483  *
 484  * info is based on the board revision register
 485  */
 486 static int ipath_pe_boardname(struct ipath_devdata *dd, char *name,
 487                               size_t namelen)
 488 {
 489         char *n = NULL;
 490         u8 boardrev = dd->ipath_boardrev;
 491         int ret;
 492
 493         switch (boardrev) {
 494         case 0:
 495                 n = "InfiniPath_Emulation";
 496                 break;
 497         case 1:
 498                 n = "InfiniPath_QLE7140-Bringup";
 499                 break;
 500         case 2:
 501                 n = "InfiniPath_QLE7140";
 502                 break;
 503         case 3:
 504                 n = "InfiniPath_QMI7140";
 505                 break;
 506         case 4:
 507                 n = "InfiniPath_QEM7140";
 508                 break;
 509         case 5:
 510                 n = "InfiniPath_QMH7140";
 511                 break;
 512         default:
 513                 ipath_dev_err(dd,
 514                               "Don't yet know about board with ID %u\n",
 515                               boardrev);
 516                 snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u",
 517                          boardrev);
 518                 break;
 519         }
 520         if (n)
 521                 snprintf(name, namelen, "%s", n);
 522
 523         if (dd->ipath_majrev != 4 || !dd->ipath_minrev || dd->ipath_minrev>2) {
 524                 ipath_dev_err(dd, "Unsupported InfiniPath hardware revision %u.%u!\n",
 525                               dd->ipath_majrev, dd->ipath_minrev);
 526                 ret = 1;
 527         } else
 528                 ret = 0;
 529
 530         return ret;
 531 }
 532
 533 /**
 534  * ipath_pe_init_hwerrors - enable hardware errors
 535  * @dd: the infinipath device
 536  *
 537  * now that we have finished initializing everything that might reasonably
 538  * cause a hardware error, and cleared those errors bits as they occur,
 539  * we can enable hardware errors in the mask (potentially enabling
 540  * freeze mode), and enable hardware errors as errors (along with
 541  * everything else) in errormask
 542  */
 543 static void ipath_pe_init_hwerrors(struct ipath_devdata *dd)
 544 {
 545         ipath_err_t val;
 546         u64 extsval;
 547
 548         extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
 549
 550         if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
 551                 ipath_dev_err(dd, "MemBIST did not complete!\n");
 552
 553         val = ~0ULL;    /* barring bugs, all hwerrors become interrupts, */
 554
 555         if (!dd->ipath_boardrev)        // no PLL for Emulator
 556                 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 557
 558         if (dd->ipath_minrev < 2) {
 559                 /* workaround bug 9460 in internal interface bus parity
 560                  * checking. Fixed (HW bug 9490) in Rev2.
 561                  */
 562                 val &= ~INFINIPATH_HWE_PCIEBUSPARITYRADM;
 563         }
 564         dd->ipath_hwerrmask = val;
 565 }
 566
 567 /**
 568  * ipath_pe_bringup_serdes - bring up the serdes
 569  * @dd: the infinipath device
 570  */
 571 static int ipath_pe_bringup_serdes(struct ipath_devdata *dd)
 572 {
 573         u64 val, tmp, config1, prev_val;
 574         int ret = 0;
 575
 576         ipath_dbg("Trying to bringup serdes\n");
 577
 578         if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
 579             INFINIPATH_HWE_SERDESPLLFAILED) {
 580                 ipath_dbg("At start, serdes PLL failed bit set "
 581                           "in hwerrstatus, clearing and continuing\n");
 582                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 583                                  INFINIPATH_HWE_SERDESPLLFAILED);
 584         }
 585
 586         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
 587         config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
 588
 589         ipath_cdbg(VERBOSE, "SerDes status config0=%llx config1=%llx, "
 590                    "xgxsconfig %llx\n", (unsigned long long) val,
 591                    (unsigned long long) config1, (unsigned long long)
 592                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
 593
 594         /*
 595          * Force reset on, also set rxdetect enable.  Must do before reading
 596          * serdesstatus at least for simulation, or some of the bits in
 597          * serdes status will come back as undefined and cause simulation
 598          * failures
 599          */
 600         val |= INFINIPATH_SERDC0_RESET_PLL | INFINIPATH_SERDC0_RXDETECT_EN
 601                 | INFINIPATH_SERDC0_L1PWR_DN;
 602         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 603         /* be sure chip saw it */
 604         tmp = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 605         udelay(5);              /* need pll reset set at least for a bit */
 606         /*
 607          * after PLL is reset, set the per-lane Resets and TxIdle and
 608          * clear the PLL reset and rxdetect (to get falling edge).
 609          * Leave L1PWR bits set (permanently)
 610          */
 611         val &= ~(INFINIPATH_SERDC0_RXDETECT_EN | INFINIPATH_SERDC0_RESET_PLL
 612                  | INFINIPATH_SERDC0_L1PWR_DN);
 613         val |= INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE;
 614         ipath_cdbg(VERBOSE, "Clearing pll reset and setting lane resets "
 615                    "and txidle (%llx)\n", (unsigned long long) val);
 616         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 617         /* be sure chip saw it */
 618         tmp = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 619         /* need PLL reset clear for at least 11 usec before lane
 620          * resets cleared; give it a few more to be sure */
 621         udelay(15);
 622         val &= ~(INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE);
 623
 624         ipath_cdbg(VERBOSE, "Clearing lane resets and txidle "
 625                    "(writing %llx)\n", (unsigned long long) val);
 626         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 627         /* be sure chip saw it */
 628         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 629
 630         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
 631         prev_val = val;
 632         if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
 633              INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
 634                 val &=
 635                         ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
 636                           INFINIPATH_XGXS_MDIOADDR_SHIFT);
 637                 /* MDIO address 3 */
 638                 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
 639         }
 640         if (val & INFINIPATH_XGXS_RESET) {
 641                 val &= ~INFINIPATH_XGXS_RESET;
 642         }
 643         if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
 644              INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
 645                 /* need to compensate for Tx inversion in partner */
 646                 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
 647                          INFINIPATH_XGXS_RX_POL_SHIFT);
 648                 val |= dd->ipath_rx_pol_inv <<
 649                         INFINIPATH_XGXS_RX_POL_SHIFT;
 650         }
 651         if (dd->ipath_minrev >= 2) {
 652                 /* Rev 2. can tolerate multiple writes to PBC, and
 653                  * allowing them can provide lower latency on some
 654                  * CPUs, but this feature is off by default, only
 655                  * turned on by setting D63 of XGXSconfig reg.
 656                  * May want to make this conditional more
 657                  * fine-grained in future. This is not exactly
 658                  * related to XGXS, but where the bit ended up.
 659                  */
 660                 val |= INFINIPATH_XGXS_SUPPRESS_ARMLAUNCH_ERR;
 661         }
 662         if (val != prev_val)
 663                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
 664
 665         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
 666
 667         /* clear current and de-emphasis bits */
 668         config1 &= ~0x0ffffffff00ULL;
 669         /* set current to 20ma */
 670         config1 |= 0x00000000000ULL;
 671         /* set de-emphasis to -5.68dB */
 672         config1 |= 0x0cccc000000ULL;
 673         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
 674
 675         ipath_cdbg(VERBOSE, "done: SerDes status config0=%llx "
 676                    "config1=%llx, sstatus=%llx xgxs=%llx\n",
 677                    (unsigned long long) val, (unsigned long long) config1,
 678                    (unsigned long long)
 679                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
 680                    (unsigned long long)
 681                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
 682
 683         if (!ipath_waitfor_mdio_cmdready(dd)) {
 684                 ipath_write_kreg(
 685                         dd, dd->ipath_kregs->kr_mdio,
 686                         ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
 687                                        IPATH_MDIO_CTRL_XGXS_REG_8, 0));
 688                 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
 689                                            IPATH_MDIO_DATAVALID, &val))
 690                         ipath_dbg("Never got MDIO data for XGXS "
 691                                   "status read\n");
 692                 else
 693                         ipath_cdbg(VERBOSE, "MDIO Read reg8, "
 694                                    "'bank' 31 %x\n", (u32) val);
 695         } else
 696                 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
 697
 698         return ret;
 699 }
 700
 701 /**
 702  * ipath_pe_quiet_serdes - set serdes to txidle
 703  * @dd: the infinipath device
 704  * Called when driver is being unloaded
 705  */
 706 static void ipath_pe_quiet_serdes(struct ipath_devdata *dd)
 707 {
 708         u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
 709
 710         val |= INFINIPATH_SERDC0_TXIDLE;
 711         ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
 712                   (unsigned long long) val);
 713         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 714 }
 715
 716 static int ipath_pe_intconfig(struct ipath_devdata *dd)
 717 {
 718         u64 val;
 719         u32 chiprev;
 720
 721         /*
 722          * If the chip supports added error indication via GPIO pins,
 723          * enable interrupts on those bits so the interrupt routine
 724          * can count the events. Also set flag so interrupt routine
 725          * can know they are expected.
 726          */
 727         chiprev = dd->ipath_revision >> INFINIPATH_R_CHIPREVMINOR_SHIFT;
 728         if ((chiprev & INFINIPATH_R_CHIPREVMINOR_MASK) > 1) {
 729                 /* Rev2+ reports extra errors via internal GPIO pins */
 730                 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
 731                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_gpio_mask);
 732                 val |= IPATH_GPIO_ERRINTR_MASK;
 733                 ipath_write_kreg( dd, dd->ipath_kregs->kr_gpio_mask, val);
 734         }
 735         return 0;
 736 }
 737
 738 /**
 739  * ipath_setup_pe_setextled - set the state of the two external LEDs
 740  * @dd: the infinipath device
 741  * @lst: the L state
 742  * @ltst: the LT state
 743
 744  * These LEDs indicate the physical and logical state of IB link.
 745  * For this chip (at least with recommended board pinouts), LED1
 746  * is Yellow (logical state) and LED2 is Green (physical state),
 747  *
 748  * Note:  We try to match the Mellanox HCA LED behavior as best
 749  * we can.  Green indicates physical link state is OK (something is
 750  * plugged in, and we can train).
 751  * Amber indicates the link is logically up (ACTIVE).
 752  * Mellanox further blinks the amber LED to indicate data packet
 753  * activity, but we have no hardware support for that, so it would
 754  * require waking up every 10-20 msecs and checking the counters
 755  * on the chip, and then turning the LED off if appropriate.  That's
 756  * visible overhead, so not something we will do.
 757  *
 758  */
 759 static void ipath_setup_pe_setextled(struct ipath_devdata *dd, u64 lst,
 760                                      u64 ltst)
 761 {
 762         u64 extctl;
 763
 764         /* the diags use the LED to indicate diag info, so we leave
 765          * the external LED alone when the diags are running */
 766         if (ipath_diag_inuse)
 767                 return;
 768
 769         extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
 770                                        INFINIPATH_EXTC_LED2PRIPORT_ON);
 771
 772         if (ltst & INFINIPATH_IBCS_LT_STATE_LINKUP)
 773                 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
 774         if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
 775                 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
 776         dd->ipath_extctrl = extctl;
 777         ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
 778 }
 779
 780 /**
 781  * ipath_setup_pe_cleanup - clean up any per-chip chip-specific stuff
 782  * @dd: the infinipath device
 783  *
 784  * This is called during driver unload.
 785  * We do the pci_disable_msi here, not in generic code, because it
 786  * isn't used for the HT chips. If we do end up needing pci_enable_msi
 787  * at some point in the future for HT, we'll move the call back
 788  * into the main init_one code.
 789  */
 790 static void ipath_setup_pe_cleanup(struct ipath_devdata *dd)
 791 {
 792         dd->ipath_msi_lo = 0;   /* just in case unload fails */
 793         pci_disable_msi(dd->pcidev);
 794 }
 795
 796 /**
 797  * ipath_setup_pe_config - setup PCIe config related stuff
 798  * @dd: the infinipath device
 799  * @pdev: the PCI device
 800  *
 801  * The pci_enable_msi() call will fail on systems with MSI quirks
 802  * such as those with AMD8131, even if the device of interest is not
 803  * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
 804  * late in 2.6.16).
 805  * All that can be done is to edit the kernel source to remove the quirk
 806  * check until that is fixed.
 807  * We do not need to call enable_msi() for our HyperTransport chip,
 808  * even though it uses MSI, and we want to avoid the quirk warning, so
 809  * So we call enable_msi only for PCIe.  If we do end up needing
 810  * pci_enable_msi at some point in the future for HT, we'll move the
 811  * call back into the main init_one code.
 812  * We save the msi lo and hi values, so we can restore them after
 813  * chip reset (the kernel PCI infrastructure doesn't yet handle that
 814  * correctly).
 815  */
 816 static int ipath_setup_pe_config(struct ipath_devdata *dd,
 817                                  struct pci_dev *pdev)
 818 {
 819         int pos, ret;
 820
 821         dd->ipath_msi_lo = 0;   /* used as a flag during reset processing */
 822         ret = pci_enable_msi(dd->pcidev);
 823         if (ret)
 824                 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
 825                               "interrupts may not work\n", ret);
 826         /* continue even if it fails, we may still be OK... */
 827
 828         if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
 829                 u16 control;
 830                 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
 831                                       &dd->ipath_msi_lo);
 832                 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
 833                                       &dd->ipath_msi_hi);
 834                 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
 835                                      &control);
 836                 /* now save the data (vector) info */
 837                 pci_read_config_word(dd->pcidev,
 838                                      pos + ((control & PCI_MSI_FLAGS_64BIT)
 839                                             ? 12 : 8),
 840                                      &dd->ipath_msi_data);
 841                 ipath_cdbg(VERBOSE, "Read msi data 0x%x from config offset "
 842                            "0x%x, control=0x%x\n", dd->ipath_msi_data,
 843                            pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
 844                            control);
 845                 /* we save the cachelinesize also, although it doesn't
 846                  * really matter */
 847                 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
 848                                      &dd->ipath_pci_cacheline);
 849         } else
 850                 ipath_dev_err(dd, "Can't find MSI capability, "
 851                               "can't save MSI settings for reset\n");
 852         if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP))) {
 853                 u16 linkstat;
 854                 pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
 855                                      &linkstat);
 856                 linkstat >>= 4;
 857                 linkstat &= 0x1f;
 858                 if (linkstat != 8)
 859                         ipath_dev_err(dd, "PCIe width %u, "
 860                                       "performance reduced\n", linkstat);
 861         }
 862         else
 863                 ipath_dev_err(dd, "Can't find PCI Express "
 864                               "capability!\n");
 865         return 0;
 866 }
 867
 868 static void ipath_init_pe_variables(void)
 869 {
 870         /*
 871          * bits for selecting i2c direction and values,
 872          * used for I2C serial flash
 873          */
 874         ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
 875         ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
 876         ipath_gpio_sda = IPATH_GPIO_SDA;
 877         ipath_gpio_scl = IPATH_GPIO_SCL;
 878
 879         /* variables for sanity checking interrupt and errors */
 880         infinipath_hwe_bitsextant =
 881                 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
 882                  INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
 883                 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK <<
 884                  INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) |
 885                 INFINIPATH_HWE_PCIE1PLLFAILED |
 886                 INFINIPATH_HWE_PCIE0PLLFAILED |
 887                 INFINIPATH_HWE_PCIEPOISONEDTLP |
 888                 INFINIPATH_HWE_PCIECPLTIMEOUT |
 889                 INFINIPATH_HWE_PCIEBUSPARITYXTLH |
 890                 INFINIPATH_HWE_PCIEBUSPARITYXADM |
 891                 INFINIPATH_HWE_PCIEBUSPARITYRADM |
 892                 INFINIPATH_HWE_MEMBISTFAILED |
 893                 INFINIPATH_HWE_COREPLL_FBSLIP |
 894                 INFINIPATH_HWE_COREPLL_RFSLIP |
 895                 INFINIPATH_HWE_SERDESPLLFAILED |
 896                 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
 897                 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
 898         infinipath_i_bitsextant =
 899                 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
 900                 (INFINIPATH_I_RCVAVAIL_MASK <<
 901                  INFINIPATH_I_RCVAVAIL_SHIFT) |
 902                 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
 903                 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
 904         infinipath_e_bitsextant =
 905                 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
 906                 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
 907                 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
 908                 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
 909                 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
 910                 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
 911                 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
 912                 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
 913                 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
 914                 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
 915                 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
 916                 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
 917                 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
 918                 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
 919                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
 920                 INFINIPATH_E_HARDWARE;
 921
 922         infinipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
 923         infinipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
 924 }
 925
 926 /* setup the MSI stuff again after a reset.  I'd like to just call
 927  * pci_enable_msi() and request_irq() again, but when I do that,
 928  * the MSI enable bit doesn't get set in the command word, and
 929  * we switch to to a different interrupt vector, which is confusing,
 930  * so I instead just do it all inline.  Perhaps somehow can tie this
 931  * into the PCIe hotplug support at some point
 932  * Note, because I'm doing it all here, I don't call pci_disable_msi()
 933  * or free_irq() at the start of ipath_setup_pe_reset().
 934  */
 935 static int ipath_reinit_msi(struct ipath_devdata *dd)
 936 {
 937         int pos;
 938         u16 control;
 939         int ret;
 940
 941         if (!dd->ipath_msi_lo) {
 942                 dev_info(&dd->pcidev->dev, "Can't restore MSI config, "
 943                          "initial setup failed?\n");
 944                 ret = 0;
 945                 goto bail;
 946         }
 947
 948         if (!(pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
 949                 ipath_dev_err(dd, "Can't find MSI capability, "
 950                               "can't restore MSI settings\n");
 951                 ret = 0;
 952                 goto bail;
 953         }
 954         ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
 955                    dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
 956         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
 957                                dd->ipath_msi_lo);
 958         ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
 959                    dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
 960         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
 961                                dd->ipath_msi_hi);
 962         pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
 963         if (!(control & PCI_MSI_FLAGS_ENABLE)) {
 964                 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, "
 965                            "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS,
 966                            control, control | PCI_MSI_FLAGS_ENABLE);
 967                 control |= PCI_MSI_FLAGS_ENABLE;
 968                 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
 969                                       control);
 970         }
 971         /* now rewrite the data (vector) info */
 972         pci_write_config_word(dd->pcidev, pos +
 973                               ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
 974                               dd->ipath_msi_data);
 975         /* we restore the cachelinesize also, although it doesn't really
 976          * matter */
 977         pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
 978                               dd->ipath_pci_cacheline);
 979         /* and now set the pci master bit again */
 980         pci_set_master(dd->pcidev);
 981         ret = 1;
 982
 983 bail:
 984         return ret;
 985 }
 986
 987 /* This routine sleeps, so it can only be called from user context, not
 988  * from interrupt context.  If we need interrupt context, we can split
 989  * it into two routines.
 990 */
 991 static int ipath_setup_pe_reset(struct ipath_devdata *dd)
 992 {
 993         u64 val;
 994         int i;
 995         int ret;
 996
 997         /* Use ERROR so it shows up in logs, etc. */
 998         ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
 999         /* keep chip from being accessed in a few places */
1000         dd->ipath_flags &= ~(IPATH_INITTED|IPATH_PRESENT);
1001         val = dd->ipath_control | INFINIPATH_C_RESET;
1002         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
1003         mb();
1004
1005         for (i = 1; i <= 5; i++) {
1006                 int r;
1007                 /* allow MBIST, etc. to complete; longer on each retry.
1008                  * We sometimes get machine checks from bus timeout if no
1009                  * response, so for now, make it *really* long.
1010                  */
1011                 msleep(1000 + (1 + i) * 2000);
1012                 if ((r =
1013                      pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
1014                                             dd->ipath_pcibar0)))
1015                         ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n",
1016                                       r);
1017                 if ((r =
1018                      pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
1019                                             dd->ipath_pcibar1)))
1020                         ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n",
1021                                       r);
1022                 /* now re-enable memory access */
1023                 if ((r = pci_enable_device(dd->pcidev)))
1024                         ipath_dev_err(dd, "pci_enable_device failed after "
1025                                       "reset: %d\n", r);
1026                 /* whether it worked or not, mark as present, again */
1027                 dd->ipath_flags |= IPATH_PRESENT;
1028                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1029                 if (val == dd->ipath_revision) {
1030                         ipath_cdbg(VERBOSE, "Got matching revision "
1031                                    "register %llx on try %d\n",
1032                                    (unsigned long long) val, i);
1033                         ret = ipath_reinit_msi(dd);
1034                         goto bail;
1035                 }
1036                 /* Probably getting -1 back */
1037                 ipath_dbg("Didn't get expected revision register, "
1038                           "got %llx, try %d\n", (unsigned long long) val,
1039                           i + 1);
1040         }
1041         ret = 0; /* failed */
1042
1043 bail:
1044         return ret;
1045 }
1046
1047 /**
1048  * ipath_pe_put_tid - write a TID in chip
1049  * @dd: the infinipath device
1050  * @tidptr: pointer to the expected TID (in chip) to udpate
1051  * @tidtype: 0 for eager, 1 for expected
1052  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1053  *
1054  * This exists as a separate routine to allow for special locking etc.
1055  * It's used for both the full cleanup on exit, as well as the normal
1056  * setup and teardown.
1057  */
1058 static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1059                              u32 type, unsigned long pa)
1060 {
1061         u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1062         unsigned long flags = 0; /* keep gcc quiet */
1063
1064         if (pa != dd->ipath_tidinvalid) {
1065                 if (pa & ((1U << 11) - 1)) {
1066                         dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1067                                  "not 4KB aligned!\n", pa);
1068                         return;
1069                 }
1070                 pa >>= 11;
1071                 /* paranoia check */
1072                 if (pa & (7<<29))
1073                         ipath_dev_err(dd,
1074                                       "BUG: Physical page address 0x%lx "
1075                                       "has bits set in 31-29\n", pa);
1076
1077                 if (type == 0)
1078                         pa |= dd->ipath_tidtemplate;
1079                 else /* for now, always full 4KB page */
1080                         pa |= 2 << 29;
1081         }
1082
1083         /* workaround chip bug 9437 by writing each TID twice
1084          * and holding a spinlock around the writes, so they don't
1085          * intermix with other TID (eager or expected) writes
1086          * Unfortunately, this call can be done from interrupt level
1087          * for the port 0 eager TIDs, so we have to use irqsave
1088          */
1089         spin_lock_irqsave(&dd->ipath_tid_lock, flags);
1090         ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf);
1091         if (dd->ipath_kregbase)
1092                 writel(pa, tidp32);
1093         ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef);
1094         mmiowb();
1095         spin_unlock_irqrestore(&dd->ipath_tid_lock, flags);
1096 }
1097 /**
1098  * ipath_pe_put_tid_2 - write a TID in chip, Revision 2 or higher
1099  * @dd: the infinipath device
1100  * @tidptr: pointer to the expected TID (in chip) to udpate
1101  * @tidtype: 0 for eager, 1 for expected
1102  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1103  *
1104  * This exists as a separate routine to allow for selection of the
1105  * appropriate "flavor". The static calls in cleanup just use the
1106  * revision-agnostic form, as they are not performance critical.
1107  */
1108 static void ipath_pe_put_tid_2(struct ipath_devdata *dd, u64 __iomem *tidptr,
1109                              u32 type, unsigned long pa)
1110 {
1111         u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1112
1113         if (pa != dd->ipath_tidinvalid) {
1114                 if (pa & ((1U << 11) - 1)) {
1115                         dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1116                                  "not 4KB aligned!\n", pa);
1117                         return;
1118                 }
1119                 pa >>= 11;
1120                 /* paranoia check */
1121                 if (pa & (7<<29))
1122                         ipath_dev_err(dd,
1123                                       "BUG: Physical page address 0x%lx "
1124                                       "has bits set in 31-29\n", pa);
1125
1126                 if (type == 0)
1127                         pa |= dd->ipath_tidtemplate;
1128                 else /* for now, always full 4KB page */
1129                         pa |= 2 << 29;
1130         }
1131         if (dd->ipath_kregbase)
1132                 writel(pa, tidp32);
1133         mmiowb();
1134 }
1135
1136
1137 /**
1138  * ipath_pe_clear_tid - clear all TID entries for a port, expected and eager
1139  * @dd: the infinipath device
1140  * @port: the port
1141  *
1142  * clear all TID entries for a port, expected and eager.
1143  * Used from ipath_close().  On this chip, TIDs are only 32 bits,
1144  * not 64, but they are still on 64 bit boundaries, so tidbase
1145  * is declared as u64 * for the pointer math, even though we write 32 bits
1146  */
1147 static void ipath_pe_clear_tids(struct ipath_devdata *dd, unsigned port)
1148 {
1149         u64 __iomem *tidbase;
1150         unsigned long tidinv;
1151         int i;
1152
1153         if (!dd->ipath_kregbase)
1154                 return;
1155
1156         ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1157
1158         tidinv = dd->ipath_tidinvalid;
1159         tidbase = (u64 __iomem *)
1160                 ((char __iomem *)(dd->ipath_kregbase) +
1161                  dd->ipath_rcvtidbase +
1162                  port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1163
1164         for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1165                 ipath_pe_put_tid(dd, &tidbase[i], 0, tidinv);
1166
1167         tidbase = (u64 __iomem *)
1168                 ((char __iomem *)(dd->ipath_kregbase) +
1169                  dd->ipath_rcvegrbase +
1170                  port * dd->ipath_rcvegrcnt * sizeof(*tidbase));
1171
1172         for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1173                 ipath_pe_put_tid(dd, &tidbase[i], 1, tidinv);
1174 }
1175
1176 /**
1177  * ipath_pe_tidtemplate - setup constants for TID updates
1178  * @dd: the infinipath device
1179  *
1180  * We setup stuff that we use a lot, to avoid calculating each time
1181  */
1182 static void ipath_pe_tidtemplate(struct ipath_devdata *dd)
1183 {
1184         u32 egrsize = dd->ipath_rcvegrbufsize;
1185
1186         /* For now, we always allocate 4KB buffers (at init) so we can
1187          * receive max size packets.  We may want a module parameter to
1188          * specify 2KB or 4KB and/or make be per port instead of per device
1189          * for those who want to reduce memory footprint.  Note that the
1190          * ipath_rcvhdrentsize size must be large enough to hold the largest
1191          * IB header (currently 96 bytes) that we expect to handle (plus of
1192          * course the 2 dwords of RHF).
1193          */
1194         if (egrsize == 2048)
1195                 dd->ipath_tidtemplate = 1U << 29;
1196         else if (egrsize == 4096)
1197                 dd->ipath_tidtemplate = 2U << 29;
1198         else {
1199                 egrsize = 4096;
1200                 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1201                          "%u, using %u\n", dd->ipath_rcvegrbufsize,
1202                          egrsize);
1203                 dd->ipath_tidtemplate = 2U << 29;
1204         }
1205         dd->ipath_tidinvalid = 0;
1206 }
1207
1208 static int ipath_pe_early_init(struct ipath_devdata *dd)
1209 {
1210         dd->ipath_flags |= IPATH_4BYTE_TID;
1211
1212         /*
1213          * For openfabrics, we need to be able to handle an IB header of
1214          * 24 dwords.  HT chip has arbitrary sized receive buffers, so we
1215          * made them the same size as the PIO buffers.  This chip does not
1216          * handle arbitrary size buffers, so we need the header large enough
1217          * to handle largest IB header, but still have room for a 2KB MTU
1218          * standard IB packet.
1219          */
1220         dd->ipath_rcvhdrentsize = 24;
1221         dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1222
1223         /*
1224          * To truly support a 4KB MTU (for usermode), we need to
1225          * bump this to a larger value.  For now, we use them for
1226          * the kernel only.
1227          */
1228         dd->ipath_rcvegrbufsize = 2048;
1229         /*
1230          * the min() check here is currently a nop, but it may not always
1231          * be, depending on just how we do ipath_rcvegrbufsize
1232          */
1233         dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1234                                  dd->ipath_rcvegrbufsize +
1235                                  (dd->ipath_rcvhdrentsize << 2));
1236         dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1237
1238         /*
1239          * We can request a receive interrupt for 1 or
1240          * more packets from current offset.  For now, we set this
1241          * up for a single packet.
1242          */
1243         dd->ipath_rhdrhead_intr_off = 1ULL<<32;
1244
1245         ipath_get_eeprom_info(dd);
1246
1247         return 0;
1248 }
1249
1250 int __attribute__((weak)) ipath_unordered_wc(void)
1251 {
1252         return 0;
1253 }
1254
1255 /**
1256  * ipath_init_pe_get_base_info - set chip-specific flags for user code
1257  * @pd: the infinipath port
1258  * @kbase: ipath_base_info pointer
1259  *
1260  * We set the PCIE flag because the lower bandwidth on PCIe vs
1261  * HyperTransport can affect some user packet algorithims.
1262  */
1263 static int ipath_pe_get_base_info(struct ipath_portdata *pd, void *kbase)
1264 {
1265         struct ipath_base_info *kinfo = kbase;
1266         struct ipath_devdata *dd;
1267
1268         if (ipath_unordered_wc()) {
1269                 kinfo->spi_runtime_flags |= IPATH_RUNTIME_FORCE_WC_ORDER;
1270                 ipath_cdbg(PROC, "Intel processor, forcing WC order\n");
1271         }
1272         else
1273                 ipath_cdbg(PROC, "Not Intel processor, WC ordered\n");
1274
1275         if (pd == NULL)
1276                 goto done;
1277
1278         dd = pd->port_dd;
1279
1280         if (dd != NULL && dd->ipath_minrev >= 2) {
1281                 ipath_cdbg(PROC, "IBA6120 Rev2, allow multiple PBC write\n");
1282                 kinfo->spi_runtime_flags |= IPATH_RUNTIME_PBC_REWRITE;
1283                 ipath_cdbg(PROC, "IBA6120 Rev2, allow loose DMA alignment\n");
1284                 kinfo->spi_runtime_flags |= IPATH_RUNTIME_LOOSE_DMA_ALIGN;
1285         }
1286
1287 done:
1288         kinfo->spi_runtime_flags |= IPATH_RUNTIME_PCIE;
1289         return 0;
1290 }
1291
1292 /**
1293  * ipath_init_iba6120_funcs - set up the chip-specific function pointers
1294  * @dd: the infinipath device
1295  *
1296  * This is global, and is called directly at init to set up the
1297  * chip-specific function pointers for later use.
1298  */
1299 void ipath_init_iba6120_funcs(struct ipath_devdata *dd)
1300 {
1301         dd->ipath_f_intrsetup = ipath_pe_intconfig;
1302         dd->ipath_f_bus = ipath_setup_pe_config;
1303         dd->ipath_f_reset = ipath_setup_pe_reset;
1304         dd->ipath_f_get_boardname = ipath_pe_boardname;
1305         dd->ipath_f_init_hwerrors = ipath_pe_init_hwerrors;
1306         dd->ipath_f_early_init = ipath_pe_early_init;
1307         dd->ipath_f_handle_hwerrors = ipath_pe_handle_hwerrors;
1308         dd->ipath_f_quiet_serdes = ipath_pe_quiet_serdes;
1309         dd->ipath_f_bringup_serdes = ipath_pe_bringup_serdes;
1310         dd->ipath_f_clear_tids = ipath_pe_clear_tids;
1311         if (dd->ipath_minrev >= 2)
1312                 dd->ipath_f_put_tid = ipath_pe_put_tid_2;
1313         else
1314                 dd->ipath_f_put_tid = ipath_pe_put_tid;
1315         dd->ipath_f_cleanup = ipath_setup_pe_cleanup;
1316         dd->ipath_f_setextled = ipath_setup_pe_setextled;
1317         dd->ipath_f_get_base_info = ipath_pe_get_base_info;
1318
1319         /* initialize chip-specific variables */
1320         dd->ipath_f_tidtemplate = ipath_pe_tidtemplate;
1321
1322         /*
1323          * setup the register offsets, since they are different for each
1324          * chip
1325          */
1326         dd->ipath_kregs = &ipath_pe_kregs;
1327         dd->ipath_cregs = &ipath_pe_cregs;
1328
1329         ipath_init_pe_variables();
1330 }
1331