drivers/usb/host/ehci.h

   1 /*
   2  * Copyright (c) 2001-2002 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2 of the License, or (at your
   7  * option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software Foundation,
  16  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #ifndef __LINUX_EHCI_HCD_H
  20 #define __LINUX_EHCI_HCD_H
  21
  22 /* definitions used for the EHCI driver */
  23
  24 /*
  25  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  26  * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
  27  * the host controller implementation.
  28  *
  29  * To facilitate the strongest possible byte-order checking from "sparse"
  30  * and so on, we use __leXX unless that's not practical.
  31  */
  32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
  33 typedef __u32 __bitwise __hc32;
  34 typedef __u16 __bitwise __hc16;
  35 #else
  36 #define __hc32  __le32
  37 #define __hc16  __le16
  38 #endif
  39
  40 /* statistics can be kept for for tuning/monitoring */
  41 struct ehci_stats {
  42         /* irq usage */
  43         unsigned long           normal;
  44         unsigned long           error;
  45         unsigned long           reclaim;
  46         unsigned long           lost_iaa;
  47
  48         /* termination of urbs from core */
  49         unsigned long           complete;
  50         unsigned long           unlink;
  51 };
  52
  53 /* ehci_hcd->lock guards shared data against other CPUs:
  54  *   ehci_hcd:  async, reclaim, periodic (and shadow), ...
  55  *   usb_host_endpoint: hcpriv
  56  *   ehci_qh:   qh_next, qtd_list
  57  *   ehci_qtd:  qtd_list
  58  *
  59  * Also, hold this lock when talking to HC registers or
  60  * when updating hw_* fields in shared qh/qtd/... structures.
  61  */
  62
  63 #define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
  64
  65 struct ehci_hcd {                       /* one per controller */
  66         /* glue to PCI and HCD framework */
  67         struct ehci_caps __iomem *caps;
  68         struct ehci_regs __iomem *regs;
  69         struct ehci_dbg_port __iomem *debug;
  70
  71         __u32                   hcs_params;     /* cached register copy */
  72         spinlock_t              lock;
  73
  74         /* async schedule support */
  75         struct ehci_qh          *async;
  76         struct ehci_qh          *reclaim;
  77         unsigned                scanning : 1;
  78
  79         /* periodic schedule support */
  80 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
  81         unsigned                periodic_size;
  82         __hc32                  *periodic;      /* hw periodic table */
  83         dma_addr_t              periodic_dma;
  84         unsigned                i_thresh;       /* uframes HC might cache */
  85
  86         union ehci_shadow       *pshadow;       /* mirror hw periodic table */
  87         int                     next_uframe;    /* scan periodic, start here */
  88         unsigned                periodic_sched; /* periodic activity count */
  89
  90         /* list of itds completed while clock_frame was still active */
  91         struct list_head        cached_itd_list;
  92         unsigned                clock_frame;
  93
  94         /* per root hub port */
  95         unsigned long           reset_done [EHCI_MAX_ROOT_PORTS];
  96
  97         /* bit vectors (one bit per port) */
  98         unsigned long           bus_suspended;          /* which ports were
  99                         already suspended at the start of a bus suspend */
 100         unsigned long           companion_ports;        /* which ports are
 101                         dedicated to the companion controller */
 102         unsigned long           owned_ports;            /* which ports are
 103                         owned by the companion during a bus suspend */
 104         unsigned long           port_c_suspend;         /* which ports have
 105                         the change-suspend feature turned on */
 106         unsigned long           suspended_ports;        /* which ports are
 107                         suspended */
 108
 109         /* per-HC memory pools (could be per-bus, but ...) */
 110         struct dma_pool         *qh_pool;       /* qh per active urb */
 111         struct dma_pool         *qtd_pool;      /* one or more per qh */
 112         struct dma_pool         *itd_pool;      /* itd per iso urb */
 113         struct dma_pool         *sitd_pool;     /* sitd per split iso urb */
 114
 115         struct timer_list       iaa_watchdog;
 116         struct timer_list       watchdog;
 117         unsigned long           actions;
 118         unsigned                stamp;
 119         unsigned long           next_statechange;
 120         u32                     command;
 121
 122         /* SILICON QUIRKS */
 123         unsigned                no_selective_suspend:1;
 124         unsigned                has_fsl_port_bug:1; /* FreeScale */
 125         unsigned                big_endian_mmio:1;
 126         unsigned                big_endian_desc:1;
 127         unsigned                has_amcc_usb23:1;
 128
 129         /* required for usb32 quirk */
 130         #define OHCI_CTRL_HCFS          (3 << 6)
 131         #define OHCI_USB_OPER           (2 << 6)
 132         #define OHCI_USB_SUSPEND        (3 << 6)
 133
 134         #define OHCI_HCCTRL_OFFSET      0x4
 135         #define OHCI_HCCTRL_LEN         0x4
 136         __hc32                  *ohci_hcctrl_reg;
 137
 138         u8                      sbrn;           /* packed release number */
 139
 140         /* irq statistics */
 141 #ifdef EHCI_STATS
 142         struct ehci_stats       stats;
 143 #       define COUNT(x) do { (x)++; } while (0)
 144 #else
 145 #       define COUNT(x) do {} while (0)
 146 #endif
 147
 148         /* debug files */
 149 #ifdef DEBUG
 150         struct dentry           *debug_dir;
 151         struct dentry           *debug_async;
 152         struct dentry           *debug_periodic;
 153         struct dentry           *debug_registers;
 154 #endif
 155 };
 156
 157 /* convert between an HCD pointer and the corresponding EHCI_HCD */
 158 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
 159 {
 160         return (struct ehci_hcd *) (hcd->hcd_priv);
 161 }
 162 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
 163 {
 164         return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
 165 }
 166
 167
 168 static inline void
 169 iaa_watchdog_start(struct ehci_hcd *ehci)
 170 {
 171         WARN_ON(timer_pending(&ehci->iaa_watchdog));
 172         mod_timer(&ehci->iaa_watchdog,
 173                         jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
 174 }
 175
 176 static inline void iaa_watchdog_done(struct ehci_hcd *ehci)
 177 {
 178         del_timer(&ehci->iaa_watchdog);
 179 }
 180
 181 enum ehci_timer_action {
 182         TIMER_IO_WATCHDOG,
 183         TIMER_ASYNC_SHRINK,
 184         TIMER_ASYNC_OFF,
 185 };
 186
 187 static inline void
 188 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
 189 {
 190         clear_bit (action, &ehci->actions);
 191 }
 192
 193 static void free_cached_itd_list(struct ehci_hcd *ehci);
 194
 195 /*-------------------------------------------------------------------------*/
 196
 197 #include <linux/usb/ehci_def.h>
 198
 199 /*-------------------------------------------------------------------------*/
 200
 201 #define QTD_NEXT(ehci, dma)     cpu_to_hc32(ehci, (u32)dma)
 202
 203 /*
 204  * EHCI Specification 0.95 Section 3.5
 205  * QTD: describe data transfer components (buffer, direction, ...)
 206  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 207  *
 208  * These are associated only with "QH" (Queue Head) structures,
 209  * used with control, bulk, and interrupt transfers.
 210  */
 211 struct ehci_qtd {
 212         /* first part defined by EHCI spec */
 213         __hc32                  hw_next;        /* see EHCI 3.5.1 */
 214         __hc32                  hw_alt_next;    /* see EHCI 3.5.2 */
 215         __hc32                  hw_token;       /* see EHCI 3.5.3 */
 216 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 217 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 218 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 219 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 220 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 221 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 222 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 223 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 224 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 225 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 226 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 227 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 228 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 229
 230 #define ACTIVE_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_ACTIVE)
 231 #define HALT_BIT(ehci)          cpu_to_hc32(ehci, QTD_STS_HALT)
 232 #define STATUS_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_STS)
 233
 234         __hc32                  hw_buf [5];        /* see EHCI 3.5.4 */
 235         __hc32                  hw_buf_hi [5];        /* Appendix B */
 236
 237         /* the rest is HCD-private */
 238         dma_addr_t              qtd_dma;                /* qtd address */
 239         struct list_head        qtd_list;               /* sw qtd list */
 240         struct urb              *urb;                   /* qtd's urb */
 241         size_t                  length;                 /* length of buffer */
 242 } __attribute__ ((aligned (32)));
 243
 244 /* mask NakCnt+T in qh->hw_alt_next */
 245 #define QTD_MASK(ehci)  cpu_to_hc32 (ehci, ~0x1f)
 246
 247 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
 248
 249 /*-------------------------------------------------------------------------*/
 250
 251 /* type tag from {qh,itd,sitd,fstn}->hw_next */
 252 #define Q_NEXT_TYPE(ehci,dma)   ((dma) & cpu_to_hc32(ehci, 3 << 1))
 253
 254 /*
 255  * Now the following defines are not converted using the
 256  * cpu_to_le32() macro anymore, since we have to support
 257  * "dynamic" switching between be and le support, so that the driver
 258  * can be used on one system with SoC EHCI controller using big-endian
 259  * descriptors as well as a normal little-endian PCI EHCI controller.
 260  */
 261 /* values for that type tag */
 262 #define Q_TYPE_ITD      (0 << 1)
 263 #define Q_TYPE_QH       (1 << 1)
 264 #define Q_TYPE_SITD     (2 << 1)
 265 #define Q_TYPE_FSTN     (3 << 1)
 266
 267 /* next async queue entry, or pointer to interrupt/periodic QH */
 268 #define QH_NEXT(ehci,dma)       (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
 269
 270 /* for periodic/async schedules and qtd lists, mark end of list */
 271 #define EHCI_LIST_END(ehci)     cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
 272
 273 /*
 274  * Entries in periodic shadow table are pointers to one of four kinds
 275  * of data structure.  That's dictated by the hardware; a type tag is
 276  * encoded in the low bits of the hardware's periodic schedule.  Use
 277  * Q_NEXT_TYPE to get the tag.
 278  *
 279  * For entries in the async schedule, the type tag always says "qh".
 280  */
 281 union ehci_shadow {
 282         struct ehci_qh          *qh;            /* Q_TYPE_QH */
 283         struct ehci_itd         *itd;           /* Q_TYPE_ITD */
 284         struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
 285         struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
 286         __hc32                  *hw_next;       /* (all types) */
 287         void                    *ptr;
 288 };
 289
 290 /*-------------------------------------------------------------------------*/
 291
 292 /*
 293  * EHCI Specification 0.95 Section 3.6
 294  * QH: describes control/bulk/interrupt endpoints
 295  * See Fig 3-7 "Queue Head Structure Layout".
 296  *
 297  * These appear in both the async and (for interrupt) periodic schedules.
 298  */
 299
 300 struct ehci_qh {
 301         /* first part defined by EHCI spec */
 302         __hc32                  hw_next;        /* see EHCI 3.6.1 */
 303         __hc32                  hw_info1;       /* see EHCI 3.6.2 */
 304 #define QH_HEAD         0x00008000
 305         __hc32                  hw_info2;        /* see EHCI 3.6.2 */
 306 #define QH_SMASK        0x000000ff
 307 #define QH_CMASK        0x0000ff00
 308 #define QH_HUBADDR      0x007f0000
 309 #define QH_HUBPORT      0x3f800000
 310 #define QH_MULT         0xc0000000
 311         __hc32                  hw_current;     /* qtd list - see EHCI 3.6.4 */
 312
 313         /* qtd overlay (hardware parts of a struct ehci_qtd) */
 314         __hc32                  hw_qtd_next;
 315         __hc32                  hw_alt_next;
 316         __hc32                  hw_token;
 317         __hc32                  hw_buf [5];
 318         __hc32                  hw_buf_hi [5];
 319
 320         /* the rest is HCD-private */
 321         dma_addr_t              qh_dma;         /* address of qh */
 322         union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
 323         struct list_head        qtd_list;       /* sw qtd list */
 324         struct ehci_qtd         *dummy;
 325         struct ehci_qh          *reclaim;       /* next to reclaim */
 326
 327         struct ehci_hcd         *ehci;
 328
 329         /*
 330          * Do NOT use atomic operations for QH refcounting. On some CPUs
 331          * (PPC7448 for example), atomic operations cannot be performed on
 332          * memory that is cache-inhibited (i.e. being used for DMA).
 333          * Spinlocks are used to protect all QH fields.
 334          */
 335         u32                     refcount;
 336         unsigned                stamp;
 337
 338         u8                      qh_state;
 339 #define QH_STATE_LINKED         1               /* HC sees this */
 340 #define QH_STATE_UNLINK         2               /* HC may still see this */
 341 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 342 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on reclaim q */
 343 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 344
 345         u8                      xacterrs;       /* XactErr retry counter */
 346 #define QH_XACTERR_MAX          32              /* XactErr retry limit */
 347
 348         /* periodic schedule info */
 349         u8                      usecs;          /* intr bandwidth */
 350         u8                      gap_uf;         /* uframes split/csplit gap */
 351         u8                      c_usecs;        /* ... split completion bw */
 352         u16                     tt_usecs;       /* tt downstream bandwidth */
 353         unsigned short          period;         /* polling interval */
 354         unsigned short          start;          /* where polling starts */
 355 #define NO_FRAME ((unsigned short)~0)                   /* pick new start */
 356         struct usb_device       *dev;           /* access to TT */
 357 } __attribute__ ((aligned (32)));
 358
 359 /*-------------------------------------------------------------------------*/
 360
 361 /* description of one iso transaction (up to 3 KB data if highspeed) */
 362 struct ehci_iso_packet {
 363         /* These will be copied to iTD when scheduling */
 364         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 365         __hc32                  transaction;    /* itd->hw_transaction[i] |= */
 366         u8                      cross;          /* buf crosses pages */
 367         /* for full speed OUT splits */
 368         u32                     buf1;
 369 };
 370
 371 /* temporary schedule data for packets from iso urbs (both speeds)
 372  * each packet is one logical usb transaction to the device (not TT),
 373  * beginning at stream->next_uframe
 374  */
 375 struct ehci_iso_sched {
 376         struct list_head        td_list;
 377         unsigned                span;
 378         struct ehci_iso_packet  packet [0];
 379 };
 380
 381 /*
 382  * ehci_iso_stream - groups all (s)itds for this endpoint.
 383  * acts like a qh would, if EHCI had them for ISO.
 384  */
 385 struct ehci_iso_stream {
 386         /* first two fields match QH, but info1 == 0 */
 387         __hc32                  hw_next;
 388         __hc32                  hw_info1;
 389
 390         u32                     refcount;
 391         u8                      bEndpointAddress;
 392         u8                      highspeed;
 393         u16                     depth;          /* depth in uframes */
 394         struct list_head        td_list;        /* queued itds/sitds */
 395         struct list_head        free_list;      /* list of unused itds/sitds */
 396         struct usb_device       *udev;
 397         struct usb_host_endpoint *ep;
 398
 399         /* output of (re)scheduling */
 400         unsigned long           start;          /* jiffies */
 401         unsigned long           rescheduled;
 402         int                     next_uframe;
 403         __hc32                  splits;
 404
 405         /* the rest is derived from the endpoint descriptor,
 406          * trusting urb->interval == f(epdesc->bInterval) and
 407          * including the extra info for hw_bufp[0..2]
 408          */
 409         u8                      usecs, c_usecs;
 410         u16                     interval;
 411         u16                     tt_usecs;
 412         u16                     maxp;
 413         u16                     raw_mask;
 414         unsigned                bandwidth;
 415
 416         /* This is used to initialize iTD's hw_bufp fields */
 417         __hc32                  buf0;
 418         __hc32                  buf1;
 419         __hc32                  buf2;
 420
 421         /* this is used to initialize sITD's tt info */
 422         __hc32                  address;
 423 };
 424
 425 /*-------------------------------------------------------------------------*/
 426
 427 /*
 428  * EHCI Specification 0.95 Section 3.3
 429  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 430  *
 431  * Schedule records for high speed iso xfers
 432  */
 433 struct ehci_itd {
 434         /* first part defined by EHCI spec */
 435         __hc32                  hw_next;           /* see EHCI 3.3.1 */
 436         __hc32                  hw_transaction [8]; /* see EHCI 3.3.2 */
 437 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
 438 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
 439 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
 440 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
 441 #define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
 442 #define EHCI_ITD_IOC            (1 << 15)       /* interrupt on complete */
 443
 444 #define ITD_ACTIVE(ehci)        cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
 445
 446         __hc32                  hw_bufp [7];    /* see EHCI 3.3.3 */
 447         __hc32                  hw_bufp_hi [7]; /* Appendix B */
 448
 449         /* the rest is HCD-private */
 450         dma_addr_t              itd_dma;        /* for this itd */
 451         union ehci_shadow       itd_next;       /* ptr to periodic q entry */
 452
 453         struct urb              *urb;
 454         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 455         struct list_head        itd_list;       /* list of stream's itds */
 456
 457         /* any/all hw_transactions here may be used by that urb */
 458         unsigned                frame;          /* where scheduled */
 459         unsigned                pg;
 460         unsigned                index[8];       /* in urb->iso_frame_desc */
 461 } __attribute__ ((aligned (32)));
 462
 463 /*-------------------------------------------------------------------------*/
 464
 465 /*
 466  * EHCI Specification 0.95 Section 3.4
 467  * siTD, aka split-transaction isochronous Transfer Descriptor
 468  *       ... describe full speed iso xfers through TT in hubs
 469  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
 470  */
 471 struct ehci_sitd {
 472         /* first part defined by EHCI spec */
 473         __hc32                  hw_next;
 474 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
 475         __hc32                  hw_fullspeed_ep;        /* EHCI table 3-9 */
 476         __hc32                  hw_uframe;              /* EHCI table 3-10 */
 477         __hc32                  hw_results;             /* EHCI table 3-11 */
 478 #define SITD_IOC        (1 << 31)       /* interrupt on completion */
 479 #define SITD_PAGE       (1 << 30)       /* buffer 0/1 */
 480 #define SITD_LENGTH(x)  (0x3ff & ((x)>>16))
 481 #define SITD_STS_ACTIVE (1 << 7)        /* HC may execute this */
 482 #define SITD_STS_ERR    (1 << 6)        /* error from TT */
 483 #define SITD_STS_DBE    (1 << 5)        /* data buffer error (in HC) */
 484 #define SITD_STS_BABBLE (1 << 4)        /* device was babbling */
 485 #define SITD_STS_XACT   (1 << 3)        /* illegal IN response */
 486 #define SITD_STS_MMF    (1 << 2)        /* incomplete split transaction */
 487 #define SITD_STS_STS    (1 << 1)        /* split transaction state */
 488
 489 #define SITD_ACTIVE(ehci)       cpu_to_hc32(ehci, SITD_STS_ACTIVE)
 490
 491         __hc32                  hw_buf [2];             /* EHCI table 3-12 */
 492         __hc32                  hw_backpointer;         /* EHCI table 3-13 */
 493         __hc32                  hw_buf_hi [2];          /* Appendix B */
 494
 495         /* the rest is HCD-private */
 496         dma_addr_t              sitd_dma;
 497         union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
 498
 499         struct urb              *urb;
 500         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 501         struct list_head        sitd_list;      /* list of stream's sitds */
 502         unsigned                frame;
 503         unsigned                index;
 504 } __attribute__ ((aligned (32)));
 505
 506 /*-------------------------------------------------------------------------*/
 507
 508 /*
 509  * EHCI Specification 0.96 Section 3.7
 510  * Periodic Frame Span Traversal Node (FSTN)
 511  *
 512  * Manages split interrupt transactions (using TT) that span frame boundaries
 513  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 514  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 515  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 516  */
 517 struct ehci_fstn {
 518         __hc32                  hw_next;        /* any periodic q entry */
 519         __hc32                  hw_prev;        /* qh or EHCI_LIST_END */
 520
 521         /* the rest is HCD-private */
 522         dma_addr_t              fstn_dma;
 523         union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
 524 } __attribute__ ((aligned (32)));
 525
 526 /*-------------------------------------------------------------------------*/
 527
 528 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
 529
 530 /*
 531  * Some EHCI controllers have a Transaction Translator built into the
 532  * root hub. This is a non-standard feature.  Each controller will need
 533  * to add code to the following inline functions, and call them as
 534  * needed (mostly in root hub code).
 535  */
 536
 537 #define ehci_is_TDI(e)                  (ehci_to_hcd(e)->has_tt)
 538
 539 /* Returns the speed of a device attached to a port on the root hub. */
 540 static inline unsigned int
 541 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
 542 {
 543         if (ehci_is_TDI(ehci)) {
 544                 switch ((portsc>>26)&3) {
 545                 case 0:
 546                         return 0;
 547                 case 1:
 548                         return (1<<USB_PORT_FEAT_LOWSPEED);
 549                 case 2:
 550                 default:
 551                         return (1<<USB_PORT_FEAT_HIGHSPEED);
 552                 }
 553         }
 554         return (1<<USB_PORT_FEAT_HIGHSPEED);
 555 }
 556
 557 #else
 558
 559 #define ehci_is_TDI(e)                  (0)
 560
 561 #define ehci_port_speed(ehci, portsc)   (1<<USB_PORT_FEAT_HIGHSPEED)
 562 #endif
 563
 564 /*-------------------------------------------------------------------------*/
 565
 566 #ifdef CONFIG_PPC_83xx
 567 /* Some Freescale processors have an erratum in which the TT
 568  * port number in the queue head was 0..N-1 instead of 1..N.
 569  */
 570 #define ehci_has_fsl_portno_bug(e)              ((e)->has_fsl_port_bug)
 571 #else
 572 #define ehci_has_fsl_portno_bug(e)              (0)
 573 #endif
 574
 575 /*
 576  * While most USB host controllers implement their registers in
 577  * little-endian format, a minority (celleb companion chip) implement
 578  * them in big endian format.
 579  *
 580  * This attempts to support either format at compile time without a
 581  * runtime penalty, or both formats with the additional overhead
 582  * of checking a flag bit.
 583  */
 584
 585 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 586 #define ehci_big_endian_mmio(e)         ((e)->big_endian_mmio)
 587 #else
 588 #define ehci_big_endian_mmio(e)         0
 589 #endif
 590
 591 /*
 592  * Big-endian read/write functions are arch-specific.
 593  * Other arches can be added if/when they're needed.
 594  */
 595 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
 596 #define readl_be(addr)          __raw_readl((__force unsigned *)addr)
 597 #define writel_be(val, addr)    __raw_writel(val, (__force unsigned *)addr)
 598 #endif
 599
 600 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
 601                 __u32 __iomem * regs)
 602 {
 603 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 604         return ehci_big_endian_mmio(ehci) ?
 605                 readl_be(regs) :
 606                 readl(regs);
 607 #else
 608         return readl(regs);
 609 #endif
 610 }
 611
 612 static inline void ehci_writel(const struct ehci_hcd *ehci,
 613                 const unsigned int val, __u32 __iomem *regs)
 614 {
 615 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 616         ehci_big_endian_mmio(ehci) ?
 617                 writel_be(val, regs) :
 618                 writel(val, regs);
 619 #else
 620         writel(val, regs);
 621 #endif
 622 }
 623
 624 /*
 625  * On certain ppc-44x SoC there is a HW issue, that could only worked around with
 626  * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
 627  * Other common bits are dependant on has_amcc_usb23 quirk flag.
 628  */
 629 #ifdef CONFIG_44x
 630 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
 631 {
 632         u32 hc_control;
 633
 634         hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
 635         if (operational)
 636                 hc_control |= OHCI_USB_OPER;
 637         else
 638                 hc_control |= OHCI_USB_SUSPEND;
 639
 640         writel_be(hc_control, ehci->ohci_hcctrl_reg);
 641         (void) readl_be(ehci->ohci_hcctrl_reg);
 642 }
 643 #else
 644 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
 645 { }
 646 #endif
 647
 648 /*-------------------------------------------------------------------------*/
 649
 650 /*
 651  * The AMCC 440EPx not only implements its EHCI registers in big-endian
 652  * format, but also its DMA data structures (descriptors).
 653  *
 654  * EHCI controllers accessed through PCI work normally (little-endian
 655  * everywhere), so we won't bother supporting a BE-only mode for now.
 656  */
 657 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
 658 #define ehci_big_endian_desc(e)         ((e)->big_endian_desc)
 659
 660 /* cpu to ehci */
 661 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 662 {
 663         return ehci_big_endian_desc(ehci)
 664                 ? (__force __hc32)cpu_to_be32(x)
 665                 : (__force __hc32)cpu_to_le32(x);
 666 }
 667
 668 /* ehci to cpu */
 669 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 670 {
 671         return ehci_big_endian_desc(ehci)
 672                 ? be32_to_cpu((__force __be32)x)
 673                 : le32_to_cpu((__force __le32)x);
 674 }
 675
 676 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 677 {
 678         return ehci_big_endian_desc(ehci)
 679                 ? be32_to_cpup((__force __be32 *)x)
 680                 : le32_to_cpup((__force __le32 *)x);
 681 }
 682
 683 #else
 684
 685 /* cpu to ehci */
 686 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 687 {
 688         return cpu_to_le32(x);
 689 }
 690
 691 /* ehci to cpu */
 692 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 693 {
 694         return le32_to_cpu(x);
 695 }
 696
 697 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 698 {
 699         return le32_to_cpup(x);
 700 }
 701
 702 #endif
 703
 704 /*-------------------------------------------------------------------------*/
 705
 706 #ifndef DEBUG
 707 #define STUB_DEBUG_FILES
 708 #endif  /* DEBUG */
 709
 710 /*-------------------------------------------------------------------------*/
 711
 712 #endif /* __LINUX_EHCI_HCD_H */