x86, VisWS: turn into generic arch, add NR_IRQS quirk
[linux-2.6/x86.git] / include / asm-x86 / irq_vectors.h
blob0ac864ef3cd4f112dd03c9e2b6b9600dbb094277
1 #ifndef _ASM_IRQ_VECTORS_H
2 #define _ASM_IRQ_VECTORS_H
4 #include <linux/threads.h>
6 #define NMI_VECTOR 0x02
8 /*
9 * IDT vectors usable for external interrupt sources start
10 * at 0x20:
12 #define FIRST_EXTERNAL_VECTOR 0x20
14 #ifdef CONFIG_X86_32
15 # define SYSCALL_VECTOR 0x80
16 #else
17 # define IA32_SYSCALL_VECTOR 0x80
18 #endif
21 * Reserve the lowest usable priority level 0x20 - 0x2f for triggering
22 * cleanup after irq migration on 64 bit.
24 #define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR
27 * Vectors 0x20-0x2f are used for ISA interrupts on 32 bit.
28 * Vectors 0x30-0x3f are used for ISA interrupts on 64 bit.
30 #ifdef CONFIG_X86_32
31 #define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR)
32 #else
33 #define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR + 0x10)
34 #endif
35 #define IRQ1_VECTOR (IRQ0_VECTOR + 1)
36 #define IRQ2_VECTOR (IRQ0_VECTOR + 2)
37 #define IRQ3_VECTOR (IRQ0_VECTOR + 3)
38 #define IRQ4_VECTOR (IRQ0_VECTOR + 4)
39 #define IRQ5_VECTOR (IRQ0_VECTOR + 5)
40 #define IRQ6_VECTOR (IRQ0_VECTOR + 6)
41 #define IRQ7_VECTOR (IRQ0_VECTOR + 7)
42 #define IRQ8_VECTOR (IRQ0_VECTOR + 8)
43 #define IRQ9_VECTOR (IRQ0_VECTOR + 9)
44 #define IRQ10_VECTOR (IRQ0_VECTOR + 10)
45 #define IRQ11_VECTOR (IRQ0_VECTOR + 11)
46 #define IRQ12_VECTOR (IRQ0_VECTOR + 12)
47 #define IRQ13_VECTOR (IRQ0_VECTOR + 13)
48 #define IRQ14_VECTOR (IRQ0_VECTOR + 14)
49 #define IRQ15_VECTOR (IRQ0_VECTOR + 15)
52 * Special IRQ vectors used by the SMP architecture, 0xf0-0xff
54 * some of the following vectors are 'rare', they are merged
55 * into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
56 * TLB, reschedule and local APIC vectors are performance-critical.
58 * Vectors 0xf0-0xfa are free (reserved for future Linux use).
60 #ifdef CONFIG_X86_32
62 # define SPURIOUS_APIC_VECTOR 0xff
63 # define ERROR_APIC_VECTOR 0xfe
64 # define INVALIDATE_TLB_VECTOR 0xfd
65 # define RESCHEDULE_VECTOR 0xfc
66 # define CALL_FUNCTION_VECTOR 0xfb
67 # define THERMAL_APIC_VECTOR 0xf0
69 #else
71 #define SPURIOUS_APIC_VECTOR 0xff
72 #define ERROR_APIC_VECTOR 0xfe
73 #define RESCHEDULE_VECTOR 0xfd
74 #define CALL_FUNCTION_VECTOR 0xfc
75 #define THERMAL_APIC_VECTOR 0xfa
76 #define THRESHOLD_APIC_VECTOR 0xf9
77 #define INVALIDATE_TLB_VECTOR_END 0xf7
78 #define INVALIDATE_TLB_VECTOR_START 0xf0 /* f0-f7 used for TLB flush */
80 #define NUM_INVALIDATE_TLB_VECTORS 8
82 #endif
85 * Local APIC timer IRQ vector is on a different priority level,
86 * to work around the 'lost local interrupt if more than 2 IRQ
87 * sources per level' errata.
89 #define LOCAL_TIMER_VECTOR 0xef
92 * First APIC vector available to drivers: (vectors 0x30-0xee) we
93 * start at 0x31(0x41) to spread out vectors evenly between priority
94 * levels. (0x80 is the syscall vector)
96 #ifdef CONFIG_X86_32
97 # define FIRST_DEVICE_VECTOR 0x31
98 #else
99 # define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 2)
100 #endif
102 #define NR_VECTORS 256
104 #define FPU_IRQ 13
106 #define FIRST_VM86_IRQ 3
107 #define LAST_VM86_IRQ 15
108 #define invalid_vm86_irq(irq) ((irq) < 3 || (irq) > 15)
110 #if !defined(CONFIG_X86_VOYAGER)
112 # if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_PARAVIRT) || defined(CONFIG_X86_VISWS)
114 # define NR_IRQS 224
116 # if (224 >= 32 * NR_CPUS)
117 # define NR_IRQ_VECTORS NR_IRQS
118 # else
119 # define NR_IRQ_VECTORS (32 * NR_CPUS)
120 # endif
122 # else /* IO_APIC || PARAVIRT */
124 # define NR_IRQS 16
125 # define NR_IRQ_VECTORS NR_IRQS
127 # endif
129 #else /* !VISWS && !VOYAGER */
131 # define NR_IRQS 224
132 # define NR_IRQ_VECTORS NR_IRQS
134 #endif /* VISWS */
136 /* Voyager specific defines */
137 /* These define the CPIs we use in linux */
138 #define VIC_CPI_LEVEL0 0
139 #define VIC_CPI_LEVEL1 1
140 /* now the fake CPIs */
141 #define VIC_TIMER_CPI 2
142 #define VIC_INVALIDATE_CPI 3
143 #define VIC_RESCHEDULE_CPI 4
144 #define VIC_ENABLE_IRQ_CPI 5
145 #define VIC_CALL_FUNCTION_CPI 6
147 /* Now the QIC CPIs: Since we don't need the two initial levels,
148 * these are 2 less than the VIC CPIs */
149 #define QIC_CPI_OFFSET 1
150 #define QIC_TIMER_CPI (VIC_TIMER_CPI - QIC_CPI_OFFSET)
151 #define QIC_INVALIDATE_CPI (VIC_INVALIDATE_CPI - QIC_CPI_OFFSET)
152 #define QIC_RESCHEDULE_CPI (VIC_RESCHEDULE_CPI - QIC_CPI_OFFSET)
153 #define QIC_ENABLE_IRQ_CPI (VIC_ENABLE_IRQ_CPI - QIC_CPI_OFFSET)
154 #define QIC_CALL_FUNCTION_CPI (VIC_CALL_FUNCTION_CPI - QIC_CPI_OFFSET)
156 #define VIC_START_FAKE_CPI VIC_TIMER_CPI
157 #define VIC_END_FAKE_CPI VIC_CALL_FUNCTION_CPI
159 /* this is the SYS_INT CPI. */
160 #define VIC_SYS_INT 8
161 #define VIC_CMN_INT 15
163 /* This is the boot CPI for alternate processors. It gets overwritten
164 * by the above once the system has activated all available processors */
165 #define VIC_CPU_BOOT_CPI VIC_CPI_LEVEL0
166 #define VIC_CPU_BOOT_ERRATA_CPI (VIC_CPI_LEVEL0 + 8)
169 #endif /* _ASM_IRQ_VECTORS_H */