2 * Driver for Xilinx TEMAC Ethernet device
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
8 * This is a driver for the Xilinx ll_temac ipcore which is often used
9 * in the Virtex and Spartan series of chips.
12 * - The ll_temac hardware uses indirect access for many of the TEMAC
13 * registers, include the MDIO bus. However, indirect access to MDIO
14 * registers take considerably more clock cycles than to TEMAC registers.
15 * MDIO accesses are long, so threads doing them should probably sleep
16 * rather than busywait. However, since only one indirect access can be
17 * in progress at any given time, that means that *all* indirect accesses
18 * could end up sleeping (to wait for an MDIO access to complete).
19 * Fortunately none of the indirect accesses are on the 'hot' path for tx
20 * or rx, so this should be okay.
23 * - Factor out locallink DMA code into separate driver
24 * - Fix multicast assignment.
25 * - Fix support for hardware checksumming.
26 * - Testing. Lots and lots of testing.
30 #include <linux/delay.h>
31 #include <linux/etherdevice.h>
32 #include <linux/init.h>
33 #include <linux/mii.h>
34 #include <linux/module.h>
35 #include <linux/mutex.h>
36 #include <linux/netdevice.h>
38 #include <linux/of_device.h>
39 #include <linux/of_mdio.h>
40 #include <linux/of_platform.h>
41 #include <linux/skbuff.h>
42 #include <linux/spinlock.h>
43 #include <linux/tcp.h> /* needed for sizeof(tcphdr) */
44 #include <linux/udp.h> /* needed for sizeof(udphdr) */
45 #include <linux/phy.h>
49 #include <linux/slab.h>
56 /* ---------------------------------------------------------------------
57 * Low level register access functions
60 u32
temac_ior(struct temac_local
*lp
, int offset
)
62 return in_be32((u32
*)(lp
->regs
+ offset
));
65 void temac_iow(struct temac_local
*lp
, int offset
, u32 value
)
67 out_be32((u32
*) (lp
->regs
+ offset
), value
);
70 int temac_indirect_busywait(struct temac_local
*lp
)
72 long end
= jiffies
+ 2;
74 while (!(temac_ior(lp
, XTE_RDY0_OFFSET
) & XTE_RDY0_HARD_ACS_RDY_MASK
)) {
75 if (end
- jiffies
<= 0) {
87 * lp->indirect_mutex must be held when calling this function
89 u32
temac_indirect_in32(struct temac_local
*lp
, int reg
)
93 if (temac_indirect_busywait(lp
))
95 temac_iow(lp
, XTE_CTL0_OFFSET
, reg
);
96 if (temac_indirect_busywait(lp
))
98 val
= temac_ior(lp
, XTE_LSW0_OFFSET
);
104 * temac_indirect_out32
106 * lp->indirect_mutex must be held when calling this function
108 void temac_indirect_out32(struct temac_local
*lp
, int reg
, u32 value
)
110 if (temac_indirect_busywait(lp
))
112 temac_iow(lp
, XTE_LSW0_OFFSET
, value
);
113 temac_iow(lp
, XTE_CTL0_OFFSET
, CNTLREG_WRITE_ENABLE_MASK
| reg
);
117 * temac_dma_in32 - Memory mapped DMA read, this function expects a
118 * register input that is based on DCR word addresses which
119 * are then converted to memory mapped byte addresses
121 static u32
temac_dma_in32(struct temac_local
*lp
, int reg
)
123 return in_be32((u32
*)(lp
->sdma_regs
+ (reg
<< 2)));
127 * temac_dma_out32 - Memory mapped DMA read, this function expects a
128 * register input that is based on DCR word addresses which
129 * are then converted to memory mapped byte addresses
131 static void temac_dma_out32(struct temac_local
*lp
, int reg
, u32 value
)
133 out_be32((u32
*)(lp
->sdma_regs
+ (reg
<< 2)), value
);
136 /* DMA register access functions can be DCR based or memory mapped.
137 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
140 #ifdef CONFIG_PPC_DCR
143 * temac_dma_dcr_in32 - DCR based DMA read
145 static u32
temac_dma_dcr_in(struct temac_local
*lp
, int reg
)
147 return dcr_read(lp
->sdma_dcrs
, reg
);
151 * temac_dma_dcr_out32 - DCR based DMA write
153 static void temac_dma_dcr_out(struct temac_local
*lp
, int reg
, u32 value
)
155 dcr_write(lp
->sdma_dcrs
, reg
, value
);
159 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
162 static int temac_dcr_setup(struct temac_local
*lp
, struct of_device
*op
,
163 struct device_node
*np
)
167 /* setup the dcr address mapping if it's in the device tree */
169 dcrs
= dcr_resource_start(np
, 0);
171 lp
->sdma_dcrs
= dcr_map(np
, dcrs
, dcr_resource_len(np
, 0));
172 lp
->dma_in
= temac_dma_dcr_in
;
173 lp
->dma_out
= temac_dma_dcr_out
;
174 dev_dbg(&op
->dev
, "DCR base: %x\n", dcrs
);
177 /* no DCR in the device tree, indicate a failure */
184 * temac_dcr_setup - This is a stub for when DCR is not supported,
185 * such as with MicroBlaze
187 static int temac_dcr_setup(struct temac_local
*lp
, struct of_device
*op
,
188 struct device_node
*np
)
196 * * temac_dma_bd_release - Release buffer descriptor rings
198 static void temac_dma_bd_release(struct net_device
*ndev
)
200 struct temac_local
*lp
= netdev_priv(ndev
);
203 for (i
= 0; i
< RX_BD_NUM
; i
++) {
207 dma_unmap_single(ndev
->dev
.parent
, lp
->rx_bd_v
[i
].phys
,
208 XTE_MAX_JUMBO_FRAME_SIZE
, DMA_FROM_DEVICE
);
209 dev_kfree_skb(lp
->rx_skb
[i
]);
213 dma_free_coherent(ndev
->dev
.parent
,
214 sizeof(*lp
->rx_bd_v
) * RX_BD_NUM
,
215 lp
->rx_bd_v
, lp
->rx_bd_p
);
217 dma_free_coherent(ndev
->dev
.parent
,
218 sizeof(*lp
->tx_bd_v
) * TX_BD_NUM
,
219 lp
->tx_bd_v
, lp
->tx_bd_p
);
225 * temac_dma_bd_init - Setup buffer descriptor rings
227 static int temac_dma_bd_init(struct net_device
*ndev
)
229 struct temac_local
*lp
= netdev_priv(ndev
);
233 lp
->rx_skb
= kzalloc(sizeof(*lp
->rx_skb
) * RX_BD_NUM
, GFP_KERNEL
);
236 "can't allocate memory for DMA RX buffer\n");
239 /* allocate the tx and rx ring buffer descriptors. */
240 /* returns a virtual addres and a physical address. */
241 lp
->tx_bd_v
= dma_alloc_coherent(ndev
->dev
.parent
,
242 sizeof(*lp
->tx_bd_v
) * TX_BD_NUM
,
243 &lp
->tx_bd_p
, GFP_KERNEL
);
246 "unable to allocate DMA TX buffer descriptors");
249 lp
->rx_bd_v
= dma_alloc_coherent(ndev
->dev
.parent
,
250 sizeof(*lp
->rx_bd_v
) * RX_BD_NUM
,
251 &lp
->rx_bd_p
, GFP_KERNEL
);
254 "unable to allocate DMA RX buffer descriptors");
258 memset(lp
->tx_bd_v
, 0, sizeof(*lp
->tx_bd_v
) * TX_BD_NUM
);
259 for (i
= 0; i
< TX_BD_NUM
; i
++) {
260 lp
->tx_bd_v
[i
].next
= lp
->tx_bd_p
+
261 sizeof(*lp
->tx_bd_v
) * ((i
+ 1) % TX_BD_NUM
);
264 memset(lp
->rx_bd_v
, 0, sizeof(*lp
->rx_bd_v
) * RX_BD_NUM
);
265 for (i
= 0; i
< RX_BD_NUM
; i
++) {
266 lp
->rx_bd_v
[i
].next
= lp
->rx_bd_p
+
267 sizeof(*lp
->rx_bd_v
) * ((i
+ 1) % RX_BD_NUM
);
269 skb
= netdev_alloc_skb_ip_align(ndev
,
270 XTE_MAX_JUMBO_FRAME_SIZE
);
273 dev_err(&ndev
->dev
, "alloc_skb error %d\n", i
);
277 /* returns physical address of skb->data */
278 lp
->rx_bd_v
[i
].phys
= dma_map_single(ndev
->dev
.parent
,
280 XTE_MAX_JUMBO_FRAME_SIZE
,
282 lp
->rx_bd_v
[i
].len
= XTE_MAX_JUMBO_FRAME_SIZE
;
283 lp
->rx_bd_v
[i
].app0
= STS_CTRL_APP0_IRQONEND
;
286 lp
->dma_out(lp
, TX_CHNL_CTRL
, 0x10220400 |
288 CHNL_CTRL_IRQ_DLY_EN
|
289 CHNL_CTRL_IRQ_COAL_EN
);
292 lp
->dma_out(lp
, RX_CHNL_CTRL
, 0xff070000 |
294 CHNL_CTRL_IRQ_DLY_EN
|
295 CHNL_CTRL_IRQ_COAL_EN
|
299 lp
->dma_out(lp
, RX_CURDESC_PTR
, lp
->rx_bd_p
);
300 lp
->dma_out(lp
, RX_TAILDESC_PTR
,
301 lp
->rx_bd_p
+ (sizeof(*lp
->rx_bd_v
) * (RX_BD_NUM
- 1)));
302 lp
->dma_out(lp
, TX_CURDESC_PTR
, lp
->tx_bd_p
);
307 temac_dma_bd_release(ndev
);
311 /* ---------------------------------------------------------------------
315 static int temac_set_mac_address(struct net_device
*ndev
, void *address
)
317 struct temac_local
*lp
= netdev_priv(ndev
);
320 memcpy(ndev
->dev_addr
, address
, ETH_ALEN
);
322 if (!is_valid_ether_addr(ndev
->dev_addr
))
323 random_ether_addr(ndev
->dev_addr
);
325 /* set up unicast MAC address filter set its mac address */
326 mutex_lock(&lp
->indirect_mutex
);
327 temac_indirect_out32(lp
, XTE_UAW0_OFFSET
,
328 (ndev
->dev_addr
[0]) |
329 (ndev
->dev_addr
[1] << 8) |
330 (ndev
->dev_addr
[2] << 16) |
331 (ndev
->dev_addr
[3] << 24));
332 /* There are reserved bits in EUAW1
333 * so don't affect them Set MAC bits [47:32] in EUAW1 */
334 temac_indirect_out32(lp
, XTE_UAW1_OFFSET
,
335 (ndev
->dev_addr
[4] & 0x000000ff) |
336 (ndev
->dev_addr
[5] << 8));
337 mutex_unlock(&lp
->indirect_mutex
);
342 static int netdev_set_mac_address(struct net_device
*ndev
, void *p
)
344 struct sockaddr
*addr
= p
;
346 return temac_set_mac_address(ndev
, addr
->sa_data
);
349 static void temac_set_multicast_list(struct net_device
*ndev
)
351 struct temac_local
*lp
= netdev_priv(ndev
);
352 u32 multi_addr_msw
, multi_addr_lsw
, val
;
355 mutex_lock(&lp
->indirect_mutex
);
356 if (ndev
->flags
& (IFF_ALLMULTI
| IFF_PROMISC
) ||
357 netdev_mc_count(ndev
) > MULTICAST_CAM_TABLE_NUM
) {
359 * We must make the kernel realise we had to move
360 * into promisc mode or we start all out war on
361 * the cable. If it was a promisc request the
362 * flag is already set. If not we assert it.
364 ndev
->flags
|= IFF_PROMISC
;
365 temac_indirect_out32(lp
, XTE_AFM_OFFSET
, XTE_AFM_EPPRM_MASK
);
366 dev_info(&ndev
->dev
, "Promiscuous mode enabled.\n");
367 } else if (!netdev_mc_empty(ndev
)) {
368 struct netdev_hw_addr
*ha
;
371 netdev_for_each_mc_addr(ha
, ndev
) {
372 if (i
>= MULTICAST_CAM_TABLE_NUM
)
374 multi_addr_msw
= ((ha
->addr
[3] << 24) |
375 (ha
->addr
[2] << 16) |
378 temac_indirect_out32(lp
, XTE_MAW0_OFFSET
,
380 multi_addr_lsw
= ((ha
->addr
[5] << 8) |
381 (ha
->addr
[4]) | (i
<< 16));
382 temac_indirect_out32(lp
, XTE_MAW1_OFFSET
,
387 val
= temac_indirect_in32(lp
, XTE_AFM_OFFSET
);
388 temac_indirect_out32(lp
, XTE_AFM_OFFSET
,
389 val
& ~XTE_AFM_EPPRM_MASK
);
390 temac_indirect_out32(lp
, XTE_MAW0_OFFSET
, 0);
391 temac_indirect_out32(lp
, XTE_MAW1_OFFSET
, 0);
392 dev_info(&ndev
->dev
, "Promiscuous mode disabled.\n");
394 mutex_unlock(&lp
->indirect_mutex
);
397 struct temac_option
{
403 } temac_options
[] = {
404 /* Turn on jumbo packet support for both Rx and Tx */
406 .opt
= XTE_OPTION_JUMBO
,
407 .reg
= XTE_TXC_OFFSET
,
408 .m_or
= XTE_TXC_TXJMBO_MASK
,
411 .opt
= XTE_OPTION_JUMBO
,
412 .reg
= XTE_RXC1_OFFSET
,
413 .m_or
=XTE_RXC1_RXJMBO_MASK
,
415 /* Turn on VLAN packet support for both Rx and Tx */
417 .opt
= XTE_OPTION_VLAN
,
418 .reg
= XTE_TXC_OFFSET
,
419 .m_or
=XTE_TXC_TXVLAN_MASK
,
422 .opt
= XTE_OPTION_VLAN
,
423 .reg
= XTE_RXC1_OFFSET
,
424 .m_or
=XTE_RXC1_RXVLAN_MASK
,
426 /* Turn on FCS stripping on receive packets */
428 .opt
= XTE_OPTION_FCS_STRIP
,
429 .reg
= XTE_RXC1_OFFSET
,
430 .m_or
=XTE_RXC1_RXFCS_MASK
,
432 /* Turn on FCS insertion on transmit packets */
434 .opt
= XTE_OPTION_FCS_INSERT
,
435 .reg
= XTE_TXC_OFFSET
,
436 .m_or
=XTE_TXC_TXFCS_MASK
,
438 /* Turn on length/type field checking on receive packets */
440 .opt
= XTE_OPTION_LENTYPE_ERR
,
441 .reg
= XTE_RXC1_OFFSET
,
442 .m_or
=XTE_RXC1_RXLT_MASK
,
444 /* Turn on flow control */
446 .opt
= XTE_OPTION_FLOW_CONTROL
,
447 .reg
= XTE_FCC_OFFSET
,
448 .m_or
=XTE_FCC_RXFLO_MASK
,
450 /* Turn on flow control */
452 .opt
= XTE_OPTION_FLOW_CONTROL
,
453 .reg
= XTE_FCC_OFFSET
,
454 .m_or
=XTE_FCC_TXFLO_MASK
,
456 /* Turn on promiscuous frame filtering (all frames are received ) */
458 .opt
= XTE_OPTION_PROMISC
,
459 .reg
= XTE_AFM_OFFSET
,
460 .m_or
=XTE_AFM_EPPRM_MASK
,
462 /* Enable transmitter if not already enabled */
464 .opt
= XTE_OPTION_TXEN
,
465 .reg
= XTE_TXC_OFFSET
,
466 .m_or
=XTE_TXC_TXEN_MASK
,
468 /* Enable receiver? */
470 .opt
= XTE_OPTION_RXEN
,
471 .reg
= XTE_RXC1_OFFSET
,
472 .m_or
=XTE_RXC1_RXEN_MASK
,
480 static u32
temac_setoptions(struct net_device
*ndev
, u32 options
)
482 struct temac_local
*lp
= netdev_priv(ndev
);
483 struct temac_option
*tp
= &temac_options
[0];
486 mutex_lock(&lp
->indirect_mutex
);
488 reg
= temac_indirect_in32(lp
, tp
->reg
) & ~tp
->m_or
;
489 if (options
& tp
->opt
)
491 temac_indirect_out32(lp
, tp
->reg
, reg
);
494 lp
->options
|= options
;
495 mutex_unlock(&lp
->indirect_mutex
);
500 /* Initilize temac */
501 static void temac_device_reset(struct net_device
*ndev
)
503 struct temac_local
*lp
= netdev_priv(ndev
);
507 /* Perform a software reset */
509 /* 0x300 host enable bit ? */
510 /* reset PHY through control register ?:1 */
512 dev_dbg(&ndev
->dev
, "%s()\n", __func__
);
514 mutex_lock(&lp
->indirect_mutex
);
515 /* Reset the receiver and wait for it to finish reset */
516 temac_indirect_out32(lp
, XTE_RXC1_OFFSET
, XTE_RXC1_RXRST_MASK
);
518 while (temac_indirect_in32(lp
, XTE_RXC1_OFFSET
) & XTE_RXC1_RXRST_MASK
) {
520 if (--timeout
== 0) {
522 "temac_device_reset RX reset timeout!!\n");
527 /* Reset the transmitter and wait for it to finish reset */
528 temac_indirect_out32(lp
, XTE_TXC_OFFSET
, XTE_TXC_TXRST_MASK
);
530 while (temac_indirect_in32(lp
, XTE_TXC_OFFSET
) & XTE_TXC_TXRST_MASK
) {
532 if (--timeout
== 0) {
534 "temac_device_reset TX reset timeout!!\n");
539 /* Disable the receiver */
540 val
= temac_indirect_in32(lp
, XTE_RXC1_OFFSET
);
541 temac_indirect_out32(lp
, XTE_RXC1_OFFSET
, val
& ~XTE_RXC1_RXEN_MASK
);
543 /* Reset Local Link (DMA) */
544 lp
->dma_out(lp
, DMA_CONTROL_REG
, DMA_CONTROL_RST
);
546 while (lp
->dma_in(lp
, DMA_CONTROL_REG
) & DMA_CONTROL_RST
) {
548 if (--timeout
== 0) {
550 "temac_device_reset DMA reset timeout!!\n");
554 lp
->dma_out(lp
, DMA_CONTROL_REG
, DMA_TAIL_ENABLE
);
556 if (temac_dma_bd_init(ndev
)) {
558 "temac_device_reset descriptor allocation failed\n");
561 temac_indirect_out32(lp
, XTE_RXC0_OFFSET
, 0);
562 temac_indirect_out32(lp
, XTE_RXC1_OFFSET
, 0);
563 temac_indirect_out32(lp
, XTE_TXC_OFFSET
, 0);
564 temac_indirect_out32(lp
, XTE_FCC_OFFSET
, XTE_FCC_RXFLO_MASK
);
566 mutex_unlock(&lp
->indirect_mutex
);
568 /* Sync default options with HW
569 * but leave receiver and transmitter disabled. */
570 temac_setoptions(ndev
,
571 lp
->options
& ~(XTE_OPTION_TXEN
| XTE_OPTION_RXEN
));
573 temac_set_mac_address(ndev
, NULL
);
575 /* Set address filter table */
576 temac_set_multicast_list(ndev
);
577 if (temac_setoptions(ndev
, lp
->options
))
578 dev_err(&ndev
->dev
, "Error setting TEMAC options\n");
580 /* Init Driver variable */
581 ndev
->trans_start
= jiffies
; /* prevent tx timeout */
584 void temac_adjust_link(struct net_device
*ndev
)
586 struct temac_local
*lp
= netdev_priv(ndev
);
587 struct phy_device
*phy
= lp
->phy_dev
;
591 /* hash together the state values to decide if something has changed */
592 link_state
= phy
->speed
| (phy
->duplex
<< 1) | phy
->link
;
594 mutex_lock(&lp
->indirect_mutex
);
595 if (lp
->last_link
!= link_state
) {
596 mii_speed
= temac_indirect_in32(lp
, XTE_EMCFG_OFFSET
);
597 mii_speed
&= ~XTE_EMCFG_LINKSPD_MASK
;
599 switch (phy
->speed
) {
600 case SPEED_1000
: mii_speed
|= XTE_EMCFG_LINKSPD_1000
; break;
601 case SPEED_100
: mii_speed
|= XTE_EMCFG_LINKSPD_100
; break;
602 case SPEED_10
: mii_speed
|= XTE_EMCFG_LINKSPD_10
; break;
605 /* Write new speed setting out to TEMAC */
606 temac_indirect_out32(lp
, XTE_EMCFG_OFFSET
, mii_speed
);
607 lp
->last_link
= link_state
;
608 phy_print_status(phy
);
610 mutex_unlock(&lp
->indirect_mutex
);
613 static void temac_start_xmit_done(struct net_device
*ndev
)
615 struct temac_local
*lp
= netdev_priv(ndev
);
616 struct cdmac_bd
*cur_p
;
617 unsigned int stat
= 0;
619 cur_p
= &lp
->tx_bd_v
[lp
->tx_bd_ci
];
622 while (stat
& STS_CTRL_APP0_CMPLT
) {
623 dma_unmap_single(ndev
->dev
.parent
, cur_p
->phys
, cur_p
->len
,
626 dev_kfree_skb_irq((struct sk_buff
*)cur_p
->app4
);
633 ndev
->stats
.tx_packets
++;
634 ndev
->stats
.tx_bytes
+= cur_p
->len
;
637 if (lp
->tx_bd_ci
>= TX_BD_NUM
)
640 cur_p
= &lp
->tx_bd_v
[lp
->tx_bd_ci
];
644 netif_wake_queue(ndev
);
647 static inline int temac_check_tx_bd_space(struct temac_local
*lp
, int num_frag
)
649 struct cdmac_bd
*cur_p
;
652 tail
= lp
->tx_bd_tail
;
653 cur_p
= &lp
->tx_bd_v
[tail
];
657 return NETDEV_TX_BUSY
;
660 if (tail
>= TX_BD_NUM
)
663 cur_p
= &lp
->tx_bd_v
[tail
];
665 } while (num_frag
>= 0);
670 static int temac_start_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
672 struct temac_local
*lp
= netdev_priv(ndev
);
673 struct cdmac_bd
*cur_p
;
674 dma_addr_t start_p
, tail_p
;
676 unsigned long num_frag
;
679 num_frag
= skb_shinfo(skb
)->nr_frags
;
680 frag
= &skb_shinfo(skb
)->frags
[0];
681 start_p
= lp
->tx_bd_p
+ sizeof(*lp
->tx_bd_v
) * lp
->tx_bd_tail
;
682 cur_p
= &lp
->tx_bd_v
[lp
->tx_bd_tail
];
684 if (temac_check_tx_bd_space(lp
, num_frag
)) {
685 if (!netif_queue_stopped(ndev
)) {
686 netif_stop_queue(ndev
);
687 return NETDEV_TX_BUSY
;
689 return NETDEV_TX_BUSY
;
693 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
694 unsigned int csum_start_off
= skb_transport_offset(skb
);
695 unsigned int csum_index_off
= csum_start_off
+ skb
->csum_offset
;
697 cur_p
->app0
|= 1; /* TX Checksum Enabled */
698 cur_p
->app1
= (csum_start_off
<< 16) | csum_index_off
;
699 cur_p
->app2
= 0; /* initial checksum seed */
702 cur_p
->app0
|= STS_CTRL_APP0_SOP
;
703 cur_p
->len
= skb_headlen(skb
);
704 cur_p
->phys
= dma_map_single(ndev
->dev
.parent
, skb
->data
, skb
->len
,
706 cur_p
->app4
= (unsigned long)skb
;
708 for (ii
= 0; ii
< num_frag
; ii
++) {
710 if (lp
->tx_bd_tail
>= TX_BD_NUM
)
713 cur_p
= &lp
->tx_bd_v
[lp
->tx_bd_tail
];
714 cur_p
->phys
= dma_map_single(ndev
->dev
.parent
,
715 (void *)page_address(frag
->page
) +
717 frag
->size
, DMA_TO_DEVICE
);
718 cur_p
->len
= frag
->size
;
722 cur_p
->app0
|= STS_CTRL_APP0_EOP
;
724 tail_p
= lp
->tx_bd_p
+ sizeof(*lp
->tx_bd_v
) * lp
->tx_bd_tail
;
726 if (lp
->tx_bd_tail
>= TX_BD_NUM
)
729 /* Kick off the transfer */
730 lp
->dma_out(lp
, TX_TAILDESC_PTR
, tail_p
); /* DMA start */
736 static void ll_temac_recv(struct net_device
*ndev
)
738 struct temac_local
*lp
= netdev_priv(ndev
);
739 struct sk_buff
*skb
, *new_skb
;
741 struct cdmac_bd
*cur_p
;
746 spin_lock_irqsave(&lp
->rx_lock
, flags
);
748 tail_p
= lp
->rx_bd_p
+ sizeof(*lp
->rx_bd_v
) * lp
->rx_bd_ci
;
749 cur_p
= &lp
->rx_bd_v
[lp
->rx_bd_ci
];
751 bdstat
= cur_p
->app0
;
752 while ((bdstat
& STS_CTRL_APP0_CMPLT
)) {
754 skb
= lp
->rx_skb
[lp
->rx_bd_ci
];
755 length
= cur_p
->app4
& 0x3FFF;
757 dma_unmap_single(ndev
->dev
.parent
, cur_p
->phys
, length
,
760 skb_put(skb
, length
);
762 skb
->protocol
= eth_type_trans(skb
, ndev
);
763 skb
->ip_summed
= CHECKSUM_NONE
;
765 /* if we're doing rx csum offload, set it up */
766 if (((lp
->temac_features
& TEMAC_FEATURE_RX_CSUM
) != 0) &&
767 (skb
->protocol
== __constant_htons(ETH_P_IP
)) &&
770 skb
->csum
= cur_p
->app3
& 0xFFFF;
771 skb
->ip_summed
= CHECKSUM_COMPLETE
;
776 ndev
->stats
.rx_packets
++;
777 ndev
->stats
.rx_bytes
+= length
;
779 new_skb
= netdev_alloc_skb_ip_align(ndev
,
780 XTE_MAX_JUMBO_FRAME_SIZE
);
783 dev_err(&ndev
->dev
, "no memory for new sk_buff\n");
784 spin_unlock_irqrestore(&lp
->rx_lock
, flags
);
788 cur_p
->app0
= STS_CTRL_APP0_IRQONEND
;
789 cur_p
->phys
= dma_map_single(ndev
->dev
.parent
, new_skb
->data
,
790 XTE_MAX_JUMBO_FRAME_SIZE
,
792 cur_p
->len
= XTE_MAX_JUMBO_FRAME_SIZE
;
793 lp
->rx_skb
[lp
->rx_bd_ci
] = new_skb
;
796 if (lp
->rx_bd_ci
>= RX_BD_NUM
)
799 cur_p
= &lp
->rx_bd_v
[lp
->rx_bd_ci
];
800 bdstat
= cur_p
->app0
;
802 lp
->dma_out(lp
, RX_TAILDESC_PTR
, tail_p
);
804 spin_unlock_irqrestore(&lp
->rx_lock
, flags
);
807 static irqreturn_t
ll_temac_tx_irq(int irq
, void *_ndev
)
809 struct net_device
*ndev
= _ndev
;
810 struct temac_local
*lp
= netdev_priv(ndev
);
813 status
= lp
->dma_in(lp
, TX_IRQ_REG
);
814 lp
->dma_out(lp
, TX_IRQ_REG
, status
);
816 if (status
& (IRQ_COAL
| IRQ_DLY
))
817 temac_start_xmit_done(lp
->ndev
);
819 dev_err(&ndev
->dev
, "DMA error 0x%x\n", status
);
824 static irqreturn_t
ll_temac_rx_irq(int irq
, void *_ndev
)
826 struct net_device
*ndev
= _ndev
;
827 struct temac_local
*lp
= netdev_priv(ndev
);
830 /* Read and clear the status registers */
831 status
= lp
->dma_in(lp
, RX_IRQ_REG
);
832 lp
->dma_out(lp
, RX_IRQ_REG
, status
);
834 if (status
& (IRQ_COAL
| IRQ_DLY
))
835 ll_temac_recv(lp
->ndev
);
840 static int temac_open(struct net_device
*ndev
)
842 struct temac_local
*lp
= netdev_priv(ndev
);
845 dev_dbg(&ndev
->dev
, "temac_open()\n");
848 lp
->phy_dev
= of_phy_connect(lp
->ndev
, lp
->phy_node
,
849 temac_adjust_link
, 0, 0);
851 dev_err(lp
->dev
, "of_phy_connect() failed\n");
855 phy_start(lp
->phy_dev
);
858 rc
= request_irq(lp
->tx_irq
, ll_temac_tx_irq
, 0, ndev
->name
, ndev
);
861 rc
= request_irq(lp
->rx_irq
, ll_temac_rx_irq
, 0, ndev
->name
, ndev
);
865 temac_device_reset(ndev
);
869 free_irq(lp
->tx_irq
, ndev
);
872 phy_disconnect(lp
->phy_dev
);
874 dev_err(lp
->dev
, "request_irq() failed\n");
878 static int temac_stop(struct net_device
*ndev
)
880 struct temac_local
*lp
= netdev_priv(ndev
);
882 dev_dbg(&ndev
->dev
, "temac_close()\n");
884 free_irq(lp
->tx_irq
, ndev
);
885 free_irq(lp
->rx_irq
, ndev
);
888 phy_disconnect(lp
->phy_dev
);
891 temac_dma_bd_release(ndev
);
896 #ifdef CONFIG_NET_POLL_CONTROLLER
898 temac_poll_controller(struct net_device
*ndev
)
900 struct temac_local
*lp
= netdev_priv(ndev
);
902 disable_irq(lp
->tx_irq
);
903 disable_irq(lp
->rx_irq
);
905 ll_temac_rx_irq(lp
->tx_irq
, lp
);
906 ll_temac_tx_irq(lp
->rx_irq
, lp
);
908 enable_irq(lp
->tx_irq
);
909 enable_irq(lp
->rx_irq
);
913 static const struct net_device_ops temac_netdev_ops
= {
914 .ndo_open
= temac_open
,
915 .ndo_stop
= temac_stop
,
916 .ndo_start_xmit
= temac_start_xmit
,
917 .ndo_set_mac_address
= netdev_set_mac_address
,
918 .ndo_validate_addr
= eth_validate_addr
,
919 //.ndo_set_multicast_list = temac_set_multicast_list,
920 #ifdef CONFIG_NET_POLL_CONTROLLER
921 .ndo_poll_controller
= temac_poll_controller
,
925 /* ---------------------------------------------------------------------
926 * SYSFS device attributes
928 static ssize_t
temac_show_llink_regs(struct device
*dev
,
929 struct device_attribute
*attr
, char *buf
)
931 struct net_device
*ndev
= dev_get_drvdata(dev
);
932 struct temac_local
*lp
= netdev_priv(ndev
);
935 for (i
= 0; i
< 0x11; i
++)
936 len
+= sprintf(buf
+ len
, "%.8x%s", lp
->dma_in(lp
, i
),
937 (i
% 8) == 7 ? "\n" : " ");
938 len
+= sprintf(buf
+ len
, "\n");
943 static DEVICE_ATTR(llink_regs
, 0440, temac_show_llink_regs
, NULL
);
945 static struct attribute
*temac_device_attrs
[] = {
946 &dev_attr_llink_regs
.attr
,
950 static const struct attribute_group temac_attr_group
= {
951 .attrs
= temac_device_attrs
,
955 temac_of_probe(struct of_device
*op
, const struct of_device_id
*match
)
957 struct device_node
*np
;
958 struct temac_local
*lp
;
959 struct net_device
*ndev
;
964 /* Init network device structure */
965 ndev
= alloc_etherdev(sizeof(*lp
));
967 dev_err(&op
->dev
, "could not allocate device.\n");
971 dev_set_drvdata(&op
->dev
, ndev
);
972 SET_NETDEV_DEV(ndev
, &op
->dev
);
973 ndev
->flags
&= ~IFF_MULTICAST
; /* clear multicast */
974 ndev
->features
= NETIF_F_SG
| NETIF_F_FRAGLIST
;
975 ndev
->netdev_ops
= &temac_netdev_ops
;
977 ndev
->features
|= NETIF_F_IP_CSUM
; /* Can checksum TCP/UDP over IPv4. */
978 ndev
->features
|= NETIF_F_HW_CSUM
; /* Can checksum all the packets. */
979 ndev
->features
|= NETIF_F_IPV6_CSUM
; /* Can checksum IPV6 TCP/UDP */
980 ndev
->features
|= NETIF_F_HIGHDMA
; /* Can DMA to high memory. */
981 ndev
->features
|= NETIF_F_HW_VLAN_TX
; /* Transmit VLAN hw accel */
982 ndev
->features
|= NETIF_F_HW_VLAN_RX
; /* Receive VLAN hw acceleration */
983 ndev
->features
|= NETIF_F_HW_VLAN_FILTER
; /* Receive VLAN filtering */
984 ndev
->features
|= NETIF_F_VLAN_CHALLENGED
; /* cannot handle VLAN pkts */
985 ndev
->features
|= NETIF_F_GSO
; /* Enable software GSO. */
986 ndev
->features
|= NETIF_F_MULTI_QUEUE
; /* Has multiple TX/RX queues */
987 ndev
->features
|= NETIF_F_LRO
; /* large receive offload */
990 /* setup temac private info structure */
991 lp
= netdev_priv(ndev
);
994 lp
->options
= XTE_OPTION_DEFAULTS
;
995 spin_lock_init(&lp
->rx_lock
);
996 mutex_init(&lp
->indirect_mutex
);
998 /* map device registers */
999 lp
->regs
= of_iomap(op
->dev
.of_node
, 0);
1001 dev_err(&op
->dev
, "could not map temac regs.\n");
1005 /* Setup checksum offload, but default to off if not specified */
1006 lp
->temac_features
= 0;
1007 p
= (__be32
*)of_get_property(op
->dev
.of_node
, "xlnx,txcsum", NULL
);
1008 if (p
&& be32_to_cpu(*p
)) {
1009 lp
->temac_features
|= TEMAC_FEATURE_TX_CSUM
;
1010 /* Can checksum TCP/UDP over IPv4. */
1011 ndev
->features
|= NETIF_F_IP_CSUM
;
1013 p
= (__be32
*)of_get_property(op
->dev
.of_node
, "xlnx,rxcsum", NULL
);
1014 if (p
&& be32_to_cpu(*p
))
1015 lp
->temac_features
|= TEMAC_FEATURE_RX_CSUM
;
1017 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
1018 np
= of_parse_phandle(op
->dev
.of_node
, "llink-connected", 0);
1020 dev_err(&op
->dev
, "could not find DMA node\n");
1024 /* Setup the DMA register accesses, could be DCR or memory mapped */
1025 if (temac_dcr_setup(lp
, op
, np
)) {
1027 /* no DCR in the device tree, try non-DCR */
1028 lp
->sdma_regs
= of_iomap(np
, 0);
1029 if (lp
->sdma_regs
) {
1030 lp
->dma_in
= temac_dma_in32
;
1031 lp
->dma_out
= temac_dma_out32
;
1032 dev_dbg(&op
->dev
, "MEM base: %p\n", lp
->sdma_regs
);
1034 dev_err(&op
->dev
, "unable to map DMA registers\n");
1040 lp
->rx_irq
= irq_of_parse_and_map(np
, 0);
1041 lp
->tx_irq
= irq_of_parse_and_map(np
, 1);
1043 of_node_put(np
); /* Finished with the DMA node; drop the reference */
1045 if ((lp
->rx_irq
== NO_IRQ
) || (lp
->tx_irq
== NO_IRQ
)) {
1046 dev_err(&op
->dev
, "could not determine irqs\n");
1052 /* Retrieve the MAC address */
1053 addr
= of_get_property(op
->dev
.of_node
, "local-mac-address", &size
);
1054 if ((!addr
) || (size
!= 6)) {
1055 dev_err(&op
->dev
, "could not find MAC address\n");
1059 temac_set_mac_address(ndev
, (void *)addr
);
1061 rc
= temac_mdio_setup(lp
, op
->dev
.of_node
);
1063 dev_warn(&op
->dev
, "error registering MDIO bus\n");
1065 lp
->phy_node
= of_parse_phandle(op
->dev
.of_node
, "phy-handle", 0);
1067 dev_dbg(lp
->dev
, "using PHY node %s (%p)\n", np
->full_name
, np
);
1069 /* Add the device attributes */
1070 rc
= sysfs_create_group(&lp
->dev
->kobj
, &temac_attr_group
);
1072 dev_err(lp
->dev
, "Error creating sysfs files\n");
1076 rc
= register_netdev(lp
->ndev
);
1078 dev_err(lp
->dev
, "register_netdev() error (%i)\n", rc
);
1079 goto err_register_ndev
;
1085 sysfs_remove_group(&lp
->dev
->kobj
, &temac_attr_group
);
1088 iounmap(lp
->sdma_regs
);
1097 static int __devexit
temac_of_remove(struct of_device
*op
)
1099 struct net_device
*ndev
= dev_get_drvdata(&op
->dev
);
1100 struct temac_local
*lp
= netdev_priv(ndev
);
1102 temac_mdio_teardown(lp
);
1103 unregister_netdev(ndev
);
1104 sysfs_remove_group(&lp
->dev
->kobj
, &temac_attr_group
);
1106 of_node_put(lp
->phy_node
);
1107 lp
->phy_node
= NULL
;
1108 dev_set_drvdata(&op
->dev
, NULL
);
1111 iounmap(lp
->sdma_regs
);
1116 static struct of_device_id temac_of_match
[] __devinitdata
= {
1117 { .compatible
= "xlnx,xps-ll-temac-1.01.b", },
1118 { .compatible
= "xlnx,xps-ll-temac-2.00.a", },
1119 { .compatible
= "xlnx,xps-ll-temac-2.02.a", },
1120 { .compatible
= "xlnx,xps-ll-temac-2.03.a", },
1123 MODULE_DEVICE_TABLE(of
, temac_of_match
);
1125 static struct of_platform_driver temac_of_driver
= {
1126 .probe
= temac_of_probe
,
1127 .remove
= __devexit_p(temac_of_remove
),
1129 .owner
= THIS_MODULE
,
1130 .name
= "xilinx_temac",
1131 .of_match_table
= temac_of_match
,
1135 static int __init
temac_init(void)
1137 return of_register_platform_driver(&temac_of_driver
);
1139 module_init(temac_init
);
1141 static void __exit
temac_exit(void)
1143 of_unregister_platform_driver(&temac_of_driver
);
1145 module_exit(temac_exit
);
1147 MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1148 MODULE_AUTHOR("Yoshio Kashiwagi");
1149 MODULE_LICENSE("GPL");