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Staging: et131x: kill of FBR_WORD2
[linux-2.6/x86.git] / drivers / staging / et131x / et1310_rx.h
blobdb252cafa94ae6924fa112ec338ac7cc97a39511
1 /*
2 * Agere Systems Inc.
3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
4 *
5 * Copyright © 2005 Agere Systems Inc.
6 * All rights reserved.
7 * http://www.agere.com
8 *
9 *------------------------------------------------------------------------------
10 *
11 * et1310_rx.h - Defines, structs, enums, prototypes, etc. pertaining to data
12 * reception.
13 *
14 *------------------------------------------------------------------------------
15 *
16 * SOFTWARE LICENSE
17 *
18 * This software is provided subject to the following terms and conditions,
19 * which you should read carefully before using the software. Using this
20 * software indicates your acceptance of these terms and conditions. If you do
21 * not agree with these terms and conditions, do not use the software.
22 *
23 * Copyright © 2005 Agere Systems Inc.
24 * All rights reserved.
25 *
26 * Redistribution and use in source or binary forms, with or without
27 * modifications, are permitted provided that the following conditions are met:
28 *
29 * . Redistributions of source code must retain the above copyright notice, this
30 * list of conditions and the following Disclaimer as comments in the code as
31 * well as in the documentation and/or other materials provided with the
32 * distribution.
33 *
34 * . Redistributions in binary form must reproduce the above copyright notice,
35 * this list of conditions and the following Disclaimer in the documentation
36 * and/or other materials provided with the distribution.
37 *
38 * . Neither the name of Agere Systems Inc. nor the names of the contributors
39 * may be used to endorse or promote products derived from this software
40 * without specific prior written permission.
41 *
42 * Disclaimer
43 *
44 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
45 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
46 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
47 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
48 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
49 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
50 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
51 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
52 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
54 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
55 * DAMAGE.
56 *
57 */
58
59 #ifndef __ET1310_RX_H__
60 #define __ET1310_RX_H__
61
62 #include "et1310_address_map.h"
63
64 #define USE_FBR0 true
65
66 #ifdef USE_FBR0
67 /* #define FBR0_BUFFER_SIZE 256 */
68 #endif
69
70 /* #define FBR1_BUFFER_SIZE 2048 */
71
72 #define FBR_CHUNKS 32
73
74 #define MAX_DESC_PER_RING_RX 1024
75
76 /* number of RFDs - default and min */
77 #ifdef USE_FBR0
78 #define RFD_LOW_WATER_MARK 40
79 #define NIC_MIN_NUM_RFD 64
80 #define NIC_DEFAULT_NUM_RFD 1024
81 #else
82 #define RFD_LOW_WATER_MARK 20
83 #define NIC_MIN_NUM_RFD 64
84 #define NIC_DEFAULT_NUM_RFD 256
85 #endif
86
87 #define NUM_PACKETS_HANDLED 256
88
89 #define ALCATEL_BAD_STATUS 0xe47f0000
90 #define ALCATEL_MULTICAST_PKT 0x01000000
91 #define ALCATEL_BROADCAST_PKT 0x02000000
92
93 /* typedefs for Free Buffer Descriptors */
94 typedef struct _FBR_DESC_t {
95 u32 addr_lo;
96 u32 addr_hi;
97 u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */
98 } FBR_DESC_t, *PFBR_DESC_t;
99
100 /* Typedefs for Packet Status Ring Descriptors */
101 typedef union _PKT_STAT_DESC_WORD0_t {
102 u32 value;
103 struct {
104 #ifdef _BIT_FIELDS_HTOL
105 /* top 16 bits are from the Alcatel Status Word as enumerated in */
106 /* PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2) */
107 #if 0
108 u32 asw_trunc:1; /* bit 31(Rx frame truncated) */
109 #endif
110 u32 asw_long_evt:1; /* bit 31(Rx long event) */
111 u32 asw_VLAN_tag:1; /* bit 30(VLAN tag detected) */
112 u32 asw_unsupported_op:1; /* bit 29(unsupported OP code) */
113 u32 asw_pause_frame:1; /* bit 28(is a pause frame) */
114 u32 asw_control_frame:1; /* bit 27(is a control frame) */
115 u32 asw_dribble_nibble:1; /* bit 26(spurious bits after EOP) */
116 u32 asw_broadcast:1; /* bit 25(has a broadcast address) */
117 u32 asw_multicast:1; /* bit 24(has a multicast address) */
118 u32 asw_OK:1; /* bit 23(valid CRC + no code error) */
119 u32 asw_too_long:1; /* bit 22(frame length > 1518 bytes) */
120 u32 asw_len_chk_err:1; /* bit 21(frame length field incorrect) */
121 u32 asw_CRC_err:1; /* bit 20(CRC error) */
122 u32 asw_code_err:1; /* bit 19(one or more nibbles signalled as errors) */
123 u32 asw_false_carrier_event:1; /* bit 18(bad carrier since last good packet) */
124 u32 asw_RX_DV_event:1; /* bit 17(short receive event detected) */
125 u32 asw_prev_pkt_dropped:1;/* bit 16(e.g. IFG too small on previous) */
126 u32 unused:5; /* bits 11-15 */
127 u32 vp:1; /* bit 10(VLAN Packet) */
128 u32 jp:1; /* bit 9(Jumbo Packet) */
129 u32 ft:1; /* bit 8(Frame Truncated) */
130 u32 drop:1; /* bit 7(Drop packet) */
131 u32 rxmac_error:1; /* bit 6(RXMAC Error Indicator) */
132 u32 wol:1; /* bit 5(WOL Event) */
133 u32 tcpp:1; /* bit 4(TCP checksum pass) */
134 u32 tcpa:1; /* bit 3(TCP checksum assist) */
135 u32 ipp:1; /* bit 2(IP checksum pass) */
136 u32 ipa:1; /* bit 1(IP checksum assist) */
137 u32 hp:1; /* bit 0(hash pass) */
138 #else
139 u32 hp:1; /* bit 0(hash pass) */
140 u32 ipa:1; /* bit 1(IP checksum assist) */
141 u32 ipp:1; /* bit 2(IP checksum pass) */
142 u32 tcpa:1; /* bit 3(TCP checksum assist) */
143 u32 tcpp:1; /* bit 4(TCP checksum pass) */
144 u32 wol:1; /* bit 5(WOL Event) */
145 u32 rxmac_error:1; /* bit 6(RXMAC Error Indicator) */
146 u32 drop:1; /* bit 7(Drop packet) */
147 u32 ft:1; /* bit 8(Frame Truncated) */
148 u32 jp:1; /* bit 9(Jumbo Packet) */
149 u32 vp:1; /* bit 10(VLAN Packet) */
150 u32 unused:5; /* bits 11-15 */
151 u32 asw_prev_pkt_dropped:1;/* bit 16(e.g. IFG too small on previous) */
152 u32 asw_RX_DV_event:1; /* bit 17(short receive event detected) */
153 u32 asw_false_carrier_event:1; /* bit 18(bad carrier since last good packet) */
154 u32 asw_code_err:1; /* bit 19(one or more nibbles signalled as errors) */
155 u32 asw_CRC_err:1; /* bit 20(CRC error) */
156 u32 asw_len_chk_err:1; /* bit 21(frame length field incorrect) */
157 u32 asw_too_long:1; /* bit 22(frame length > 1518 bytes) */
158 u32 asw_OK:1; /* bit 23(valid CRC + no code error) */
159 u32 asw_multicast:1; /* bit 24(has a multicast address) */
160 u32 asw_broadcast:1; /* bit 25(has a broadcast address) */
161 u32 asw_dribble_nibble:1; /* bit 26(spurious bits after EOP) */
162 u32 asw_control_frame:1; /* bit 27(is a control frame) */
163 u32 asw_pause_frame:1; /* bit 28(is a pause frame) */
164 u32 asw_unsupported_op:1; /* bit 29(unsupported OP code) */
165 u32 asw_VLAN_tag:1; /* bit 30(VLAN tag detected) */
166 u32 asw_long_evt:1; /* bit 31(Rx long event) */
167 #if 0
168 u32 asw_trunc:1; /* bit 31(Rx frame truncated) */
169 #endif
170 #endif
171 } bits;
172 } PKT_STAT_DESC_WORD0_t, *PPKT_STAT_WORD0_t;
173
174 typedef union _PKT_STAT_DESC_WORD1_t {
175 u32 value;
176 struct {
177 #ifdef _BIT_FIELDS_HTOL
178 u32 unused:4; /* bits 28-31 */
179 u32 ri:2; /* bits 26-27(Ring Index) */
180 u32 bi:10; /* bits 16-25(Buffer Index) */
181 u32 length:16; /* bit 0-15(length in bytes) */
182 #else
183 u32 length:16; /* bit 0-15(length in bytes) */
184 u32 bi:10; /* bits 16-25(Buffer Index) */
185 u32 ri:2; /* bits 26-27(Ring Index) */
186 u32 unused:4; /* bits 28-31 */
187 #endif
188 } bits;
189 } PKT_STAT_DESC_WORD1_t, *PPKT_STAT_WORD1_t;
190
191 typedef struct _PKT_STAT_DESC_t {
192 PKT_STAT_DESC_WORD0_t word0;
193 PKT_STAT_DESC_WORD1_t word1;
194 } PKT_STAT_DESC_t, *PPKT_STAT_DESC_t;
195
196 /* Typedefs for the RX DMA status word */
197
198 /*
199 * rx status word 0 holds part of the status bits of the Rx DMA engine
200 * that get copied out to memory by the ET-1310. Word 0 is a 32 bit word
201 * which contains the Free Buffer ring 0 and 1 available offset.
202 *
203 * bit 0-9 FBR1 offset
204 * bit 10 Wrap flag for FBR1
205 * bit 16-25 FBR0 offset
206 * bit 26 Wrap flag for FBR0
207 */
208
209 /*
210 * RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
211 * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word
212 * which contains the Packet Status Ring available offset.
213 */
214
215 #define RXSTAT1_OFFSET 16
216 #define RXSTAT1_MASK 0xFFF
217 #define RXSTAT1_WRAP 0x10000000
218
219 typedef union _rxstat_word1_t {
220 u32 value;
221 struct {
222 #ifdef _BIT_FIELDS_HTOL
223 u32 PSRunused:3; /* bits 29-31 */
224 u32 PSRwrap:1; /* bit 28 */
225 u32 PSRoffset:12; /* bits 16-27 */
226 u32 reserved:16; /* bits 0-15 */
227 #else
228 u32 reserved:16; /* bits 0-15 */
229 u32 PSRoffset:12; /* bits 16-27 */
230 u32 PSRwrap:1; /* bit 28 */
231 u32 PSRunused:3; /* bits 29-31 */
232 #endif
233 } bits;
234 } RXSTAT_WORD1_t, *PRXSTAT_WORD1_t;
235
236 /*
237 * RX_STATUS_BLOCK_t is sructure representing the status of the Rx DMA engine
238 * it sits in free memory, and is pointed to by 0x101c / 0x1020
239 */
240 typedef struct _rx_status_block_t {
241 u32 Word0;
242 RXSTAT_WORD1_t Word1;
243 } RX_STATUS_BLOCK_t, *PRX_STATUS_BLOCK_t;
244
245 /*
246 * Structure for look-up table holding free buffer ring pointers
247 */
248 typedef struct _FbrLookupTable {
249 void *Va[MAX_DESC_PER_RING_RX];
250 void *Buffer1[MAX_DESC_PER_RING_RX];
251 void *Buffer2[MAX_DESC_PER_RING_RX];
252 u32 PAHigh[MAX_DESC_PER_RING_RX];
253 u32 PALow[MAX_DESC_PER_RING_RX];
254 } FBRLOOKUPTABLE, *PFBRLOOKUPTABLE;
255
256 typedef enum {
257 ONE_PACKET_INTERRUPT,
258 FOUR_PACKET_INTERRUPT
259 } eRX_INTERRUPT_STATE_t, *PeRX_INTERRUPT_STATE_t;
260
261 /*
262 * RX_RING_t is sructure representing the adaptor's local reference(s) to the
263 * rings
264 */
265 typedef struct _rx_ring_t {
266 #ifdef USE_FBR0
267 void *pFbr0RingVa;
268 dma_addr_t pFbr0RingPa;
269 void *Fbr0MemVa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
270 dma_addr_t Fbr0MemPa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
271 uint64_t Fbr0Realpa;
272 uint64_t Fbr0offset;
273 u32 local_Fbr0_full;
274 u32 Fbr0NumEntries;
275 u32 Fbr0BufferSize;
276 #endif
277 void *pFbr1RingVa;
278 dma_addr_t pFbr1RingPa;
279 void *Fbr1MemVa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
280 dma_addr_t Fbr1MemPa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
281 uint64_t Fbr1Realpa;
282 uint64_t Fbr1offset;
283 FBRLOOKUPTABLE *Fbr[2];
284 u32 local_Fbr1_full;
285 u32 Fbr1NumEntries;
286 u32 Fbr1BufferSize;
287
288 void *pPSRingVa;
289 dma_addr_t pPSRingPa;
290 u32 local_psr_full;
291 u32 PsrNumEntries;
292
293 void *pRxStatusVa;
294 dma_addr_t pRxStatusPa;
295
296 struct list_head RecvBufferPool;
297
298 /* RECV */
299 struct list_head RecvList;
300 u32 nReadyRecv;
301
302 u32 NumRfd;
303
304 bool UnfinishedReceives;
305
306 struct list_head RecvPacketPool;
307
308 /* lookaside lists */
309 struct kmem_cache *RecvLookaside;
310 } RX_RING_t, *PRX_RING_t;
311
312 /* Forward reference of RFD */
313 struct _MP_RFD;
314
315 /* Forward declaration of the private adapter structure */
316 struct et131x_adapter;
317
318 /* PROTOTYPES for Initialization */
319 int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter);
320 void et131x_rx_dma_memory_free(struct et131x_adapter *adapter);
321 int et131x_rfd_resources_alloc(struct et131x_adapter *adapter,
322 struct _MP_RFD *pMpRfd);
323 void et131x_rfd_resources_free(struct et131x_adapter *adapter,
324 struct _MP_RFD *pMpRfd);
325 int et131x_init_recv(struct et131x_adapter *adapter);
326
327 void ConfigRxDmaRegs(struct et131x_adapter *adapter);
328 void SetRxDmaTimer(struct et131x_adapter *adapter);
329 void et131x_rx_dma_disable(struct et131x_adapter *adapter);
330 void et131x_rx_dma_enable(struct et131x_adapter *adapter);
331
332 void et131x_reset_recv(struct et131x_adapter *adapter);
333
334 void et131x_handle_recv_interrupt(struct et131x_adapter *adapter);
335
336 #endif /* __ET1310_RX_H__ */
x86 "subsystem" repository