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[PATCH] cleanup asm/setup.h userspace visibility
[linux-2.6/x86.git] / arch / mips / sgi-ip22 / ip22-int.c
blobc44f8be0644f43bf58d38cb744d2509724dac2ee
1 /*
2 * ip22-int.c: Routines for generic manipulation of the INT[23] ASIC
3 * found on INDY and Indigo2 workstations.
4 *
5 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
6 * Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org)
7 * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu)
8 * - Indigo2 changes
9 * - Interrupt handling fixes
10 * Copyright (C) 2001, 2003 Ladislav Michl (ladis@linux-mips.org)
11 */
12 #include <linux/types.h>
13 #include <linux/init.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/signal.h>
16 #include <linux/sched.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19
20 #include <asm/mipsregs.h>
21 #include <asm/addrspace.h>
22
23 #include <asm/sgi/ioc.h>
24 #include <asm/sgi/hpc3.h>
25 #include <asm/sgi/ip22.h>
26
27 /* #define DEBUG_SGINT */
28
29 /* So far nothing hangs here */
30 #undef USE_LIO3_IRQ
31
32 struct sgint_regs *sgint;
33
34 static char lc0msk_to_irqnr[256];
35 static char lc1msk_to_irqnr[256];
36 static char lc2msk_to_irqnr[256];
37 static char lc3msk_to_irqnr[256];
38
39 extern int ip22_eisa_init(void);
40
41 static void enable_local0_irq(unsigned int irq)
42 {
43 /* don't allow mappable interrupt to be enabled from setup_irq,
44 * we have our own way to do so */
45 if (irq != SGI_MAP_0_IRQ)
46 sgint->imask0 |= (1 << (irq - SGINT_LOCAL0));
47 }
48
49 static void disable_local0_irq(unsigned int irq)
50 {
51 sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0));
52 }
53
54 static struct irq_chip ip22_local0_irq_type = {
55 .typename = "IP22 local 0",
56 .ack = disable_local0_irq,
57 .mask = disable_local0_irq,
58 .mask_ack = disable_local0_irq,
59 .unmask = enable_local0_irq,
60 };
61
62 static void enable_local1_irq(unsigned int irq)
63 {
64 /* don't allow mappable interrupt to be enabled from setup_irq,
65 * we have our own way to do so */
66 if (irq != SGI_MAP_1_IRQ)
67 sgint->imask1 |= (1 << (irq - SGINT_LOCAL1));
68 }
69
70 void disable_local1_irq(unsigned int irq)
71 {
72 sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1));
73 }
74
75 static struct irq_chip ip22_local1_irq_type = {
76 .typename = "IP22 local 1",
77 .ack = disable_local1_irq,
78 .mask = disable_local1_irq,
79 .mask_ack = disable_local1_irq,
80 .unmask = enable_local1_irq,
81 };
82
83 static void enable_local2_irq(unsigned int irq)
84 {
85 sgint->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
86 sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2));
87 }
88
89 void disable_local2_irq(unsigned int irq)
90 {
91 sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2));
92 if (!sgint->cmeimask0)
93 sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
94 }
95
96 static struct irq_chip ip22_local2_irq_type = {
97 .typename = "IP22 local 2",
98 .ack = disable_local2_irq,
99 .mask = disable_local2_irq,
100 .mask_ack = disable_local2_irq,
101 .unmask = enable_local2_irq,
102 };
103
104 static void enable_local3_irq(unsigned int irq)
105 {
106 sgint->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
107 sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3));
108 }
109
110 void disable_local3_irq(unsigned int irq)
111 {
112 sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3));
113 if (!sgint->cmeimask1)
114 sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
115 }
116
117 static struct irq_chip ip22_local3_irq_type = {
118 .typename = "IP22 local 3",
119 .ack = disable_local3_irq,
120 .mask = disable_local3_irq,
121 .mask_ack = disable_local3_irq,
122 .unmask = enable_local3_irq,
123 };
124
125 static void indy_local0_irqdispatch(void)
126 {
127 u8 mask = sgint->istat0 & sgint->imask0;
128 u8 mask2;
129 int irq;
130
131 if (mask & SGINT_ISTAT0_LIO2) {
132 mask2 = sgint->vmeistat & sgint->cmeimask0;
133 irq = lc2msk_to_irqnr[mask2];
134 } else
135 irq = lc0msk_to_irqnr[mask];
136
137 /* if irq == 0, then the interrupt has already been cleared */
138 if (irq)
139 do_IRQ(irq);
140 }
141
142 static void indy_local1_irqdispatch(void)
143 {
144 u8 mask = sgint->istat1 & sgint->imask1;
145 u8 mask2;
146 int irq;
147
148 if (mask & SGINT_ISTAT1_LIO3) {
149 mask2 = sgint->vmeistat & sgint->cmeimask1;
150 irq = lc3msk_to_irqnr[mask2];
151 } else
152 irq = lc1msk_to_irqnr[mask];
153
154 /* if irq == 0, then the interrupt has already been cleared */
155 if (irq)
156 do_IRQ(irq);
157 }
158
159 extern void ip22_be_interrupt(int irq);
160
161 static void indy_buserror_irq(void)
162 {
163 int irq = SGI_BUSERR_IRQ;
164
165 irq_enter();
166 kstat_this_cpu.irqs[irq]++;
167 ip22_be_interrupt(irq);
168 irq_exit();
169 }
170
171 static struct irqaction local0_cascade = {
172 .handler = no_action,
173 .flags = IRQF_DISABLED,
174 .name = "local0 cascade",
175 };
176
177 static struct irqaction local1_cascade = {
178 .handler = no_action,
179 .flags = IRQF_DISABLED,
180 .name = "local1 cascade",
181 };
182
183 static struct irqaction buserr = {
184 .handler = no_action,
185 .flags = IRQF_DISABLED,
186 .name = "Bus Error",
187 };
188
189 static struct irqaction map0_cascade = {
190 .handler = no_action,
191 .flags = IRQF_DISABLED,
192 .name = "mapable0 cascade",
193 };
194
195 #ifdef USE_LIO3_IRQ
196 static struct irqaction map1_cascade = {
197 .handler = no_action,
198 .flags = IRQF_DISABLED,
199 .name = "mapable1 cascade",
200 };
201 #define SGI_INTERRUPTS SGINT_END
202 #else
203 #define SGI_INTERRUPTS SGINT_LOCAL3
204 #endif
205
206 extern void indy_r4k_timer_interrupt(void);
207 extern void indy_8254timer_irq(void);
208
209 /*
210 * IRQs on the INDY look basically (barring software IRQs which we don't use
211 * at all) like:
212 *
213 * MIPS IRQ Source
214 * -------- ------
215 * 0 Software (ignored)
216 * 1 Software (ignored)
217 * 2 Local IRQ level zero
218 * 3 Local IRQ level one
219 * 4 8254 Timer zero
220 * 5 8254 Timer one
221 * 6 Bus Error
222 * 7 R4k timer (what we use)
223 *
224 * We handle the IRQ according to _our_ priority which is:
225 *
226 * Highest ---- R4k Timer
227 * Local IRQ zero
228 * Local IRQ one
229 * Bus Error
230 * 8254 Timer zero
231 * Lowest ---- 8254 Timer one
232 *
233 * then we just return, if multiple IRQs are pending then we will just take
234 * another exception, big deal.
235 */
236
237 asmlinkage void plat_irq_dispatch(void)
238 {
239 unsigned int pending = read_c0_cause();
240
241 /*
242 * First we check for r4k counter/timer IRQ.
243 */
244 if (pending & CAUSEF_IP7)
245 indy_r4k_timer_interrupt();
246 else if (pending & CAUSEF_IP2)
247 indy_local0_irqdispatch();
248 else if (pending & CAUSEF_IP3)
249 indy_local1_irqdispatch();
250 else if (pending & CAUSEF_IP6)
251 indy_buserror_irq();
252 else if (pending & (CAUSEF_IP4 | CAUSEF_IP5))
253 indy_8254timer_irq();
254 }
255
256 extern void mips_cpu_irq_init(unsigned int irq_base);
257
258 void __init arch_init_irq(void)
259 {
260 int i;
261
262 /* Init local mask --> irq tables. */
263 for (i = 0; i < 256; i++) {
264 if (i & 0x80) {
265 lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 7;
266 lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 7;
267 lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 7;
268 lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 7;
269 } else if (i & 0x40) {
270 lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 6;
271 lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 6;
272 lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 6;
273 lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 6;
274 } else if (i & 0x20) {
275 lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 5;
276 lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 5;
277 lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 5;
278 lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 5;
279 } else if (i & 0x10) {
280 lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 4;
281 lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 4;
282 lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 4;
283 lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 4;
284 } else if (i & 0x08) {
285 lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 3;
286 lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 3;
287 lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 3;
288 lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 3;
289 } else if (i & 0x04) {
290 lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 2;
291 lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 2;
292 lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 2;
293 lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 2;
294 } else if (i & 0x02) {
295 lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 1;
296 lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 1;
297 lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 1;
298 lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 1;
299 } else if (i & 0x01) {
300 lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 0;
301 lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 0;
302 lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 0;
303 lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 0;
304 } else {
305 lc0msk_to_irqnr[i] = 0;
306 lc1msk_to_irqnr[i] = 0;
307 lc2msk_to_irqnr[i] = 0;
308 lc3msk_to_irqnr[i] = 0;
309 }
310 }
311
312 /* Mask out all interrupts. */
313 sgint->imask0 = 0;
314 sgint->imask1 = 0;
315 sgint->cmeimask0 = 0;
316 sgint->cmeimask1 = 0;
317
318 /* init CPU irqs */
319 mips_cpu_irq_init(SGINT_CPU);
320
321 for (i = SGINT_LOCAL0; i < SGI_INTERRUPTS; i++) {
322 struct irq_chip *handler;
323
324 if (i < SGINT_LOCAL1)
325 handler = &ip22_local0_irq_type;
326 else if (i < SGINT_LOCAL2)
327 handler = &ip22_local1_irq_type;
328 else if (i < SGINT_LOCAL3)
329 handler = &ip22_local2_irq_type;
330 else
331 handler = &ip22_local3_irq_type;
332
333 set_irq_chip_and_handler(i, handler, handle_level_irq);
334 }
335
336 /* vector handler. this register the IRQ as non-sharable */
337 setup_irq(SGI_LOCAL_0_IRQ, &local0_cascade);
338 setup_irq(SGI_LOCAL_1_IRQ, &local1_cascade);
339 setup_irq(SGI_BUSERR_IRQ, &buserr);
340
341 /* cascade in cascade. i love Indy ;-) */
342 setup_irq(SGI_MAP_0_IRQ, &map0_cascade);
343 #ifdef USE_LIO3_IRQ
344 setup_irq(SGI_MAP_1_IRQ, &map1_cascade);
345 #endif
346
347 #ifdef CONFIG_EISA
348 if (ip22_is_fullhouse()) /* Only Indigo-2 has EISA stuff */
349 ip22_eisa_init ();
350 #endif
351 }
x86 "subsystem" repository