2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
16 config RWSEM_GENERIC_SPINLOCK
20 config RWSEM_XCHGADD_ALGORITHM
32 config SEMAPHORE_SLEEPERS
36 config GENERIC_FIND_NEXT_BIT
40 config GENERIC_HWEIGHT
44 config GENERIC_HARDIRQS
48 config GENERIC_IRQ_PROBE
60 config FORCE_MAX_ZONEORDER
64 config GENERIC_CALIBRATE_DELAY
68 config IRQCHIP_DEMUX_GPIO
70 depends on (BF52x || BF53x || BF561 || BF54x)
74 source "kernel/Kconfig.preempt"
76 menu "Blackfin Processor Options"
78 comment "Processor and Board Settings"
87 BF522 Processor Support.
92 BF525 Processor Support.
97 BF527 Processor Support.
102 BF531 Processor Support.
107 BF532 Processor Support.
112 BF533 Processor Support.
117 BF534 Processor Support.
122 BF536 Processor Support.
127 BF537 Processor Support.
132 BF542 Processor Support.
137 BF544 Processor Support.
142 BF547 Processor Support.
147 BF548 Processor Support.
152 BF549 Processor Support.
157 Not Supported Yet - Work in progress - BF561 Processor Support.
163 default BF_REV_0_1 if BF527
164 default BF_REV_0_2 if BF537
165 default BF_REV_0_3 if BF533
166 default BF_REV_0_0 if BF549
170 depends on (BF52x || BF54x)
174 depends on (BF52x || BF54x)
178 depends on (BF537 || BF536 || BF534)
182 depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
186 depends on (BF561 || BF533 || BF532 || BF531)
190 depends on (BF561 || BF533 || BF532 || BF531)
202 depends on (BF522 || BF525 || BF527)
207 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
212 depends on (BF542 || BF544 || BF547 || BF548 || BF549)
215 config BFIN_DUAL_CORE
220 config BFIN_SINGLE_CORE
222 depends on !BFIN_DUAL_CORE
225 config MEM_GENERIC_BOARD
227 depends on GENERIC_BOARD
230 config MEM_MT48LC64M4A2FB_7E
232 depends on (BFIN533_STAMP)
235 config MEM_MT48LC16M16A2TG_75
237 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
238 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
242 config MEM_MT48LC32M8A2_75
244 depends on (BFIN537_STAMP || PNAV10)
247 config MEM_MT48LC8M32B2B5_7
249 depends on (BFIN561_BLUETECHNIX_CM)
252 config MEM_MT48LC32M16A2TG_75
254 depends on (BFIN527_EZKIT)
257 config BFIN_SHARED_FLASH_ENET
259 depends on (BFIN533_STAMP)
262 source "arch/blackfin/mach-bf527/Kconfig"
263 source "arch/blackfin/mach-bf533/Kconfig"
264 source "arch/blackfin/mach-bf561/Kconfig"
265 source "arch/blackfin/mach-bf537/Kconfig"
266 source "arch/blackfin/mach-bf548/Kconfig"
268 menu "Board customizations"
271 bool "Default bootloader kernel arguments"
274 string "Initial kernel command string"
275 depends on CMDLINE_BOOL
276 default "console=ttyBF0,57600"
278 If you don't have a boot loader capable of passing a command line string
279 to the kernel, you may specify one here. As a minimum, you should specify
280 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
282 comment "Clock/PLL Setup"
285 int "Crystal Frequency in Hz"
286 default "11059200" if BFIN533_STAMP
287 default "27000000" if BFIN533_EZKIT
288 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
289 default "30000000" if BFIN561_EZKIT
290 default "24576000" if PNAV10
292 The frequency of CLKIN crystal oscillator on the board in Hz.
294 config BFIN_KERNEL_CLOCK
295 bool "Re-program Clocks while Kernel boots?"
298 This option decides if kernel clocks are re-programed from the
299 bootloader settings. If the clocks are not set, the SDRAM settings
300 are also not changed, and the Bootloader does 100% of the hardware
305 depends on BFIN_KERNEL_CLOCK
310 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
313 If this is set the clock will be divided by 2, before it goes to the PLL.
317 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
319 default "22" if BFIN533_EZKIT
320 default "45" if BFIN533_STAMP
321 default "20" if (BFIN537_STAMP || BFIN527_EZKIT)
322 default "22" if BFIN533_BLUETECHNIX_CM
323 default "20" if BFIN537_BLUETECHNIX_CM
324 default "20" if BFIN561_BLUETECHNIX_CM
325 default "20" if BFIN561_EZKIT
326 default "16" if H8606_HVSISTEMAS
328 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
329 PLL Frequency = (Crystal Frequency) * (this setting)
332 prompt "Core Clock Divider"
333 depends on BFIN_KERNEL_CLOCK
336 This sets the frequency of the core. It can be 1, 2, 4 or 8
337 Core Frequency = (PLL frequency) / (this setting)
353 int "System Clock Divider"
354 depends on BFIN_KERNEL_CLOCK
356 default 5 if BFIN533_EZKIT
357 default 5 if BFIN533_STAMP
358 default 4 if (BFIN537_STAMP || BFIN527_EZKIT)
359 default 5 if BFIN533_BLUETECHNIX_CM
360 default 4 if BFIN537_BLUETECHNIX_CM
361 default 4 if BFIN561_BLUETECHNIX_CM
362 default 5 if BFIN561_EZKIT
363 default 3 if H8606_HVSISTEMAS
365 This sets the frequency of the system clock (including SDRAM or DDR).
366 This can be between 1 and 15
367 System Clock = (PLL frequency) / (this setting)
370 # Max & Min Speeds for various Chips
374 default 600000000 if BF522
375 default 600000000 if BF525
376 default 600000000 if BF527
377 default 400000000 if BF531
378 default 400000000 if BF532
379 default 750000000 if BF533
380 default 500000000 if BF534
381 default 400000000 if BF536
382 default 600000000 if BF537
383 default 533000000 if BF538
384 default 533000000 if BF539
385 default 600000000 if BF542
386 default 533000000 if BF544
387 default 533000000 if BF549
388 default 600000000 if BF561
402 comment "Kernel Timer/Scheduler"
404 source kernel/Kconfig.hz
406 comment "Memory Setup"
409 int "SDRAM Memory Size in MBytes"
410 default 32 if BFIN533_EZKIT
411 default 64 if BFIN527_EZKIT
412 default 64 if BFIN537_STAMP
413 default 64 if BFIN561_EZKIT
414 default 128 if BFIN533_STAMP
416 default 32 if H8606_HVSISTEMAS
419 int "SDRAM Memory Address Width"
420 default 9 if BFIN533_EZKIT
421 default 9 if BFIN561_EZKIT
422 default 9 if H8606_HVSISTEMAS
423 default 10 if BFIN527_EZKIT
424 default 10 if BFIN537_STAMP
425 default 11 if BFIN533_STAMP
428 config ENET_FLASH_PIN
429 int "PF port/pin used for flash and ethernet sharing"
430 depends on (BFIN533_STAMP)
433 PF port/pin used for flash and ethernet sharing to allow other PF
434 pins to be used on other platforms without having to touch common
436 For example: PF0 --> 0,PF1 --> 1,PF2 --> 2, etc.
439 hex "Kernel load address for booting"
441 range 0x1000 0x20000000
443 This option allows you to set the load address of the kernel.
444 This can be useful if you are on a board which has a small amount
445 of memory or you wish to reserve some memory at the beginning of
448 Note that you need to keep this value above 4k (0x1000) as this
449 memory region is used to capture NULL pointer references as well
450 as some core kernel functions.
452 comment "LED Status Indicators"
453 depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM)
455 config BFIN_ALIVE_LED
456 bool "Enable Board Alive"
457 depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM)
460 Blink the LEDs you select when the kernel is running. Helps detect
463 config BFIN_ALIVE_LED_NUM
465 depends on BFIN_ALIVE_LED
466 range 1 3 if BFIN533_STAMP
467 default "3" if BFIN533_STAMP
469 Select the LED (marked on the board) for you to blink.
472 bool "Enable System Load/Idle LED"
473 depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM)
476 Blinks the LED you select when to determine kernel load.
478 config BFIN_IDLE_LED_NUM
480 depends on BFIN_IDLE_LED
481 range 1 3 if BFIN533_STAMP
482 default "2" if BFIN533_STAMP
484 Select the LED (marked on the board) for you to blink.
487 prompt "Blackfin Exception Scratch Register"
488 default BFIN_SCRATCH_REG_RETN
490 Select the resource to reserve for the Exception handler:
491 - RETN: Non-Maskable Interrupt (NMI)
492 - RETE: Exception Return (JTAG/ICE)
493 - CYCLES: Performance counter
495 If you are unsure, please select "RETN".
497 config BFIN_SCRATCH_REG_RETN
500 Use the RETN register in the Blackfin exception handler
501 as a stack scratch register. This means you cannot
502 safely use NMI on the Blackfin while running Linux, but
503 you can debug the system with a JTAG ICE and use the
504 CYCLES performance registers.
506 If you are unsure, please select "RETN".
508 config BFIN_SCRATCH_REG_RETE
511 Use the RETE register in the Blackfin exception handler
512 as a stack scratch register. This means you cannot
513 safely use a JTAG ICE while debugging a Blackfin board,
514 but you can safely use the CYCLES performance registers
517 If you are unsure, please select "RETN".
519 config BFIN_SCRATCH_REG_CYCLES
522 Use the CYCLES register in the Blackfin exception handler
523 as a stack scratch register. This means you cannot
524 safely use the CYCLES performance registers on a Blackfin
525 board at anytime, but you can debug the system with a JTAG
528 If you are unsure, please select "RETN".
533 # Sorry - but you need to put the hex address here -
537 config BFIN_ALIVE_LED_PORT
539 default 0xFFC00700 if (BFIN533_STAMP)
541 # Peripheral Flag Direction Register
542 config BFIN_ALIVE_LED_DPORT
544 default 0xFFC00730 if (BFIN533_STAMP)
546 config BFIN_ALIVE_LED_PIN
548 default 0x04 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 1)
549 default 0x08 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 2)
550 default 0x10 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 3)
552 config BFIN_IDLE_LED_PORT
554 default 0xFFC00700 if (BFIN533_STAMP)
556 # Peripheral Flag Direction Register
557 config BFIN_IDLE_LED_DPORT
559 default 0xFFC00730 if (BFIN533_STAMP)
561 config BFIN_IDLE_LED_PIN
563 default 0x04 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 1)
564 default 0x08 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 2)
565 default 0x10 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 3)
570 menu "Blackfin Kernel Optimizations"
572 comment "Memory Optimizations"
575 bool "Locate interrupt entry code in L1 Memory"
578 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
579 into L1 instruction memory. (less latency)
581 config EXCPT_IRQ_SYSC_L1
582 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
585 If enabled, the entire ASM lowlevel exception and interrupt entry code
586 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
590 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
593 If enabled, the frequently called do_irq dispatcher function is linked
594 into L1 instruction memory. (less latency)
596 config CORE_TIMER_IRQ_L1
597 bool "Locate frequently called timer_interrupt() function in L1 Memory"
600 If enabled, the frequently called timer_interrupt() function is linked
601 into L1 instruction memory. (less latency)
604 bool "Locate frequently idle function in L1 Memory"
607 If enabled, the frequently called idle function is linked
608 into L1 instruction memory. (less latency)
611 bool "Locate kernel schedule function in L1 Memory"
614 If enabled, the frequently called kernel schedule is linked
615 into L1 instruction memory. (less latency)
617 config ARITHMETIC_OPS_L1
618 bool "Locate kernel owned arithmetic functions in L1 Memory"
621 If enabled, arithmetic functions are linked
622 into L1 instruction memory. (less latency)
625 bool "Locate access_ok function in L1 Memory"
628 If enabled, the access_ok function is linked
629 into L1 instruction memory. (less latency)
632 bool "Locate memset function in L1 Memory"
635 If enabled, the memset function is linked
636 into L1 instruction memory. (less latency)
639 bool "Locate memcpy function in L1 Memory"
642 If enabled, the memcpy function is linked
643 into L1 instruction memory. (less latency)
645 config SYS_BFIN_SPINLOCK_L1
646 bool "Locate sys_bfin_spinlock function in L1 Memory"
649 If enabled, sys_bfin_spinlock function is linked
650 into L1 instruction memory. (less latency)
652 config IP_CHECKSUM_L1
653 bool "Locate IP Checksum function in L1 Memory"
656 If enabled, the IP Checksum function is linked
657 into L1 instruction memory. (less latency)
659 config CACHELINE_ALIGNED_L1
660 bool "Locate cacheline_aligned data to L1 Data Memory"
665 If enabled, cacheline_anligned data is linked
666 into L1 data memory. (less latency)
668 config SYSCALL_TAB_L1
669 bool "Locate Syscall Table L1 Data Memory"
673 If enabled, the Syscall LUT is linked
674 into L1 data memory. (less latency)
676 config CPLB_SWITCH_TAB_L1
677 bool "Locate CPLB Switch Tables L1 Data Memory"
681 If enabled, the CPLB Switch Tables are linked
682 into L1 data memory. (less latency)
688 prompt "Kernel executes from"
690 Choose the memory type that the kernel will be running in.
695 The kernel will be resident in RAM when running.
700 The kernel will be resident in FLASH/ROM when running.
707 bool "Allow allocating large blocks (> 1MB) of memory"
709 Allow the slab memory allocator to keep chains for very large
710 memory sizes - upto 32MB. You may need this if your system has
711 a lot of RAM, and you need to able to allocate very large
712 contiguous chunks. If unsure, say N.
715 tristate "Enable Blackfin General Purpose Timers API"
718 Enable support for the General Purpose Timers API. If you
721 To compile this driver as a module, choose M here: the module
722 will be called gptimers.ko.
725 bool "Enable DMA Support"
726 depends on (BF52x || BF53x || BF561 || BF54x)
729 DMA driver for BF5xx.
732 prompt "Uncached SDRAM region"
733 default DMA_UNCACHED_1M
734 depends on BFIN_DMA_5XX
735 config DMA_UNCACHED_2M
736 bool "Enable 2M DMA region"
737 config DMA_UNCACHED_1M
738 bool "Enable 1M DMA region"
739 config DMA_UNCACHED_NONE
740 bool "Disable DMA region"
744 comment "Cache Support"
749 config BFIN_DCACHE_BANKA
750 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
751 depends on BFIN_DCACHE && !BF531
753 config BFIN_ICACHE_LOCK
754 bool "Enable Instruction Cache Locking"
758 depends on BFIN_DCACHE
764 Cached data will be written back to SDRAM only when needed.
765 This can give a nice increase in performance, but beware of
766 broken drivers that do not properly invalidate/flush their
769 Write Through Policy:
770 Cached data will always be written back to SDRAM when the
771 cache is updated. This is a completely safe setting, but
772 performance is worse than Write Back.
774 If you are unsure of the options and you want to be safe,
775 then go with Write Through.
781 Cached data will be written back to SDRAM only when needed.
782 This can give a nice increase in performance, but beware of
783 broken drivers that do not properly invalidate/flush their
786 Write Through Policy:
787 Cached data will always be written back to SDRAM when the
788 cache is updated. This is a completely safe setting, but
789 performance is worse than Write Back.
791 If you are unsure of the options and you want to be safe,
792 then go with Write Through.
797 int "Set the max L1 SRAM pieces"
800 Set the max memory pieces for the L1 SRAM allocation algorithm.
801 Min value is 16. Max value is 1024.
803 comment "Asynchonous Memory Configuration"
805 menu "EBIU_AMGCTL Global Control"
811 bool "DMA has priority over core for ext. accesses"
817 bool "Bank 0 16 bit packing enable"
822 bool "Bank 1 16 bit packing enable"
827 bool "Bank 2 16 bit packing enable"
832 bool "Bank 3 16 bit packing enable"
836 prompt"Enable Asynchonous Memory Banks"
840 bool "Disable All Banks"
846 bool "Enable Bank 0 & 1"
848 config C_AMBEN_B0_B1_B2
849 bool "Enable Bank 0 & 1 & 2"
852 bool "Enable All Banks"
856 menu "EBIU_AMBCTL Control"
876 #############################################################################
877 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
884 source "drivers/pci/Kconfig"
887 bool "Support for hot-pluggable device"
889 Say Y here if you want to plug devices into your computer while
890 the system is running, and be able to use them quickly. In many
891 cases, the devices can likewise be unplugged at any time too.
893 One well known example of this is PCMCIA- or PC-cards, credit-card
894 size devices such as network cards, modems or hard drives which are
895 plugged into slots found on all modern laptop computers. Another
896 example, used on modern desktops as well as laptops, is USB.
898 Enable HOTPLUG and KMOD, and build a modular kernel. Get agent
899 software (at <http://linux-hotplug.sourceforge.net/>) and install it.
900 Then your kernel will automatically call out to a user mode "policy
901 agent" (/sbin/hotplug) to load modules and set up software needed
902 to use devices as you hotplug them.
904 source "drivers/pcmcia/Kconfig"
906 source "drivers/pci/hotplug/Kconfig"
910 menu "Executable file formats"
912 source "fs/Kconfig.binfmt"
916 menu "Power management options"
917 source "kernel/power/Kconfig"
920 prompt "Select PM Wakeup Event Source"
921 default PM_WAKEUP_GPIO_BY_SIC_IWR
924 If you have a GPIO already configured as input with the corresponding PORTx_MASK
925 bit set - "Specify Wakeup Event by SIC_IWR value"
927 config PM_WAKEUP_GPIO_BY_SIC_IWR
928 bool "Specify Wakeup Event by SIC_IWR value"
929 config PM_WAKEUP_BY_GPIO
930 bool "Cause Wakeup Event by GPIO"
931 config PM_WAKEUP_GPIO_API
932 bool "Configure Wakeup Event by PM GPIO API"
936 config PM_WAKEUP_SIC_IWR
937 hex "Wakeup Events (SIC_IWR)"
938 depends on PM_WAKEUP_GPIO_BY_SIC_IWR
939 default 0x80000000 if (BF537 || BF536 || BF534)
940 default 0x100000 if (BF533 || BF532 || BF531)
942 config PM_WAKEUP_GPIO_NUMBER
943 int "Wakeup GPIO number"
945 depends on PM_WAKEUP_BY_GPIO
946 default 2 if BFIN537_STAMP
949 prompt "GPIO Polarity"
950 depends on PM_WAKEUP_BY_GPIO
951 default PM_WAKEUP_GPIO_POLAR_H
952 config PM_WAKEUP_GPIO_POLAR_H
954 config PM_WAKEUP_GPIO_POLAR_L
956 config PM_WAKEUP_GPIO_POLAR_EDGE_F
958 config PM_WAKEUP_GPIO_POLAR_EDGE_R
960 config PM_WAKEUP_GPIO_POLAR_EDGE_B
966 if (BF537 || BF533 || BF54x)
968 menu "CPU Frequency scaling"
970 source "drivers/cpufreq/Kconfig"
976 If you want to enable this option, you should select the
977 DPMC driver from Character Devices.
984 source "drivers/Kconfig"
988 source "kernel/Kconfig.instrumentation"
990 source "arch/blackfin/Kconfig.debug"
992 source "security/Kconfig"
994 source "crypto/Kconfig"