2 * TI DaVinci EVM board support
4 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/platform_device.h>
15 #include <linux/gpio.h>
16 #include <linux/i2c.h>
17 #include <linux/i2c/pcf857x.h>
18 #include <linux/i2c/at24.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/mtd/physmap.h>
23 #include <linux/phy.h>
24 #include <linux/clk.h>
25 #include <linux/videodev2.h>
27 #include <media/tvp514x.h>
29 #include <asm/mach-types.h>
30 #include <asm/mach/arch.h>
32 #include <mach/dm644x.h>
33 #include <mach/common.h>
35 #include <mach/serial.h>
37 #include <mach/nand.h>
41 #define DM644X_EVM_PHY_MASK (0x2)
42 #define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
44 #define LXT971_PHY_ID (0x001378e2)
45 #define LXT971_PHY_MASK (0xfffffff0)
47 static struct mtd_partition davinci_evm_norflash_partitions
[] = {
48 /* bootloader (UBL, U-Boot, etc) in first 5 sectors */
53 .mask_flags
= MTD_WRITEABLE
, /* force read-only */
55 /* bootloader params in the next 1 sectors */
58 .offset
= MTDPART_OFS_APPEND
,
65 .offset
= MTDPART_OFS_APPEND
,
72 .offset
= MTDPART_OFS_APPEND
,
73 .size
= MTDPART_SIZ_FULL
,
78 static struct physmap_flash_data davinci_evm_norflash_data
= {
80 .parts
= davinci_evm_norflash_partitions
,
81 .nr_parts
= ARRAY_SIZE(davinci_evm_norflash_partitions
),
84 /* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF
85 * limits addresses to 16M, so using addresses past 16M will wrap */
86 static struct resource davinci_evm_norflash_resource
= {
87 .start
= DM644X_ASYNC_EMIF_DATA_CE0_BASE
,
88 .end
= DM644X_ASYNC_EMIF_DATA_CE0_BASE
+ SZ_16M
- 1,
89 .flags
= IORESOURCE_MEM
,
92 static struct platform_device davinci_evm_norflash_device
= {
93 .name
= "physmap-flash",
96 .platform_data
= &davinci_evm_norflash_data
,
99 .resource
= &davinci_evm_norflash_resource
,
102 /* DM644x EVM includes a 64 MByte small-page NAND flash (16K blocks).
103 * It may used instead of the (default) NOR chip to boot, using TI's
104 * tools to install the secondary boot loader (UBL) and U-Boot.
106 static struct mtd_partition davinci_evm_nandflash_partition
[] = {
107 /* Bootloader layout depends on whose u-boot is installed, but we
108 * can hide all the details.
109 * - block 0 for u-boot environment ... in mainline u-boot
110 * - block 1 for UBL (plus up to four backup copies in blocks 2..5)
111 * - blocks 6...? for u-boot
112 * - blocks 16..23 for u-boot environment ... in TI's u-boot
115 .name
= "bootloader",
117 .size
= SZ_256K
+ SZ_128K
,
118 .mask_flags
= MTD_WRITEABLE
, /* force read-only */
123 .offset
= MTDPART_OFS_APPEND
,
127 /* File system (older GIT kernels started this on the 5MB mark) */
129 .name
= "filesystem",
130 .offset
= MTDPART_OFS_APPEND
,
131 .size
= MTDPART_SIZ_FULL
,
134 /* A few blocks at end hold a flash BBT ... created by TI's CCS
135 * using flashwriter_nand.out, but ignored by TI's versions of
136 * Linux and u-boot. We boot faster by using them.
140 static struct davinci_nand_pdata davinci_evm_nandflash_data
= {
141 .parts
= davinci_evm_nandflash_partition
,
142 .nr_parts
= ARRAY_SIZE(davinci_evm_nandflash_partition
),
143 .ecc_mode
= NAND_ECC_HW
,
144 .options
= NAND_USE_FLASH_BBT
,
147 static struct resource davinci_evm_nandflash_resource
[] = {
149 .start
= DM644X_ASYNC_EMIF_DATA_CE0_BASE
,
150 .end
= DM644X_ASYNC_EMIF_DATA_CE0_BASE
+ SZ_16M
- 1,
151 .flags
= IORESOURCE_MEM
,
153 .start
= DM644X_ASYNC_EMIF_CONTROL_BASE
,
154 .end
= DM644X_ASYNC_EMIF_CONTROL_BASE
+ SZ_4K
- 1,
155 .flags
= IORESOURCE_MEM
,
159 static struct platform_device davinci_evm_nandflash_device
= {
160 .name
= "davinci_nand",
163 .platform_data
= &davinci_evm_nandflash_data
,
165 .num_resources
= ARRAY_SIZE(davinci_evm_nandflash_resource
),
166 .resource
= davinci_evm_nandflash_resource
,
169 static u64 davinci_fb_dma_mask
= DMA_BIT_MASK(32);
171 static struct platform_device davinci_fb_device
= {
175 .dma_mask
= &davinci_fb_dma_mask
,
176 .coherent_dma_mask
= DMA_BIT_MASK(32),
181 static struct tvp514x_platform_data tvp5146_pdata
= {
187 #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
188 /* Inputs available at the TVP5146 */
189 static struct v4l2_input tvp5146_inputs
[] = {
193 .type
= V4L2_INPUT_TYPE_CAMERA
,
194 .std
= TVP514X_STD_ALL
,
199 .type
= V4L2_INPUT_TYPE_CAMERA
,
200 .std
= TVP514X_STD_ALL
,
205 * this is the route info for connecting each input to decoder
206 * ouput that goes to vpfe. There is a one to one correspondence
207 * with tvp5146_inputs
209 static struct vpfe_route tvp5146_routes
[] = {
211 .input
= INPUT_CVBS_VI2B
,
212 .output
= OUTPUT_10BIT_422_EMBEDDED_SYNC
,
215 .input
= INPUT_SVIDEO_VI2C_VI1C
,
216 .output
= OUTPUT_10BIT_422_EMBEDDED_SYNC
,
220 static struct vpfe_subdev_info vpfe_sub_devs
[] = {
224 .num_inputs
= ARRAY_SIZE(tvp5146_inputs
),
225 .inputs
= tvp5146_inputs
,
226 .routes
= tvp5146_routes
,
229 .if_type
= VPFE_BT656
,
230 .hdpol
= VPFE_PINPOL_POSITIVE
,
231 .vdpol
= VPFE_PINPOL_POSITIVE
,
234 I2C_BOARD_INFO("tvp5146", 0x5d),
235 .platform_data
= &tvp5146_pdata
,
240 static struct vpfe_config vpfe_cfg
= {
241 .num_subdevs
= ARRAY_SIZE(vpfe_sub_devs
),
243 .sub_devs
= vpfe_sub_devs
,
244 .card_name
= "DM6446 EVM",
245 .ccdc
= "DM6446 CCDC",
248 static struct platform_device rtc_dev
= {
249 .name
= "rtc_davinci_evm",
253 static struct snd_platform_data dm644x_evm_snd_data
;
255 /*----------------------------------------------------------------------*/
261 #define PCF_Uxx_BASE(x) (DAVINCI_N_GPIO + ((x) * 8))
266 static struct gpio_led evm_leds
[] = {
267 { .name
= "DS8", .active_low
= 1,
268 .default_trigger
= "heartbeat", },
269 { .name
= "DS7", .active_low
= 1, },
270 { .name
= "DS6", .active_low
= 1, },
271 { .name
= "DS5", .active_low
= 1, },
272 { .name
= "DS4", .active_low
= 1, },
273 { .name
= "DS3", .active_low
= 1, },
274 { .name
= "DS2", .active_low
= 1,
275 .default_trigger
= "mmc0", },
276 { .name
= "DS1", .active_low
= 1,
277 .default_trigger
= "ide-disk", },
280 static const struct gpio_led_platform_data evm_led_data
= {
281 .num_leds
= ARRAY_SIZE(evm_leds
),
285 static struct platform_device
*evm_led_dev
;
288 evm_led_setup(struct i2c_client
*client
, int gpio
, unsigned ngpio
, void *c
)
290 struct gpio_led
*leds
= evm_leds
;
298 /* what an extremely annoying way to be forced to handle
299 * device unregistration ...
301 evm_led_dev
= platform_device_alloc("leds-gpio", 0);
302 platform_device_add_data(evm_led_dev
,
303 &evm_led_data
, sizeof evm_led_data
);
305 evm_led_dev
->dev
.parent
= &client
->dev
;
306 status
= platform_device_add(evm_led_dev
);
308 platform_device_put(evm_led_dev
);
315 evm_led_teardown(struct i2c_client
*client
, int gpio
, unsigned ngpio
, void *c
)
318 platform_device_unregister(evm_led_dev
);
324 static struct pcf857x_platform_data pcf_data_u2
= {
325 .gpio_base
= PCF_Uxx_BASE(0),
326 .setup
= evm_led_setup
,
327 .teardown
= evm_led_teardown
,
331 /* U18 - A/V clock generator and user switch */
336 sw_show(struct device
*d
, struct device_attribute
*a
, char *buf
)
338 char *s
= gpio_get_value_cansleep(sw_gpio
) ? "on\n" : "off\n";
344 static DEVICE_ATTR(user_sw
, S_IRUGO
, sw_show
, NULL
);
347 evm_u18_setup(struct i2c_client
*client
, int gpio
, unsigned ngpio
, void *c
)
351 /* export dip switch option */
353 status
= gpio_request(sw_gpio
, "user_sw");
355 status
= gpio_direction_input(sw_gpio
);
357 status
= device_create_file(&client
->dev
, &dev_attr_user_sw
);
363 /* audio PLL: 48 kHz (vs 44.1 or 32), single rate (vs double) */
364 gpio_request(gpio
+ 3, "pll_fs2");
365 gpio_direction_output(gpio
+ 3, 0);
367 gpio_request(gpio
+ 2, "pll_fs1");
368 gpio_direction_output(gpio
+ 2, 0);
370 gpio_request(gpio
+ 1, "pll_sr");
371 gpio_direction_output(gpio
+ 1, 0);
377 evm_u18_teardown(struct i2c_client
*client
, int gpio
, unsigned ngpio
, void *c
)
384 device_remove_file(&client
->dev
, &dev_attr_user_sw
);
390 static struct pcf857x_platform_data pcf_data_u18
= {
391 .gpio_base
= PCF_Uxx_BASE(1),
392 .n_latch
= (1 << 3) | (1 << 2) | (1 << 1),
393 .setup
= evm_u18_setup
,
394 .teardown
= evm_u18_teardown
,
398 /* U35 - various I/O signals used to manage USB, CF, ATA, etc */
401 evm_u35_setup(struct i2c_client
*client
, int gpio
, unsigned ngpio
, void *c
)
403 /* p0 = nDRV_VBUS (initial: don't supply it) */
404 gpio_request(gpio
+ 0, "nDRV_VBUS");
405 gpio_direction_output(gpio
+ 0, 1);
408 gpio_request(gpio
+ 1, "VDDIMX_EN");
409 gpio_direction_output(gpio
+ 1, 1);
412 gpio_request(gpio
+ 2, "VLYNQ_EN");
413 gpio_direction_output(gpio
+ 2, 1);
415 /* p3 = n3V3_CF_RESET (initial: stay in reset) */
416 gpio_request(gpio
+ 3, "nCF_RESET");
417 gpio_direction_output(gpio
+ 3, 0);
421 /* p5 = 1V8_WLAN_RESET (initial: stay in reset) */
422 gpio_request(gpio
+ 5, "WLAN_RESET");
423 gpio_direction_output(gpio
+ 5, 1);
425 /* p6 = nATA_SEL (initial: select) */
426 gpio_request(gpio
+ 6, "nATA_SEL");
427 gpio_direction_output(gpio
+ 6, 0);
429 /* p7 = nCF_SEL (initial: deselect) */
430 gpio_request(gpio
+ 7, "nCF_SEL");
431 gpio_direction_output(gpio
+ 7, 1);
433 /* irlml6401 switches over 1A, in under 8 msec;
434 * now it can be managed by nDRV_VBUS ...
436 davinci_setup_usb(1000, 8);
442 evm_u35_teardown(struct i2c_client
*client
, int gpio
, unsigned ngpio
, void *c
)
454 static struct pcf857x_platform_data pcf_data_u35
= {
455 .gpio_base
= PCF_Uxx_BASE(2),
456 .setup
= evm_u35_setup
,
457 .teardown
= evm_u35_teardown
,
460 /*----------------------------------------------------------------------*/
462 /* Most of this EEPROM is unused, but U-Boot uses some data:
463 * - 0x7f00, 6 bytes Ethernet Address
464 * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL)
465 * - ... newer boards may have more
468 static struct at24_platform_data eeprom_info
= {
469 .byte_len
= (256*1024) / 8,
471 .flags
= AT24_FLAG_ADDR16
,
472 .setup
= davinci_get_mac_addr
,
473 .context
= (void *)0x7f00,
477 * MSP430 supports RTC, card detection, input from IR remote, and
478 * a bit more. It triggers interrupts on GPIO(7) from pressing
479 * buttons on the IR remote, and for card detect switches.
481 static struct i2c_client
*dm6446evm_msp
;
483 static int dm6446evm_msp_probe(struct i2c_client
*client
,
484 const struct i2c_device_id
*id
)
486 dm6446evm_msp
= client
;
490 static int dm6446evm_msp_remove(struct i2c_client
*client
)
492 dm6446evm_msp
= NULL
;
496 static const struct i2c_device_id dm6446evm_msp_ids
[] = {
497 { "dm6446evm_msp", 0, },
498 { /* end of list */ },
501 static struct i2c_driver dm6446evm_msp_driver
= {
502 .driver
.name
= "dm6446evm_msp",
503 .id_table
= dm6446evm_msp_ids
,
504 .probe
= dm6446evm_msp_probe
,
505 .remove
= dm6446evm_msp_remove
,
508 static int dm6444evm_msp430_get_pins(void)
510 static const char txbuf
[2] = { 2, 4, };
512 struct i2c_msg msg
[2] = {
514 .addr
= dm6446evm_msp
->addr
,
517 .buf
= (void __force
*)txbuf
,
520 .addr
= dm6446evm_msp
->addr
,
531 /* Command 4 == get input state, returns port 2 and port3 data
532 * S Addr W [A] len=2 [A] cmd=4 [A]
533 * RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P
535 status
= i2c_transfer(dm6446evm_msp
->adapter
, msg
, 2);
539 dev_dbg(&dm6446evm_msp
->dev
,
540 "PINS: %02x %02x %02x %02x\n",
541 buf
[0], buf
[1], buf
[2], buf
[3]);
543 return (buf
[3] << 8) | buf
[2];
546 static int dm6444evm_mmc_get_cd(int module
)
548 int status
= dm6444evm_msp430_get_pins();
550 return (status
< 0) ? status
: !(status
& BIT(1));
553 static int dm6444evm_mmc_get_ro(int module
)
555 int status
= dm6444evm_msp430_get_pins();
557 return (status
< 0) ? status
: status
& BIT(6 + 8);
560 static struct davinci_mmc_config dm6446evm_mmc_config
= {
561 .get_cd
= dm6444evm_mmc_get_cd
,
562 .get_ro
= dm6444evm_mmc_get_ro
,
564 .version
= MMC_CTLR_VERSION_1
567 static struct i2c_board_info __initdata i2c_info
[] = {
569 I2C_BOARD_INFO("dm6446evm_msp", 0x23),
572 I2C_BOARD_INFO("pcf8574", 0x38),
573 .platform_data
= &pcf_data_u2
,
576 I2C_BOARD_INFO("pcf8574", 0x39),
577 .platform_data
= &pcf_data_u18
,
580 I2C_BOARD_INFO("pcf8574", 0x3a),
581 .platform_data
= &pcf_data_u35
,
584 I2C_BOARD_INFO("24c256", 0x50),
585 .platform_data
= &eeprom_info
,
588 I2C_BOARD_INFO("tlv320aic33", 0x1b),
592 /* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz),
593 * which requires 100 usec of idle bus after i2c writes sent to it.
595 static struct davinci_i2c_platform_data i2c_pdata
= {
596 .bus_freq
= 20 /* kHz */,
597 .bus_delay
= 100 /* usec */,
602 static void __init
evm_init_i2c(void)
604 davinci_init_i2c(&i2c_pdata
);
605 i2c_add_driver(&dm6446evm_msp_driver
);
606 i2c_register_board_info(1, i2c_info
, ARRAY_SIZE(i2c_info
));
609 static struct platform_device
*davinci_evm_devices
[] __initdata
= {
614 static struct davinci_uart_config uart_config __initdata
= {
615 .enabled_uarts
= (1 << 0),
619 davinci_evm_map_io(void)
621 /* setup input configuration for VPFE input devices */
622 dm644x_set_vpfe_config(&vpfe_cfg
);
626 static int davinci_phy_fixup(struct phy_device
*phydev
)
628 unsigned int control
;
629 /* CRITICAL: Fix for increasing PHY signal drive strength for
630 * TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY
631 * signal strength was low causing TX to fail randomly. The
632 * fix is to Set bit 11 (Increased MII drive strength) of PHY
633 * register 26 (Digital Config register) on this phy. */
634 control
= phy_read(phydev
, 26);
635 phy_write(phydev
, 26, (control
| 0x800));
639 #if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
640 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
646 #if defined(CONFIG_MTD_PHYSMAP) || \
647 defined(CONFIG_MTD_PHYSMAP_MODULE)
653 #if defined(CONFIG_MTD_NAND_DAVINCI) || \
654 defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
660 static __init
void davinci_evm_init(void)
662 struct clk
*aemif_clk
;
663 struct davinci_soc_info
*soc_info
= &davinci_soc_info
;
665 aemif_clk
= clk_get(NULL
, "aemif");
666 clk_enable(aemif_clk
);
669 if (HAS_NAND
|| HAS_NOR
)
670 pr_warning("WARNING: both IDE and Flash are "
671 "enabled, but they share AEMIF pins.\n"
672 "\tDisable IDE for NAND/NOR support.\n");
674 } else if (HAS_NAND
|| HAS_NOR
) {
675 davinci_cfg_reg(DM644X_HPIEN_DISABLE
);
676 davinci_cfg_reg(DM644X_ATAEN_DISABLE
);
678 /* only one device will be jumpered and detected */
680 platform_device_register(&davinci_evm_nandflash_device
);
681 evm_leds
[7].default_trigger
= "nand-disk";
683 pr_warning("WARNING: both NAND and NOR flash "
684 "are enabled; disable one of them.\n");
686 platform_device_register(&davinci_evm_norflash_device
);
689 platform_add_devices(davinci_evm_devices
,
690 ARRAY_SIZE(davinci_evm_devices
));
693 davinci_setup_mmc(0, &dm6446evm_mmc_config
);
695 davinci_serial_init(&uart_config
);
696 dm644x_init_asp(&dm644x_evm_snd_data
);
698 soc_info
->emac_pdata
->phy_mask
= DM644X_EVM_PHY_MASK
;
699 soc_info
->emac_pdata
->mdio_max_freq
= DM644X_EVM_MDIO_FREQUENCY
;
701 /* Register the fixup for PHY on DaVinci */
702 phy_register_fixup_for_uid(LXT971_PHY_ID
, LXT971_PHY_MASK
,
707 static __init
void davinci_evm_irq_init(void)
712 MACHINE_START(DAVINCI_EVM
, "DaVinci DM644x EVM")
713 /* Maintainer: MontaVista Software <source@mvista.com> */
715 .io_pg_offst
= (__IO_ADDRESS(IO_PHYS
) >> 18) & 0xfffc,
716 .boot_params
= (DAVINCI_DDR_BASE
+ 0x100),
717 .map_io
= davinci_evm_map_io
,
718 .init_irq
= davinci_evm_irq_init
,
719 .timer
= &davinci_timer
,
720 .init_machine
= davinci_evm_init
,