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[linux-2.6/x86.git] / drivers / scsi / sata_mv.c
blobfa901fd650856e8f7b241ff5285bcc3ab84c4c6e
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2005: EMC Corporation, all rights reserved.
5 * Copyright 2005 Red Hat, Inc. All rights reserved.
6 *
7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/sched.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/device.h>
34 #include <scsi/scsi_host.h>
35 #include <scsi/scsi_cmnd.h>
36 #include <linux/libata.h>
37 #include <asm/io.h>
38
39 #define DRV_NAME "sata_mv"
40 #define DRV_VERSION "0.6"
41
42 enum {
43 /* BAR's are enumerated in terms of pci_resource_start() terms */
44 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
45 MV_IO_BAR = 2, /* offset 0x18: IO space */
46 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
47
48 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
49 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
50
51 MV_PCI_REG_BASE = 0,
52 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
53 MV_SATAHC0_REG_BASE = 0x20000,
54 MV_FLASH_CTL = 0x1046c,
55 MV_GPIO_PORT_CTL = 0x104f0,
56 MV_RESET_CFG = 0x180d8,
57
58 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
59 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
60 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
61 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
62
63 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
64
65 MV_MAX_Q_DEPTH = 32,
66 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
67
68 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
69 * CRPB needs alignment on a 256B boundary. Size == 256B
70 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
71 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
72 */
73 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
74 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
75 MV_MAX_SG_CT = 176,
76 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
77 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
78
79 MV_PORTS_PER_HC = 4,
80 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
81 MV_PORT_HC_SHIFT = 2,
82 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
83 MV_PORT_MASK = 3,
84
85 /* Host Flags */
86 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
87 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
88 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
89 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
90 ATA_FLAG_NO_ATAPI),
91 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
92
93 CRQB_FLAG_READ = (1 << 0),
94 CRQB_TAG_SHIFT = 1,
95 CRQB_CMD_ADDR_SHIFT = 8,
96 CRQB_CMD_CS = (0x2 << 11),
97 CRQB_CMD_LAST = (1 << 15),
98
99 CRPB_FLAG_STATUS_SHIFT = 8,
100
101 EPRD_FLAG_END_OF_TBL = (1 << 31),
102
103 /* PCI interface registers */
104
105 PCI_COMMAND_OFS = 0xc00,
106
107 PCI_MAIN_CMD_STS_OFS = 0xd30,
108 STOP_PCI_MASTER = (1 << 2),
109 PCI_MASTER_EMPTY = (1 << 3),
110 GLOB_SFT_RST = (1 << 4),
111
112 MV_PCI_MODE = 0xd00,
113 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
114 MV_PCI_DISC_TIMER = 0xd04,
115 MV_PCI_MSI_TRIGGER = 0xc38,
116 MV_PCI_SERR_MASK = 0xc28,
117 MV_PCI_XBAR_TMOUT = 0x1d04,
118 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
119 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
120 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
121 MV_PCI_ERR_COMMAND = 0x1d50,
122
123 PCI_IRQ_CAUSE_OFS = 0x1d58,
124 PCI_IRQ_MASK_OFS = 0x1d5c,
125 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
126
127 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
128 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
129 PORT0_ERR = (1 << 0), /* shift by port # */
130 PORT0_DONE = (1 << 1), /* shift by port # */
131 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
132 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
133 PCI_ERR = (1 << 18),
134 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
135 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
136 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
137 GPIO_INT = (1 << 22),
138 SELF_INT = (1 << 23),
139 TWSI_INT = (1 << 24),
140 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
141 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
142 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
143 HC_MAIN_RSVD),
144
145 /* SATAHC registers */
146 HC_CFG_OFS = 0,
147
148 HC_IRQ_CAUSE_OFS = 0x14,
149 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
150 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
151 DEV_IRQ = (1 << 8), /* shift by port # */
152
153 /* Shadow block registers */
154 SHD_BLK_OFS = 0x100,
155 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
156
157 /* SATA registers */
158 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
159 SATA_ACTIVE_OFS = 0x350,
160 PHY_MODE3 = 0x310,
161 PHY_MODE4 = 0x314,
162 PHY_MODE2 = 0x330,
163 MV5_PHY_MODE = 0x74,
164 MV5_LT_MODE = 0x30,
165 MV5_PHY_CTL = 0x0C,
166 SATA_INTERFACE_CTL = 0x050,
167
168 MV_M2_PREAMP_MASK = 0x7e0,
169
170 /* Port registers */
171 EDMA_CFG_OFS = 0,
172 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
173 EDMA_CFG_NCQ = (1 << 5),
174 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
175 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
176 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
177
178 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
179 EDMA_ERR_IRQ_MASK_OFS = 0xc,
180 EDMA_ERR_D_PAR = (1 << 0),
181 EDMA_ERR_PRD_PAR = (1 << 1),
182 EDMA_ERR_DEV = (1 << 2),
183 EDMA_ERR_DEV_DCON = (1 << 3),
184 EDMA_ERR_DEV_CON = (1 << 4),
185 EDMA_ERR_SERR = (1 << 5),
186 EDMA_ERR_SELF_DIS = (1 << 7),
187 EDMA_ERR_BIST_ASYNC = (1 << 8),
188 EDMA_ERR_CRBQ_PAR = (1 << 9),
189 EDMA_ERR_CRPB_PAR = (1 << 10),
190 EDMA_ERR_INTRL_PAR = (1 << 11),
191 EDMA_ERR_IORDY = (1 << 12),
192 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
193 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
194 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
195 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
196 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
197 EDMA_ERR_TRANS_PROTO = (1 << 31),
198 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
199 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
200 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
201 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
202 EDMA_ERR_LNK_DATA_RX |
203 EDMA_ERR_LNK_DATA_TX |
204 EDMA_ERR_TRANS_PROTO),
205
206 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
207 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
208
209 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
210 EDMA_REQ_Q_PTR_SHIFT = 5,
211
212 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
213 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
214 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
215 EDMA_RSP_Q_PTR_SHIFT = 3,
216
217 EDMA_CMD_OFS = 0x28,
218 EDMA_EN = (1 << 0),
219 EDMA_DS = (1 << 1),
220 ATA_RST = (1 << 2),
221
222 EDMA_IORDY_TMOUT = 0x34,
223 EDMA_ARB_CFG = 0x38,
224
225 /* Host private flags (hp_flags) */
226 MV_HP_FLAG_MSI = (1 << 0),
227 MV_HP_ERRATA_50XXB0 = (1 << 1),
228 MV_HP_ERRATA_50XXB2 = (1 << 2),
229 MV_HP_ERRATA_60X1B2 = (1 << 3),
230 MV_HP_ERRATA_60X1C0 = (1 << 4),
231 MV_HP_ERRATA_XX42A0 = (1 << 5),
232 MV_HP_50XX = (1 << 6),
233 MV_HP_GEN_IIE = (1 << 7),
234
235 /* Port private flags (pp_flags) */
236 MV_PP_FLAG_EDMA_EN = (1 << 0),
237 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
238 };
239
240 #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
241 #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
242 #define IS_GEN_I(hpriv) IS_50XX(hpriv)
243 #define IS_GEN_II(hpriv) IS_60XX(hpriv)
244 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
245
246 enum {
247 /* Our DMA boundary is determined by an ePRD being unable to handle
248 * anything larger than 64KB
249 */
250 MV_DMA_BOUNDARY = 0xffffU,
251
252 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
253
254 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
255 };
256
257 enum chip_type {
258 chip_504x,
259 chip_508x,
260 chip_5080,
261 chip_604x,
262 chip_608x,
263 chip_6042,
264 chip_7042,
265 };
266
267 /* Command ReQuest Block: 32B */
268 struct mv_crqb {
269 u32 sg_addr;
270 u32 sg_addr_hi;
271 u16 ctrl_flags;
272 u16 ata_cmd[11];
273 };
274
275 struct mv_crqb_iie {
276 u32 addr;
277 u32 addr_hi;
278 u32 flags;
279 u32 len;
280 u32 ata_cmd[4];
281 };
282
283 /* Command ResPonse Block: 8B */
284 struct mv_crpb {
285 u16 id;
286 u16 flags;
287 u32 tmstmp;
288 };
289
290 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
291 struct mv_sg {
292 u32 addr;
293 u32 flags_size;
294 u32 addr_hi;
295 u32 reserved;
296 };
297
298 struct mv_port_priv {
299 struct mv_crqb *crqb;
300 dma_addr_t crqb_dma;
301 struct mv_crpb *crpb;
302 dma_addr_t crpb_dma;
303 struct mv_sg *sg_tbl;
304 dma_addr_t sg_tbl_dma;
305
306 unsigned req_producer; /* cp of req_in_ptr */
307 unsigned rsp_consumer; /* cp of rsp_out_ptr */
308 u32 pp_flags;
309 };
310
311 struct mv_port_signal {
312 u32 amps;
313 u32 pre;
314 };
315
316 struct mv_host_priv;
317 struct mv_hw_ops {
318 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
319 unsigned int port);
320 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
321 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
322 void __iomem *mmio);
323 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
324 unsigned int n_hc);
325 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
326 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
327 };
328
329 struct mv_host_priv {
330 u32 hp_flags;
331 struct mv_port_signal signal[8];
332 const struct mv_hw_ops *ops;
333 };
334
335 static void mv_irq_clear(struct ata_port *ap);
336 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
337 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
338 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
339 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
340 static void mv_phy_reset(struct ata_port *ap);
341 static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
342 static void mv_host_stop(struct ata_host_set *host_set);
343 static int mv_port_start(struct ata_port *ap);
344 static void mv_port_stop(struct ata_port *ap);
345 static void mv_qc_prep(struct ata_queued_cmd *qc);
346 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
347 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
348 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
349 struct pt_regs *regs);
350 static void mv_eng_timeout(struct ata_port *ap);
351 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
352
353 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
354 unsigned int port);
355 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
356 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
357 void __iomem *mmio);
358 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
359 unsigned int n_hc);
360 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
361 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
362
363 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
364 unsigned int port);
365 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
366 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
367 void __iomem *mmio);
368 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
369 unsigned int n_hc);
370 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
371 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
372 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
373 unsigned int port_no);
374 static void mv_stop_and_reset(struct ata_port *ap);
375
376 static struct scsi_host_template mv_sht = {
377 .module = THIS_MODULE,
378 .name = DRV_NAME,
379 .ioctl = ata_scsi_ioctl,
380 .queuecommand = ata_scsi_queuecmd,
381 .eh_strategy_handler = ata_scsi_error,
382 .can_queue = MV_USE_Q_DEPTH,
383 .this_id = ATA_SHT_THIS_ID,
384 .sg_tablesize = MV_MAX_SG_CT / 2,
385 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
386 .emulated = ATA_SHT_EMULATED,
387 .use_clustering = ATA_SHT_USE_CLUSTERING,
388 .proc_name = DRV_NAME,
389 .dma_boundary = MV_DMA_BOUNDARY,
390 .slave_configure = ata_scsi_slave_config,
391 .bios_param = ata_std_bios_param,
392 };
393
394 static const struct ata_port_operations mv5_ops = {
395 .port_disable = ata_port_disable,
396
397 .tf_load = ata_tf_load,
398 .tf_read = ata_tf_read,
399 .check_status = ata_check_status,
400 .exec_command = ata_exec_command,
401 .dev_select = ata_std_dev_select,
402
403 .phy_reset = mv_phy_reset,
404
405 .qc_prep = mv_qc_prep,
406 .qc_issue = mv_qc_issue,
407
408 .eng_timeout = mv_eng_timeout,
409
410 .irq_handler = mv_interrupt,
411 .irq_clear = mv_irq_clear,
412
413 .scr_read = mv5_scr_read,
414 .scr_write = mv5_scr_write,
415
416 .port_start = mv_port_start,
417 .port_stop = mv_port_stop,
418 .host_stop = mv_host_stop,
419 };
420
421 static const struct ata_port_operations mv6_ops = {
422 .port_disable = ata_port_disable,
423
424 .tf_load = ata_tf_load,
425 .tf_read = ata_tf_read,
426 .check_status = ata_check_status,
427 .exec_command = ata_exec_command,
428 .dev_select = ata_std_dev_select,
429
430 .phy_reset = mv_phy_reset,
431
432 .qc_prep = mv_qc_prep,
433 .qc_issue = mv_qc_issue,
434
435 .eng_timeout = mv_eng_timeout,
436
437 .irq_handler = mv_interrupt,
438 .irq_clear = mv_irq_clear,
439
440 .scr_read = mv_scr_read,
441 .scr_write = mv_scr_write,
442
443 .port_start = mv_port_start,
444 .port_stop = mv_port_stop,
445 .host_stop = mv_host_stop,
446 };
447
448 static const struct ata_port_operations mv_iie_ops = {
449 .port_disable = ata_port_disable,
450
451 .tf_load = ata_tf_load,
452 .tf_read = ata_tf_read,
453 .check_status = ata_check_status,
454 .exec_command = ata_exec_command,
455 .dev_select = ata_std_dev_select,
456
457 .phy_reset = mv_phy_reset,
458
459 .qc_prep = mv_qc_prep_iie,
460 .qc_issue = mv_qc_issue,
461
462 .eng_timeout = mv_eng_timeout,
463
464 .irq_handler = mv_interrupt,
465 .irq_clear = mv_irq_clear,
466
467 .scr_read = mv_scr_read,
468 .scr_write = mv_scr_write,
469
470 .port_start = mv_port_start,
471 .port_stop = mv_port_stop,
472 .host_stop = mv_host_stop,
473 };
474
475 static const struct ata_port_info mv_port_info[] = {
476 { /* chip_504x */
477 .sht = &mv_sht,
478 .host_flags = MV_COMMON_FLAGS,
479 .pio_mask = 0x1f, /* pio0-4 */
480 .udma_mask = 0x7f, /* udma0-6 */
481 .port_ops = &mv5_ops,
482 },
483 { /* chip_508x */
484 .sht = &mv_sht,
485 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
486 .pio_mask = 0x1f, /* pio0-4 */
487 .udma_mask = 0x7f, /* udma0-6 */
488 .port_ops = &mv5_ops,
489 },
490 { /* chip_5080 */
491 .sht = &mv_sht,
492 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
493 .pio_mask = 0x1f, /* pio0-4 */
494 .udma_mask = 0x7f, /* udma0-6 */
495 .port_ops = &mv5_ops,
496 },
497 { /* chip_604x */
498 .sht = &mv_sht,
499 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
500 .pio_mask = 0x1f, /* pio0-4 */
501 .udma_mask = 0x7f, /* udma0-6 */
502 .port_ops = &mv6_ops,
503 },
504 { /* chip_608x */
505 .sht = &mv_sht,
506 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
507 MV_FLAG_DUAL_HC),
508 .pio_mask = 0x1f, /* pio0-4 */
509 .udma_mask = 0x7f, /* udma0-6 */
510 .port_ops = &mv6_ops,
511 },
512 { /* chip_6042 */
513 .sht = &mv_sht,
514 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
515 .pio_mask = 0x1f, /* pio0-4 */
516 .udma_mask = 0x7f, /* udma0-6 */
517 .port_ops = &mv_iie_ops,
518 },
519 { /* chip_7042 */
520 .sht = &mv_sht,
521 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
522 MV_FLAG_DUAL_HC),
523 .pio_mask = 0x1f, /* pio0-4 */
524 .udma_mask = 0x7f, /* udma0-6 */
525 .port_ops = &mv_iie_ops,
526 },
527 };
528
529 static const struct pci_device_id mv_pci_tbl[] = {
530 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x},
531 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x},
532 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_5080},
533 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x},
534
535 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x},
536 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x},
537 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6042), 0, 0, chip_6042},
538 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x},
539 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x},
540
541 {PCI_DEVICE(PCI_VENDOR_ID_ADAPTEC2, 0x0241), 0, 0, chip_604x},
542 {} /* terminate list */
543 };
544
545 static struct pci_driver mv_pci_driver = {
546 .name = DRV_NAME,
547 .id_table = mv_pci_tbl,
548 .probe = mv_init_one,
549 .remove = ata_pci_remove_one,
550 };
551
552 static const struct mv_hw_ops mv5xxx_ops = {
553 .phy_errata = mv5_phy_errata,
554 .enable_leds = mv5_enable_leds,
555 .read_preamp = mv5_read_preamp,
556 .reset_hc = mv5_reset_hc,
557 .reset_flash = mv5_reset_flash,
558 .reset_bus = mv5_reset_bus,
559 };
560
561 static const struct mv_hw_ops mv6xxx_ops = {
562 .phy_errata = mv6_phy_errata,
563 .enable_leds = mv6_enable_leds,
564 .read_preamp = mv6_read_preamp,
565 .reset_hc = mv6_reset_hc,
566 .reset_flash = mv6_reset_flash,
567 .reset_bus = mv_reset_pci_bus,
568 };
569
570 /*
571 * module options
572 */
573 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
574
575
576 /*
577 * Functions
578 */
579
580 static inline void writelfl(unsigned long data, void __iomem *addr)
581 {
582 writel(data, addr);
583 (void) readl(addr); /* flush to avoid PCI posted write */
584 }
585
586 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
587 {
588 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
589 }
590
591 static inline unsigned int mv_hc_from_port(unsigned int port)
592 {
593 return port >> MV_PORT_HC_SHIFT;
594 }
595
596 static inline unsigned int mv_hardport_from_port(unsigned int port)
597 {
598 return port & MV_PORT_MASK;
599 }
600
601 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
602 unsigned int port)
603 {
604 return mv_hc_base(base, mv_hc_from_port(port));
605 }
606
607 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
608 {
609 return mv_hc_base_from_port(base, port) +
610 MV_SATAHC_ARBTR_REG_SZ +
611 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
612 }
613
614 static inline void __iomem *mv_ap_base(struct ata_port *ap)
615 {
616 return mv_port_base(ap->host_set->mmio_base, ap->port_no);
617 }
618
619 static inline int mv_get_hc_count(unsigned long host_flags)
620 {
621 return ((host_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
622 }
623
624 static void mv_irq_clear(struct ata_port *ap)
625 {
626 }
627
628 /**
629 * mv_start_dma - Enable eDMA engine
630 * @base: port base address
631 * @pp: port private data
632 *
633 * Verify the local cache of the eDMA state is accurate with a
634 * WARN_ON.
635 *
636 * LOCKING:
637 * Inherited from caller.
638 */
639 static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
640 {
641 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
642 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
643 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
644 }
645 WARN_ON(!(EDMA_EN & readl(base + EDMA_CMD_OFS)));
646 }
647
648 /**
649 * mv_stop_dma - Disable eDMA engine
650 * @ap: ATA channel to manipulate
651 *
652 * Verify the local cache of the eDMA state is accurate with a
653 * WARN_ON.
654 *
655 * LOCKING:
656 * Inherited from caller.
657 */
658 static void mv_stop_dma(struct ata_port *ap)
659 {
660 void __iomem *port_mmio = mv_ap_base(ap);
661 struct mv_port_priv *pp = ap->private_data;
662 u32 reg;
663 int i;
664
665 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
666 /* Disable EDMA if active. The disable bit auto clears.
667 */
668 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
669 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
670 } else {
671 WARN_ON(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS));
672 }
673
674 /* now properly wait for the eDMA to stop */
675 for (i = 1000; i > 0; i--) {
676 reg = readl(port_mmio + EDMA_CMD_OFS);
677 if (!(EDMA_EN & reg)) {
678 break;
679 }
680 udelay(100);
681 }
682
683 if (EDMA_EN & reg) {
684 printk(KERN_ERR "ata%u: Unable to stop eDMA\n", ap->id);
685 /* FIXME: Consider doing a reset here to recover */
686 }
687 }
688
689 #ifdef ATA_DEBUG
690 static void mv_dump_mem(void __iomem *start, unsigned bytes)
691 {
692 int b, w;
693 for (b = 0; b < bytes; ) {
694 DPRINTK("%p: ", start + b);
695 for (w = 0; b < bytes && w < 4; w++) {
696 printk("%08x ",readl(start + b));
697 b += sizeof(u32);
698 }
699 printk("\n");
700 }
701 }
702 #endif
703
704 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
705 {
706 #ifdef ATA_DEBUG
707 int b, w;
708 u32 dw;
709 for (b = 0; b < bytes; ) {
710 DPRINTK("%02x: ", b);
711 for (w = 0; b < bytes && w < 4; w++) {
712 (void) pci_read_config_dword(pdev,b,&dw);
713 printk("%08x ",dw);
714 b += sizeof(u32);
715 }
716 printk("\n");
717 }
718 #endif
719 }
720 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
721 struct pci_dev *pdev)
722 {
723 #ifdef ATA_DEBUG
724 void __iomem *hc_base = mv_hc_base(mmio_base,
725 port >> MV_PORT_HC_SHIFT);
726 void __iomem *port_base;
727 int start_port, num_ports, p, start_hc, num_hcs, hc;
728
729 if (0 > port) {
730 start_hc = start_port = 0;
731 num_ports = 8; /* shld be benign for 4 port devs */
732 num_hcs = 2;
733 } else {
734 start_hc = port >> MV_PORT_HC_SHIFT;
735 start_port = port;
736 num_ports = num_hcs = 1;
737 }
738 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
739 num_ports > 1 ? num_ports - 1 : start_port);
740
741 if (NULL != pdev) {
742 DPRINTK("PCI config space regs:\n");
743 mv_dump_pci_cfg(pdev, 0x68);
744 }
745 DPRINTK("PCI regs:\n");
746 mv_dump_mem(mmio_base+0xc00, 0x3c);
747 mv_dump_mem(mmio_base+0xd00, 0x34);
748 mv_dump_mem(mmio_base+0xf00, 0x4);
749 mv_dump_mem(mmio_base+0x1d00, 0x6c);
750 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
751 hc_base = mv_hc_base(mmio_base, port >> MV_PORT_HC_SHIFT);
752 DPRINTK("HC regs (HC %i):\n", hc);
753 mv_dump_mem(hc_base, 0x1c);
754 }
755 for (p = start_port; p < start_port + num_ports; p++) {
756 port_base = mv_port_base(mmio_base, p);
757 DPRINTK("EDMA regs (port %i):\n",p);
758 mv_dump_mem(port_base, 0x54);
759 DPRINTK("SATA regs (port %i):\n",p);
760 mv_dump_mem(port_base+0x300, 0x60);
761 }
762 #endif
763 }
764
765 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
766 {
767 unsigned int ofs;
768
769 switch (sc_reg_in) {
770 case SCR_STATUS:
771 case SCR_CONTROL:
772 case SCR_ERROR:
773 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
774 break;
775 case SCR_ACTIVE:
776 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
777 break;
778 default:
779 ofs = 0xffffffffU;
780 break;
781 }
782 return ofs;
783 }
784
785 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
786 {
787 unsigned int ofs = mv_scr_offset(sc_reg_in);
788
789 if (0xffffffffU != ofs) {
790 return readl(mv_ap_base(ap) + ofs);
791 } else {
792 return (u32) ofs;
793 }
794 }
795
796 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
797 {
798 unsigned int ofs = mv_scr_offset(sc_reg_in);
799
800 if (0xffffffffU != ofs) {
801 writelfl(val, mv_ap_base(ap) + ofs);
802 }
803 }
804
805 /**
806 * mv_host_stop - Host specific cleanup/stop routine.
807 * @host_set: host data structure
808 *
809 * Disable ints, cleanup host memory, call general purpose
810 * host_stop.
811 *
812 * LOCKING:
813 * Inherited from caller.
814 */
815 static void mv_host_stop(struct ata_host_set *host_set)
816 {
817 struct mv_host_priv *hpriv = host_set->private_data;
818 struct pci_dev *pdev = to_pci_dev(host_set->dev);
819
820 if (hpriv->hp_flags & MV_HP_FLAG_MSI) {
821 pci_disable_msi(pdev);
822 } else {
823 pci_intx(pdev, 0);
824 }
825 kfree(hpriv);
826 ata_host_stop(host_set);
827 }
828
829 static inline void mv_priv_free(struct mv_port_priv *pp, struct device *dev)
830 {
831 dma_free_coherent(dev, MV_PORT_PRIV_DMA_SZ, pp->crpb, pp->crpb_dma);
832 }
833
834 static void mv_edma_cfg(struct mv_host_priv *hpriv, void __iomem *port_mmio)
835 {
836 u32 cfg = readl(port_mmio + EDMA_CFG_OFS);
837
838 /* set up non-NCQ EDMA configuration */
839 cfg &= ~0x1f; /* clear queue depth */
840 cfg &= ~EDMA_CFG_NCQ; /* clear NCQ mode */
841 cfg &= ~(1 << 9); /* disable equeue */
842
843 if (IS_GEN_I(hpriv))
844 cfg |= (1 << 8); /* enab config burst size mask */
845
846 else if (IS_GEN_II(hpriv))
847 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
848
849 else if (IS_GEN_IIE(hpriv)) {
850 cfg |= (1 << 23); /* dis RX PM port mask */
851 cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */
852 cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */
853 cfg |= (1 << 18); /* enab early completion */
854 cfg |= (1 << 17); /* enab host q cache */
855 cfg |= (1 << 22); /* enab cutthrough */
856 }
857
858 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
859 }
860
861 /**
862 * mv_port_start - Port specific init/start routine.
863 * @ap: ATA channel to manipulate
864 *
865 * Allocate and point to DMA memory, init port private memory,
866 * zero indices.
867 *
868 * LOCKING:
869 * Inherited from caller.
870 */
871 static int mv_port_start(struct ata_port *ap)
872 {
873 struct device *dev = ap->host_set->dev;
874 struct mv_host_priv *hpriv = ap->host_set->private_data;
875 struct mv_port_priv *pp;
876 void __iomem *port_mmio = mv_ap_base(ap);
877 void *mem;
878 dma_addr_t mem_dma;
879 int rc = -ENOMEM;
880
881 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
882 if (!pp)
883 goto err_out;
884 memset(pp, 0, sizeof(*pp));
885
886 mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
887 GFP_KERNEL);
888 if (!mem)
889 goto err_out_pp;
890 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
891
892 rc = ata_pad_alloc(ap, dev);
893 if (rc)
894 goto err_out_priv;
895
896 /* First item in chunk of DMA memory:
897 * 32-slot command request table (CRQB), 32 bytes each in size
898 */
899 pp->crqb = mem;
900 pp->crqb_dma = mem_dma;
901 mem += MV_CRQB_Q_SZ;
902 mem_dma += MV_CRQB_Q_SZ;
903
904 /* Second item:
905 * 32-slot command response table (CRPB), 8 bytes each in size
906 */
907 pp->crpb = mem;
908 pp->crpb_dma = mem_dma;
909 mem += MV_CRPB_Q_SZ;
910 mem_dma += MV_CRPB_Q_SZ;
911
912 /* Third item:
913 * Table of scatter-gather descriptors (ePRD), 16 bytes each
914 */
915 pp->sg_tbl = mem;
916 pp->sg_tbl_dma = mem_dma;
917
918 mv_edma_cfg(hpriv, port_mmio);
919
920 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
921 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
922 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
923
924 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
925 writelfl(pp->crqb_dma & 0xffffffff,
926 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
927 else
928 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
929
930 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
931
932 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
933 writelfl(pp->crpb_dma & 0xffffffff,
934 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
935 else
936 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
937
938 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
939 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
940
941 pp->req_producer = pp->rsp_consumer = 0;
942
943 /* Don't turn on EDMA here...do it before DMA commands only. Else
944 * we'll be unable to send non-data, PIO, etc due to restricted access
945 * to shadow regs.
946 */
947 ap->private_data = pp;
948 return 0;
949
950 err_out_priv:
951 mv_priv_free(pp, dev);
952 err_out_pp:
953 kfree(pp);
954 err_out:
955 return rc;
956 }
957
958 /**
959 * mv_port_stop - Port specific cleanup/stop routine.
960 * @ap: ATA channel to manipulate
961 *
962 * Stop DMA, cleanup port memory.
963 *
964 * LOCKING:
965 * This routine uses the host_set lock to protect the DMA stop.
966 */
967 static void mv_port_stop(struct ata_port *ap)
968 {
969 struct device *dev = ap->host_set->dev;
970 struct mv_port_priv *pp = ap->private_data;
971 unsigned long flags;
972
973 spin_lock_irqsave(&ap->host_set->lock, flags);
974 mv_stop_dma(ap);
975 spin_unlock_irqrestore(&ap->host_set->lock, flags);
976
977 ap->private_data = NULL;
978 ata_pad_free(ap, dev);
979 mv_priv_free(pp, dev);
980 kfree(pp);
981 }
982
983 /**
984 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
985 * @qc: queued command whose SG list to source from
986 *
987 * Populate the SG list and mark the last entry.
988 *
989 * LOCKING:
990 * Inherited from caller.
991 */
992 static void mv_fill_sg(struct ata_queued_cmd *qc)
993 {
994 struct mv_port_priv *pp = qc->ap->private_data;
995 unsigned int i = 0;
996 struct scatterlist *sg;
997
998 ata_for_each_sg(sg, qc) {
999 dma_addr_t addr;
1000 u32 sg_len, len, offset;
1001
1002 addr = sg_dma_address(sg);
1003 sg_len = sg_dma_len(sg);
1004
1005 while (sg_len) {
1006 offset = addr & MV_DMA_BOUNDARY;
1007 len = sg_len;
1008 if ((offset + sg_len) > 0x10000)
1009 len = 0x10000 - offset;
1010
1011 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
1012 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1013 pp->sg_tbl[i].flags_size = cpu_to_le32(len & 0xffff);
1014
1015 sg_len -= len;
1016 addr += len;
1017
1018 if (!sg_len && ata_sg_is_last(sg, qc))
1019 pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1020
1021 i++;
1022 }
1023 }
1024 }
1025
1026 static inline unsigned mv_inc_q_index(unsigned *index)
1027 {
1028 *index = (*index + 1) & MV_MAX_Q_DEPTH_MASK;
1029 return *index;
1030 }
1031
1032 static inline void mv_crqb_pack_cmd(u16 *cmdw, u8 data, u8 addr, unsigned last)
1033 {
1034 *cmdw = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1035 (last ? CRQB_CMD_LAST : 0);
1036 }
1037
1038 /**
1039 * mv_qc_prep - Host specific command preparation.
1040 * @qc: queued command to prepare
1041 *
1042 * This routine simply redirects to the general purpose routine
1043 * if command is not DMA. Else, it handles prep of the CRQB
1044 * (command request block), does some sanity checking, and calls
1045 * the SG load routine.
1046 *
1047 * LOCKING:
1048 * Inherited from caller.
1049 */
1050 static void mv_qc_prep(struct ata_queued_cmd *qc)
1051 {
1052 struct ata_port *ap = qc->ap;
1053 struct mv_port_priv *pp = ap->private_data;
1054 u16 *cw;
1055 struct ata_taskfile *tf;
1056 u16 flags = 0;
1057
1058 if (ATA_PROT_DMA != qc->tf.protocol)
1059 return;
1060
1061 /* the req producer index should be the same as we remember it */
1062 WARN_ON(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >>
1063 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) !=
1064 pp->req_producer);
1065
1066 /* Fill in command request block
1067 */
1068 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1069 flags |= CRQB_FLAG_READ;
1070 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1071 flags |= qc->tag << CRQB_TAG_SHIFT;
1072
1073 pp->crqb[pp->req_producer].sg_addr =
1074 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1075 pp->crqb[pp->req_producer].sg_addr_hi =
1076 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1077 pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags);
1078
1079 cw = &pp->crqb[pp->req_producer].ata_cmd[0];
1080 tf = &qc->tf;
1081
1082 /* Sadly, the CRQB cannot accomodate all registers--there are
1083 * only 11 bytes...so we must pick and choose required
1084 * registers based on the command. So, we drop feature and
1085 * hob_feature for [RW] DMA commands, but they are needed for
1086 * NCQ. NCQ will drop hob_nsect.
1087 */
1088 switch (tf->command) {
1089 case ATA_CMD_READ:
1090 case ATA_CMD_READ_EXT:
1091 case ATA_CMD_WRITE:
1092 case ATA_CMD_WRITE_EXT:
1093 case ATA_CMD_WRITE_FUA_EXT:
1094 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1095 break;
1096 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
1097 case ATA_CMD_FPDMA_READ:
1098 case ATA_CMD_FPDMA_WRITE:
1099 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1100 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1101 break;
1102 #endif /* FIXME: remove this line when NCQ added */
1103 default:
1104 /* The only other commands EDMA supports in non-queued and
1105 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1106 * of which are defined/used by Linux. If we get here, this
1107 * driver needs work.
1108 *
1109 * FIXME: modify libata to give qc_prep a return value and
1110 * return error here.
1111 */
1112 BUG_ON(tf->command);
1113 break;
1114 }
1115 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1116 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1117 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1118 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1119 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1120 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1121 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1122 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1123 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1124
1125 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1126 return;
1127 mv_fill_sg(qc);
1128 }
1129
1130 /**
1131 * mv_qc_prep_iie - Host specific command preparation.
1132 * @qc: queued command to prepare
1133 *
1134 * This routine simply redirects to the general purpose routine
1135 * if command is not DMA. Else, it handles prep of the CRQB
1136 * (command request block), does some sanity checking, and calls
1137 * the SG load routine.
1138 *
1139 * LOCKING:
1140 * Inherited from caller.
1141 */
1142 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1143 {
1144 struct ata_port *ap = qc->ap;
1145 struct mv_port_priv *pp = ap->private_data;
1146 struct mv_crqb_iie *crqb;
1147 struct ata_taskfile *tf;
1148 u32 flags = 0;
1149
1150 if (ATA_PROT_DMA != qc->tf.protocol)
1151 return;
1152
1153 /* the req producer index should be the same as we remember it */
1154 WARN_ON(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >>
1155 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) !=
1156 pp->req_producer);
1157
1158 /* Fill in Gen IIE command request block
1159 */
1160 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1161 flags |= CRQB_FLAG_READ;
1162
1163 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1164 flags |= qc->tag << CRQB_TAG_SHIFT;
1165
1166 crqb = (struct mv_crqb_iie *) &pp->crqb[pp->req_producer];
1167 crqb->addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1168 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1169 crqb->flags = cpu_to_le32(flags);
1170
1171 tf = &qc->tf;
1172 crqb->ata_cmd[0] = cpu_to_le32(
1173 (tf->command << 16) |
1174 (tf->feature << 24)
1175 );
1176 crqb->ata_cmd[1] = cpu_to_le32(
1177 (tf->lbal << 0) |
1178 (tf->lbam << 8) |
1179 (tf->lbah << 16) |
1180 (tf->device << 24)
1181 );
1182 crqb->ata_cmd[2] = cpu_to_le32(
1183 (tf->hob_lbal << 0) |
1184 (tf->hob_lbam << 8) |
1185 (tf->hob_lbah << 16) |
1186 (tf->hob_feature << 24)
1187 );
1188 crqb->ata_cmd[3] = cpu_to_le32(
1189 (tf->nsect << 0) |
1190 (tf->hob_nsect << 8)
1191 );
1192
1193 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1194 return;
1195 mv_fill_sg(qc);
1196 }
1197
1198 /**
1199 * mv_qc_issue - Initiate a command to the host
1200 * @qc: queued command to start
1201 *
1202 * This routine simply redirects to the general purpose routine
1203 * if command is not DMA. Else, it sanity checks our local
1204 * caches of the request producer/consumer indices then enables
1205 * DMA and bumps the request producer index.
1206 *
1207 * LOCKING:
1208 * Inherited from caller.
1209 */
1210 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1211 {
1212 void __iomem *port_mmio = mv_ap_base(qc->ap);
1213 struct mv_port_priv *pp = qc->ap->private_data;
1214 u32 in_ptr;
1215
1216 if (ATA_PROT_DMA != qc->tf.protocol) {
1217 /* We're about to send a non-EDMA capable command to the
1218 * port. Turn off EDMA so there won't be problems accessing
1219 * shadow block, etc registers.
1220 */
1221 mv_stop_dma(qc->ap);
1222 return ata_qc_issue_prot(qc);
1223 }
1224
1225 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1226
1227 /* the req producer index should be the same as we remember it */
1228 WARN_ON(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) !=
1229 pp->req_producer);
1230 /* until we do queuing, the queue should be empty at this point */
1231 WARN_ON(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) !=
1232 ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >>
1233 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1234
1235 mv_inc_q_index(&pp->req_producer); /* now incr producer index */
1236
1237 mv_start_dma(port_mmio, pp);
1238
1239 /* and write the request in pointer to kick the EDMA to life */
1240 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
1241 in_ptr |= pp->req_producer << EDMA_REQ_Q_PTR_SHIFT;
1242 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1243
1244 return 0;
1245 }
1246
1247 /**
1248 * mv_get_crpb_status - get status from most recently completed cmd
1249 * @ap: ATA channel to manipulate
1250 *
1251 * This routine is for use when the port is in DMA mode, when it
1252 * will be using the CRPB (command response block) method of
1253 * returning command completion information. We check indices
1254 * are good, grab status, and bump the response consumer index to
1255 * prove that we're up to date.
1256 *
1257 * LOCKING:
1258 * Inherited from caller.
1259 */
1260 static u8 mv_get_crpb_status(struct ata_port *ap)
1261 {
1262 void __iomem *port_mmio = mv_ap_base(ap);
1263 struct mv_port_priv *pp = ap->private_data;
1264 u32 out_ptr;
1265 u8 ata_status;
1266
1267 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1268
1269 /* the response consumer index should be the same as we remember it */
1270 WARN_ON(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) !=
1271 pp->rsp_consumer);
1272
1273 ata_status = pp->crpb[pp->rsp_consumer].flags >> CRPB_FLAG_STATUS_SHIFT;
1274
1275 /* increment our consumer index... */
1276 pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer);
1277
1278 /* and, until we do NCQ, there should only be 1 CRPB waiting */
1279 WARN_ON(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >>
1280 EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) !=
1281 pp->rsp_consumer);
1282
1283 /* write out our inc'd consumer index so EDMA knows we're caught up */
1284 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
1285 out_ptr |= pp->rsp_consumer << EDMA_RSP_Q_PTR_SHIFT;
1286 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1287
1288 /* Return ATA status register for completed CRPB */
1289 return ata_status;
1290 }
1291
1292 /**
1293 * mv_err_intr - Handle error interrupts on the port
1294 * @ap: ATA channel to manipulate
1295 *
1296 * In most cases, just clear the interrupt and move on. However,
1297 * some cases require an eDMA reset, which is done right before
1298 * the COMRESET in mv_phy_reset(). The SERR case requires a
1299 * clear of pending errors in the SATA SERROR register. Finally,
1300 * if the port disabled DMA, update our cached copy to match.
1301 *
1302 * LOCKING:
1303 * Inherited from caller.
1304 */
1305 static void mv_err_intr(struct ata_port *ap)
1306 {
1307 void __iomem *port_mmio = mv_ap_base(ap);
1308 u32 edma_err_cause, serr = 0;
1309
1310 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1311
1312 if (EDMA_ERR_SERR & edma_err_cause) {
1313 serr = scr_read(ap, SCR_ERROR);
1314 scr_write_flush(ap, SCR_ERROR, serr);
1315 }
1316 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1317 struct mv_port_priv *pp = ap->private_data;
1318 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1319 }
1320 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1321 "SERR: 0x%08x\n", ap->id, edma_err_cause, serr);
1322
1323 /* Clear EDMA now that SERR cleanup done */
1324 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1325
1326 /* check for fatal here and recover if needed */
1327 if (EDMA_ERR_FATAL & edma_err_cause) {
1328 mv_stop_and_reset(ap);
1329 }
1330 }
1331
1332 /**
1333 * mv_host_intr - Handle all interrupts on the given host controller
1334 * @host_set: host specific structure
1335 * @relevant: port error bits relevant to this host controller
1336 * @hc: which host controller we're to look at
1337 *
1338 * Read then write clear the HC interrupt status then walk each
1339 * port connected to the HC and see if it needs servicing. Port
1340 * success ints are reported in the HC interrupt status reg, the
1341 * port error ints are reported in the higher level main
1342 * interrupt status register and thus are passed in via the
1343 * 'relevant' argument.
1344 *
1345 * LOCKING:
1346 * Inherited from caller.
1347 */
1348 static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1349 unsigned int hc)
1350 {
1351 void __iomem *mmio = host_set->mmio_base;
1352 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1353 struct ata_queued_cmd *qc;
1354 u32 hc_irq_cause;
1355 int shift, port, port0, hard_port, handled;
1356 unsigned int err_mask;
1357
1358 if (hc == 0) {
1359 port0 = 0;
1360 } else {
1361 port0 = MV_PORTS_PER_HC;
1362 }
1363
1364 /* we'll need the HC success int register in most cases */
1365 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1366 if (hc_irq_cause) {
1367 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1368 }
1369
1370 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1371 hc,relevant,hc_irq_cause);
1372
1373 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
1374 u8 ata_status = 0;
1375 struct ata_port *ap = host_set->ports[port];
1376 struct mv_port_priv *pp = ap->private_data;
1377
1378 hard_port = port & MV_PORT_MASK; /* range 0-3 */
1379 handled = 0; /* ensure ata_status is set if handled++ */
1380
1381 /* Note that DEV_IRQ might happen spuriously during EDMA,
1382 * and should be ignored in such cases. We could mask it,
1383 * but it's pretty rare and may not be worth the overhead.
1384 */
1385 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1386 /* EDMA: check for response queue interrupt */
1387 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1388 ata_status = mv_get_crpb_status(ap);
1389 handled = 1;
1390 }
1391 } else {
1392 /* PIO: check for device (drive) interrupt */
1393 if ((DEV_IRQ << hard_port) & hc_irq_cause) {
1394 ata_status = readb((void __iomem *)
1395 ap->ioaddr.status_addr);
1396 handled = 1;
1397 }
1398 }
1399
1400 if (ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))
1401 continue;
1402
1403 err_mask = ac_err_mask(ata_status);
1404
1405 shift = port << 1; /* (port * 2) */
1406 if (port >= MV_PORTS_PER_HC) {
1407 shift++; /* skip bit 8 in the HC Main IRQ reg */
1408 }
1409 if ((PORT0_ERR << shift) & relevant) {
1410 mv_err_intr(ap);
1411 err_mask |= AC_ERR_OTHER;
1412 handled = 1;
1413 }
1414
1415 if (handled) {
1416 qc = ata_qc_from_tag(ap, ap->active_tag);
1417 if (qc && (qc->flags & ATA_QCFLAG_ACTIVE)) {
1418 VPRINTK("port %u IRQ found for qc, "
1419 "ata_status 0x%x\n", port,ata_status);
1420 /* mark qc status appropriately */
1421 if (!(qc->tf.ctl & ATA_NIEN)) {
1422 qc->err_mask |= err_mask;
1423 ata_qc_complete(qc);
1424 }
1425 }
1426 }
1427 }
1428 VPRINTK("EXIT\n");
1429 }
1430
1431 /**
1432 * mv_interrupt -
1433 * @irq: unused
1434 * @dev_instance: private data; in this case the host structure
1435 * @regs: unused
1436 *
1437 * Read the read only register to determine if any host
1438 * controllers have pending interrupts. If so, call lower level
1439 * routine to handle. Also check for PCI errors which are only
1440 * reported here.
1441 *
1442 * LOCKING:
1443 * This routine holds the host_set lock while processing pending
1444 * interrupts.
1445 */
1446 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
1447 struct pt_regs *regs)
1448 {
1449 struct ata_host_set *host_set = dev_instance;
1450 unsigned int hc, handled = 0, n_hcs;
1451 void __iomem *mmio = host_set->mmio_base;
1452 u32 irq_stat;
1453
1454 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
1455
1456 /* check the cases where we either have nothing pending or have read
1457 * a bogus register value which can indicate HW removal or PCI fault
1458 */
1459 if (!irq_stat || (0xffffffffU == irq_stat)) {
1460 return IRQ_NONE;
1461 }
1462
1463 n_hcs = mv_get_hc_count(host_set->ports[0]->flags);
1464 spin_lock(&host_set->lock);
1465
1466 for (hc = 0; hc < n_hcs; hc++) {
1467 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1468 if (relevant) {
1469 mv_host_intr(host_set, relevant, hc);
1470 handled++;
1471 }
1472 }
1473 if (PCI_ERR & irq_stat) {
1474 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1475 readl(mmio + PCI_IRQ_CAUSE_OFS));
1476
1477 DPRINTK("All regs @ PCI error\n");
1478 mv_dump_all_regs(mmio, -1, to_pci_dev(host_set->dev));
1479
1480 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1481 handled++;
1482 }
1483 spin_unlock(&host_set->lock);
1484
1485 return IRQ_RETVAL(handled);
1486 }
1487
1488 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1489 {
1490 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1491 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1492
1493 return hc_mmio + ofs;
1494 }
1495
1496 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1497 {
1498 unsigned int ofs;
1499
1500 switch (sc_reg_in) {
1501 case SCR_STATUS:
1502 case SCR_ERROR:
1503 case SCR_CONTROL:
1504 ofs = sc_reg_in * sizeof(u32);
1505 break;
1506 default:
1507 ofs = 0xffffffffU;
1508 break;
1509 }
1510 return ofs;
1511 }
1512
1513 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1514 {
1515 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1516 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1517
1518 if (ofs != 0xffffffffU)
1519 return readl(mmio + ofs);
1520 else
1521 return (u32) ofs;
1522 }
1523
1524 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1525 {
1526 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1527 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1528
1529 if (ofs != 0xffffffffU)
1530 writelfl(val, mmio + ofs);
1531 }
1532
1533 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1534 {
1535 u8 rev_id;
1536 int early_5080;
1537
1538 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1539
1540 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1541
1542 if (!early_5080) {
1543 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1544 tmp |= (1 << 0);
1545 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1546 }
1547
1548 mv_reset_pci_bus(pdev, mmio);
1549 }
1550
1551 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1552 {
1553 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1554 }
1555
1556 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
1557 void __iomem *mmio)
1558 {
1559 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1560 u32 tmp;
1561
1562 tmp = readl(phy_mmio + MV5_PHY_MODE);
1563
1564 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1565 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
1566 }
1567
1568 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1569 {
1570 u32 tmp;
1571
1572 writel(0, mmio + MV_GPIO_PORT_CTL);
1573
1574 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1575
1576 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1577 tmp |= ~(1 << 0);
1578 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1579 }
1580
1581 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1582 unsigned int port)
1583 {
1584 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1585 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1586 u32 tmp;
1587 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1588
1589 if (fix_apm_sq) {
1590 tmp = readl(phy_mmio + MV5_LT_MODE);
1591 tmp |= (1 << 19);
1592 writel(tmp, phy_mmio + MV5_LT_MODE);
1593
1594 tmp = readl(phy_mmio + MV5_PHY_CTL);
1595 tmp &= ~0x3;
1596 tmp |= 0x1;
1597 writel(tmp, phy_mmio + MV5_PHY_CTL);
1598 }
1599
1600 tmp = readl(phy_mmio + MV5_PHY_MODE);
1601 tmp &= ~mask;
1602 tmp |= hpriv->signal[port].pre;
1603 tmp |= hpriv->signal[port].amps;
1604 writel(tmp, phy_mmio + MV5_PHY_MODE);
1605 }
1606
1607
1608 #undef ZERO
1609 #define ZERO(reg) writel(0, port_mmio + (reg))
1610 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1611 unsigned int port)
1612 {
1613 void __iomem *port_mmio = mv_port_base(mmio, port);
1614
1615 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1616
1617 mv_channel_reset(hpriv, mmio, port);
1618
1619 ZERO(0x028); /* command */
1620 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1621 ZERO(0x004); /* timer */
1622 ZERO(0x008); /* irq err cause */
1623 ZERO(0x00c); /* irq err mask */
1624 ZERO(0x010); /* rq bah */
1625 ZERO(0x014); /* rq inp */
1626 ZERO(0x018); /* rq outp */
1627 ZERO(0x01c); /* respq bah */
1628 ZERO(0x024); /* respq outp */
1629 ZERO(0x020); /* respq inp */
1630 ZERO(0x02c); /* test control */
1631 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1632 }
1633 #undef ZERO
1634
1635 #define ZERO(reg) writel(0, hc_mmio + (reg))
1636 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1637 unsigned int hc)
1638 {
1639 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1640 u32 tmp;
1641
1642 ZERO(0x00c);
1643 ZERO(0x010);
1644 ZERO(0x014);
1645 ZERO(0x018);
1646
1647 tmp = readl(hc_mmio + 0x20);
1648 tmp &= 0x1c1c1c1c;
1649 tmp |= 0x03030303;
1650 writel(tmp, hc_mmio + 0x20);
1651 }
1652 #undef ZERO
1653
1654 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1655 unsigned int n_hc)
1656 {
1657 unsigned int hc, port;
1658
1659 for (hc = 0; hc < n_hc; hc++) {
1660 for (port = 0; port < MV_PORTS_PER_HC; port++)
1661 mv5_reset_hc_port(hpriv, mmio,
1662 (hc * MV_PORTS_PER_HC) + port);
1663
1664 mv5_reset_one_hc(hpriv, mmio, hc);
1665 }
1666
1667 return 0;
1668 }
1669
1670 #undef ZERO
1671 #define ZERO(reg) writel(0, mmio + (reg))
1672 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1673 {
1674 u32 tmp;
1675
1676 tmp = readl(mmio + MV_PCI_MODE);
1677 tmp &= 0xff00ffff;
1678 writel(tmp, mmio + MV_PCI_MODE);
1679
1680 ZERO(MV_PCI_DISC_TIMER);
1681 ZERO(MV_PCI_MSI_TRIGGER);
1682 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1683 ZERO(HC_MAIN_IRQ_MASK_OFS);
1684 ZERO(MV_PCI_SERR_MASK);
1685 ZERO(PCI_IRQ_CAUSE_OFS);
1686 ZERO(PCI_IRQ_MASK_OFS);
1687 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1688 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1689 ZERO(MV_PCI_ERR_ATTRIBUTE);
1690 ZERO(MV_PCI_ERR_COMMAND);
1691 }
1692 #undef ZERO
1693
1694 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1695 {
1696 u32 tmp;
1697
1698 mv5_reset_flash(hpriv, mmio);
1699
1700 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1701 tmp &= 0x3;
1702 tmp |= (1 << 5) | (1 << 6);
1703 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1704 }
1705
1706 /**
1707 * mv6_reset_hc - Perform the 6xxx global soft reset
1708 * @mmio: base address of the HBA
1709 *
1710 * This routine only applies to 6xxx parts.
1711 *
1712 * LOCKING:
1713 * Inherited from caller.
1714 */
1715 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1716 unsigned int n_hc)
1717 {
1718 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1719 int i, rc = 0;
1720 u32 t;
1721
1722 /* Following procedure defined in PCI "main command and status
1723 * register" table.
1724 */
1725 t = readl(reg);
1726 writel(t | STOP_PCI_MASTER, reg);
1727
1728 for (i = 0; i < 1000; i++) {
1729 udelay(1);
1730 t = readl(reg);
1731 if (PCI_MASTER_EMPTY & t) {
1732 break;
1733 }
1734 }
1735 if (!(PCI_MASTER_EMPTY & t)) {
1736 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1737 rc = 1;
1738 goto done;
1739 }
1740
1741 /* set reset */
1742 i = 5;
1743 do {
1744 writel(t | GLOB_SFT_RST, reg);
1745 t = readl(reg);
1746 udelay(1);
1747 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1748
1749 if (!(GLOB_SFT_RST & t)) {
1750 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1751 rc = 1;
1752 goto done;
1753 }
1754
1755 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1756 i = 5;
1757 do {
1758 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1759 t = readl(reg);
1760 udelay(1);
1761 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1762
1763 if (GLOB_SFT_RST & t) {
1764 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1765 rc = 1;
1766 }
1767 done:
1768 return rc;
1769 }
1770
1771 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
1772 void __iomem *mmio)
1773 {
1774 void __iomem *port_mmio;
1775 u32 tmp;
1776
1777 tmp = readl(mmio + MV_RESET_CFG);
1778 if ((tmp & (1 << 0)) == 0) {
1779 hpriv->signal[idx].amps = 0x7 << 8;
1780 hpriv->signal[idx].pre = 0x1 << 5;
1781 return;
1782 }
1783
1784 port_mmio = mv_port_base(mmio, idx);
1785 tmp = readl(port_mmio + PHY_MODE2);
1786
1787 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1788 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1789 }
1790
1791 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1792 {
1793 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
1794 }
1795
1796 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1797 unsigned int port)
1798 {
1799 void __iomem *port_mmio = mv_port_base(mmio, port);
1800
1801 u32 hp_flags = hpriv->hp_flags;
1802 int fix_phy_mode2 =
1803 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1804 int fix_phy_mode4 =
1805 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1806 u32 m2, tmp;
1807
1808 if (fix_phy_mode2) {
1809 m2 = readl(port_mmio + PHY_MODE2);
1810 m2 &= ~(1 << 16);
1811 m2 |= (1 << 31);
1812 writel(m2, port_mmio + PHY_MODE2);
1813
1814 udelay(200);
1815
1816 m2 = readl(port_mmio + PHY_MODE2);
1817 m2 &= ~((1 << 16) | (1 << 31));
1818 writel(m2, port_mmio + PHY_MODE2);
1819
1820 udelay(200);
1821 }
1822
1823 /* who knows what this magic does */
1824 tmp = readl(port_mmio + PHY_MODE3);
1825 tmp &= ~0x7F800000;
1826 tmp |= 0x2A800000;
1827 writel(tmp, port_mmio + PHY_MODE3);
1828
1829 if (fix_phy_mode4) {
1830 u32 m4;
1831
1832 m4 = readl(port_mmio + PHY_MODE4);
1833
1834 if (hp_flags & MV_HP_ERRATA_60X1B2)
1835 tmp = readl(port_mmio + 0x310);
1836
1837 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1838
1839 writel(m4, port_mmio + PHY_MODE4);
1840
1841 if (hp_flags & MV_HP_ERRATA_60X1B2)
1842 writel(tmp, port_mmio + 0x310);
1843 }
1844
1845 /* Revert values of pre-emphasis and signal amps to the saved ones */
1846 m2 = readl(port_mmio + PHY_MODE2);
1847
1848 m2 &= ~MV_M2_PREAMP_MASK;
1849 m2 |= hpriv->signal[port].amps;
1850 m2 |= hpriv->signal[port].pre;
1851 m2 &= ~(1 << 16);
1852
1853 /* according to mvSata 3.6.1, some IIE values are fixed */
1854 if (IS_GEN_IIE(hpriv)) {
1855 m2 &= ~0xC30FF01F;
1856 m2 |= 0x0000900F;
1857 }
1858
1859 writel(m2, port_mmio + PHY_MODE2);
1860 }
1861
1862 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1863 unsigned int port_no)
1864 {
1865 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1866
1867 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1868
1869 if (IS_60XX(hpriv)) {
1870 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
1871 ifctl |= (1 << 12) | (1 << 7);
1872 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1873 }
1874
1875 udelay(25); /* allow reset propagation */
1876
1877 /* Spec never mentions clearing the bit. Marvell's driver does
1878 * clear the bit, however.
1879 */
1880 writelfl(0, port_mmio + EDMA_CMD_OFS);
1881
1882 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1883
1884 if (IS_50XX(hpriv))
1885 mdelay(1);
1886 }
1887
1888 static void mv_stop_and_reset(struct ata_port *ap)
1889 {
1890 struct mv_host_priv *hpriv = ap->host_set->private_data;
1891 void __iomem *mmio = ap->host_set->mmio_base;
1892
1893 mv_stop_dma(ap);
1894
1895 mv_channel_reset(hpriv, mmio, ap->port_no);
1896
1897 __mv_phy_reset(ap, 0);
1898 }
1899
1900 static inline void __msleep(unsigned int msec, int can_sleep)
1901 {
1902 if (can_sleep)
1903 msleep(msec);
1904 else
1905 mdelay(msec);
1906 }
1907
1908 /**
1909 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
1910 * @ap: ATA channel to manipulate
1911 *
1912 * Part of this is taken from __sata_phy_reset and modified to
1913 * not sleep since this routine gets called from interrupt level.
1914 *
1915 * LOCKING:
1916 * Inherited from caller. This is coded to safe to call at
1917 * interrupt level, i.e. it does not sleep.
1918 */
1919 static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
1920 {
1921 struct mv_port_priv *pp = ap->private_data;
1922 struct mv_host_priv *hpriv = ap->host_set->private_data;
1923 void __iomem *port_mmio = mv_ap_base(ap);
1924 struct ata_taskfile tf;
1925 struct ata_device *dev = &ap->device[0];
1926 unsigned long timeout;
1927 int retry = 5;
1928 u32 sstatus;
1929
1930 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1931
1932 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1933 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1934 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1935
1936 /* Issue COMRESET via SControl */
1937 comreset_retry:
1938 scr_write_flush(ap, SCR_CONTROL, 0x301);
1939 __msleep(1, can_sleep);
1940
1941 scr_write_flush(ap, SCR_CONTROL, 0x300);
1942 __msleep(20, can_sleep);
1943
1944 timeout = jiffies + msecs_to_jiffies(200);
1945 do {
1946 sstatus = scr_read(ap, SCR_STATUS) & 0x3;
1947 if ((sstatus == 3) || (sstatus == 0))
1948 break;
1949
1950 __msleep(1, can_sleep);
1951 } while (time_before(jiffies, timeout));
1952
1953 /* work around errata */
1954 if (IS_60XX(hpriv) &&
1955 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1956 (retry-- > 0))
1957 goto comreset_retry;
1958
1959 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1960 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1961 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1962
1963 if (sata_dev_present(ap)) {
1964 ata_port_probe(ap);
1965 } else {
1966 printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n",
1967 ap->id, scr_read(ap, SCR_STATUS));
1968 ata_port_disable(ap);
1969 return;
1970 }
1971 ap->cbl = ATA_CBL_SATA;
1972
1973 /* even after SStatus reflects that device is ready,
1974 * it seems to take a while for link to be fully
1975 * established (and thus Status no longer 0x80/0x7F),
1976 * so we poll a bit for that, here.
1977 */
1978 retry = 20;
1979 while (1) {
1980 u8 drv_stat = ata_check_status(ap);
1981 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1982 break;
1983 __msleep(500, can_sleep);
1984 if (retry-- <= 0)
1985 break;
1986 }
1987
1988 tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr);
1989 tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr);
1990 tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr);
1991 tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr);
1992
1993 dev->class = ata_dev_classify(&tf);
1994 if (!ata_dev_present(dev)) {
1995 VPRINTK("Port disabled post-sig: No device present.\n");
1996 ata_port_disable(ap);
1997 }
1998
1999 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2000
2001 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2002
2003 VPRINTK("EXIT\n");
2004 }
2005
2006 static void mv_phy_reset(struct ata_port *ap)
2007 {
2008 __mv_phy_reset(ap, 1);
2009 }
2010
2011 /**
2012 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
2013 * @ap: ATA channel to manipulate
2014 *
2015 * Intent is to clear all pending error conditions, reset the
2016 * chip/bus, fail the command, and move on.
2017 *
2018 * LOCKING:
2019 * This routine holds the host_set lock while failing the command.
2020 */
2021 static void mv_eng_timeout(struct ata_port *ap)
2022 {
2023 struct ata_queued_cmd *qc;
2024
2025 printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id);
2026 DPRINTK("All regs @ start of eng_timeout\n");
2027 mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no,
2028 to_pci_dev(ap->host_set->dev));
2029
2030 qc = ata_qc_from_tag(ap, ap->active_tag);
2031 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
2032 ap->host_set->mmio_base, ap, qc, qc->scsicmd,
2033 &qc->scsicmd->cmnd);
2034
2035 mv_err_intr(ap);
2036 mv_stop_and_reset(ap);
2037
2038 qc->err_mask |= AC_ERR_TIMEOUT;
2039 ata_eh_qc_complete(qc);
2040 }
2041
2042 /**
2043 * mv_port_init - Perform some early initialization on a single port.
2044 * @port: libata data structure storing shadow register addresses
2045 * @port_mmio: base address of the port
2046 *
2047 * Initialize shadow register mmio addresses, clear outstanding
2048 * interrupts on the port, and unmask interrupts for the future
2049 * start of the port.
2050 *
2051 * LOCKING:
2052 * Inherited from caller.
2053 */
2054 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
2055 {
2056 unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS;
2057 unsigned serr_ofs;
2058
2059 /* PIO related setup
2060 */
2061 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
2062 port->error_addr =
2063 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2064 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2065 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2066 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2067 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2068 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
2069 port->status_addr =
2070 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2071 /* special case: control/altstatus doesn't have ATA_REG_ address */
2072 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2073
2074 /* unused: */
2075 port->cmd_addr = port->bmdma_addr = port->scr_addr = 0;
2076
2077 /* Clear any currently outstanding port interrupt conditions */
2078 serr_ofs = mv_scr_offset(SCR_ERROR);
2079 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2080 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2081
2082 /* unmask all EDMA error interrupts */
2083 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
2084
2085 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
2086 readl(port_mmio + EDMA_CFG_OFS),
2087 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2088 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
2089 }
2090
2091 static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
2092 unsigned int board_idx)
2093 {
2094 u8 rev_id;
2095 u32 hp_flags = hpriv->hp_flags;
2096
2097 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2098
2099 switch(board_idx) {
2100 case chip_5080:
2101 hpriv->ops = &mv5xxx_ops;
2102 hp_flags |= MV_HP_50XX;
2103
2104 switch (rev_id) {
2105 case 0x1:
2106 hp_flags |= MV_HP_ERRATA_50XXB0;
2107 break;
2108 case 0x3:
2109 hp_flags |= MV_HP_ERRATA_50XXB2;
2110 break;
2111 default:
2112 dev_printk(KERN_WARNING, &pdev->dev,
2113 "Applying 50XXB2 workarounds to unknown rev\n");
2114 hp_flags |= MV_HP_ERRATA_50XXB2;
2115 break;
2116 }
2117 break;
2118
2119 case chip_504x:
2120 case chip_508x:
2121 hpriv->ops = &mv5xxx_ops;
2122 hp_flags |= MV_HP_50XX;
2123
2124 switch (rev_id) {
2125 case 0x0:
2126 hp_flags |= MV_HP_ERRATA_50XXB0;
2127 break;
2128 case 0x3:
2129 hp_flags |= MV_HP_ERRATA_50XXB2;
2130 break;
2131 default:
2132 dev_printk(KERN_WARNING, &pdev->dev,
2133 "Applying B2 workarounds to unknown rev\n");
2134 hp_flags |= MV_HP_ERRATA_50XXB2;
2135 break;
2136 }
2137 break;
2138
2139 case chip_604x:
2140 case chip_608x:
2141 hpriv->ops = &mv6xxx_ops;
2142
2143 switch (rev_id) {
2144 case 0x7:
2145 hp_flags |= MV_HP_ERRATA_60X1B2;
2146 break;
2147 case 0x9:
2148 hp_flags |= MV_HP_ERRATA_60X1C0;
2149 break;
2150 default:
2151 dev_printk(KERN_WARNING, &pdev->dev,
2152 "Applying B2 workarounds to unknown rev\n");
2153 hp_flags |= MV_HP_ERRATA_60X1B2;
2154 break;
2155 }
2156 break;
2157
2158 case chip_7042:
2159 case chip_6042:
2160 hpriv->ops = &mv6xxx_ops;
2161
2162 hp_flags |= MV_HP_GEN_IIE;
2163
2164 switch (rev_id) {
2165 case 0x0:
2166 hp_flags |= MV_HP_ERRATA_XX42A0;
2167 break;
2168 case 0x1:
2169 hp_flags |= MV_HP_ERRATA_60X1C0;
2170 break;
2171 default:
2172 dev_printk(KERN_WARNING, &pdev->dev,
2173 "Applying 60X1C0 workarounds to unknown rev\n");
2174 hp_flags |= MV_HP_ERRATA_60X1C0;
2175 break;
2176 }
2177 break;
2178
2179 default:
2180 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
2181 return 1;
2182 }
2183
2184 hpriv->hp_flags = hp_flags;
2185
2186 return 0;
2187 }
2188
2189 /**
2190 * mv_init_host - Perform some early initialization of the host.
2191 * @pdev: host PCI device
2192 * @probe_ent: early data struct representing the host
2193 *
2194 * If possible, do an early global reset of the host. Then do
2195 * our port init and clear/unmask all/relevant host interrupts.
2196 *
2197 * LOCKING:
2198 * Inherited from caller.
2199 */
2200 static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
2201 unsigned int board_idx)
2202 {
2203 int rc = 0, n_hc, port, hc;
2204 void __iomem *mmio = probe_ent->mmio_base;
2205 struct mv_host_priv *hpriv = probe_ent->private_data;
2206
2207 /* global interrupt mask */
2208 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2209
2210 rc = mv_chip_id(pdev, hpriv, board_idx);
2211 if (rc)
2212 goto done;
2213
2214 n_hc = mv_get_hc_count(probe_ent->host_flags);
2215 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
2216
2217 for (port = 0; port < probe_ent->n_ports; port++)
2218 hpriv->ops->read_preamp(hpriv, port, mmio);
2219
2220 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2221 if (rc)
2222 goto done;
2223
2224 hpriv->ops->reset_flash(hpriv, mmio);
2225 hpriv->ops->reset_bus(pdev, mmio);
2226 hpriv->ops->enable_leds(hpriv, mmio);
2227
2228 for (port = 0; port < probe_ent->n_ports; port++) {
2229 if (IS_60XX(hpriv)) {
2230 void __iomem *port_mmio = mv_port_base(mmio, port);
2231
2232 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
2233 ifctl |= (1 << 12);
2234 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2235 }
2236
2237 hpriv->ops->phy_errata(hpriv, mmio, port);
2238 }
2239
2240 for (port = 0; port < probe_ent->n_ports; port++) {
2241 void __iomem *port_mmio = mv_port_base(mmio, port);
2242 mv_port_init(&probe_ent->port[port], port_mmio);
2243 }
2244
2245 for (hc = 0; hc < n_hc; hc++) {
2246 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2247
2248 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2249 "(before clear)=0x%08x\n", hc,
2250 readl(hc_mmio + HC_CFG_OFS),
2251 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2252
2253 /* Clear any currently outstanding hc interrupt conditions */
2254 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
2255 }
2256
2257 /* Clear any currently outstanding host interrupt conditions */
2258 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
2259
2260 /* and unmask interrupt generation for host regs */
2261 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
2262 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
2263
2264 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2265 "PCI int cause/mask=0x%08x/0x%08x\n",
2266 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2267 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2268 readl(mmio + PCI_IRQ_CAUSE_OFS),
2269 readl(mmio + PCI_IRQ_MASK_OFS));
2270
2271 done:
2272 return rc;
2273 }
2274
2275 /**
2276 * mv_print_info - Dump key info to kernel log for perusal.
2277 * @probe_ent: early data struct representing the host
2278 *
2279 * FIXME: complete this.
2280 *
2281 * LOCKING:
2282 * Inherited from caller.
2283 */
2284 static void mv_print_info(struct ata_probe_ent *probe_ent)
2285 {
2286 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
2287 struct mv_host_priv *hpriv = probe_ent->private_data;
2288 u8 rev_id, scc;
2289 const char *scc_s;
2290
2291 /* Use this to determine the HW stepping of the chip so we know
2292 * what errata to workaround
2293 */
2294 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2295
2296 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2297 if (scc == 0)
2298 scc_s = "SCSI";
2299 else if (scc == 0x01)
2300 scc_s = "RAID";
2301 else
2302 scc_s = "unknown";
2303
2304 dev_printk(KERN_INFO, &pdev->dev,
2305 "%u slots %u ports %s mode IRQ via %s\n",
2306 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
2307 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2308 }
2309
2310 /**
2311 * mv_init_one - handle a positive probe of a Marvell host
2312 * @pdev: PCI device found
2313 * @ent: PCI device ID entry for the matched host
2314 *
2315 * LOCKING:
2316 * Inherited from caller.
2317 */
2318 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2319 {
2320 static int printed_version = 0;
2321 struct ata_probe_ent *probe_ent = NULL;
2322 struct mv_host_priv *hpriv;
2323 unsigned int board_idx = (unsigned int)ent->driver_data;
2324 void __iomem *mmio_base;
2325 int pci_dev_busy = 0, rc;
2326
2327 if (!printed_version++)
2328 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2329
2330 rc = pci_enable_device(pdev);
2331 if (rc) {
2332 return rc;
2333 }
2334
2335 rc = pci_request_regions(pdev, DRV_NAME);
2336 if (rc) {
2337 pci_dev_busy = 1;
2338 goto err_out;
2339 }
2340
2341 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
2342 if (probe_ent == NULL) {
2343 rc = -ENOMEM;
2344 goto err_out_regions;
2345 }
2346
2347 memset(probe_ent, 0, sizeof(*probe_ent));
2348 probe_ent->dev = pci_dev_to_dev(pdev);
2349 INIT_LIST_HEAD(&probe_ent->node);
2350
2351 mmio_base = pci_iomap(pdev, MV_PRIMARY_BAR, 0);
2352 if (mmio_base == NULL) {
2353 rc = -ENOMEM;
2354 goto err_out_free_ent;
2355 }
2356
2357 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
2358 if (!hpriv) {
2359 rc = -ENOMEM;
2360 goto err_out_iounmap;
2361 }
2362 memset(hpriv, 0, sizeof(*hpriv));
2363
2364 probe_ent->sht = mv_port_info[board_idx].sht;
2365 probe_ent->host_flags = mv_port_info[board_idx].host_flags;
2366 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
2367 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
2368 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
2369
2370 probe_ent->irq = pdev->irq;
2371 probe_ent->irq_flags = SA_SHIRQ;
2372 probe_ent->mmio_base = mmio_base;
2373 probe_ent->private_data = hpriv;
2374
2375 /* initialize adapter */
2376 rc = mv_init_host(pdev, probe_ent, board_idx);
2377 if (rc) {
2378 goto err_out_hpriv;
2379 }
2380
2381 /* Enable interrupts */
2382 if (msi && pci_enable_msi(pdev) == 0) {
2383 hpriv->hp_flags |= MV_HP_FLAG_MSI;
2384 } else {
2385 pci_intx(pdev, 1);
2386 }
2387
2388 mv_dump_pci_cfg(pdev, 0x68);
2389 mv_print_info(probe_ent);
2390
2391 if (ata_device_add(probe_ent) == 0) {
2392 rc = -ENODEV; /* No devices discovered */
2393 goto err_out_dev_add;
2394 }
2395
2396 kfree(probe_ent);
2397 return 0;
2398
2399 err_out_dev_add:
2400 if (MV_HP_FLAG_MSI & hpriv->hp_flags) {
2401 pci_disable_msi(pdev);
2402 } else {
2403 pci_intx(pdev, 0);
2404 }
2405 err_out_hpriv:
2406 kfree(hpriv);
2407 err_out_iounmap:
2408 pci_iounmap(pdev, mmio_base);
2409 err_out_free_ent:
2410 kfree(probe_ent);
2411 err_out_regions:
2412 pci_release_regions(pdev);
2413 err_out:
2414 if (!pci_dev_busy) {
2415 pci_disable_device(pdev);
2416 }
2417
2418 return rc;
2419 }
2420
2421 static int __init mv_init(void)
2422 {
2423 return pci_module_init(&mv_pci_driver);
2424 }
2425
2426 static void __exit mv_exit(void)
2427 {
2428 pci_unregister_driver(&mv_pci_driver);
2429 }
2430
2431 MODULE_AUTHOR("Brett Russ");
2432 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
2433 MODULE_LICENSE("GPL");
2434 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
2435 MODULE_VERSION(DRV_VERSION);
2436
2437 module_param(msi, int, 0444);
2438 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
2439
2440 module_init(mv_init);
2441 module_exit(mv_exit);
x86 "subsystem" repository