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ALSA: wss_lib: use wss detection code instead of ad1848 one
[linux-2.6/x86.git] / sound / isa / wss / wss_lib.c
bloba5602f515f4963a86b7f9f4d0054c531c65cb30f
1 /*
2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
3 * Routines for control of CS4231(A)/CS4232/InterWave & compatible chips
4 *
5 * Bugs:
6 * - sometimes record brokes playback with WSS portion of
7 * Yamaha OPL3-SA3 chip
8 * - CS4231 (GUS MAX) - still trouble with occasional noises
9 * - broken initialization?
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 */
26
27 #include <linux/delay.h>
28 #include <linux/pm.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/slab.h>
32 #include <linux/ioport.h>
33 #include <sound/core.h>
34 #include <sound/wss.h>
35 #include <sound/pcm_params.h>
36 #include <sound/tlv.h>
37
38 #include <asm/io.h>
39 #include <asm/dma.h>
40 #include <asm/irq.h>
41
42 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
43 MODULE_DESCRIPTION("Routines for control of CS4231(A)/CS4232/InterWave & compatible chips");
44 MODULE_LICENSE("GPL");
45
46 #if 0
47 #define SNDRV_DEBUG_MCE
48 #endif
49
50 /*
51 * Some variables
52 */
53
54 static unsigned char freq_bits[14] = {
55 /* 5510 */ 0x00 | CS4231_XTAL2,
56 /* 6620 */ 0x0E | CS4231_XTAL2,
57 /* 8000 */ 0x00 | CS4231_XTAL1,
58 /* 9600 */ 0x0E | CS4231_XTAL1,
59 /* 11025 */ 0x02 | CS4231_XTAL2,
60 /* 16000 */ 0x02 | CS4231_XTAL1,
61 /* 18900 */ 0x04 | CS4231_XTAL2,
62 /* 22050 */ 0x06 | CS4231_XTAL2,
63 /* 27042 */ 0x04 | CS4231_XTAL1,
64 /* 32000 */ 0x06 | CS4231_XTAL1,
65 /* 33075 */ 0x0C | CS4231_XTAL2,
66 /* 37800 */ 0x08 | CS4231_XTAL2,
67 /* 44100 */ 0x0A | CS4231_XTAL2,
68 /* 48000 */ 0x0C | CS4231_XTAL1
69 };
70
71 static unsigned int rates[14] = {
72 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
73 27042, 32000, 33075, 37800, 44100, 48000
74 };
75
76 static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
77 .count = ARRAY_SIZE(rates),
78 .list = rates,
79 .mask = 0,
80 };
81
82 static int snd_wss_xrate(struct snd_pcm_runtime *runtime)
83 {
84 return snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
85 &hw_constraints_rates);
86 }
87
88 static unsigned char snd_wss_original_image[32] =
89 {
90 0x00, /* 00/00 - lic */
91 0x00, /* 01/01 - ric */
92 0x9f, /* 02/02 - la1ic */
93 0x9f, /* 03/03 - ra1ic */
94 0x9f, /* 04/04 - la2ic */
95 0x9f, /* 05/05 - ra2ic */
96 0xbf, /* 06/06 - loc */
97 0xbf, /* 07/07 - roc */
98 0x20, /* 08/08 - pdfr */
99 CS4231_AUTOCALIB, /* 09/09 - ic */
100 0x00, /* 0a/10 - pc */
101 0x00, /* 0b/11 - ti */
102 CS4231_MODE2, /* 0c/12 - mi */
103 0xfc, /* 0d/13 - lbc */
104 0x00, /* 0e/14 - pbru */
105 0x00, /* 0f/15 - pbrl */
106 0x80, /* 10/16 - afei */
107 0x01, /* 11/17 - afeii */
108 0x9f, /* 12/18 - llic */
109 0x9f, /* 13/19 - rlic */
110 0x00, /* 14/20 - tlb */
111 0x00, /* 15/21 - thb */
112 0x00, /* 16/22 - la3mic/reserved */
113 0x00, /* 17/23 - ra3mic/reserved */
114 0x00, /* 18/24 - afs */
115 0x00, /* 19/25 - lamoc/version */
116 0xcf, /* 1a/26 - mioc */
117 0x00, /* 1b/27 - ramoc/reserved */
118 0x20, /* 1c/28 - cdfr */
119 0x00, /* 1d/29 - res4 */
120 0x00, /* 1e/30 - cbru */
121 0x00, /* 1f/31 - cbrl */
122 };
123
124 static unsigned char snd_opti93x_original_image[32] =
125 {
126 0x00, /* 00/00 - l_mixout_outctrl */
127 0x00, /* 01/01 - r_mixout_outctrl */
128 0x88, /* 02/02 - l_cd_inctrl */
129 0x88, /* 03/03 - r_cd_inctrl */
130 0x88, /* 04/04 - l_a1/fm_inctrl */
131 0x88, /* 05/05 - r_a1/fm_inctrl */
132 0x80, /* 06/06 - l_dac_inctrl */
133 0x80, /* 07/07 - r_dac_inctrl */
134 0x00, /* 08/08 - ply_dataform_reg */
135 0x00, /* 09/09 - if_conf */
136 0x00, /* 0a/10 - pin_ctrl */
137 0x00, /* 0b/11 - err_init_reg */
138 0x0a, /* 0c/12 - id_reg */
139 0x00, /* 0d/13 - reserved */
140 0x00, /* 0e/14 - ply_upcount_reg */
141 0x00, /* 0f/15 - ply_lowcount_reg */
142 0x88, /* 10/16 - reserved/l_a1_inctrl */
143 0x88, /* 11/17 - reserved/r_a1_inctrl */
144 0x88, /* 12/18 - l_line_inctrl */
145 0x88, /* 13/19 - r_line_inctrl */
146 0x88, /* 14/20 - l_mic_inctrl */
147 0x88, /* 15/21 - r_mic_inctrl */
148 0x80, /* 16/22 - l_out_outctrl */
149 0x80, /* 17/23 - r_out_outctrl */
150 0x00, /* 18/24 - reserved */
151 0x00, /* 19/25 - reserved */
152 0x00, /* 1a/26 - reserved */
153 0x00, /* 1b/27 - reserved */
154 0x00, /* 1c/28 - cap_dataform_reg */
155 0x00, /* 1d/29 - reserved */
156 0x00, /* 1e/30 - cap_upcount_reg */
157 0x00 /* 1f/31 - cap_lowcount_reg */
158 };
159
160 /*
161 * Basic I/O functions
162 */
163
164 static inline void wss_outb(struct snd_wss *chip, u8 offset, u8 val)
165 {
166 outb(val, chip->port + offset);
167 }
168
169 static inline u8 wss_inb(struct snd_wss *chip, u8 offset)
170 {
171 return inb(chip->port + offset);
172 }
173
174 static void snd_wss_wait(struct snd_wss *chip)
175 {
176 int timeout;
177
178 for (timeout = 250;
179 timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
180 timeout--)
181 udelay(100);
182 }
183
184 static void snd_wss_outm(struct snd_wss *chip, unsigned char reg,
185 unsigned char mask, unsigned char value)
186 {
187 unsigned char tmp = (chip->image[reg] & mask) | value;
188
189 snd_wss_wait(chip);
190 #ifdef CONFIG_SND_DEBUG
191 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
192 snd_printk("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
193 #endif
194 chip->image[reg] = tmp;
195 if (!chip->calibrate_mute) {
196 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
197 wmb();
198 wss_outb(chip, CS4231P(REG), tmp);
199 mb();
200 }
201 }
202
203 static void snd_wss_dout(struct snd_wss *chip, unsigned char reg,
204 unsigned char value)
205 {
206 int timeout;
207
208 for (timeout = 250;
209 timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
210 timeout--)
211 udelay(10);
212 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
213 wss_outb(chip, CS4231P(REG), value);
214 mb();
215 }
216
217 void snd_wss_out(struct snd_wss *chip, unsigned char reg, unsigned char value)
218 {
219 snd_wss_wait(chip);
220 #ifdef CONFIG_SND_DEBUG
221 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
222 snd_printk("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
223 #endif
224 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
225 wss_outb(chip, CS4231P(REG), value);
226 chip->image[reg] = value;
227 mb();
228 snd_printdd("codec out - reg 0x%x = 0x%x\n",
229 chip->mce_bit | reg, value);
230 }
231 EXPORT_SYMBOL(snd_wss_out);
232
233 unsigned char snd_wss_in(struct snd_wss *chip, unsigned char reg)
234 {
235 snd_wss_wait(chip);
236 #ifdef CONFIG_SND_DEBUG
237 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
238 snd_printk("in: auto calibration time out - reg = 0x%x\n", reg);
239 #endif
240 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
241 mb();
242 return wss_inb(chip, CS4231P(REG));
243 }
244 EXPORT_SYMBOL(snd_wss_in);
245
246 void snd_cs4236_ext_out(struct snd_wss *chip, unsigned char reg,
247 unsigned char val)
248 {
249 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
250 wss_outb(chip, CS4231P(REG),
251 reg | (chip->image[CS4236_EXT_REG] & 0x01));
252 wss_outb(chip, CS4231P(REG), val);
253 chip->eimage[CS4236_REG(reg)] = val;
254 #if 0
255 printk("ext out : reg = 0x%x, val = 0x%x\n", reg, val);
256 #endif
257 }
258 EXPORT_SYMBOL(snd_cs4236_ext_out);
259
260 unsigned char snd_cs4236_ext_in(struct snd_wss *chip, unsigned char reg)
261 {
262 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
263 wss_outb(chip, CS4231P(REG),
264 reg | (chip->image[CS4236_EXT_REG] & 0x01));
265 #if 1
266 return wss_inb(chip, CS4231P(REG));
267 #else
268 {
269 unsigned char res;
270 res = wss_inb(chip, CS4231P(REG));
271 printk("ext in : reg = 0x%x, val = 0x%x\n", reg, res);
272 return res;
273 }
274 #endif
275 }
276 EXPORT_SYMBOL(snd_cs4236_ext_in);
277
278 #if 0
279
280 static void snd_wss_debug(struct snd_wss *chip)
281 {
282 printk(KERN_DEBUG
283 "CS4231 REGS: INDEX = 0x%02x "
284 " STATUS = 0x%02x\n",
285 wss_inb(chip, CS4231P(REGSEL),
286 wss_inb(chip, CS4231P(STATUS)));
287 printk(KERN_DEBUG
288 " 0x00: left input = 0x%02x "
289 " 0x10: alt 1 (CFIG 2) = 0x%02x\n",
290 snd_wss_in(chip, 0x00),
291 snd_wss_in(chip, 0x10));
292 printk(KERN_DEBUG
293 " 0x01: right input = 0x%02x "
294 " 0x11: alt 2 (CFIG 3) = 0x%02x\n",
295 snd_wss_in(chip, 0x01),
296 snd_wss_in(chip, 0x11));
297 printk(KERN_DEBUG
298 " 0x02: GF1 left input = 0x%02x "
299 " 0x12: left line in = 0x%02x\n",
300 snd_wss_in(chip, 0x02),
301 snd_wss_in(chip, 0x12));
302 printk(KERN_DEBUG
303 " 0x03: GF1 right input = 0x%02x "
304 " 0x13: right line in = 0x%02x\n",
305 snd_wss_in(chip, 0x03),
306 snd_wss_in(chip, 0x13));
307 printk(KERN_DEBUG
308 " 0x04: CD left input = 0x%02x "
309 " 0x14: timer low = 0x%02x\n",
310 snd_wss_in(chip, 0x04),
311 snd_wss_in(chip, 0x14));
312 printk(KERN_DEBUG
313 " 0x05: CD right input = 0x%02x "
314 " 0x15: timer high = 0x%02x\n",
315 snd_wss_in(chip, 0x05),
316 snd_wss_in(chip, 0x15));
317 printk(KERN_DEBUG
318 " 0x06: left output = 0x%02x "
319 " 0x16: left MIC (PnP) = 0x%02x\n",
320 snd_wss_in(chip, 0x06),
321 snd_wss_in(chip, 0x16));
322 printk(KERN_DEBUG
323 " 0x07: right output = 0x%02x "
324 " 0x17: right MIC (PnP) = 0x%02x\n",
325 snd_wss_in(chip, 0x07),
326 snd_wss_in(chip, 0x17));
327 printk(KERN_DEBUG
328 " 0x08: playback format = 0x%02x "
329 " 0x18: IRQ status = 0x%02x\n",
330 snd_wss_in(chip, 0x08),
331 snd_wss_in(chip, 0x18));
332 printk(KERN_DEBUG
333 " 0x09: iface (CFIG 1) = 0x%02x "
334 " 0x19: left line out = 0x%02x\n",
335 snd_wss_in(chip, 0x09),
336 snd_wss_in(chip, 0x19));
337 printk(KERN_DEBUG
338 " 0x0a: pin control = 0x%02x "
339 " 0x1a: mono control = 0x%02x\n",
340 snd_wss_in(chip, 0x0a),
341 snd_wss_in(chip, 0x1a));
342 printk(KERN_DEBUG
343 " 0x0b: init & status = 0x%02x "
344 " 0x1b: right line out = 0x%02x\n",
345 snd_wss_in(chip, 0x0b),
346 snd_wss_in(chip, 0x1b));
347 printk(KERN_DEBUG
348 " 0x0c: revision & mode = 0x%02x "
349 " 0x1c: record format = 0x%02x\n",
350 snd_wss_in(chip, 0x0c),
351 snd_wss_in(chip, 0x1c));
352 printk(KERN_DEBUG
353 " 0x0d: loopback = 0x%02x "
354 " 0x1d: var freq (PnP) = 0x%02x\n",
355 snd_wss_in(chip, 0x0d),
356 snd_wss_in(chip, 0x1d));
357 printk(KERN_DEBUG
358 " 0x0e: ply upr count = 0x%02x "
359 " 0x1e: ply lwr count = 0x%02x\n",
360 snd_wss_in(chip, 0x0e),
361 snd_wss_in(chip, 0x1e));
362 printk(KERN_DEBUG
363 " 0x0f: rec upr count = 0x%02x "
364 " 0x1f: rec lwr count = 0x%02x\n",
365 snd_wss_in(chip, 0x0f),
366 snd_wss_in(chip, 0x1f));
367 }
368
369 #endif
370
371 /*
372 * CS4231 detection / MCE routines
373 */
374
375 static void snd_wss_busy_wait(struct snd_wss *chip)
376 {
377 int timeout;
378
379 /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
380 for (timeout = 5; timeout > 0; timeout--)
381 wss_inb(chip, CS4231P(REGSEL));
382 /* end of cleanup sequence */
383 for (timeout = 25000;
384 timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
385 timeout--)
386 udelay(10);
387 }
388
389 void snd_wss_mce_up(struct snd_wss *chip)
390 {
391 unsigned long flags;
392 int timeout;
393
394 snd_wss_wait(chip);
395 #ifdef CONFIG_SND_DEBUG
396 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
397 snd_printk("mce_up - auto calibration time out (0)\n");
398 #endif
399 spin_lock_irqsave(&chip->reg_lock, flags);
400 chip->mce_bit |= CS4231_MCE;
401 timeout = wss_inb(chip, CS4231P(REGSEL));
402 if (timeout == 0x80)
403 snd_printk("mce_up [0x%lx]: serious init problem - codec still busy\n", chip->port);
404 if (!(timeout & CS4231_MCE))
405 wss_outb(chip, CS4231P(REGSEL),
406 chip->mce_bit | (timeout & 0x1f));
407 spin_unlock_irqrestore(&chip->reg_lock, flags);
408 }
409 EXPORT_SYMBOL(snd_wss_mce_up);
410
411 void snd_wss_mce_down(struct snd_wss *chip)
412 {
413 unsigned long flags;
414 unsigned long end_time;
415 int timeout;
416 int hw_mask = WSS_HW_CS4231_MASK | WSS_HW_CS4232_MASK | WSS_HW_AD1848;
417
418 snd_wss_busy_wait(chip);
419
420 #ifdef CONFIG_SND_DEBUG
421 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
422 snd_printk("mce_down [0x%lx] - auto calibration time out (0)\n", (long)CS4231P(REGSEL));
423 #endif
424 spin_lock_irqsave(&chip->reg_lock, flags);
425 chip->mce_bit &= ~CS4231_MCE;
426 timeout = wss_inb(chip, CS4231P(REGSEL));
427 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
428 spin_unlock_irqrestore(&chip->reg_lock, flags);
429 if (timeout == 0x80)
430 snd_printk("mce_down [0x%lx]: serious init problem - codec still busy\n", chip->port);
431 if ((timeout & CS4231_MCE) == 0 || !(chip->hardware & hw_mask))
432 return;
433
434 /*
435 * Wait for (possible -- during init auto-calibration may not be set)
436 * calibration process to start. Needs upto 5 sample periods on AD1848
437 * which at the slowest possible rate of 5.5125 kHz means 907 us.
438 */
439 msleep(1);
440
441 snd_printdd("(1) jiffies = %lu\n", jiffies);
442
443 /* check condition up to 250 ms */
444 end_time = jiffies + msecs_to_jiffies(250);
445 while (snd_wss_in(chip, CS4231_TEST_INIT) &
446 CS4231_CALIB_IN_PROGRESS) {
447
448 if (time_after(jiffies, end_time)) {
449 snd_printk(KERN_ERR "mce_down - "
450 "auto calibration time out (2)\n");
451 return;
452 }
453 msleep(1);
454 }
455
456 snd_printdd("(2) jiffies = %lu\n", jiffies);
457
458 /* check condition up to 100 ms */
459 end_time = jiffies + msecs_to_jiffies(100);
460 while (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {
461 if (time_after(jiffies, end_time)) {
462 snd_printk(KERN_ERR "mce_down - auto calibration time out (3)\n");
463 return;
464 }
465 msleep(1);
466 }
467
468 snd_printdd("(3) jiffies = %lu\n", jiffies);
469 snd_printd("mce_down - exit = 0x%x\n", wss_inb(chip, CS4231P(REGSEL)));
470 }
471 EXPORT_SYMBOL(snd_wss_mce_down);
472
473 static unsigned int snd_wss_get_count(unsigned char format, unsigned int size)
474 {
475 switch (format & 0xe0) {
476 case CS4231_LINEAR_16:
477 case CS4231_LINEAR_16_BIG:
478 size >>= 1;
479 break;
480 case CS4231_ADPCM_16:
481 return size >> 2;
482 }
483 if (format & CS4231_STEREO)
484 size >>= 1;
485 return size;
486 }
487
488 static int snd_wss_trigger(struct snd_pcm_substream *substream,
489 int cmd)
490 {
491 struct snd_wss *chip = snd_pcm_substream_chip(substream);
492 int result = 0;
493 unsigned int what;
494 struct snd_pcm_substream *s;
495 int do_start;
496
497 switch (cmd) {
498 case SNDRV_PCM_TRIGGER_START:
499 case SNDRV_PCM_TRIGGER_RESUME:
500 do_start = 1; break;
501 case SNDRV_PCM_TRIGGER_STOP:
502 case SNDRV_PCM_TRIGGER_SUSPEND:
503 do_start = 0; break;
504 default:
505 return -EINVAL;
506 }
507
508 what = 0;
509 snd_pcm_group_for_each_entry(s, substream) {
510 if (s == chip->playback_substream) {
511 what |= CS4231_PLAYBACK_ENABLE;
512 snd_pcm_trigger_done(s, substream);
513 } else if (s == chip->capture_substream) {
514 what |= CS4231_RECORD_ENABLE;
515 snd_pcm_trigger_done(s, substream);
516 }
517 }
518 spin_lock(&chip->reg_lock);
519 if (do_start) {
520 chip->image[CS4231_IFACE_CTRL] |= what;
521 if (chip->trigger)
522 chip->trigger(chip, what, 1);
523 } else {
524 chip->image[CS4231_IFACE_CTRL] &= ~what;
525 if (chip->trigger)
526 chip->trigger(chip, what, 0);
527 }
528 snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
529 spin_unlock(&chip->reg_lock);
530 #if 0
531 snd_wss_debug(chip);
532 #endif
533 return result;
534 }
535
536 /*
537 * CODEC I/O
538 */
539
540 static unsigned char snd_wss_get_rate(unsigned int rate)
541 {
542 int i;
543
544 for (i = 0; i < ARRAY_SIZE(rates); i++)
545 if (rate == rates[i])
546 return freq_bits[i];
547 // snd_BUG();
548 return freq_bits[ARRAY_SIZE(rates) - 1];
549 }
550
551 static unsigned char snd_wss_get_format(struct snd_wss *chip,
552 int format,
553 int channels)
554 {
555 unsigned char rformat;
556
557 rformat = CS4231_LINEAR_8;
558 switch (format) {
559 case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break;
560 case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break;
561 case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break;
562 case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break;
563 case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break;
564 }
565 if (channels > 1)
566 rformat |= CS4231_STEREO;
567 #if 0
568 snd_printk("get_format: 0x%x (mode=0x%x)\n", format, mode);
569 #endif
570 return rformat;
571 }
572
573 static void snd_wss_calibrate_mute(struct snd_wss *chip, int mute)
574 {
575 unsigned long flags;
576
577 mute = mute ? 1 : 0;
578 spin_lock_irqsave(&chip->reg_lock, flags);
579 if (chip->calibrate_mute == mute) {
580 spin_unlock_irqrestore(&chip->reg_lock, flags);
581 return;
582 }
583 if (!mute) {
584 snd_wss_dout(chip, CS4231_LEFT_INPUT,
585 chip->image[CS4231_LEFT_INPUT]);
586 snd_wss_dout(chip, CS4231_RIGHT_INPUT,
587 chip->image[CS4231_RIGHT_INPUT]);
588 snd_wss_dout(chip, CS4231_LOOPBACK,
589 chip->image[CS4231_LOOPBACK]);
590 }
591 snd_wss_dout(chip, CS4231_AUX1_LEFT_INPUT,
592 mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
593 snd_wss_dout(chip, CS4231_AUX1_RIGHT_INPUT,
594 mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
595 snd_wss_dout(chip, CS4231_AUX2_LEFT_INPUT,
596 mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
597 snd_wss_dout(chip, CS4231_AUX2_RIGHT_INPUT,
598 mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
599 snd_wss_dout(chip, CS4231_LEFT_OUTPUT,
600 mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
601 snd_wss_dout(chip, CS4231_RIGHT_OUTPUT,
602 mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
603 if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
604 snd_wss_dout(chip, CS4231_LEFT_LINE_IN,
605 mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
606 snd_wss_dout(chip, CS4231_RIGHT_LINE_IN,
607 mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
608 snd_wss_dout(chip, CS4231_MONO_CTRL,
609 mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
610 }
611 if (chip->hardware == WSS_HW_INTERWAVE) {
612 snd_wss_dout(chip, CS4231_LEFT_MIC_INPUT,
613 mute ? 0x80 : chip->image[CS4231_LEFT_MIC_INPUT]);
614 snd_wss_dout(chip, CS4231_RIGHT_MIC_INPUT,
615 mute ? 0x80 : chip->image[CS4231_RIGHT_MIC_INPUT]);
616 snd_wss_dout(chip, CS4231_LINE_LEFT_OUTPUT,
617 mute ? 0x80 : chip->image[CS4231_LINE_LEFT_OUTPUT]);
618 snd_wss_dout(chip, CS4231_LINE_RIGHT_OUTPUT,
619 mute ? 0x80 : chip->image[CS4231_LINE_RIGHT_OUTPUT]);
620 }
621 chip->calibrate_mute = mute;
622 spin_unlock_irqrestore(&chip->reg_lock, flags);
623 }
624
625 static void snd_wss_playback_format(struct snd_wss *chip,
626 struct snd_pcm_hw_params *params,
627 unsigned char pdfr)
628 {
629 unsigned long flags;
630 int full_calib = 1;
631
632 mutex_lock(&chip->mce_mutex);
633 snd_wss_calibrate_mute(chip, 1);
634 if (chip->hardware == WSS_HW_CS4231A ||
635 (chip->hardware & WSS_HW_CS4232_MASK)) {
636 spin_lock_irqsave(&chip->reg_lock, flags);
637 if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (pdfr & 0x0f)) { /* rate is same? */
638 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
639 chip->image[CS4231_ALT_FEATURE_1] | 0x10);
640 chip->image[CS4231_PLAYBK_FORMAT] = pdfr;
641 snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
642 chip->image[CS4231_PLAYBK_FORMAT]);
643 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
644 chip->image[CS4231_ALT_FEATURE_1] &= ~0x10);
645 udelay(100); /* Fixes audible clicks at least on GUS MAX */
646 full_calib = 0;
647 }
648 spin_unlock_irqrestore(&chip->reg_lock, flags);
649 }
650 if (full_calib) {
651 snd_wss_mce_up(chip);
652 spin_lock_irqsave(&chip->reg_lock, flags);
653 if (chip->hardware != WSS_HW_INTERWAVE && !chip->single_dma) {
654 if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE)
655 pdfr = (pdfr & 0xf0) |
656 (chip->image[CS4231_REC_FORMAT] & 0x0f);
657 } else {
658 chip->image[CS4231_PLAYBK_FORMAT] = pdfr;
659 }
660 snd_wss_out(chip, CS4231_PLAYBK_FORMAT, pdfr);
661 spin_unlock_irqrestore(&chip->reg_lock, flags);
662 if (chip->hardware == WSS_HW_OPL3SA2)
663 udelay(100); /* this seems to help */
664 snd_wss_mce_down(chip);
665 }
666 snd_wss_calibrate_mute(chip, 0);
667 mutex_unlock(&chip->mce_mutex);
668 }
669
670 static void snd_wss_capture_format(struct snd_wss *chip,
671 struct snd_pcm_hw_params *params,
672 unsigned char cdfr)
673 {
674 unsigned long flags;
675 int full_calib = 1;
676
677 mutex_lock(&chip->mce_mutex);
678 snd_wss_calibrate_mute(chip, 1);
679 if (chip->hardware == WSS_HW_CS4231A ||
680 (chip->hardware & WSS_HW_CS4232_MASK)) {
681 spin_lock_irqsave(&chip->reg_lock, flags);
682 if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (cdfr & 0x0f) || /* rate is same? */
683 (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
684 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
685 chip->image[CS4231_ALT_FEATURE_1] | 0x20);
686 snd_wss_out(chip, CS4231_REC_FORMAT,
687 chip->image[CS4231_REC_FORMAT] = cdfr);
688 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
689 chip->image[CS4231_ALT_FEATURE_1] &= ~0x20);
690 full_calib = 0;
691 }
692 spin_unlock_irqrestore(&chip->reg_lock, flags);
693 }
694 if (full_calib) {
695 snd_wss_mce_up(chip);
696 spin_lock_irqsave(&chip->reg_lock, flags);
697 if (chip->hardware != WSS_HW_INTERWAVE &&
698 !(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
699 if (chip->single_dma)
700 snd_wss_out(chip, CS4231_PLAYBK_FORMAT, cdfr);
701 else
702 snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
703 (chip->image[CS4231_PLAYBK_FORMAT] & 0xf0) |
704 (cdfr & 0x0f));
705 spin_unlock_irqrestore(&chip->reg_lock, flags);
706 snd_wss_mce_down(chip);
707 snd_wss_mce_up(chip);
708 spin_lock_irqsave(&chip->reg_lock, flags);
709 }
710 if (chip->hardware & WSS_HW_AD1848_MASK)
711 snd_wss_out(chip, CS4231_PLAYBK_FORMAT, cdfr);
712 else
713 snd_wss_out(chip, CS4231_REC_FORMAT, cdfr);
714 spin_unlock_irqrestore(&chip->reg_lock, flags);
715 snd_wss_mce_down(chip);
716 }
717 snd_wss_calibrate_mute(chip, 0);
718 mutex_unlock(&chip->mce_mutex);
719 }
720
721 /*
722 * Timer interface
723 */
724
725 static unsigned long snd_wss_timer_resolution(struct snd_timer *timer)
726 {
727 struct snd_wss *chip = snd_timer_chip(timer);
728 if (chip->hardware & WSS_HW_CS4236B_MASK)
729 return 14467;
730 else
731 return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
732 }
733
734 static int snd_wss_timer_start(struct snd_timer *timer)
735 {
736 unsigned long flags;
737 unsigned int ticks;
738 struct snd_wss *chip = snd_timer_chip(timer);
739 spin_lock_irqsave(&chip->reg_lock, flags);
740 ticks = timer->sticks;
741 if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
742 (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
743 (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
744 chip->image[CS4231_TIMER_HIGH] = (unsigned char) (ticks >> 8);
745 snd_wss_out(chip, CS4231_TIMER_HIGH,
746 chip->image[CS4231_TIMER_HIGH]);
747 chip->image[CS4231_TIMER_LOW] = (unsigned char) ticks;
748 snd_wss_out(chip, CS4231_TIMER_LOW,
749 chip->image[CS4231_TIMER_LOW]);
750 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
751 chip->image[CS4231_ALT_FEATURE_1] |
752 CS4231_TIMER_ENABLE);
753 }
754 spin_unlock_irqrestore(&chip->reg_lock, flags);
755 return 0;
756 }
757
758 static int snd_wss_timer_stop(struct snd_timer *timer)
759 {
760 unsigned long flags;
761 struct snd_wss *chip = snd_timer_chip(timer);
762 spin_lock_irqsave(&chip->reg_lock, flags);
763 chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE;
764 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
765 chip->image[CS4231_ALT_FEATURE_1]);
766 spin_unlock_irqrestore(&chip->reg_lock, flags);
767 return 0;
768 }
769
770 static void snd_wss_init(struct snd_wss *chip)
771 {
772 unsigned long flags;
773
774 snd_wss_mce_down(chip);
775
776 #ifdef SNDRV_DEBUG_MCE
777 snd_printk("init: (1)\n");
778 #endif
779 snd_wss_mce_up(chip);
780 spin_lock_irqsave(&chip->reg_lock, flags);
781 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
782 CS4231_PLAYBACK_PIO |
783 CS4231_RECORD_ENABLE |
784 CS4231_RECORD_PIO |
785 CS4231_CALIB_MODE);
786 chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
787 snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
788 spin_unlock_irqrestore(&chip->reg_lock, flags);
789 snd_wss_mce_down(chip);
790
791 #ifdef SNDRV_DEBUG_MCE
792 snd_printk("init: (2)\n");
793 #endif
794
795 snd_wss_mce_up(chip);
796 spin_lock_irqsave(&chip->reg_lock, flags);
797 snd_wss_out(chip,
798 CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
799 spin_unlock_irqrestore(&chip->reg_lock, flags);
800 snd_wss_mce_down(chip);
801
802 #ifdef SNDRV_DEBUG_MCE
803 snd_printk("init: (3) - afei = 0x%x\n",
804 chip->image[CS4231_ALT_FEATURE_1]);
805 #endif
806
807 spin_lock_irqsave(&chip->reg_lock, flags);
808 snd_wss_out(chip, CS4231_ALT_FEATURE_2,
809 chip->image[CS4231_ALT_FEATURE_2]);
810 spin_unlock_irqrestore(&chip->reg_lock, flags);
811
812 snd_wss_mce_up(chip);
813 spin_lock_irqsave(&chip->reg_lock, flags);
814 snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
815 chip->image[CS4231_PLAYBK_FORMAT]);
816 spin_unlock_irqrestore(&chip->reg_lock, flags);
817 snd_wss_mce_down(chip);
818
819 #ifdef SNDRV_DEBUG_MCE
820 snd_printk("init: (4)\n");
821 #endif
822
823 snd_wss_mce_up(chip);
824 spin_lock_irqsave(&chip->reg_lock, flags);
825 if (!(chip->hardware & WSS_HW_AD1848_MASK))
826 snd_wss_out(chip, CS4231_REC_FORMAT,
827 chip->image[CS4231_REC_FORMAT]);
828 spin_unlock_irqrestore(&chip->reg_lock, flags);
829 snd_wss_mce_down(chip);
830
831 #ifdef SNDRV_DEBUG_MCE
832 snd_printk("init: (5)\n");
833 #endif
834 }
835
836 static int snd_wss_open(struct snd_wss *chip, unsigned int mode)
837 {
838 unsigned long flags;
839
840 mutex_lock(&chip->open_mutex);
841 if ((chip->mode & mode) ||
842 ((chip->mode & WSS_MODE_OPEN) && chip->single_dma)) {
843 mutex_unlock(&chip->open_mutex);
844 return -EAGAIN;
845 }
846 if (chip->mode & WSS_MODE_OPEN) {
847 chip->mode |= mode;
848 mutex_unlock(&chip->open_mutex);
849 return 0;
850 }
851 /* ok. now enable and ack CODEC IRQ */
852 spin_lock_irqsave(&chip->reg_lock, flags);
853 if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
854 snd_wss_out(chip, CS4231_IRQ_STATUS,
855 CS4231_PLAYBACK_IRQ |
856 CS4231_RECORD_IRQ |
857 CS4231_TIMER_IRQ);
858 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
859 }
860 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
861 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
862 chip->image[CS4231_PIN_CTRL] |= CS4231_IRQ_ENABLE;
863 snd_wss_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
864 if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
865 snd_wss_out(chip, CS4231_IRQ_STATUS,
866 CS4231_PLAYBACK_IRQ |
867 CS4231_RECORD_IRQ |
868 CS4231_TIMER_IRQ);
869 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
870 }
871 spin_unlock_irqrestore(&chip->reg_lock, flags);
872
873 chip->mode = mode;
874 mutex_unlock(&chip->open_mutex);
875 return 0;
876 }
877
878 static void snd_wss_close(struct snd_wss *chip, unsigned int mode)
879 {
880 unsigned long flags;
881
882 mutex_lock(&chip->open_mutex);
883 chip->mode &= ~mode;
884 if (chip->mode & WSS_MODE_OPEN) {
885 mutex_unlock(&chip->open_mutex);
886 return;
887 }
888 snd_wss_calibrate_mute(chip, 1);
889
890 /* disable IRQ */
891 spin_lock_irqsave(&chip->reg_lock, flags);
892 if (!(chip->hardware & WSS_HW_AD1848_MASK))
893 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
894 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
895 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
896 chip->image[CS4231_PIN_CTRL] &= ~CS4231_IRQ_ENABLE;
897 snd_wss_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
898
899 /* now disable record & playback */
900
901 if (chip->image[CS4231_IFACE_CTRL] & (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
902 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
903 spin_unlock_irqrestore(&chip->reg_lock, flags);
904 snd_wss_mce_up(chip);
905 spin_lock_irqsave(&chip->reg_lock, flags);
906 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
907 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
908 snd_wss_out(chip, CS4231_IFACE_CTRL,
909 chip->image[CS4231_IFACE_CTRL]);
910 spin_unlock_irqrestore(&chip->reg_lock, flags);
911 snd_wss_mce_down(chip);
912 spin_lock_irqsave(&chip->reg_lock, flags);
913 }
914
915 /* clear IRQ again */
916 if (!(chip->hardware & WSS_HW_AD1848_MASK))
917 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
918 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
919 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
920 spin_unlock_irqrestore(&chip->reg_lock, flags);
921
922 snd_wss_calibrate_mute(chip, 0);
923
924 chip->mode = 0;
925 mutex_unlock(&chip->open_mutex);
926 }
927
928 /*
929 * timer open/close
930 */
931
932 static int snd_wss_timer_open(struct snd_timer *timer)
933 {
934 struct snd_wss *chip = snd_timer_chip(timer);
935 snd_wss_open(chip, WSS_MODE_TIMER);
936 return 0;
937 }
938
939 static int snd_wss_timer_close(struct snd_timer *timer)
940 {
941 struct snd_wss *chip = snd_timer_chip(timer);
942 snd_wss_close(chip, WSS_MODE_TIMER);
943 return 0;
944 }
945
946 static struct snd_timer_hardware snd_wss_timer_table =
947 {
948 .flags = SNDRV_TIMER_HW_AUTO,
949 .resolution = 9945,
950 .ticks = 65535,
951 .open = snd_wss_timer_open,
952 .close = snd_wss_timer_close,
953 .c_resolution = snd_wss_timer_resolution,
954 .start = snd_wss_timer_start,
955 .stop = snd_wss_timer_stop,
956 };
957
958 /*
959 * ok.. exported functions..
960 */
961
962 static int snd_wss_playback_hw_params(struct snd_pcm_substream *substream,
963 struct snd_pcm_hw_params *hw_params)
964 {
965 struct snd_wss *chip = snd_pcm_substream_chip(substream);
966 unsigned char new_pdfr;
967 int err;
968
969 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
970 return err;
971 new_pdfr = snd_wss_get_format(chip, params_format(hw_params),
972 params_channels(hw_params)) |
973 snd_wss_get_rate(params_rate(hw_params));
974 chip->set_playback_format(chip, hw_params, new_pdfr);
975 return 0;
976 }
977
978 static int snd_wss_playback_hw_free(struct snd_pcm_substream *substream)
979 {
980 return snd_pcm_lib_free_pages(substream);
981 }
982
983 static int snd_wss_playback_prepare(struct snd_pcm_substream *substream)
984 {
985 struct snd_wss *chip = snd_pcm_substream_chip(substream);
986 struct snd_pcm_runtime *runtime = substream->runtime;
987 unsigned long flags;
988 unsigned int size = snd_pcm_lib_buffer_bytes(substream);
989 unsigned int count = snd_pcm_lib_period_bytes(substream);
990
991 spin_lock_irqsave(&chip->reg_lock, flags);
992 chip->p_dma_size = size;
993 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO);
994 snd_dma_program(chip->dma1, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT);
995 count = snd_wss_get_count(chip->image[CS4231_PLAYBK_FORMAT], count) - 1;
996 snd_wss_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
997 snd_wss_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));
998 spin_unlock_irqrestore(&chip->reg_lock, flags);
999 #if 0
1000 snd_wss_debug(chip);
1001 #endif
1002 return 0;
1003 }
1004
1005 static int snd_wss_capture_hw_params(struct snd_pcm_substream *substream,
1006 struct snd_pcm_hw_params *hw_params)
1007 {
1008 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1009 unsigned char new_cdfr;
1010 int err;
1011
1012 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1013 return err;
1014 new_cdfr = snd_wss_get_format(chip, params_format(hw_params),
1015 params_channels(hw_params)) |
1016 snd_wss_get_rate(params_rate(hw_params));
1017 chip->set_capture_format(chip, hw_params, new_cdfr);
1018 return 0;
1019 }
1020
1021 static int snd_wss_capture_hw_free(struct snd_pcm_substream *substream)
1022 {
1023 return snd_pcm_lib_free_pages(substream);
1024 }
1025
1026 static int snd_wss_capture_prepare(struct snd_pcm_substream *substream)
1027 {
1028 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1029 struct snd_pcm_runtime *runtime = substream->runtime;
1030 unsigned long flags;
1031 unsigned int size = snd_pcm_lib_buffer_bytes(substream);
1032 unsigned int count = snd_pcm_lib_period_bytes(substream);
1033
1034 spin_lock_irqsave(&chip->reg_lock, flags);
1035 chip->c_dma_size = size;
1036 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
1037 snd_dma_program(chip->dma2, runtime->dma_addr, size, DMA_MODE_READ | DMA_AUTOINIT);
1038 if (chip->hardware & WSS_HW_AD1848_MASK)
1039 count = snd_wss_get_count(chip->image[CS4231_PLAYBK_FORMAT],
1040 count);
1041 else
1042 count = snd_wss_get_count(chip->image[CS4231_REC_FORMAT],
1043 count);
1044 count--;
1045 if (chip->single_dma && chip->hardware != WSS_HW_INTERWAVE) {
1046 snd_wss_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
1047 snd_wss_out(chip, CS4231_PLY_UPR_CNT,
1048 (unsigned char) (count >> 8));
1049 } else {
1050 snd_wss_out(chip, CS4231_REC_LWR_CNT, (unsigned char) count);
1051 snd_wss_out(chip, CS4231_REC_UPR_CNT,
1052 (unsigned char) (count >> 8));
1053 }
1054 spin_unlock_irqrestore(&chip->reg_lock, flags);
1055 return 0;
1056 }
1057
1058 void snd_wss_overrange(struct snd_wss *chip)
1059 {
1060 unsigned long flags;
1061 unsigned char res;
1062
1063 spin_lock_irqsave(&chip->reg_lock, flags);
1064 res = snd_wss_in(chip, CS4231_TEST_INIT);
1065 spin_unlock_irqrestore(&chip->reg_lock, flags);
1066 if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */
1067 chip->capture_substream->runtime->overrange++;
1068 }
1069 EXPORT_SYMBOL(snd_wss_overrange);
1070
1071 irqreturn_t snd_wss_interrupt(int irq, void *dev_id)
1072 {
1073 struct snd_wss *chip = dev_id;
1074 unsigned char status;
1075
1076 if (chip->hardware & WSS_HW_AD1848_MASK)
1077 /* pretend it was the only possible irq for AD1848 */
1078 status = CS4231_PLAYBACK_IRQ;
1079 else
1080 status = snd_wss_in(chip, CS4231_IRQ_STATUS);
1081 if (status & CS4231_TIMER_IRQ) {
1082 if (chip->timer)
1083 snd_timer_interrupt(chip->timer, chip->timer->sticks);
1084 }
1085 if (chip->single_dma && chip->hardware != WSS_HW_INTERWAVE) {
1086 if (status & CS4231_PLAYBACK_IRQ) {
1087 if (chip->mode & WSS_MODE_PLAY) {
1088 if (chip->playback_substream)
1089 snd_pcm_period_elapsed(chip->playback_substream);
1090 }
1091 if (chip->mode & WSS_MODE_RECORD) {
1092 if (chip->capture_substream) {
1093 snd_wss_overrange(chip);
1094 snd_pcm_period_elapsed(chip->capture_substream);
1095 }
1096 }
1097 }
1098 } else {
1099 if (status & CS4231_PLAYBACK_IRQ) {
1100 if (chip->playback_substream)
1101 snd_pcm_period_elapsed(chip->playback_substream);
1102 }
1103 if (status & CS4231_RECORD_IRQ) {
1104 if (chip->capture_substream) {
1105 snd_wss_overrange(chip);
1106 snd_pcm_period_elapsed(chip->capture_substream);
1107 }
1108 }
1109 }
1110
1111 spin_lock(&chip->reg_lock);
1112 status = ~CS4231_ALL_IRQS | ~status;
1113 if (chip->hardware & WSS_HW_AD1848_MASK)
1114 wss_outb(chip, CS4231P(STATUS), 0);
1115 else
1116 snd_wss_outm(chip, CS4231_IRQ_STATUS, status, 0);
1117 spin_unlock(&chip->reg_lock);
1118 return IRQ_HANDLED;
1119 }
1120 EXPORT_SYMBOL(snd_wss_interrupt);
1121
1122 static snd_pcm_uframes_t snd_wss_playback_pointer(struct snd_pcm_substream *substream)
1123 {
1124 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1125 size_t ptr;
1126
1127 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
1128 return 0;
1129 ptr = snd_dma_pointer(chip->dma1, chip->p_dma_size);
1130 return bytes_to_frames(substream->runtime, ptr);
1131 }
1132
1133 static snd_pcm_uframes_t snd_wss_capture_pointer(struct snd_pcm_substream *substream)
1134 {
1135 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1136 size_t ptr;
1137
1138 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
1139 return 0;
1140 ptr = snd_dma_pointer(chip->dma2, chip->c_dma_size);
1141 return bytes_to_frames(substream->runtime, ptr);
1142 }
1143
1144 /*
1145
1146 */
1147
1148 static int snd_ad1848_probe(struct snd_wss *chip)
1149 {
1150 unsigned long flags;
1151 int i, id, rev, ad1847;
1152
1153 id = 0;
1154 ad1847 = 0;
1155 for (i = 0; i < 1000; i++) {
1156 mb();
1157 if (inb(chip->port + CS4231P(REGSEL)) & CS4231_INIT)
1158 msleep(1);
1159 else {
1160 spin_lock_irqsave(&chip->reg_lock, flags);
1161 snd_wss_out(chip, CS4231_MISC_INFO, 0x00);
1162 snd_wss_out(chip, CS4231_LEFT_INPUT, 0xaa);
1163 snd_wss_out(chip, CS4231_RIGHT_INPUT, 0x45);
1164 rev = snd_wss_in(chip, CS4231_RIGHT_INPUT);
1165 if (rev == 0x65) {
1166 spin_unlock_irqrestore(&chip->reg_lock, flags);
1167 id = 1;
1168 ad1847 = 1;
1169 break;
1170 }
1171 if (snd_wss_in(chip, CS4231_LEFT_INPUT) == 0xaa &&
1172 rev == 0x45) {
1173 spin_unlock_irqrestore(&chip->reg_lock, flags);
1174 id = 1;
1175 break;
1176 }
1177 spin_unlock_irqrestore(&chip->reg_lock, flags);
1178 }
1179 }
1180 if (id != 1)
1181 return -ENODEV; /* no valid device found */
1182 id = 0;
1183 if (chip->hardware == WSS_HW_DETECT)
1184 id = ad1847 ? WSS_HW_AD1847 : WSS_HW_AD1848;
1185
1186 spin_lock_irqsave(&chip->reg_lock, flags);
1187 inb(chip->port + CS4231P(STATUS)); /* clear any pendings IRQ */
1188 outb(0, chip->port + CS4231P(STATUS));
1189 mb();
1190 if (id == WSS_HW_AD1848) {
1191 /* check if there are more than 16 registers */
1192 rev = snd_wss_in(chip, CS4231_MISC_INFO);
1193 snd_wss_out(chip, CS4231_MISC_INFO, 0x40);
1194 for (i = 0; i < 16; ++i) {
1195 if (snd_wss_in(chip, i) != snd_wss_in(chip, i + 16)) {
1196 id = WSS_HW_CMI8330;
1197 break;
1198 }
1199 }
1200 snd_wss_out(chip, CS4231_MISC_INFO, 0x00);
1201 if (id != WSS_HW_CMI8330 && (rev & 0x80))
1202 id = WSS_HW_CS4248;
1203 if (id == WSS_HW_CMI8330 && (rev & 0x0f) != 0x0a)
1204 id = 0;
1205 }
1206 if (id == WSS_HW_CMI8330) {
1207 /* verify it is not CS4231 by changing the version register */
1208 /* on CMI8330 it is volume control register and can be set 0 */
1209 snd_wss_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
1210 snd_wss_dout(chip, CS4231_VERSION, 0x00);
1211 rev = snd_wss_in(chip, CS4231_VERSION) & 0xe7;
1212 if (rev)
1213 id = 0;
1214 snd_wss_out(chip, CS4231_MISC_INFO, 0);
1215 }
1216 if (id)
1217 chip->hardware = id;
1218
1219 spin_unlock_irqrestore(&chip->reg_lock, flags);
1220 return 0; /* all things are ok.. */
1221 }
1222
1223 static int snd_wss_probe(struct snd_wss *chip)
1224 {
1225 unsigned long flags;
1226 int i, id, rev, regnum;
1227 unsigned char *ptr;
1228 unsigned int hw;
1229
1230 id = snd_ad1848_probe(chip);
1231 if (id < 0)
1232 return id;
1233
1234 hw = chip->hardware;
1235 if ((hw & WSS_HW_TYPE_MASK) == WSS_HW_DETECT) {
1236 for (i = 0; i < 50; i++) {
1237 mb();
1238 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
1239 msleep(2);
1240 else {
1241 spin_lock_irqsave(&chip->reg_lock, flags);
1242 snd_wss_out(chip, CS4231_MISC_INFO,
1243 CS4231_MODE2);
1244 id = snd_wss_in(chip, CS4231_MISC_INFO) & 0x0f;
1245 spin_unlock_irqrestore(&chip->reg_lock, flags);
1246 if (id == 0x0a)
1247 break; /* this is valid value */
1248 }
1249 }
1250 snd_printdd("wss: port = 0x%lx, id = 0x%x\n", chip->port, id);
1251 if (id != 0x0a)
1252 return -ENODEV; /* no valid device found */
1253
1254 rev = snd_wss_in(chip, CS4231_VERSION) & 0xe7;
1255 snd_printdd("CS4231: VERSION (I25) = 0x%x\n", rev);
1256 if (rev == 0x80) {
1257 unsigned char tmp = snd_wss_in(chip, 23);
1258 snd_wss_out(chip, 23, ~tmp);
1259 if (snd_wss_in(chip, 23) != tmp)
1260 chip->hardware = WSS_HW_AD1845;
1261 else
1262 chip->hardware = WSS_HW_CS4231;
1263 } else if (rev == 0xa0) {
1264 chip->hardware = WSS_HW_CS4231A;
1265 } else if (rev == 0xa2) {
1266 chip->hardware = WSS_HW_CS4232;
1267 } else if (rev == 0xb2) {
1268 chip->hardware = WSS_HW_CS4232A;
1269 } else if (rev == 0x83) {
1270 chip->hardware = WSS_HW_CS4236;
1271 } else if (rev == 0x03) {
1272 chip->hardware = WSS_HW_CS4236B;
1273 } else {
1274 snd_printk("unknown CS chip with version 0x%x\n", rev);
1275 return -ENODEV; /* unknown CS4231 chip? */
1276 }
1277 }
1278 spin_lock_irqsave(&chip->reg_lock, flags);
1279 wss_inb(chip, CS4231P(STATUS)); /* clear any pendings IRQ */
1280 wss_outb(chip, CS4231P(STATUS), 0);
1281 mb();
1282 spin_unlock_irqrestore(&chip->reg_lock, flags);
1283
1284 if (!(chip->hardware & WSS_HW_AD1848_MASK))
1285 chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
1286 switch (chip->hardware) {
1287 case WSS_HW_INTERWAVE:
1288 chip->image[CS4231_MISC_INFO] = CS4231_IW_MODE3;
1289 break;
1290 case WSS_HW_CS4235:
1291 case WSS_HW_CS4236B:
1292 case WSS_HW_CS4237B:
1293 case WSS_HW_CS4238B:
1294 case WSS_HW_CS4239:
1295 if (hw == WSS_HW_DETECT3)
1296 chip->image[CS4231_MISC_INFO] = CS4231_4236_MODE3;
1297 else
1298 chip->hardware = WSS_HW_CS4236;
1299 break;
1300 }
1301
1302 chip->image[CS4231_IFACE_CTRL] =
1303 (chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA) |
1304 (chip->single_dma ? CS4231_SINGLE_DMA : 0);
1305 if (chip->hardware != WSS_HW_OPTI93X) {
1306 chip->image[CS4231_ALT_FEATURE_1] = 0x80;
1307 chip->image[CS4231_ALT_FEATURE_2] =
1308 chip->hardware == WSS_HW_INTERWAVE ? 0xc2 : 0x01;
1309 }
1310 ptr = (unsigned char *) &chip->image;
1311 regnum = (chip->hardware & WSS_HW_AD1848_MASK) ? 16 : 32;
1312 snd_wss_mce_down(chip);
1313 spin_lock_irqsave(&chip->reg_lock, flags);
1314 for (i = 0; i < regnum; i++) /* ok.. fill all registers */
1315 snd_wss_out(chip, i, *ptr++);
1316 spin_unlock_irqrestore(&chip->reg_lock, flags);
1317 snd_wss_mce_up(chip);
1318 snd_wss_mce_down(chip);
1319
1320 mdelay(2);
1321
1322 /* ok.. try check hardware version for CS4236+ chips */
1323 if ((hw & WSS_HW_TYPE_MASK) == WSS_HW_DETECT) {
1324 if (chip->hardware == WSS_HW_CS4236B) {
1325 rev = snd_cs4236_ext_in(chip, CS4236_VERSION);
1326 snd_cs4236_ext_out(chip, CS4236_VERSION, 0xff);
1327 id = snd_cs4236_ext_in(chip, CS4236_VERSION);
1328 snd_cs4236_ext_out(chip, CS4236_VERSION, rev);
1329 snd_printdd("CS4231: ext version; rev = 0x%x, id = 0x%x\n", rev, id);
1330 if ((id & 0x1f) == 0x1d) { /* CS4235 */
1331 chip->hardware = WSS_HW_CS4235;
1332 switch (id >> 5) {
1333 case 4:
1334 case 5:
1335 case 6:
1336 break;
1337 default:
1338 snd_printk("unknown CS4235 chip (enhanced version = 0x%x)\n", id);
1339 }
1340 } else if ((id & 0x1f) == 0x0b) { /* CS4236/B */
1341 switch (id >> 5) {
1342 case 4:
1343 case 5:
1344 case 6:
1345 case 7:
1346 chip->hardware = WSS_HW_CS4236B;
1347 break;
1348 default:
1349 snd_printk("unknown CS4236 chip (enhanced version = 0x%x)\n", id);
1350 }
1351 } else if ((id & 0x1f) == 0x08) { /* CS4237B */
1352 chip->hardware = WSS_HW_CS4237B;
1353 switch (id >> 5) {
1354 case 4:
1355 case 5:
1356 case 6:
1357 case 7:
1358 break;
1359 default:
1360 snd_printk("unknown CS4237B chip (enhanced version = 0x%x)\n", id);
1361 }
1362 } else if ((id & 0x1f) == 0x09) { /* CS4238B */
1363 chip->hardware = WSS_HW_CS4238B;
1364 switch (id >> 5) {
1365 case 5:
1366 case 6:
1367 case 7:
1368 break;
1369 default:
1370 snd_printk("unknown CS4238B chip (enhanced version = 0x%x)\n", id);
1371 }
1372 } else if ((id & 0x1f) == 0x1e) { /* CS4239 */
1373 chip->hardware = WSS_HW_CS4239;
1374 switch (id >> 5) {
1375 case 4:
1376 case 5:
1377 case 6:
1378 break;
1379 default:
1380 snd_printk("unknown CS4239 chip (enhanced version = 0x%x)\n", id);
1381 }
1382 } else {
1383 snd_printk("unknown CS4236/CS423xB chip (enhanced version = 0x%x)\n", id);
1384 }
1385 }
1386 }
1387 return 0; /* all things are ok.. */
1388 }
1389
1390 /*
1391
1392 */
1393
1394 static struct snd_pcm_hardware snd_wss_playback =
1395 {
1396 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1397 SNDRV_PCM_INFO_MMAP_VALID |
1398 SNDRV_PCM_INFO_RESUME |
1399 SNDRV_PCM_INFO_SYNC_START),
1400 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
1401 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
1402 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1403 .rate_min = 5510,
1404 .rate_max = 48000,
1405 .channels_min = 1,
1406 .channels_max = 2,
1407 .buffer_bytes_max = (128*1024),
1408 .period_bytes_min = 64,
1409 .period_bytes_max = (128*1024),
1410 .periods_min = 1,
1411 .periods_max = 1024,
1412 .fifo_size = 0,
1413 };
1414
1415 static struct snd_pcm_hardware snd_wss_capture =
1416 {
1417 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1418 SNDRV_PCM_INFO_MMAP_VALID |
1419 SNDRV_PCM_INFO_RESUME |
1420 SNDRV_PCM_INFO_SYNC_START),
1421 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
1422 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
1423 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1424 .rate_min = 5510,
1425 .rate_max = 48000,
1426 .channels_min = 1,
1427 .channels_max = 2,
1428 .buffer_bytes_max = (128*1024),
1429 .period_bytes_min = 64,
1430 .period_bytes_max = (128*1024),
1431 .periods_min = 1,
1432 .periods_max = 1024,
1433 .fifo_size = 0,
1434 };
1435
1436 /*
1437
1438 */
1439
1440 static int snd_wss_playback_open(struct snd_pcm_substream *substream)
1441 {
1442 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1443 struct snd_pcm_runtime *runtime = substream->runtime;
1444 int err;
1445
1446 runtime->hw = snd_wss_playback;
1447
1448 /* hardware limitation of older chipsets */
1449 if (chip->hardware & WSS_HW_AD1848_MASK)
1450 runtime->hw.formats &= ~(SNDRV_PCM_FMTBIT_IMA_ADPCM |
1451 SNDRV_PCM_FMTBIT_S16_BE);
1452
1453 /* hardware bug in InterWave chipset */
1454 if (chip->hardware == WSS_HW_INTERWAVE && chip->dma1 > 3)
1455 runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_MU_LAW;
1456
1457 /* hardware limitation of cheap chips */
1458 if (chip->hardware == WSS_HW_CS4235 ||
1459 chip->hardware == WSS_HW_CS4239)
1460 runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;
1461
1462 snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.buffer_bytes_max);
1463 snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.period_bytes_max);
1464
1465 if (chip->claim_dma) {
1466 if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma1)) < 0)
1467 return err;
1468 }
1469
1470 err = snd_wss_open(chip, WSS_MODE_PLAY);
1471 if (err < 0) {
1472 if (chip->release_dma)
1473 chip->release_dma(chip, chip->dma_private_data, chip->dma1);
1474 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1475 return err;
1476 }
1477 chip->playback_substream = substream;
1478 snd_pcm_set_sync(substream);
1479 chip->rate_constraint(runtime);
1480 return 0;
1481 }
1482
1483 static int snd_wss_capture_open(struct snd_pcm_substream *substream)
1484 {
1485 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1486 struct snd_pcm_runtime *runtime = substream->runtime;
1487 int err;
1488
1489 runtime->hw = snd_wss_capture;
1490
1491 /* hardware limitation of older chipsets */
1492 if (chip->hardware & WSS_HW_AD1848_MASK)
1493 runtime->hw.formats &= ~(SNDRV_PCM_FMTBIT_IMA_ADPCM |
1494 SNDRV_PCM_FMTBIT_S16_BE);
1495
1496 /* hardware limitation of cheap chips */
1497 if (chip->hardware == WSS_HW_CS4235 ||
1498 chip->hardware == WSS_HW_CS4239)
1499 runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;
1500
1501 snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.buffer_bytes_max);
1502 snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.period_bytes_max);
1503
1504 if (chip->claim_dma) {
1505 if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma2)) < 0)
1506 return err;
1507 }
1508
1509 err = snd_wss_open(chip, WSS_MODE_RECORD);
1510 if (err < 0) {
1511 if (chip->release_dma)
1512 chip->release_dma(chip, chip->dma_private_data, chip->dma2);
1513 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1514 return err;
1515 }
1516 chip->capture_substream = substream;
1517 snd_pcm_set_sync(substream);
1518 chip->rate_constraint(runtime);
1519 return 0;
1520 }
1521
1522 static int snd_wss_playback_close(struct snd_pcm_substream *substream)
1523 {
1524 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1525
1526 chip->playback_substream = NULL;
1527 snd_wss_close(chip, WSS_MODE_PLAY);
1528 return 0;
1529 }
1530
1531 static int snd_wss_capture_close(struct snd_pcm_substream *substream)
1532 {
1533 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1534
1535 chip->capture_substream = NULL;
1536 snd_wss_close(chip, WSS_MODE_RECORD);
1537 return 0;
1538 }
1539
1540 static void snd_wss_thinkpad_twiddle(struct snd_wss *chip, int on)
1541 {
1542 int tmp;
1543
1544 if (!chip->thinkpad_flag)
1545 return;
1546
1547 outb(0x1c, AD1848_THINKPAD_CTL_PORT1);
1548 tmp = inb(AD1848_THINKPAD_CTL_PORT2);
1549
1550 if (on)
1551 /* turn it on */
1552 tmp |= AD1848_THINKPAD_CS4248_ENABLE_BIT;
1553 else
1554 /* turn it off */
1555 tmp &= ~AD1848_THINKPAD_CS4248_ENABLE_BIT;
1556
1557 outb(tmp, AD1848_THINKPAD_CTL_PORT2);
1558 }
1559
1560 #ifdef CONFIG_PM
1561
1562 /* lowlevel suspend callback for CS4231 */
1563 static void snd_wss_suspend(struct snd_wss *chip)
1564 {
1565 int reg;
1566 unsigned long flags;
1567
1568 snd_pcm_suspend_all(chip->pcm);
1569 spin_lock_irqsave(&chip->reg_lock, flags);
1570 for (reg = 0; reg < 32; reg++)
1571 chip->image[reg] = snd_wss_in(chip, reg);
1572 spin_unlock_irqrestore(&chip->reg_lock, flags);
1573 if (chip->thinkpad_flag)
1574 snd_wss_thinkpad_twiddle(chip, 0);
1575 }
1576
1577 /* lowlevel resume callback for CS4231 */
1578 static void snd_wss_resume(struct snd_wss *chip)
1579 {
1580 int reg;
1581 unsigned long flags;
1582 /* int timeout; */
1583
1584 if (chip->thinkpad_flag)
1585 snd_wss_thinkpad_twiddle(chip, 1);
1586 snd_wss_mce_up(chip);
1587 spin_lock_irqsave(&chip->reg_lock, flags);
1588 for (reg = 0; reg < 32; reg++) {
1589 switch (reg) {
1590 case CS4231_VERSION:
1591 break;
1592 default:
1593 snd_wss_out(chip, reg, chip->image[reg]);
1594 break;
1595 }
1596 }
1597 spin_unlock_irqrestore(&chip->reg_lock, flags);
1598 #if 1
1599 snd_wss_mce_down(chip);
1600 #else
1601 /* The following is a workaround to avoid freeze after resume on TP600E.
1602 This is the first half of copy of snd_wss_mce_down(), but doesn't
1603 include rescheduling. -- iwai
1604 */
1605 snd_wss_busy_wait(chip);
1606 spin_lock_irqsave(&chip->reg_lock, flags);
1607 chip->mce_bit &= ~CS4231_MCE;
1608 timeout = wss_inb(chip, CS4231P(REGSEL));
1609 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
1610 spin_unlock_irqrestore(&chip->reg_lock, flags);
1611 if (timeout == 0x80)
1612 snd_printk("down [0x%lx]: serious init problem - codec still busy\n", chip->port);
1613 if ((timeout & CS4231_MCE) == 0 ||
1614 !(chip->hardware & (WSS_HW_CS4231_MASK | WSS_HW_CS4232_MASK))) {
1615 return;
1616 }
1617 snd_wss_busy_wait(chip);
1618 #endif
1619 }
1620 #endif /* CONFIG_PM */
1621
1622 static int snd_wss_free(struct snd_wss *chip)
1623 {
1624 release_and_free_resource(chip->res_port);
1625 release_and_free_resource(chip->res_cport);
1626 if (chip->irq >= 0) {
1627 disable_irq(chip->irq);
1628 if (!(chip->hwshare & WSS_HWSHARE_IRQ))
1629 free_irq(chip->irq, (void *) chip);
1630 }
1631 if (!(chip->hwshare & WSS_HWSHARE_DMA1) && chip->dma1 >= 0) {
1632 snd_dma_disable(chip->dma1);
1633 free_dma(chip->dma1);
1634 }
1635 if (!(chip->hwshare & WSS_HWSHARE_DMA2) &&
1636 chip->dma2 >= 0 && chip->dma2 != chip->dma1) {
1637 snd_dma_disable(chip->dma2);
1638 free_dma(chip->dma2);
1639 }
1640 if (chip->timer)
1641 snd_device_free(chip->card, chip->timer);
1642 kfree(chip);
1643 return 0;
1644 }
1645
1646 static int snd_wss_dev_free(struct snd_device *device)
1647 {
1648 struct snd_wss *chip = device->device_data;
1649 return snd_wss_free(chip);
1650 }
1651
1652 const char *snd_wss_chip_id(struct snd_wss *chip)
1653 {
1654 switch (chip->hardware) {
1655 case WSS_HW_CS4231:
1656 return "CS4231";
1657 case WSS_HW_CS4231A:
1658 return "CS4231A";
1659 case WSS_HW_CS4232:
1660 return "CS4232";
1661 case WSS_HW_CS4232A:
1662 return "CS4232A";
1663 case WSS_HW_CS4235:
1664 return "CS4235";
1665 case WSS_HW_CS4236:
1666 return "CS4236";
1667 case WSS_HW_CS4236B:
1668 return "CS4236B";
1669 case WSS_HW_CS4237B:
1670 return "CS4237B";
1671 case WSS_HW_CS4238B:
1672 return "CS4238B";
1673 case WSS_HW_CS4239:
1674 return "CS4239";
1675 case WSS_HW_INTERWAVE:
1676 return "AMD InterWave";
1677 case WSS_HW_OPL3SA2:
1678 return chip->card->shortname;
1679 case WSS_HW_AD1845:
1680 return "AD1845";
1681 case WSS_HW_OPTI93X:
1682 return "OPTi 93x";
1683 case WSS_HW_AD1847:
1684 return "AD1847";
1685 case WSS_HW_AD1848:
1686 return "AD1848";
1687 case WSS_HW_CS4248:
1688 return "CS4248";
1689 case WSS_HW_CMI8330:
1690 return "CMI8330/C3D";
1691 default:
1692 return "???";
1693 }
1694 }
1695 EXPORT_SYMBOL(snd_wss_chip_id);
1696
1697 static int snd_wss_new(struct snd_card *card,
1698 unsigned short hardware,
1699 unsigned short hwshare,
1700 struct snd_wss **rchip)
1701 {
1702 struct snd_wss *chip;
1703
1704 *rchip = NULL;
1705 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1706 if (chip == NULL)
1707 return -ENOMEM;
1708 chip->hardware = hardware;
1709 chip->hwshare = hwshare;
1710
1711 spin_lock_init(&chip->reg_lock);
1712 mutex_init(&chip->mce_mutex);
1713 mutex_init(&chip->open_mutex);
1714 chip->card = card;
1715 chip->rate_constraint = snd_wss_xrate;
1716 chip->set_playback_format = snd_wss_playback_format;
1717 chip->set_capture_format = snd_wss_capture_format;
1718 if (chip->hardware == WSS_HW_OPTI93X)
1719 memcpy(&chip->image, &snd_opti93x_original_image,
1720 sizeof(snd_opti93x_original_image));
1721 else
1722 memcpy(&chip->image, &snd_wss_original_image,
1723 sizeof(snd_wss_original_image));
1724 if (chip->hardware & WSS_HW_AD1848_MASK) {
1725 chip->image[CS4231_PIN_CTRL] = 0;
1726 chip->image[CS4231_TEST_INIT] = 0;
1727 }
1728
1729 *rchip = chip;
1730 return 0;
1731 }
1732
1733 int snd_wss_create(struct snd_card *card,
1734 unsigned long port,
1735 unsigned long cport,
1736 int irq, int dma1, int dma2,
1737 unsigned short hardware,
1738 unsigned short hwshare,
1739 struct snd_wss **rchip)
1740 {
1741 static struct snd_device_ops ops = {
1742 .dev_free = snd_wss_dev_free,
1743 };
1744 struct snd_wss *chip;
1745 int err;
1746
1747 err = snd_wss_new(card, hardware, hwshare, &chip);
1748 if (err < 0)
1749 return err;
1750
1751 chip->irq = -1;
1752 chip->dma1 = -1;
1753 chip->dma2 = -1;
1754
1755 chip->res_port = request_region(port, 4, "WSS");
1756 if (!chip->res_port) {
1757 snd_printk(KERN_ERR "wss: can't grab port 0x%lx\n", port);
1758 snd_wss_free(chip);
1759 return -EBUSY;
1760 }
1761 chip->port = port;
1762 if ((long)cport >= 0) {
1763 chip->res_cport = request_region(cport, 8, "CS4232 Control");
1764 if (!chip->res_cport) {
1765 snd_printk(KERN_ERR
1766 "wss: can't grab control port 0x%lx\n", cport);
1767 snd_wss_free(chip);
1768 return -ENODEV;
1769 }
1770 }
1771 chip->cport = cport;
1772 if (!(hwshare & WSS_HWSHARE_IRQ))
1773 if (request_irq(irq, snd_wss_interrupt, IRQF_DISABLED,
1774 "WSS", (void *) chip)) {
1775 snd_printk(KERN_ERR "wss: can't grab IRQ %d\n", irq);
1776 snd_wss_free(chip);
1777 return -EBUSY;
1778 }
1779 chip->irq = irq;
1780 if (!(hwshare & WSS_HWSHARE_DMA1) && request_dma(dma1, "WSS - 1")) {
1781 snd_printk(KERN_ERR "wss: can't grab DMA1 %d\n", dma1);
1782 snd_wss_free(chip);
1783 return -EBUSY;
1784 }
1785 chip->dma1 = dma1;
1786 if (!(hwshare & WSS_HWSHARE_DMA2) && dma1 != dma2 &&
1787 dma2 >= 0 && request_dma(dma2, "WSS - 2")) {
1788 snd_printk(KERN_ERR "wss: can't grab DMA2 %d\n", dma2);
1789 snd_wss_free(chip);
1790 return -EBUSY;
1791 }
1792 if (dma1 == dma2 || dma2 < 0) {
1793 chip->single_dma = 1;
1794 chip->dma2 = chip->dma1;
1795 } else
1796 chip->dma2 = dma2;
1797
1798 if (hardware == WSS_HW_THINKPAD) {
1799 chip->thinkpad_flag = 1;
1800 chip->hardware = WSS_HW_DETECT; /* reset */
1801 snd_wss_thinkpad_twiddle(chip, 1);
1802 }
1803
1804 /* global setup */
1805 if (snd_wss_probe(chip) < 0) {
1806 snd_wss_free(chip);
1807 return -ENODEV;
1808 }
1809 snd_wss_init(chip);
1810
1811 #if 0
1812 if (chip->hardware & WSS_HW_CS4232_MASK) {
1813 if (chip->res_cport == NULL)
1814 snd_printk("CS4232 control port features are not accessible\n");
1815 }
1816 #endif
1817
1818 /* Register device */
1819 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1820 if (err < 0) {
1821 snd_wss_free(chip);
1822 return err;
1823 }
1824
1825 #ifdef CONFIG_PM
1826 /* Power Management */
1827 chip->suspend = snd_wss_suspend;
1828 chip->resume = snd_wss_resume;
1829 #endif
1830
1831 *rchip = chip;
1832 return 0;
1833 }
1834 EXPORT_SYMBOL(snd_wss_create);
1835
1836 static struct snd_pcm_ops snd_wss_playback_ops = {
1837 .open = snd_wss_playback_open,
1838 .close = snd_wss_playback_close,
1839 .ioctl = snd_pcm_lib_ioctl,
1840 .hw_params = snd_wss_playback_hw_params,
1841 .hw_free = snd_wss_playback_hw_free,
1842 .prepare = snd_wss_playback_prepare,
1843 .trigger = snd_wss_trigger,
1844 .pointer = snd_wss_playback_pointer,
1845 };
1846
1847 static struct snd_pcm_ops snd_wss_capture_ops = {
1848 .open = snd_wss_capture_open,
1849 .close = snd_wss_capture_close,
1850 .ioctl = snd_pcm_lib_ioctl,
1851 .hw_params = snd_wss_capture_hw_params,
1852 .hw_free = snd_wss_capture_hw_free,
1853 .prepare = snd_wss_capture_prepare,
1854 .trigger = snd_wss_trigger,
1855 .pointer = snd_wss_capture_pointer,
1856 };
1857
1858 int snd_wss_pcm(struct snd_wss *chip, int device, struct snd_pcm **rpcm)
1859 {
1860 struct snd_pcm *pcm;
1861 int err;
1862
1863 err = snd_pcm_new(chip->card, "WSS", device, 1, 1, &pcm);
1864 if (err < 0)
1865 return err;
1866
1867 spin_lock_init(&chip->reg_lock);
1868 mutex_init(&chip->mce_mutex);
1869 mutex_init(&chip->open_mutex);
1870
1871 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_wss_playback_ops);
1872 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_wss_capture_ops);
1873
1874 /* global setup */
1875 pcm->private_data = chip;
1876 pcm->info_flags = 0;
1877 if (chip->single_dma)
1878 pcm->info_flags |= SNDRV_PCM_INFO_HALF_DUPLEX;
1879 if (chip->hardware != WSS_HW_INTERWAVE)
1880 pcm->info_flags |= SNDRV_PCM_INFO_JOINT_DUPLEX;
1881 strcpy(pcm->name, snd_wss_chip_id(chip));
1882
1883 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1884 snd_dma_isa_data(),
1885 64*1024, chip->dma1 > 3 || chip->dma2 > 3 ? 128*1024 : 64*1024);
1886
1887 chip->pcm = pcm;
1888 if (rpcm)
1889 *rpcm = pcm;
1890 return 0;
1891 }
1892 EXPORT_SYMBOL(snd_wss_pcm);
1893
1894 static void snd_wss_timer_free(struct snd_timer *timer)
1895 {
1896 struct snd_wss *chip = timer->private_data;
1897 chip->timer = NULL;
1898 }
1899
1900 int snd_wss_timer(struct snd_wss *chip, int device, struct snd_timer **rtimer)
1901 {
1902 struct snd_timer *timer;
1903 struct snd_timer_id tid;
1904 int err;
1905
1906 /* Timer initialization */
1907 tid.dev_class = SNDRV_TIMER_CLASS_CARD;
1908 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
1909 tid.card = chip->card->number;
1910 tid.device = device;
1911 tid.subdevice = 0;
1912 if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0)
1913 return err;
1914 strcpy(timer->name, snd_wss_chip_id(chip));
1915 timer->private_data = chip;
1916 timer->private_free = snd_wss_timer_free;
1917 timer->hw = snd_wss_timer_table;
1918 chip->timer = timer;
1919 if (rtimer)
1920 *rtimer = timer;
1921 return 0;
1922 }
1923 EXPORT_SYMBOL(snd_wss_timer);
1924
1925 /*
1926 * MIXER part
1927 */
1928
1929 static int snd_wss_info_mux(struct snd_kcontrol *kcontrol,
1930 struct snd_ctl_elem_info *uinfo)
1931 {
1932 static char *texts[4] = {
1933 "Line", "Aux", "Mic", "Mix"
1934 };
1935 static char *opl3sa_texts[4] = {
1936 "Line", "CD", "Mic", "Mix"
1937 };
1938 static char *gusmax_texts[4] = {
1939 "Line", "Synth", "Mic", "Mix"
1940 };
1941 char **ptexts = texts;
1942 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
1943
1944 snd_assert(chip->card != NULL, return -EINVAL);
1945 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1946 uinfo->count = 2;
1947 uinfo->value.enumerated.items = 4;
1948 if (uinfo->value.enumerated.item > 3)
1949 uinfo->value.enumerated.item = 3;
1950 if (!strcmp(chip->card->driver, "GUS MAX"))
1951 ptexts = gusmax_texts;
1952 switch (chip->hardware) {
1953 case WSS_HW_INTERWAVE:
1954 ptexts = gusmax_texts;
1955 break;
1956 case WSS_HW_OPL3SA2:
1957 ptexts = opl3sa_texts;
1958 break;
1959 }
1960 strcpy(uinfo->value.enumerated.name, ptexts[uinfo->value.enumerated.item]);
1961 return 0;
1962 }
1963
1964 static int snd_wss_get_mux(struct snd_kcontrol *kcontrol,
1965 struct snd_ctl_elem_value *ucontrol)
1966 {
1967 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
1968 unsigned long flags;
1969
1970 spin_lock_irqsave(&chip->reg_lock, flags);
1971 ucontrol->value.enumerated.item[0] = (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
1972 ucontrol->value.enumerated.item[1] = (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
1973 spin_unlock_irqrestore(&chip->reg_lock, flags);
1974 return 0;
1975 }
1976
1977 static int snd_wss_put_mux(struct snd_kcontrol *kcontrol,
1978 struct snd_ctl_elem_value *ucontrol)
1979 {
1980 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
1981 unsigned long flags;
1982 unsigned short left, right;
1983 int change;
1984
1985 if (ucontrol->value.enumerated.item[0] > 3 ||
1986 ucontrol->value.enumerated.item[1] > 3)
1987 return -EINVAL;
1988 left = ucontrol->value.enumerated.item[0] << 6;
1989 right = ucontrol->value.enumerated.item[1] << 6;
1990 spin_lock_irqsave(&chip->reg_lock, flags);
1991 left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
1992 right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
1993 change = left != chip->image[CS4231_LEFT_INPUT] ||
1994 right != chip->image[CS4231_RIGHT_INPUT];
1995 snd_wss_out(chip, CS4231_LEFT_INPUT, left);
1996 snd_wss_out(chip, CS4231_RIGHT_INPUT, right);
1997 spin_unlock_irqrestore(&chip->reg_lock, flags);
1998 return change;
1999 }
2000
2001 int snd_wss_info_single(struct snd_kcontrol *kcontrol,
2002 struct snd_ctl_elem_info *uinfo)
2003 {
2004 int mask = (kcontrol->private_value >> 16) & 0xff;
2005
2006 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2007 uinfo->count = 1;
2008 uinfo->value.integer.min = 0;
2009 uinfo->value.integer.max = mask;
2010 return 0;
2011 }
2012 EXPORT_SYMBOL(snd_wss_info_single);
2013
2014 int snd_wss_get_single(struct snd_kcontrol *kcontrol,
2015 struct snd_ctl_elem_value *ucontrol)
2016 {
2017 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2018 unsigned long flags;
2019 int reg = kcontrol->private_value & 0xff;
2020 int shift = (kcontrol->private_value >> 8) & 0xff;
2021 int mask = (kcontrol->private_value >> 16) & 0xff;
2022 int invert = (kcontrol->private_value >> 24) & 0xff;
2023
2024 spin_lock_irqsave(&chip->reg_lock, flags);
2025 ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
2026 spin_unlock_irqrestore(&chip->reg_lock, flags);
2027 if (invert)
2028 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
2029 return 0;
2030 }
2031 EXPORT_SYMBOL(snd_wss_get_single);
2032
2033 int snd_wss_put_single(struct snd_kcontrol *kcontrol,
2034 struct snd_ctl_elem_value *ucontrol)
2035 {
2036 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2037 unsigned long flags;
2038 int reg = kcontrol->private_value & 0xff;
2039 int shift = (kcontrol->private_value >> 8) & 0xff;
2040 int mask = (kcontrol->private_value >> 16) & 0xff;
2041 int invert = (kcontrol->private_value >> 24) & 0xff;
2042 int change;
2043 unsigned short val;
2044
2045 val = (ucontrol->value.integer.value[0] & mask);
2046 if (invert)
2047 val = mask - val;
2048 val <<= shift;
2049 spin_lock_irqsave(&chip->reg_lock, flags);
2050 val = (chip->image[reg] & ~(mask << shift)) | val;
2051 change = val != chip->image[reg];
2052 snd_wss_out(chip, reg, val);
2053 spin_unlock_irqrestore(&chip->reg_lock, flags);
2054 return change;
2055 }
2056 EXPORT_SYMBOL(snd_wss_put_single);
2057
2058 int snd_wss_info_double(struct snd_kcontrol *kcontrol,
2059 struct snd_ctl_elem_info *uinfo)
2060 {
2061 int mask = (kcontrol->private_value >> 24) & 0xff;
2062
2063 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2064 uinfo->count = 2;
2065 uinfo->value.integer.min = 0;
2066 uinfo->value.integer.max = mask;
2067 return 0;
2068 }
2069 EXPORT_SYMBOL(snd_wss_info_double);
2070
2071 int snd_wss_get_double(struct snd_kcontrol *kcontrol,
2072 struct snd_ctl_elem_value *ucontrol)
2073 {
2074 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2075 unsigned long flags;
2076 int left_reg = kcontrol->private_value & 0xff;
2077 int right_reg = (kcontrol->private_value >> 8) & 0xff;
2078 int shift_left = (kcontrol->private_value >> 16) & 0x07;
2079 int shift_right = (kcontrol->private_value >> 19) & 0x07;
2080 int mask = (kcontrol->private_value >> 24) & 0xff;
2081 int invert = (kcontrol->private_value >> 22) & 1;
2082
2083 spin_lock_irqsave(&chip->reg_lock, flags);
2084 ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
2085 ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
2086 spin_unlock_irqrestore(&chip->reg_lock, flags);
2087 if (invert) {
2088 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
2089 ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
2090 }
2091 return 0;
2092 }
2093 EXPORT_SYMBOL(snd_wss_get_double);
2094
2095 int snd_wss_put_double(struct snd_kcontrol *kcontrol,
2096 struct snd_ctl_elem_value *ucontrol)
2097 {
2098 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2099 unsigned long flags;
2100 int left_reg = kcontrol->private_value & 0xff;
2101 int right_reg = (kcontrol->private_value >> 8) & 0xff;
2102 int shift_left = (kcontrol->private_value >> 16) & 0x07;
2103 int shift_right = (kcontrol->private_value >> 19) & 0x07;
2104 int mask = (kcontrol->private_value >> 24) & 0xff;
2105 int invert = (kcontrol->private_value >> 22) & 1;
2106 int change;
2107 unsigned short val1, val2;
2108
2109 val1 = ucontrol->value.integer.value[0] & mask;
2110 val2 = ucontrol->value.integer.value[1] & mask;
2111 if (invert) {
2112 val1 = mask - val1;
2113 val2 = mask - val2;
2114 }
2115 val1 <<= shift_left;
2116 val2 <<= shift_right;
2117 spin_lock_irqsave(&chip->reg_lock, flags);
2118 if (left_reg != right_reg) {
2119 val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
2120 val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
2121 change = val1 != chip->image[left_reg] ||
2122 val2 != chip->image[right_reg];
2123 snd_wss_out(chip, left_reg, val1);
2124 snd_wss_out(chip, right_reg, val2);
2125 } else {
2126 mask = (mask << shift_left) | (mask << shift_right);
2127 val1 = (chip->image[left_reg] & ~mask) | val1 | val2;
2128 change = val1 != chip->image[left_reg];
2129 snd_wss_out(chip, left_reg, val1);
2130 }
2131 spin_unlock_irqrestore(&chip->reg_lock, flags);
2132 return change;
2133 }
2134 EXPORT_SYMBOL(snd_wss_put_double);
2135
2136 static const DECLARE_TLV_DB_SCALE(db_scale_6bit, -9450, 150, 0);
2137 static const DECLARE_TLV_DB_SCALE(db_scale_5bit_12db_max, -3450, 150, 0);
2138 static const DECLARE_TLV_DB_SCALE(db_scale_rec_gain, 0, 150, 0);
2139
2140 static struct snd_kcontrol_new snd_ad1848_controls[] = {
2141 WSS_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT,
2142 7, 7, 1, 1),
2143 WSS_DOUBLE_TLV("PCM Playback Volume", 0,
2144 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1,
2145 db_scale_6bit),
2146 WSS_DOUBLE("Aux Playback Switch", 0,
2147 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
2148 WSS_DOUBLE_TLV("Aux Playback Volume", 0,
2149 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1,
2150 db_scale_5bit_12db_max),
2151 WSS_DOUBLE("Aux Playback Switch", 1,
2152 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
2153 WSS_DOUBLE_TLV("Aux Playback Volume", 1,
2154 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1,
2155 db_scale_5bit_12db_max),
2156 WSS_DOUBLE_TLV("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT,
2157 0, 0, 15, 0, db_scale_rec_gain),
2158 {
2159 .name = "Capture Source",
2160 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2161 .info = snd_wss_info_mux,
2162 .get = snd_wss_get_mux,
2163 .put = snd_wss_put_mux,
2164 },
2165 WSS_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
2166 WSS_SINGLE_TLV("Loopback Capture Volume", 0, CS4231_LOOPBACK, 1, 63, 0,
2167 db_scale_6bit),
2168 };
2169
2170 static struct snd_kcontrol_new snd_wss_controls[] = {
2171 WSS_DOUBLE("PCM Playback Switch", 0,
2172 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
2173 WSS_DOUBLE("PCM Playback Volume", 0,
2174 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
2175 WSS_DOUBLE("Line Playback Switch", 0,
2176 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
2177 WSS_DOUBLE("Line Playback Volume", 0,
2178 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
2179 WSS_DOUBLE("Aux Playback Switch", 0,
2180 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
2181 WSS_DOUBLE("Aux Playback Volume", 0,
2182 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
2183 WSS_DOUBLE("Aux Playback Switch", 1,
2184 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
2185 WSS_DOUBLE("Aux Playback Volume", 1,
2186 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
2187 WSS_SINGLE("Mono Playback Switch", 0,
2188 CS4231_MONO_CTRL, 7, 1, 1),
2189 WSS_SINGLE("Mono Playback Volume", 0,
2190 CS4231_MONO_CTRL, 0, 15, 1),
2191 WSS_SINGLE("Mono Output Playback Switch", 0,
2192 CS4231_MONO_CTRL, 6, 1, 1),
2193 WSS_SINGLE("Mono Output Playback Bypass", 0,
2194 CS4231_MONO_CTRL, 5, 1, 0),
2195 WSS_DOUBLE("Capture Volume", 0,
2196 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
2197 {
2198 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2199 .name = "Capture Source",
2200 .info = snd_wss_info_mux,
2201 .get = snd_wss_get_mux,
2202 .put = snd_wss_put_mux,
2203 },
2204 WSS_DOUBLE("Mic Boost", 0,
2205 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
2206 WSS_SINGLE("Loopback Capture Switch", 0,
2207 CS4231_LOOPBACK, 0, 1, 0),
2208 WSS_SINGLE("Loopback Capture Volume", 0,
2209 CS4231_LOOPBACK, 2, 63, 1)
2210 };
2211
2212 static struct snd_kcontrol_new snd_opti93x_controls[] = {
2213 WSS_DOUBLE("Master Playback Switch", 0,
2214 OPTi93X_OUT_LEFT, OPTi93X_OUT_RIGHT, 7, 7, 1, 1),
2215 WSS_DOUBLE("Master Playback Volume", 0,
2216 OPTi93X_OUT_LEFT, OPTi93X_OUT_RIGHT, 1, 1, 31, 1),
2217 WSS_DOUBLE("PCM Playback Switch", 0,
2218 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
2219 WSS_DOUBLE("PCM Playback Volume", 0,
2220 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 31, 1),
2221 WSS_DOUBLE("FM Playback Switch", 0,
2222 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
2223 WSS_DOUBLE("FM Playback Volume", 0,
2224 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 1, 1, 15, 1),
2225 WSS_DOUBLE("Line Playback Switch", 0,
2226 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
2227 WSS_DOUBLE("Line Playback Volume", 0,
2228 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 15, 1),
2229 WSS_DOUBLE("Mic Playback Switch", 0,
2230 OPTi93X_MIC_LEFT_INPUT, OPTi93X_MIC_RIGHT_INPUT, 7, 7, 1, 1),
2231 WSS_DOUBLE("Mic Playback Volume", 0,
2232 OPTi93X_MIC_LEFT_INPUT, OPTi93X_MIC_RIGHT_INPUT, 1, 1, 15, 1),
2233 WSS_DOUBLE("Mic Boost", 0,
2234 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
2235 WSS_DOUBLE("CD Playback Switch", 0,
2236 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
2237 WSS_DOUBLE("CD Playback Volume", 0,
2238 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 1, 1, 15, 1),
2239 WSS_DOUBLE("Aux Playback Switch", 0,
2240 OPTi931_AUX_LEFT_INPUT, OPTi931_AUX_RIGHT_INPUT, 7, 7, 1, 1),
2241 WSS_DOUBLE("Aux Playback Volume", 0,
2242 OPTi931_AUX_LEFT_INPUT, OPTi931_AUX_RIGHT_INPUT, 1, 1, 15, 1),
2243 WSS_DOUBLE("Capture Volume", 0,
2244 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
2245 {
2246 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2247 .name = "Capture Source",
2248 .info = snd_wss_info_mux,
2249 .get = snd_wss_get_mux,
2250 .put = snd_wss_put_mux,
2251 }
2252 };
2253
2254 int snd_wss_mixer(struct snd_wss *chip)
2255 {
2256 struct snd_card *card;
2257 unsigned int idx;
2258 int err;
2259
2260 snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
2261
2262 card = chip->card;
2263
2264 strcpy(card->mixername, chip->pcm->name);
2265
2266 if (chip->hardware == WSS_HW_OPTI93X)
2267 for (idx = 0; idx < ARRAY_SIZE(snd_opti93x_controls); idx++) {
2268 err = snd_ctl_add(card,
2269 snd_ctl_new1(&snd_opti93x_controls[idx],
2270 chip));
2271 if (err < 0)
2272 return err;
2273 }
2274 else if (chip->hardware & WSS_HW_AD1848_MASK)
2275 for (idx = 0; idx < ARRAY_SIZE(snd_ad1848_controls); idx++) {
2276 err = snd_ctl_add(card,
2277 snd_ctl_new1(&snd_ad1848_controls[idx],
2278 chip));
2279 if (err < 0)
2280 return err;
2281 }
2282 else
2283 for (idx = 0; idx < ARRAY_SIZE(snd_wss_controls); idx++) {
2284 err = snd_ctl_add(card,
2285 snd_ctl_new1(&snd_wss_controls[idx],
2286 chip));
2287 if (err < 0)
2288 return err;
2289 }
2290 return 0;
2291 }
2292 EXPORT_SYMBOL(snd_wss_mixer);
2293
2294 const struct snd_pcm_ops *snd_wss_get_pcm_ops(int direction)
2295 {
2296 return direction == SNDRV_PCM_STREAM_PLAYBACK ?
2297 &snd_wss_playback_ops : &snd_wss_capture_ops;
2298 }
2299 EXPORT_SYMBOL(snd_wss_get_pcm_ops);
2300
2301 /*
2302 * INIT part
2303 */
2304
2305 static int __init alsa_wss_init(void)
2306 {
2307 return 0;
2308 }
2309
2310 static void __exit alsa_wss_exit(void)
2311 {
2312 }
2313
2314 module_init(alsa_wss_init);
2315 module_exit(alsa_wss_exit);
x86 "subsystem" repository