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Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
[linux-2.6/x86.git] / drivers / ata / pata_sis.c
blob66bd0e83ac07c64a0f5c635fd3c461b97b909206
1 /*
2 * pata_sis.c - SiS ATA driver
3 *
4 * (C) 2005 Red Hat <alan@redhat.com>
5 * (C) 2007 Bartlomiej Zolnierkiewicz
6 *
7 * Based upon linux/drivers/ide/pci/sis5513.c
8 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
9 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
10 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
11 * SiS Taiwan : for direct support and hardware.
12 * Daniela Engert : for initial ATA100 advices and numerous others.
13 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
14 * for checking code correctness, providing patches.
15 * Original tests and design on the SiS620 chipset.
16 * ATA100 tests and design on the SiS735 chipset.
17 * ATA16/33 support from specs
18 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
19 *
20 *
21 * TODO
22 * Check MWDMA on drives that don't support MWDMA speed pio cycles ?
23 * More Testing
24 */
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/blkdev.h>
31 #include <linux/delay.h>
32 #include <linux/device.h>
33 #include <scsi/scsi_host.h>
34 #include <linux/libata.h>
35 #include <linux/ata.h>
36 #include "sis.h"
37
38 #define DRV_NAME "pata_sis"
39 #define DRV_VERSION "0.5.2"
40
41 struct sis_chipset {
42 u16 device; /* PCI host ID */
43 const struct ata_port_info *info; /* Info block */
44 /* Probably add family, cable detect type etc here to clean
45 up code later */
46 };
47
48 struct sis_laptop {
49 u16 device;
50 u16 subvendor;
51 u16 subdevice;
52 };
53
54 static const struct sis_laptop sis_laptop[] = {
55 /* devid, subvendor, subdev */
56 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
57 /* end marker */
58 { 0, }
59 };
60
61 static int sis_short_ata40(struct pci_dev *dev)
62 {
63 const struct sis_laptop *lap = &sis_laptop[0];
64
65 while (lap->device) {
66 if (lap->device == dev->device &&
67 lap->subvendor == dev->subsystem_vendor &&
68 lap->subdevice == dev->subsystem_device)
69 return 1;
70 lap++;
71 }
72
73 return 0;
74 }
75
76 /**
77 * sis_old_port_base - return PCI configuration base for dev
78 * @adev: device
79 *
80 * Returns the base of the PCI configuration registers for this port
81 * number.
82 */
83
84 static int sis_old_port_base(struct ata_device *adev)
85 {
86 return 0x40 + (4 * adev->ap->port_no) + (2 * adev->devno);
87 }
88
89 /**
90 * sis_133_cable_detect - check for 40/80 pin
91 * @ap: Port
92 * @deadline: deadline jiffies for the operation
93 *
94 * Perform cable detection for the later UDMA133 capable
95 * SiS chipset.
96 */
97
98 static int sis_133_cable_detect(struct ata_port *ap)
99 {
100 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
101 u16 tmp;
102
103 /* The top bit of this register is the cable detect bit */
104 pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp);
105 if ((tmp & 0x8000) && !sis_short_ata40(pdev))
106 return ATA_CBL_PATA40;
107 return ATA_CBL_PATA80;
108 }
109
110 /**
111 * sis_66_cable_detect - check for 40/80 pin
112 * @ap: Port
113 * @deadline: deadline jiffies for the operation
114 *
115 * Perform cable detection on the UDMA66, UDMA100 and early UDMA133
116 * SiS IDE controllers.
117 */
118
119 static int sis_66_cable_detect(struct ata_port *ap)
120 {
121 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
122 u8 tmp;
123
124 /* Older chips keep cable detect in bits 4/5 of reg 0x48 */
125 pci_read_config_byte(pdev, 0x48, &tmp);
126 tmp >>= ap->port_no;
127 if ((tmp & 0x10) && !sis_short_ata40(pdev))
128 return ATA_CBL_PATA40;
129 return ATA_CBL_PATA80;
130 }
131
132
133 /**
134 * sis_pre_reset - probe begin
135 * @ap: ATA port
136 * @deadline: deadline jiffies for the operation
137 *
138 * Set up cable type and use generic probe init
139 */
140
141 static int sis_pre_reset(struct ata_port *ap, unsigned long deadline)
142 {
143 static const struct pci_bits sis_enable_bits[] = {
144 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
145 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
146 };
147
148 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
149
150 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no]))
151 return -ENOENT;
152
153 /* Clear the FIFO settings. We can't enable the FIFO until
154 we know we are poking at a disk */
155 pci_write_config_byte(pdev, 0x4B, 0);
156 return ata_std_prereset(ap, deadline);
157 }
158
159
160 /**
161 * sis_error_handler - Probe specified port on PATA host controller
162 * @ap: Port to probe
163 *
164 * LOCKING:
165 * None (inherited from caller).
166 */
167
168 static void sis_error_handler(struct ata_port *ap)
169 {
170 ata_bmdma_drive_eh(ap, sis_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
171 }
172
173 /**
174 * sis_set_fifo - Set RWP fifo bits for this device
175 * @ap: Port
176 * @adev: Device
177 *
178 * SIS chipsets implement prefetch/postwrite bits for each device
179 * on both channels. This functionality is not ATAPI compatible and
180 * must be configured according to the class of device present
181 */
182
183 static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev)
184 {
185 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
186 u8 fifoctrl;
187 u8 mask = 0x11;
188
189 mask <<= (2 * ap->port_no);
190 mask <<= adev->devno;
191
192 /* This holds various bits including the FIFO control */
193 pci_read_config_byte(pdev, 0x4B, &fifoctrl);
194 fifoctrl &= ~mask;
195
196 /* Enable for ATA (disk) only */
197 if (adev->class == ATA_DEV_ATA)
198 fifoctrl |= mask;
199 pci_write_config_byte(pdev, 0x4B, fifoctrl);
200 }
201
202 /**
203 * sis_old_set_piomode - Initialize host controller PATA PIO timings
204 * @ap: Port whose timings we are configuring
205 * @adev: Device we are configuring for.
206 *
207 * Set PIO mode for device, in host controller PCI config space. This
208 * function handles PIO set up for all chips that are pre ATA100 and
209 * also early ATA100 devices.
210 *
211 * LOCKING:
212 * None (inherited from caller).
213 */
214
215 static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev)
216 {
217 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
218 int port = sis_old_port_base(adev);
219 u8 t1, t2;
220 int speed = adev->pio_mode - XFER_PIO_0;
221
222 const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 };
223 const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 };
224
225 sis_set_fifo(ap, adev);
226
227 pci_read_config_byte(pdev, port, &t1);
228 pci_read_config_byte(pdev, port + 1, &t2);
229
230 t1 &= ~0x0F; /* Clear active/recovery timings */
231 t2 &= ~0x07;
232
233 t1 |= active[speed];
234 t2 |= recovery[speed];
235
236 pci_write_config_byte(pdev, port, t1);
237 pci_write_config_byte(pdev, port + 1, t2);
238 }
239
240 /**
241 * sis_100_set_piomode - Initialize host controller PATA PIO timings
242 * @ap: Port whose timings we are configuring
243 * @adev: Device we are configuring for.
244 *
245 * Set PIO mode for device, in host controller PCI config space. This
246 * function handles PIO set up for ATA100 devices and early ATA133.
247 *
248 * LOCKING:
249 * None (inherited from caller).
250 */
251
252 static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev)
253 {
254 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
255 int port = sis_old_port_base(adev);
256 int speed = adev->pio_mode - XFER_PIO_0;
257
258 const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
259
260 sis_set_fifo(ap, adev);
261
262 pci_write_config_byte(pdev, port, actrec[speed]);
263 }
264
265 /**
266 * sis_133_set_piomode - Initialize host controller PATA PIO timings
267 * @ap: Port whose timings we are configuring
268 * @adev: Device we are configuring for.
269 *
270 * Set PIO mode for device, in host controller PCI config space. This
271 * function handles PIO set up for the later ATA133 devices.
272 *
273 * LOCKING:
274 * None (inherited from caller).
275 */
276
277 static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev)
278 {
279 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
280 int port = 0x40;
281 u32 t1;
282 u32 reg54;
283 int speed = adev->pio_mode - XFER_PIO_0;
284
285 const u32 timing133[] = {
286 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */
287 0x0C266000,
288 0x04263000,
289 0x0C0A3000,
290 0x05093000
291 };
292 const u32 timing100[] = {
293 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */
294 0x091C4000,
295 0x031C2000,
296 0x09072000,
297 0x04062000
298 };
299
300 sis_set_fifo(ap, adev);
301
302 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */
303 pci_read_config_dword(pdev, 0x54, &reg54);
304 if (reg54 & 0x40000000)
305 port = 0x70;
306 port += 8 * ap->port_no + 4 * adev->devno;
307
308 pci_read_config_dword(pdev, port, &t1);
309 t1 &= 0xC0C00FFF; /* Mask out timing */
310
311 if (t1 & 0x08) /* 100 or 133 ? */
312 t1 |= timing133[speed];
313 else
314 t1 |= timing100[speed];
315 pci_write_config_byte(pdev, port, t1);
316 }
317
318 /**
319 * sis_old_set_dmamode - Initialize host controller PATA DMA timings
320 * @ap: Port whose timings we are configuring
321 * @adev: Device to program
322 *
323 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
324 * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike
325 * the old ide/pci driver.
326 *
327 * LOCKING:
328 * None (inherited from caller).
329 */
330
331 static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev)
332 {
333 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
334 int speed = adev->dma_mode - XFER_MW_DMA_0;
335 int drive_pci = sis_old_port_base(adev);
336 u16 timing;
337
338 const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 };
339 const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 };
340
341 pci_read_config_word(pdev, drive_pci, &timing);
342
343 if (adev->dma_mode < XFER_UDMA_0) {
344 /* bits 3-0 hold recovery timing bits 8-10 active timing and
345 the higer bits are dependant on the device */
346 timing &= ~0x870F;
347 timing |= mwdma_bits[speed];
348 } else {
349 /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */
350 speed = adev->dma_mode - XFER_UDMA_0;
351 timing &= ~0x6000;
352 timing |= udma_bits[speed];
353 }
354 pci_write_config_word(pdev, drive_pci, timing);
355 }
356
357 /**
358 * sis_66_set_dmamode - Initialize host controller PATA DMA timings
359 * @ap: Port whose timings we are configuring
360 * @adev: Device to program
361 *
362 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
363 * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike
364 * the old ide/pci driver.
365 *
366 * LOCKING:
367 * None (inherited from caller).
368 */
369
370 static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev)
371 {
372 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
373 int speed = adev->dma_mode - XFER_MW_DMA_0;
374 int drive_pci = sis_old_port_base(adev);
375 u16 timing;
376
377 const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 };
378 const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000};
379
380 pci_read_config_word(pdev, drive_pci, &timing);
381
382 if (adev->dma_mode < XFER_UDMA_0) {
383 /* bits 3-0 hold recovery timing bits 8-10 active timing and
384 the higer bits are dependant on the device, bit 15 udma */
385 timing &= ~0x870F;
386 timing |= mwdma_bits[speed];
387 } else {
388 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
389 speed = adev->dma_mode - XFER_UDMA_0;
390 timing &= ~0xF000;
391 timing |= udma_bits[speed];
392 }
393 pci_write_config_word(pdev, drive_pci, timing);
394 }
395
396 /**
397 * sis_100_set_dmamode - Initialize host controller PATA DMA timings
398 * @ap: Port whose timings we are configuring
399 * @adev: Device to program
400 *
401 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
402 * Handles UDMA66 and early UDMA100 devices.
403 *
404 * LOCKING:
405 * None (inherited from caller).
406 */
407
408 static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev)
409 {
410 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
411 int speed = adev->dma_mode - XFER_MW_DMA_0;
412 int drive_pci = sis_old_port_base(adev);
413 u8 timing;
414
415 const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81};
416
417 pci_read_config_byte(pdev, drive_pci + 1, &timing);
418
419 if (adev->dma_mode < XFER_UDMA_0) {
420 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
421 } else {
422 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */
423 speed = adev->dma_mode - XFER_UDMA_0;
424 timing &= ~0x8F;
425 timing |= udma_bits[speed];
426 }
427 pci_write_config_byte(pdev, drive_pci + 1, timing);
428 }
429
430 /**
431 * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings
432 * @ap: Port whose timings we are configuring
433 * @adev: Device to program
434 *
435 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
436 * Handles early SiS 961 bridges.
437 *
438 * LOCKING:
439 * None (inherited from caller).
440 */
441
442 static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev)
443 {
444 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
445 int speed = adev->dma_mode - XFER_MW_DMA_0;
446 int drive_pci = sis_old_port_base(adev);
447 u8 timing;
448 /* Low 4 bits are timing */
449 static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81};
450
451 pci_read_config_byte(pdev, drive_pci + 1, &timing);
452
453 if (adev->dma_mode < XFER_UDMA_0) {
454 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
455 } else {
456 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */
457 speed = adev->dma_mode - XFER_UDMA_0;
458 timing &= ~0x8F;
459 timing |= udma_bits[speed];
460 }
461 pci_write_config_byte(pdev, drive_pci + 1, timing);
462 }
463
464 /**
465 * sis_133_set_dmamode - Initialize host controller PATA DMA timings
466 * @ap: Port whose timings we are configuring
467 * @adev: Device to program
468 *
469 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
470 *
471 * LOCKING:
472 * None (inherited from caller).
473 */
474
475 static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev)
476 {
477 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
478 int speed = adev->dma_mode - XFER_MW_DMA_0;
479 int port = 0x40;
480 u32 t1;
481 u32 reg54;
482
483 /* bits 4- cycle time 8 - cvs time */
484 static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 };
485 static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 };
486
487 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */
488 pci_read_config_dword(pdev, 0x54, &reg54);
489 if (reg54 & 0x40000000)
490 port = 0x70;
491 port += (8 * ap->port_no) + (4 * adev->devno);
492
493 pci_read_config_dword(pdev, port, &t1);
494
495 if (adev->dma_mode < XFER_UDMA_0) {
496 t1 &= ~0x00000004;
497 /* FIXME: need data sheet to add MWDMA here. Also lacking on
498 ide/pci driver */
499 } else {
500 speed = adev->dma_mode - XFER_UDMA_0;
501 /* if & 8 no UDMA133 - need info for ... */
502 t1 &= ~0x00000FF0;
503 t1 |= 0x00000004;
504 if (t1 & 0x08)
505 t1 |= timing_u133[speed];
506 else
507 t1 |= timing_u100[speed];
508 }
509 pci_write_config_dword(pdev, port, t1);
510 }
511
512 static struct scsi_host_template sis_sht = {
513 .module = THIS_MODULE,
514 .name = DRV_NAME,
515 .ioctl = ata_scsi_ioctl,
516 .queuecommand = ata_scsi_queuecmd,
517 .can_queue = ATA_DEF_QUEUE,
518 .this_id = ATA_SHT_THIS_ID,
519 .sg_tablesize = LIBATA_MAX_PRD,
520 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
521 .emulated = ATA_SHT_EMULATED,
522 .use_clustering = ATA_SHT_USE_CLUSTERING,
523 .proc_name = DRV_NAME,
524 .dma_boundary = ATA_DMA_BOUNDARY,
525 .slave_configure = ata_scsi_slave_config,
526 .slave_destroy = ata_scsi_slave_destroy,
527 .bios_param = ata_std_bios_param,
528 };
529
530 static const struct ata_port_operations sis_133_ops = {
531 .port_disable = ata_port_disable,
532 .set_piomode = sis_133_set_piomode,
533 .set_dmamode = sis_133_set_dmamode,
534 .mode_filter = ata_pci_default_filter,
535
536 .tf_load = ata_tf_load,
537 .tf_read = ata_tf_read,
538 .check_status = ata_check_status,
539 .exec_command = ata_exec_command,
540 .dev_select = ata_std_dev_select,
541
542 .freeze = ata_bmdma_freeze,
543 .thaw = ata_bmdma_thaw,
544 .error_handler = sis_error_handler,
545 .post_internal_cmd = ata_bmdma_post_internal_cmd,
546 .cable_detect = sis_133_cable_detect,
547
548 .bmdma_setup = ata_bmdma_setup,
549 .bmdma_start = ata_bmdma_start,
550 .bmdma_stop = ata_bmdma_stop,
551 .bmdma_status = ata_bmdma_status,
552 .qc_prep = ata_qc_prep,
553 .qc_issue = ata_qc_issue_prot,
554 .data_xfer = ata_data_xfer,
555
556 .irq_handler = ata_interrupt,
557 .irq_clear = ata_bmdma_irq_clear,
558 .irq_on = ata_irq_on,
559 .irq_ack = ata_irq_ack,
560
561 .port_start = ata_port_start,
562 };
563
564 static const struct ata_port_operations sis_133_for_sata_ops = {
565 .port_disable = ata_port_disable,
566 .set_piomode = sis_133_set_piomode,
567 .set_dmamode = sis_133_set_dmamode,
568 .mode_filter = ata_pci_default_filter,
569
570 .tf_load = ata_tf_load,
571 .tf_read = ata_tf_read,
572 .check_status = ata_check_status,
573 .exec_command = ata_exec_command,
574 .dev_select = ata_std_dev_select,
575
576 .freeze = ata_bmdma_freeze,
577 .thaw = ata_bmdma_thaw,
578 .error_handler = ata_bmdma_error_handler,
579 .post_internal_cmd = ata_bmdma_post_internal_cmd,
580 .cable_detect = sis_133_cable_detect,
581
582 .bmdma_setup = ata_bmdma_setup,
583 .bmdma_start = ata_bmdma_start,
584 .bmdma_stop = ata_bmdma_stop,
585 .bmdma_status = ata_bmdma_status,
586 .qc_prep = ata_qc_prep,
587 .qc_issue = ata_qc_issue_prot,
588 .data_xfer = ata_data_xfer,
589
590 .irq_handler = ata_interrupt,
591 .irq_clear = ata_bmdma_irq_clear,
592 .irq_on = ata_irq_on,
593 .irq_ack = ata_irq_ack,
594
595 .port_start = ata_port_start,
596 };
597
598 static const struct ata_port_operations sis_133_early_ops = {
599 .port_disable = ata_port_disable,
600 .set_piomode = sis_100_set_piomode,
601 .set_dmamode = sis_133_early_set_dmamode,
602 .mode_filter = ata_pci_default_filter,
603
604 .tf_load = ata_tf_load,
605 .tf_read = ata_tf_read,
606 .check_status = ata_check_status,
607 .exec_command = ata_exec_command,
608 .dev_select = ata_std_dev_select,
609
610 .freeze = ata_bmdma_freeze,
611 .thaw = ata_bmdma_thaw,
612 .error_handler = sis_error_handler,
613 .post_internal_cmd = ata_bmdma_post_internal_cmd,
614 .cable_detect = sis_66_cable_detect,
615
616 .bmdma_setup = ata_bmdma_setup,
617 .bmdma_start = ata_bmdma_start,
618 .bmdma_stop = ata_bmdma_stop,
619 .bmdma_status = ata_bmdma_status,
620 .qc_prep = ata_qc_prep,
621 .qc_issue = ata_qc_issue_prot,
622 .data_xfer = ata_data_xfer,
623
624 .irq_handler = ata_interrupt,
625 .irq_clear = ata_bmdma_irq_clear,
626 .irq_on = ata_irq_on,
627 .irq_ack = ata_irq_ack,
628
629 .port_start = ata_port_start,
630 };
631
632 static const struct ata_port_operations sis_100_ops = {
633 .port_disable = ata_port_disable,
634 .set_piomode = sis_100_set_piomode,
635 .set_dmamode = sis_100_set_dmamode,
636 .mode_filter = ata_pci_default_filter,
637
638 .tf_load = ata_tf_load,
639 .tf_read = ata_tf_read,
640 .check_status = ata_check_status,
641 .exec_command = ata_exec_command,
642 .dev_select = ata_std_dev_select,
643
644 .freeze = ata_bmdma_freeze,
645 .thaw = ata_bmdma_thaw,
646 .error_handler = sis_error_handler,
647 .post_internal_cmd = ata_bmdma_post_internal_cmd,
648 .cable_detect = sis_66_cable_detect,
649
650 .bmdma_setup = ata_bmdma_setup,
651 .bmdma_start = ata_bmdma_start,
652 .bmdma_stop = ata_bmdma_stop,
653 .bmdma_status = ata_bmdma_status,
654 .qc_prep = ata_qc_prep,
655 .qc_issue = ata_qc_issue_prot,
656 .data_xfer = ata_data_xfer,
657
658 .irq_handler = ata_interrupt,
659 .irq_clear = ata_bmdma_irq_clear,
660 .irq_on = ata_irq_on,
661 .irq_ack = ata_irq_ack,
662
663 .port_start = ata_port_start,
664 };
665
666 static const struct ata_port_operations sis_66_ops = {
667 .port_disable = ata_port_disable,
668 .set_piomode = sis_old_set_piomode,
669 .set_dmamode = sis_66_set_dmamode,
670 .mode_filter = ata_pci_default_filter,
671
672 .tf_load = ata_tf_load,
673 .tf_read = ata_tf_read,
674 .check_status = ata_check_status,
675 .exec_command = ata_exec_command,
676 .dev_select = ata_std_dev_select,
677 .cable_detect = sis_66_cable_detect,
678
679 .freeze = ata_bmdma_freeze,
680 .thaw = ata_bmdma_thaw,
681 .error_handler = sis_error_handler,
682 .post_internal_cmd = ata_bmdma_post_internal_cmd,
683
684 .bmdma_setup = ata_bmdma_setup,
685 .bmdma_start = ata_bmdma_start,
686 .bmdma_stop = ata_bmdma_stop,
687 .bmdma_status = ata_bmdma_status,
688 .qc_prep = ata_qc_prep,
689 .qc_issue = ata_qc_issue_prot,
690 .data_xfer = ata_data_xfer,
691
692 .irq_handler = ata_interrupt,
693 .irq_clear = ata_bmdma_irq_clear,
694 .irq_on = ata_irq_on,
695 .irq_ack = ata_irq_ack,
696
697 .port_start = ata_port_start,
698 };
699
700 static const struct ata_port_operations sis_old_ops = {
701 .port_disable = ata_port_disable,
702 .set_piomode = sis_old_set_piomode,
703 .set_dmamode = sis_old_set_dmamode,
704 .mode_filter = ata_pci_default_filter,
705
706 .tf_load = ata_tf_load,
707 .tf_read = ata_tf_read,
708 .check_status = ata_check_status,
709 .exec_command = ata_exec_command,
710 .dev_select = ata_std_dev_select,
711
712 .freeze = ata_bmdma_freeze,
713 .thaw = ata_bmdma_thaw,
714 .error_handler = sis_error_handler,
715 .post_internal_cmd = ata_bmdma_post_internal_cmd,
716 .cable_detect = ata_cable_40wire,
717
718 .bmdma_setup = ata_bmdma_setup,
719 .bmdma_start = ata_bmdma_start,
720 .bmdma_stop = ata_bmdma_stop,
721 .bmdma_status = ata_bmdma_status,
722 .qc_prep = ata_qc_prep,
723 .qc_issue = ata_qc_issue_prot,
724 .data_xfer = ata_data_xfer,
725
726 .irq_handler = ata_interrupt,
727 .irq_clear = ata_bmdma_irq_clear,
728 .irq_on = ata_irq_on,
729 .irq_ack = ata_irq_ack,
730
731 .port_start = ata_port_start,
732 };
733
734 static const struct ata_port_info sis_info = {
735 .sht = &sis_sht,
736 .flags = ATA_FLAG_SLAVE_POSS,
737 .pio_mask = 0x1f, /* pio0-4 */
738 .mwdma_mask = 0x07,
739 .udma_mask = 0,
740 .port_ops = &sis_old_ops,
741 };
742 static const struct ata_port_info sis_info33 = {
743 .sht = &sis_sht,
744 .flags = ATA_FLAG_SLAVE_POSS,
745 .pio_mask = 0x1f, /* pio0-4 */
746 .mwdma_mask = 0x07,
747 .udma_mask = ATA_UDMA2, /* UDMA 33 */
748 .port_ops = &sis_old_ops,
749 };
750 static const struct ata_port_info sis_info66 = {
751 .sht = &sis_sht,
752 .flags = ATA_FLAG_SLAVE_POSS,
753 .pio_mask = 0x1f, /* pio0-4 */
754 .udma_mask = ATA_UDMA4, /* UDMA 66 */
755 .port_ops = &sis_66_ops,
756 };
757 static const struct ata_port_info sis_info100 = {
758 .sht = &sis_sht,
759 .flags = ATA_FLAG_SLAVE_POSS,
760 .pio_mask = 0x1f, /* pio0-4 */
761 .udma_mask = ATA_UDMA5,
762 .port_ops = &sis_100_ops,
763 };
764 static const struct ata_port_info sis_info100_early = {
765 .sht = &sis_sht,
766 .flags = ATA_FLAG_SLAVE_POSS,
767 .udma_mask = ATA_UDMA5,
768 .pio_mask = 0x1f, /* pio0-4 */
769 .port_ops = &sis_66_ops,
770 };
771 static const struct ata_port_info sis_info133 = {
772 .sht = &sis_sht,
773 .flags = ATA_FLAG_SLAVE_POSS,
774 .pio_mask = 0x1f, /* pio0-4 */
775 .udma_mask = ATA_UDMA6,
776 .port_ops = &sis_133_ops,
777 };
778 const struct ata_port_info sis_info133_for_sata = {
779 .sht = &sis_sht,
780 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
781 .pio_mask = 0x1f, /* pio0-4 */
782 .udma_mask = ATA_UDMA6,
783 .port_ops = &sis_133_for_sata_ops,
784 };
785 static const struct ata_port_info sis_info133_early = {
786 .sht = &sis_sht,
787 .flags = ATA_FLAG_SLAVE_POSS,
788 .pio_mask = 0x1f, /* pio0-4 */
789 .udma_mask = ATA_UDMA6,
790 .port_ops = &sis_133_early_ops,
791 };
792
793 /* Privately shared with the SiS180 SATA driver, not for use elsewhere */
794 EXPORT_SYMBOL_GPL(sis_info133_for_sata);
795
796 static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis)
797 {
798 u16 regw;
799 u8 reg;
800
801 if (sis->info == &sis_info133) {
802 pci_read_config_word(pdev, 0x50, &regw);
803 if (regw & 0x08)
804 pci_write_config_word(pdev, 0x50, regw & ~0x08);
805 pci_read_config_word(pdev, 0x52, &regw);
806 if (regw & 0x08)
807 pci_write_config_word(pdev, 0x52, regw & ~0x08);
808 return;
809 }
810
811 if (sis->info == &sis_info133_early || sis->info == &sis_info100) {
812 /* Fix up latency */
813 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
814 /* Set compatibility bit */
815 pci_read_config_byte(pdev, 0x49, &reg);
816 if (!(reg & 0x01))
817 pci_write_config_byte(pdev, 0x49, reg | 0x01);
818 return;
819 }
820
821 if (sis->info == &sis_info66 || sis->info == &sis_info100_early) {
822 /* Fix up latency */
823 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
824 /* Set compatibility bit */
825 pci_read_config_byte(pdev, 0x52, &reg);
826 if (!(reg & 0x04))
827 pci_write_config_byte(pdev, 0x52, reg | 0x04);
828 return;
829 }
830
831 if (sis->info == &sis_info33) {
832 pci_read_config_byte(pdev, PCI_CLASS_PROG, &reg);
833 if (( reg & 0x0F ) != 0x00)
834 pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0);
835 /* Fall through to ATA16 fixup below */
836 }
837
838 if (sis->info == &sis_info || sis->info == &sis_info33) {
839 /* force per drive recovery and active timings
840 needed on ATA_33 and below chips */
841 pci_read_config_byte(pdev, 0x52, &reg);
842 if (!(reg & 0x08))
843 pci_write_config_byte(pdev, 0x52, reg|0x08);
844 return;
845 }
846
847 BUG();
848 }
849
850 /**
851 * sis_init_one - Register SiS ATA PCI device with kernel services
852 * @pdev: PCI device to register
853 * @ent: Entry in sis_pci_tbl matching with @pdev
854 *
855 * Called from kernel PCI layer. We probe for combined mode (sigh),
856 * and then hand over control to libata, for it to do the rest.
857 *
858 * LOCKING:
859 * Inherited from PCI layer (may sleep).
860 *
861 * RETURNS:
862 * Zero on success, or -ERRNO value.
863 */
864
865 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
866 {
867 static int printed_version;
868 struct ata_port_info port;
869 const struct ata_port_info *ppi[] = { &port, NULL };
870 struct pci_dev *host = NULL;
871 struct sis_chipset *chipset = NULL;
872 struct sis_chipset *sets;
873
874 static struct sis_chipset sis_chipsets[] = {
875
876 { 0x0968, &sis_info133 },
877 { 0x0966, &sis_info133 },
878 { 0x0965, &sis_info133 },
879 { 0x0745, &sis_info100 },
880 { 0x0735, &sis_info100 },
881 { 0x0733, &sis_info100 },
882 { 0x0635, &sis_info100 },
883 { 0x0633, &sis_info100 },
884
885 { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */
886 { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */
887
888 { 0x0640, &sis_info66 },
889 { 0x0630, &sis_info66 },
890 { 0x0620, &sis_info66 },
891 { 0x0540, &sis_info66 },
892 { 0x0530, &sis_info66 },
893
894 { 0x5600, &sis_info33 },
895 { 0x5598, &sis_info33 },
896 { 0x5597, &sis_info33 },
897 { 0x5591, &sis_info33 },
898 { 0x5582, &sis_info33 },
899 { 0x5581, &sis_info33 },
900
901 { 0x5596, &sis_info },
902 { 0x5571, &sis_info },
903 { 0x5517, &sis_info },
904 { 0x5511, &sis_info },
905
906 {0}
907 };
908 static struct sis_chipset sis133_early = {
909 0x0, &sis_info133_early
910 };
911 static struct sis_chipset sis133 = {
912 0x0, &sis_info133
913 };
914 static struct sis_chipset sis100_early = {
915 0x0, &sis_info100_early
916 };
917 static struct sis_chipset sis100 = {
918 0x0, &sis_info100
919 };
920
921 if (!printed_version++)
922 dev_printk(KERN_DEBUG, &pdev->dev,
923 "version " DRV_VERSION "\n");
924
925 /* We have to find the bridge first */
926
927 for (sets = &sis_chipsets[0]; sets->device; sets++) {
928 host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL);
929 if (host != NULL) {
930 chipset = sets; /* Match found */
931 if (sets->device == 0x630) { /* SIS630 */
932 if (host->revision >= 0x30) /* 630 ET */
933 chipset = &sis100_early;
934 }
935 break;
936 }
937 }
938
939 /* Look for concealed bridges */
940 if (chipset == NULL) {
941 /* Second check */
942 u32 idemisc;
943 u16 trueid;
944
945 /* Disable ID masking and register remapping then
946 see what the real ID is */
947
948 pci_read_config_dword(pdev, 0x54, &idemisc);
949 pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff);
950 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
951 pci_write_config_dword(pdev, 0x54, idemisc);
952
953 switch(trueid) {
954 case 0x5518: /* SIS 962/963 */
955 chipset = &sis133;
956 if ((idemisc & 0x40000000) == 0) {
957 pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000);
958 printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
959 }
960 break;
961 case 0x0180: /* SIS 965/965L */
962 chipset = &sis133;
963 break;
964 case 0x1180: /* SIS 966/966L */
965 chipset = &sis133;
966 break;
967 }
968 }
969
970 /* Further check */
971 if (chipset == NULL) {
972 struct pci_dev *lpc_bridge;
973 u16 trueid;
974 u8 prefctl;
975 u8 idecfg;
976
977 /* Try the second unmasking technique */
978 pci_read_config_byte(pdev, 0x4a, &idecfg);
979 pci_write_config_byte(pdev, 0x4a, idecfg | 0x10);
980 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
981 pci_write_config_byte(pdev, 0x4a, idecfg);
982
983 switch(trueid) {
984 case 0x5517:
985 lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */
986 if (lpc_bridge == NULL)
987 break;
988 pci_read_config_byte(pdev, 0x49, &prefctl);
989 pci_dev_put(lpc_bridge);
990
991 if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
992 chipset = &sis133_early;
993 break;
994 }
995 chipset = &sis100;
996 break;
997 }
998 }
999 pci_dev_put(host);
1000
1001 /* No chipset info, no support */
1002 if (chipset == NULL)
1003 return -ENODEV;
1004
1005 port = *chipset->info;
1006 port.private_data = chipset;
1007
1008 sis_fixup(pdev, chipset);
1009
1010 return ata_pci_init_one(pdev, ppi);
1011 }
1012
1013 static const struct pci_device_id sis_pci_tbl[] = {
1014 { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */
1015 { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */
1016 { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */
1017
1018 { }
1019 };
1020
1021 static struct pci_driver sis_pci_driver = {
1022 .name = DRV_NAME,
1023 .id_table = sis_pci_tbl,
1024 .probe = sis_init_one,
1025 .remove = ata_pci_remove_one,
1026 #ifdef CONFIG_PM
1027 .suspend = ata_pci_device_suspend,
1028 .resume = ata_pci_device_resume,
1029 #endif
1030 };
1031
1032 static int __init sis_init(void)
1033 {
1034 return pci_register_driver(&sis_pci_driver);
1035 }
1036
1037 static void __exit sis_exit(void)
1038 {
1039 pci_unregister_driver(&sis_pci_driver);
1040 }
1041
1042 module_init(sis_init);
1043 module_exit(sis_exit);
1044
1045 MODULE_AUTHOR("Alan Cox");
1046 MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA");
1047 MODULE_LICENSE("GPL");
1048 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
1049 MODULE_VERSION(DRV_VERSION);
1050
x86 "subsystem" repository