include/asm-avr32/io.h

   1 #ifndef __ASM_AVR32_IO_H
   2 #define __ASM_AVR32_IO_H
   3
   4 #include <linux/string.h>
   5
   6 #ifdef __KERNEL__
   7
   8 #include <asm/addrspace.h>
   9 #include <asm/byteorder.h>
  10
  11 /* virt_to_phys will only work when address is in P1 or P2 */
  12 static __inline__ unsigned long virt_to_phys(volatile void *address)
  13 {
  14         return PHYSADDR(address);
  15 }
  16
  17 static __inline__ void * phys_to_virt(unsigned long address)
  18 {
  19         return (void *)P1SEGADDR(address);
  20 }
  21
  22 #define cached_to_phys(addr)    ((unsigned long)PHYSADDR(addr))
  23 #define uncached_to_phys(addr)  ((unsigned long)PHYSADDR(addr))
  24 #define phys_to_cached(addr)    ((void *)P1SEGADDR(addr))
  25 #define phys_to_uncached(addr)  ((void *)P2SEGADDR(addr))
  26
  27 /*
  28  * Generic IO read/write.  These perform native-endian accesses.  Note
  29  * that some architectures will want to re-define __raw_{read,write}w.
  30  */
  31 extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
  32 extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
  33 extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
  34
  35 extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
  36 extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
  37 extern void __raw_readsl(unsigned int addr, void *data, int longlen);
  38
  39 static inline void writeb(unsigned char b, volatile void __iomem *addr)
  40 {
  41         *(volatile unsigned char __force *)addr = b;
  42 }
  43 static inline void writew(unsigned short b, volatile void __iomem *addr)
  44 {
  45         *(volatile unsigned short __force *)addr = b;
  46 }
  47 static inline void writel(unsigned int b, volatile void __iomem *addr)
  48 {
  49         *(volatile unsigned int __force *)addr = b;
  50 }
  51 #define __raw_writeb writeb
  52 #define __raw_writew writew
  53 #define __raw_writel writel
  54
  55 static inline unsigned char readb(const volatile void __iomem *addr)
  56 {
  57         return *(const volatile unsigned char __force *)addr;
  58 }
  59 static inline unsigned short readw(const volatile void __iomem *addr)
  60 {
  61         return *(const volatile unsigned short __force *)addr;
  62 }
  63 static inline unsigned int readl(const volatile void __iomem *addr)
  64 {
  65         return *(const volatile unsigned int __force *)addr;
  66 }
  67 #define __raw_readb readb
  68 #define __raw_readw readw
  69 #define __raw_readl readl
  70
  71 #define writesb(p, d, l)        __raw_writesb((unsigned int)p, d, l)
  72 #define writesw(p, d, l)        __raw_writesw((unsigned int)p, d, l)
  73 #define writesl(p, d, l)        __raw_writesl((unsigned int)p, d, l)
  74
  75 #define readsb(p, d, l)         __raw_readsb((unsigned int)p, d, l)
  76 #define readsw(p, d, l)         __raw_readsw((unsigned int)p, d, l)
  77 #define readsl(p, d, l)         __raw_readsl((unsigned int)p, d, l)
  78
  79
  80 /*
  81  * io{read,write}{8,16,32} macros in both le (for PCI style consumers) and native be
  82  */
  83 #ifndef ioread8
  84
  85 #define ioread8(p)      ({ unsigned int __v = __raw_readb(p); __v; })
  86
  87 #define ioread16(p)     ({ unsigned int __v = le16_to_cpu(__raw_readw(p)); __v; })
  88 #define ioread16be(p)   ({ unsigned int __v = be16_to_cpu(__raw_readw(p)); __v; })
  89
  90 #define ioread32(p)     ({ unsigned int __v = le32_to_cpu(__raw_readl(p)); __v; })
  91 #define ioread32be(p)   ({ unsigned int __v = be32_to_cpu(__raw_readl(p)); __v; })
  92
  93 #define iowrite8(v,p)   __raw_writeb(v, p)
  94
  95 #define iowrite16(v,p)  __raw_writew(cpu_to_le16(v), p)
  96 #define iowrite16be(v,p)        __raw_writew(cpu_to_be16(v), p)
  97
  98 #define iowrite32(v,p)  __raw_writel(cpu_to_le32(v), p)
  99 #define iowrite32be(v,p)        __raw_writel(cpu_to_be32(v), p)
 100
 101 #define ioread8_rep(p,d,c)      __raw_readsb(p,d,c)
 102 #define ioread16_rep(p,d,c)     __raw_readsw(p,d,c)
 103 #define ioread32_rep(p,d,c)     __raw_readsl(p,d,c)
 104
 105 #define iowrite8_rep(p,s,c)     __raw_writesb(p,s,c)
 106 #define iowrite16_rep(p,s,c)    __raw_writesw(p,s,c)
 107 #define iowrite32_rep(p,s,c)    __raw_writesl(p,s,c)
 108
 109 #endif
 110
 111
 112 /*
 113  * These two are only here because ALSA _thinks_ it needs them...
 114  */
 115 static inline void memcpy_fromio(void * to, const volatile void __iomem *from,
 116                                  unsigned long count)
 117 {
 118         char *p = to;
 119         while (count) {
 120                 count--;
 121                 *p = readb(from);
 122                 p++;
 123                 from++;
 124         }
 125 }
 126
 127 static inline void  memcpy_toio(volatile void __iomem *to, const void * from,
 128                                 unsigned long count)
 129 {
 130         const char *p = from;
 131         while (count) {
 132                 count--;
 133                 writeb(*p, to);
 134                 p++;
 135                 to++;
 136         }
 137 }
 138
 139 static inline void memset_io(volatile void __iomem *addr, unsigned char val,
 140                              unsigned long count)
 141 {
 142         memset((void __force *)addr, val, count);
 143 }
 144
 145 /*
 146  * Bad read/write accesses...
 147  */
 148 extern void __readwrite_bug(const char *fn);
 149
 150 #define IO_SPACE_LIMIT  0xffffffff
 151
 152 /* Convert I/O port address to virtual address */
 153 #define __io(p)         ((void __iomem *)phys_to_uncached(p))
 154
 155 /*
 156  *  IO port access primitives
 157  *  -------------------------
 158  *
 159  * The AVR32 doesn't have special IO access instructions; all IO is memory
 160  * mapped. Note that these are defined to perform little endian accesses
 161  * only. Their primary purpose is to access PCI and ISA peripherals.
 162  *
 163  * Note that for a big endian machine, this implies that the following
 164  * big endian mode connectivity is in place.
 165  *
 166  * The machine specific io.h include defines __io to translate an "IO"
 167  * address to a memory address.
 168  *
 169  * Note that we prevent GCC re-ordering or caching values in expressions
 170  * by introducing sequence points into the in*() definitions.  Note that
 171  * __raw_* do not guarantee this behaviour.
 172  *
 173  * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
 174  */
 175 #define outb(v, p)              __raw_writeb(v, __io(p))
 176 #define outw(v, p)              __raw_writew(cpu_to_le16(v), __io(p))
 177 #define outl(v, p)              __raw_writel(cpu_to_le32(v), __io(p))
 178
 179 #define inb(p)                  __raw_readb(__io(p))
 180 #define inw(p)                  le16_to_cpu(__raw_readw(__io(p)))
 181 #define inl(p)                  le32_to_cpu(__raw_readl(__io(p)))
 182
 183 static inline void __outsb(unsigned long port, void *addr, unsigned int count)
 184 {
 185         while (count--) {
 186                 outb(*(u8 *)addr, port);
 187                 addr++;
 188         }
 189 }
 190
 191 static inline void __insb(unsigned long port, void *addr, unsigned int count)
 192 {
 193         while (count--) {
 194                 *(u8 *)addr = inb(port);
 195                 addr++;
 196         }
 197 }
 198
 199 static inline void __outsw(unsigned long port, void *addr, unsigned int count)
 200 {
 201         while (count--) {
 202                 outw(*(u16 *)addr, port);
 203                 addr += 2;
 204         }
 205 }
 206
 207 static inline void __insw(unsigned long port, void *addr, unsigned int count)
 208 {
 209         while (count--) {
 210                 *(u16 *)addr = inw(port);
 211                 addr += 2;
 212         }
 213 }
 214
 215 static inline void __outsl(unsigned long port, void *addr, unsigned int count)
 216 {
 217         while (count--) {
 218                 outl(*(u32 *)addr, port);
 219                 addr += 4;
 220         }
 221 }
 222
 223 static inline void __insl(unsigned long port, void *addr, unsigned int count)
 224 {
 225         while (count--) {
 226                 *(u32 *)addr = inl(port);
 227                 addr += 4;
 228         }
 229 }
 230
 231 #define outsb(port, addr, count)        __outsb(port, addr, count)
 232 #define insb(port, addr, count)         __insb(port, addr, count)
 233 #define outsw(port, addr, count)        __outsw(port, addr, count)
 234 #define insw(port, addr, count)         __insw(port, addr, count)
 235 #define outsl(port, addr, count)        __outsl(port, addr, count)
 236 #define insl(port, addr, count)         __insl(port, addr, count)
 237
 238 extern void __iomem *__ioremap(unsigned long offset, size_t size,
 239                                unsigned long flags);
 240 extern void __iounmap(void __iomem *addr);
 241
 242 /*
 243  * ioremap      -   map bus memory into CPU space
 244  * @offset      bus address of the memory
 245  * @size        size of the resource to map
 246  *
 247  * ioremap performs a platform specific sequence of operations to make
 248  * bus memory CPU accessible via the readb/.../writel functions and
 249  * the other mmio helpers. The returned address is not guaranteed to
 250  * be usable directly as a virtual address.
 251  */
 252 #define ioremap(offset, size)                   \
 253         __ioremap((offset), (size), 0)
 254
 255 #define iounmap(addr)                           \
 256         __iounmap(addr)
 257
 258 #define cached(addr) P1SEGADDR(addr)
 259 #define uncached(addr) P2SEGADDR(addr)
 260
 261 #define virt_to_bus virt_to_phys
 262 #define bus_to_virt phys_to_virt
 263 #define page_to_bus page_to_phys
 264 #define bus_to_page phys_to_page
 265
 266 #define dma_cache_wback_inv(_start, _size)      \
 267         flush_dcache_region(_start, _size)
 268 #define dma_cache_inv(_start, _size)            \
 269         invalidate_dcache_region(_start, _size)
 270 #define dma_cache_wback(_start, _size)          \
 271         clean_dcache_region(_start, _size)
 272
 273 /*
 274  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 275  * access
 276  */
 277 #define xlate_dev_mem_ptr(p)    __va(p)
 278
 279 /*
 280  * Convert a virtual cached pointer to an uncached pointer
 281  */
 282 #define xlate_dev_kmem_ptr(p)   p
 283
 284 #endif /* __KERNEL__ */
 285
 286 #endif /* __ASM_AVR32_IO_H */