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[netdrvr] sfc: Remove garbage from comment
[linux-2.6/x86.git] / drivers / net / tulip / uli526x.c
blob2511ca7a12aa168eb09bd6de536db8f88a99cbd6
1 /*
2 This program is free software; you can redistribute it and/or
3 modify it under the terms of the GNU General Public License
4 as published by the Free Software Foundation; either version 2
5 of the License, or (at your option) any later version.
6
7 This program is distributed in the hope that it will be useful,
8 but WITHOUT ANY WARRANTY; without even the implied warranty of
9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 GNU General Public License for more details.
11
12
13 */
14
15 #define DRV_NAME "uli526x"
16 #define DRV_VERSION "0.9.3"
17 #define DRV_RELDATE "2005-7-29"
18
19 #include <linux/module.h>
20
21 #include <linux/kernel.h>
22 #include <linux/string.h>
23 #include <linux/timer.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/slab.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/skbuff.h>
34 #include <linux/delay.h>
35 #include <linux/spinlock.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/bitops.h>
38
39 #include <asm/processor.h>
40 #include <asm/io.h>
41 #include <asm/dma.h>
42 #include <asm/uaccess.h>
43
44
45 /* Board/System/Debug information/definition ---------------- */
46 #define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/
47 #define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/
48
49 #define ULI526X_IO_SIZE 0x100
50 #define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */
51 #define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */
52 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
53 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
54 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
55 #define TX_BUF_ALLOC 0x600
56 #define RX_ALLOC_SIZE 0x620
57 #define ULI526X_RESET 1
58 #define CR0_DEFAULT 0
59 #define CR6_DEFAULT 0x22200000
60 #define CR7_DEFAULT 0x180c1
61 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
62 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
63 #define MAX_PACKET_SIZE 1514
64 #define ULI5261_MAX_MULTICAST 14
65 #define RX_COPY_SIZE 100
66 #define MAX_CHECK_PACKET 0x8000
67
68 #define ULI526X_10MHF 0
69 #define ULI526X_100MHF 1
70 #define ULI526X_10MFD 4
71 #define ULI526X_100MFD 5
72 #define ULI526X_AUTO 8
73
74 #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
75 #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
76 #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
77 #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
78 #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
79 #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
80
81 #define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
82 #define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */
83 #define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */
84
85 #define ULI526X_DBUG(dbug_now, msg, value) if (uli526x_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
86
87 #define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
88
89
90 /* CR9 definition: SROM/MII */
91 #define CR9_SROM_READ 0x4800
92 #define CR9_SRCS 0x1
93 #define CR9_SRCLK 0x2
94 #define CR9_CRDOUT 0x8
95 #define SROM_DATA_0 0x0
96 #define SROM_DATA_1 0x4
97 #define PHY_DATA_1 0x20000
98 #define PHY_DATA_0 0x00000
99 #define MDCLKH 0x10000
100
101 #define PHY_POWER_DOWN 0x800
102
103 #define SROM_V41_CODE 0x14
104
105 #define SROM_CLK_WRITE(data, ioaddr) \
106 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
107 udelay(5); \
108 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
109 udelay(5); \
110 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
111 udelay(5);
112
113 /* Structure/enum declaration ------------------------------- */
114 struct tx_desc {
115 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
116 char *tx_buf_ptr; /* Data for us */
117 struct tx_desc *next_tx_desc;
118 } __attribute__(( aligned(32) ));
119
120 struct rx_desc {
121 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
122 struct sk_buff *rx_skb_ptr; /* Data for us */
123 struct rx_desc *next_rx_desc;
124 } __attribute__(( aligned(32) ));
125
126 struct uli526x_board_info {
127 u32 chip_id; /* Chip vendor/Device ID */
128 struct net_device *next_dev; /* next device */
129 struct pci_dev *pdev; /* PCI device */
130 spinlock_t lock;
131
132 long ioaddr; /* I/O base address */
133 u32 cr0_data;
134 u32 cr5_data;
135 u32 cr6_data;
136 u32 cr7_data;
137 u32 cr15_data;
138
139 /* pointer for memory physical address */
140 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
141 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
142 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
143 dma_addr_t first_tx_desc_dma;
144 dma_addr_t first_rx_desc_dma;
145
146 /* descriptor pointer */
147 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
148 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
149 unsigned char *desc_pool_ptr; /* descriptor pool memory */
150 struct tx_desc *first_tx_desc;
151 struct tx_desc *tx_insert_ptr;
152 struct tx_desc *tx_remove_ptr;
153 struct rx_desc *first_rx_desc;
154 struct rx_desc *rx_insert_ptr;
155 struct rx_desc *rx_ready_ptr; /* packet come pointer */
156 unsigned long tx_packet_cnt; /* transmitted packet count */
157 unsigned long rx_avail_cnt; /* available rx descriptor count */
158 unsigned long interval_rx_cnt; /* rx packet count a callback time */
159
160 u16 dbug_cnt;
161 u16 NIC_capability; /* NIC media capability */
162 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
163
164 u8 media_mode; /* user specify media mode */
165 u8 op_mode; /* real work media mode */
166 u8 phy_addr;
167 u8 link_failed; /* Ever link failed */
168 u8 wait_reset; /* Hardware failed, need to reset */
169 struct timer_list timer;
170
171 /* System defined statistic counter */
172 struct net_device_stats stats;
173
174 /* Driver defined statistic counter */
175 unsigned long tx_fifo_underrun;
176 unsigned long tx_loss_carrier;
177 unsigned long tx_no_carrier;
178 unsigned long tx_late_collision;
179 unsigned long tx_excessive_collision;
180 unsigned long tx_jabber_timeout;
181 unsigned long reset_count;
182 unsigned long reset_cr8;
183 unsigned long reset_fatal;
184 unsigned long reset_TXtimeout;
185
186 /* NIC SROM data */
187 unsigned char srom[128];
188 u8 init;
189 };
190
191 enum uli526x_offsets {
192 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
193 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
194 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
195 DCR15 = 0x78
196 };
197
198 enum uli526x_CR6_bits {
199 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
200 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
201 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
202 };
203
204 /* Global variable declaration ----------------------------- */
205 static int __devinitdata printed_version;
206 static char version[] __devinitdata =
207 KERN_INFO DRV_NAME ": ULi M5261/M5263 net driver, version "
208 DRV_VERSION " (" DRV_RELDATE ")\n";
209
210 static int uli526x_debug;
211 static unsigned char uli526x_media_mode = ULI526X_AUTO;
212 static u32 uli526x_cr6_user_set;
213
214 /* For module input parameter */
215 static int debug;
216 static u32 cr6set;
217 static int mode = 8;
218
219 /* function declaration ------------------------------------- */
220 static int uli526x_open(struct net_device *);
221 static int uli526x_start_xmit(struct sk_buff *, struct net_device *);
222 static int uli526x_stop(struct net_device *);
223 static struct net_device_stats * uli526x_get_stats(struct net_device *);
224 static void uli526x_set_filter_mode(struct net_device *);
225 static const struct ethtool_ops netdev_ethtool_ops;
226 static u16 read_srom_word(long, int);
227 static irqreturn_t uli526x_interrupt(int, void *);
228 static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
229 static void allocate_rx_buffer(struct uli526x_board_info *);
230 static void update_cr6(u32, unsigned long);
231 static void send_filter_frame(struct net_device *, int);
232 static u16 phy_read(unsigned long, u8, u8, u32);
233 static u16 phy_readby_cr10(unsigned long, u8, u8);
234 static void phy_write(unsigned long, u8, u8, u16, u32);
235 static void phy_writeby_cr10(unsigned long, u8, u8, u16);
236 static void phy_write_1bit(unsigned long, u32, u32);
237 static u16 phy_read_1bit(unsigned long, u32);
238 static u8 uli526x_sense_speed(struct uli526x_board_info *);
239 static void uli526x_process_mode(struct uli526x_board_info *);
240 static void uli526x_timer(unsigned long);
241 static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *);
242 static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *);
243 static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *);
244 static void uli526x_dynamic_reset(struct net_device *);
245 static void uli526x_free_rxbuffer(struct uli526x_board_info *);
246 static void uli526x_init(struct net_device *);
247 static void uli526x_set_phyxcer(struct uli526x_board_info *);
248
249 /* ULI526X network board routine ---------------------------- */
250
251 /*
252 * Search ULI526X board, allocate space and register it
253 */
254
255 static int __devinit uli526x_init_one (struct pci_dev *pdev,
256 const struct pci_device_id *ent)
257 {
258 struct uli526x_board_info *db; /* board information structure */
259 struct net_device *dev;
260 int i, err;
261 DECLARE_MAC_BUF(mac);
262
263 ULI526X_DBUG(0, "uli526x_init_one()", 0);
264
265 if (!printed_version++)
266 printk(version);
267
268 /* Init network device */
269 dev = alloc_etherdev(sizeof(*db));
270 if (dev == NULL)
271 return -ENOMEM;
272 SET_NETDEV_DEV(dev, &pdev->dev);
273
274 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
275 printk(KERN_WARNING DRV_NAME ": 32-bit PCI DMA not available.\n");
276 err = -ENODEV;
277 goto err_out_free;
278 }
279
280 /* Enable Master/IO access, Disable memory access */
281 err = pci_enable_device(pdev);
282 if (err)
283 goto err_out_free;
284
285 if (!pci_resource_start(pdev, 0)) {
286 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
287 err = -ENODEV;
288 goto err_out_disable;
289 }
290
291 if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) {
292 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
293 err = -ENODEV;
294 goto err_out_disable;
295 }
296
297 if (pci_request_regions(pdev, DRV_NAME)) {
298 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
299 err = -ENODEV;
300 goto err_out_disable;
301 }
302
303 /* Init system & device */
304 db = netdev_priv(dev);
305
306 /* Allocate Tx/Rx descriptor memory */
307 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
308 if(db->desc_pool_ptr == NULL)
309 {
310 err = -ENOMEM;
311 goto err_out_nomem;
312 }
313 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
314 if(db->buf_pool_ptr == NULL)
315 {
316 err = -ENOMEM;
317 goto err_out_nomem;
318 }
319
320 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
321 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
322 db->buf_pool_start = db->buf_pool_ptr;
323 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
324
325 db->chip_id = ent->driver_data;
326 db->ioaddr = pci_resource_start(pdev, 0);
327
328 db->pdev = pdev;
329 db->init = 1;
330
331 dev->base_addr = db->ioaddr;
332 dev->irq = pdev->irq;
333 pci_set_drvdata(pdev, dev);
334
335 /* Register some necessary functions */
336 dev->open = &uli526x_open;
337 dev->hard_start_xmit = &uli526x_start_xmit;
338 dev->stop = &uli526x_stop;
339 dev->get_stats = &uli526x_get_stats;
340 dev->set_multicast_list = &uli526x_set_filter_mode;
341 dev->ethtool_ops = &netdev_ethtool_ops;
342 spin_lock_init(&db->lock);
343
344
345 /* read 64 word srom data */
346 for (i = 0; i < 64; i++)
347 ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i));
348
349 /* Set Node address */
350 if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */
351 {
352 outl(0x10000, db->ioaddr + DCR0); //Diagnosis mode
353 outl(0x1c0, db->ioaddr + DCR13); //Reset dianostic pointer port
354 outl(0, db->ioaddr + DCR14); //Clear reset port
355 outl(0x10, db->ioaddr + DCR14); //Reset ID Table pointer
356 outl(0, db->ioaddr + DCR14); //Clear reset port
357 outl(0, db->ioaddr + DCR13); //Clear CR13
358 outl(0x1b0, db->ioaddr + DCR13); //Select ID Table access port
359 //Read MAC address from CR14
360 for (i = 0; i < 6; i++)
361 dev->dev_addr[i] = inl(db->ioaddr + DCR14);
362 //Read end
363 outl(0, db->ioaddr + DCR13); //Clear CR13
364 outl(0, db->ioaddr + DCR0); //Clear CR0
365 udelay(10);
366 }
367 else /*Exist SROM*/
368 {
369 for (i = 0; i < 6; i++)
370 dev->dev_addr[i] = db->srom[20 + i];
371 }
372 err = register_netdev (dev);
373 if (err)
374 goto err_out_res;
375
376 printk(KERN_INFO "%s: ULi M%04lx at pci%s, %s, irq %d.\n",
377 dev->name,ent->driver_data >> 16,pci_name(pdev),
378 print_mac(mac, dev->dev_addr), dev->irq);
379
380 pci_set_master(pdev);
381
382 return 0;
383
384 err_out_res:
385 pci_release_regions(pdev);
386 err_out_nomem:
387 if(db->desc_pool_ptr)
388 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
389 db->desc_pool_ptr, db->desc_pool_dma_ptr);
390
391 if(db->buf_pool_ptr != NULL)
392 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
393 db->buf_pool_ptr, db->buf_pool_dma_ptr);
394 err_out_disable:
395 pci_disable_device(pdev);
396 err_out_free:
397 pci_set_drvdata(pdev, NULL);
398 free_netdev(dev);
399
400 return err;
401 }
402
403
404 static void __devexit uli526x_remove_one (struct pci_dev *pdev)
405 {
406 struct net_device *dev = pci_get_drvdata(pdev);
407 struct uli526x_board_info *db = netdev_priv(dev);
408
409 ULI526X_DBUG(0, "uli526x_remove_one()", 0);
410
411 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
412 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
413 db->desc_pool_dma_ptr);
414 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
415 db->buf_pool_ptr, db->buf_pool_dma_ptr);
416 unregister_netdev(dev);
417 pci_release_regions(pdev);
418 free_netdev(dev); /* free board information */
419 pci_set_drvdata(pdev, NULL);
420 pci_disable_device(pdev);
421 ULI526X_DBUG(0, "uli526x_remove_one() exit", 0);
422 }
423
424
425 /*
426 * Open the interface.
427 * The interface is opened whenever "ifconfig" activates it.
428 */
429
430 static int uli526x_open(struct net_device *dev)
431 {
432 int ret;
433 struct uli526x_board_info *db = netdev_priv(dev);
434
435 ULI526X_DBUG(0, "uli526x_open", 0);
436
437 /* system variable init */
438 db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
439 db->tx_packet_cnt = 0;
440 db->rx_avail_cnt = 0;
441 db->link_failed = 1;
442 netif_carrier_off(dev);
443 db->wait_reset = 0;
444
445 db->NIC_capability = 0xf; /* All capability*/
446 db->PHY_reg4 = 0x1e0;
447
448 /* CR6 operation mode decision */
449 db->cr6_data |= ULI526X_TXTH_256;
450 db->cr0_data = CR0_DEFAULT;
451
452 /* Initialize ULI526X board */
453 uli526x_init(dev);
454
455 ret = request_irq(dev->irq, &uli526x_interrupt, IRQF_SHARED, dev->name, dev);
456 if (ret)
457 return ret;
458
459 /* Active System Interface */
460 netif_wake_queue(dev);
461
462 /* set and active a timer process */
463 init_timer(&db->timer);
464 db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
465 db->timer.data = (unsigned long)dev;
466 db->timer.function = &uli526x_timer;
467 add_timer(&db->timer);
468
469 return 0;
470 }
471
472
473 /* Initialize ULI526X board
474 * Reset ULI526X board
475 * Initialize TX/Rx descriptor chain structure
476 * Send the set-up frame
477 * Enable Tx/Rx machine
478 */
479
480 static void uli526x_init(struct net_device *dev)
481 {
482 struct uli526x_board_info *db = netdev_priv(dev);
483 unsigned long ioaddr = db->ioaddr;
484 u8 phy_tmp;
485 u8 timeout;
486 u16 phy_value;
487 u16 phy_reg_reset;
488
489
490 ULI526X_DBUG(0, "uli526x_init()", 0);
491
492 /* Reset M526x MAC controller */
493 outl(ULI526X_RESET, ioaddr + DCR0); /* RESET MAC */
494 udelay(100);
495 outl(db->cr0_data, ioaddr + DCR0);
496 udelay(5);
497
498 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
499 db->phy_addr = 1;
500 for(phy_tmp=0;phy_tmp<32;phy_tmp++)
501 {
502 phy_value=phy_read(db->ioaddr,phy_tmp,3,db->chip_id);//peer add
503 if(phy_value != 0xffff&&phy_value!=0)
504 {
505 db->phy_addr = phy_tmp;
506 break;
507 }
508 }
509 if(phy_tmp == 32)
510 printk(KERN_WARNING "Can not find the phy address!!!");
511 /* Parser SROM and media mode */
512 db->media_mode = uli526x_media_mode;
513
514 /* phyxcer capability setting */
515 phy_reg_reset = phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id);
516 phy_reg_reset = (phy_reg_reset | 0x8000);
517 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg_reset, db->chip_id);
518
519 /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management
520 * functions") or phy data sheet for details on phy reset
521 */
522 udelay(500);
523 timeout = 10;
524 while (timeout-- &&
525 phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id) & 0x8000)
526 udelay(100);
527
528 /* Process Phyxcer Media Mode */
529 uli526x_set_phyxcer(db);
530
531 /* Media Mode Process */
532 if ( !(db->media_mode & ULI526X_AUTO) )
533 db->op_mode = db->media_mode; /* Force Mode */
534
535 /* Initialize Transmit/Receive decriptor and CR3/4 */
536 uli526x_descriptor_init(db, ioaddr);
537
538 /* Init CR6 to program M526X operation */
539 update_cr6(db->cr6_data, ioaddr);
540
541 /* Send setup frame */
542 send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */
543
544 /* Init CR7, interrupt active bit */
545 db->cr7_data = CR7_DEFAULT;
546 outl(db->cr7_data, ioaddr + DCR7);
547
548 /* Init CR15, Tx jabber and Rx watchdog timer */
549 outl(db->cr15_data, ioaddr + DCR15);
550
551 /* Enable ULI526X Tx/Rx function */
552 db->cr6_data |= CR6_RXSC | CR6_TXSC;
553 update_cr6(db->cr6_data, ioaddr);
554 }
555
556
557 /*
558 * Hardware start transmission.
559 * Send a packet to media from the upper layer.
560 */
561
562 static int uli526x_start_xmit(struct sk_buff *skb, struct net_device *dev)
563 {
564 struct uli526x_board_info *db = netdev_priv(dev);
565 struct tx_desc *txptr;
566 unsigned long flags;
567
568 ULI526X_DBUG(0, "uli526x_start_xmit", 0);
569
570 /* Resource flag check */
571 netif_stop_queue(dev);
572
573 /* Too large packet check */
574 if (skb->len > MAX_PACKET_SIZE) {
575 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
576 dev_kfree_skb(skb);
577 return 0;
578 }
579
580 spin_lock_irqsave(&db->lock, flags);
581
582 /* No Tx resource check, it never happen nromally */
583 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
584 spin_unlock_irqrestore(&db->lock, flags);
585 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n", db->tx_packet_cnt);
586 return 1;
587 }
588
589 /* Disable NIC interrupt */
590 outl(0, dev->base_addr + DCR7);
591
592 /* transmit this packet */
593 txptr = db->tx_insert_ptr;
594 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
595 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
596
597 /* Point to next transmit free descriptor */
598 db->tx_insert_ptr = txptr->next_tx_desc;
599
600 /* Transmit Packet Process */
601 if ( (db->tx_packet_cnt < TX_DESC_CNT) ) {
602 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
603 db->tx_packet_cnt++; /* Ready to send */
604 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
605 dev->trans_start = jiffies; /* saved time stamp */
606 }
607
608 /* Tx resource check */
609 if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
610 netif_wake_queue(dev);
611
612 /* Restore CR7 to enable interrupt */
613 spin_unlock_irqrestore(&db->lock, flags);
614 outl(db->cr7_data, dev->base_addr + DCR7);
615
616 /* free this SKB */
617 dev_kfree_skb(skb);
618
619 return 0;
620 }
621
622
623 /*
624 * Stop the interface.
625 * The interface is stopped when it is brought.
626 */
627
628 static int uli526x_stop(struct net_device *dev)
629 {
630 struct uli526x_board_info *db = netdev_priv(dev);
631 unsigned long ioaddr = dev->base_addr;
632
633 ULI526X_DBUG(0, "uli526x_stop", 0);
634
635 /* disable system */
636 netif_stop_queue(dev);
637
638 /* deleted timer */
639 del_timer_sync(&db->timer);
640
641 /* Reset & stop ULI526X board */
642 outl(ULI526X_RESET, ioaddr + DCR0);
643 udelay(5);
644 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
645
646 /* free interrupt */
647 free_irq(dev->irq, dev);
648
649 /* free allocated rx buffer */
650 uli526x_free_rxbuffer(db);
651
652 #if 0
653 /* show statistic counter */
654 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
655 db->tx_fifo_underrun, db->tx_excessive_collision,
656 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
657 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
658 db->reset_fatal, db->reset_TXtimeout);
659 #endif
660
661 return 0;
662 }
663
664
665 /*
666 * M5261/M5263 insterrupt handler
667 * receive the packet to upper layer, free the transmitted packet
668 */
669
670 static irqreturn_t uli526x_interrupt(int irq, void *dev_id)
671 {
672 struct net_device *dev = dev_id;
673 struct uli526x_board_info *db = netdev_priv(dev);
674 unsigned long ioaddr = dev->base_addr;
675 unsigned long flags;
676
677 spin_lock_irqsave(&db->lock, flags);
678 outl(0, ioaddr + DCR7);
679
680 /* Got ULI526X status */
681 db->cr5_data = inl(ioaddr + DCR5);
682 outl(db->cr5_data, ioaddr + DCR5);
683 if ( !(db->cr5_data & 0x180c1) ) {
684 spin_unlock_irqrestore(&db->lock, flags);
685 outl(db->cr7_data, ioaddr + DCR7);
686 return IRQ_HANDLED;
687 }
688
689 /* Check system status */
690 if (db->cr5_data & 0x2000) {
691 /* system bus error happen */
692 ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
693 db->reset_fatal++;
694 db->wait_reset = 1; /* Need to RESET */
695 spin_unlock_irqrestore(&db->lock, flags);
696 return IRQ_HANDLED;
697 }
698
699 /* Received the coming packet */
700 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
701 uli526x_rx_packet(dev, db);
702
703 /* reallocate rx descriptor buffer */
704 if (db->rx_avail_cnt<RX_DESC_CNT)
705 allocate_rx_buffer(db);
706
707 /* Free the transmitted descriptor */
708 if ( db->cr5_data & 0x01)
709 uli526x_free_tx_pkt(dev, db);
710
711 /* Restore CR7 to enable interrupt mask */
712 outl(db->cr7_data, ioaddr + DCR7);
713
714 spin_unlock_irqrestore(&db->lock, flags);
715 return IRQ_HANDLED;
716 }
717
718
719 /*
720 * Free TX resource after TX complete
721 */
722
723 static void uli526x_free_tx_pkt(struct net_device *dev, struct uli526x_board_info * db)
724 {
725 struct tx_desc *txptr;
726 u32 tdes0;
727
728 txptr = db->tx_remove_ptr;
729 while(db->tx_packet_cnt) {
730 tdes0 = le32_to_cpu(txptr->tdes0);
731 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
732 if (tdes0 & 0x80000000)
733 break;
734
735 /* A packet sent completed */
736 db->tx_packet_cnt--;
737 db->stats.tx_packets++;
738
739 /* Transmit statistic counter */
740 if ( tdes0 != 0x7fffffff ) {
741 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
742 db->stats.collisions += (tdes0 >> 3) & 0xf;
743 db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
744 if (tdes0 & TDES0_ERR_MASK) {
745 db->stats.tx_errors++;
746 if (tdes0 & 0x0002) { /* UnderRun */
747 db->tx_fifo_underrun++;
748 if ( !(db->cr6_data & CR6_SFT) ) {
749 db->cr6_data = db->cr6_data | CR6_SFT;
750 update_cr6(db->cr6_data, db->ioaddr);
751 }
752 }
753 if (tdes0 & 0x0100)
754 db->tx_excessive_collision++;
755 if (tdes0 & 0x0200)
756 db->tx_late_collision++;
757 if (tdes0 & 0x0400)
758 db->tx_no_carrier++;
759 if (tdes0 & 0x0800)
760 db->tx_loss_carrier++;
761 if (tdes0 & 0x4000)
762 db->tx_jabber_timeout++;
763 }
764 }
765
766 txptr = txptr->next_tx_desc;
767 }/* End of while */
768
769 /* Update TX remove pointer to next */
770 db->tx_remove_ptr = txptr;
771
772 /* Resource available check */
773 if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
774 netif_wake_queue(dev); /* Active upper layer, send again */
775 }
776
777
778 /*
779 * Receive the come packet and pass to upper layer
780 */
781
782 static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
783 {
784 struct rx_desc *rxptr;
785 struct sk_buff *skb;
786 int rxlen;
787 u32 rdes0;
788
789 rxptr = db->rx_ready_ptr;
790
791 while(db->rx_avail_cnt) {
792 rdes0 = le32_to_cpu(rxptr->rdes0);
793 if (rdes0 & 0x80000000) /* packet owner check */
794 {
795 break;
796 }
797
798 db->rx_avail_cnt--;
799 db->interval_rx_cnt++;
800
801 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
802 if ( (rdes0 & 0x300) != 0x300) {
803 /* A packet without First/Last flag */
804 /* reuse this SKB */
805 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
806 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
807 } else {
808 /* A packet with First/Last flag */
809 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
810
811 /* error summary bit check */
812 if (rdes0 & 0x8000) {
813 /* This is a error packet */
814 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
815 db->stats.rx_errors++;
816 if (rdes0 & 1)
817 db->stats.rx_fifo_errors++;
818 if (rdes0 & 2)
819 db->stats.rx_crc_errors++;
820 if (rdes0 & 0x80)
821 db->stats.rx_length_errors++;
822 }
823
824 if ( !(rdes0 & 0x8000) ||
825 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
826 skb = rxptr->rx_skb_ptr;
827
828 /* Good packet, send to upper layer */
829 /* Shorst packet used new SKB */
830 if ( (rxlen < RX_COPY_SIZE) &&
831 ( (skb = dev_alloc_skb(rxlen + 2) )
832 != NULL) ) {
833 /* size less than COPY_SIZE, allocate a rxlen SKB */
834 skb_reserve(skb, 2); /* 16byte align */
835 memcpy(skb_put(skb, rxlen),
836 skb_tail_pointer(rxptr->rx_skb_ptr),
837 rxlen);
838 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
839 } else
840 skb_put(skb, rxlen);
841
842 skb->protocol = eth_type_trans(skb, dev);
843 netif_rx(skb);
844 dev->last_rx = jiffies;
845 db->stats.rx_packets++;
846 db->stats.rx_bytes += rxlen;
847
848 } else {
849 /* Reuse SKB buffer when the packet is error */
850 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
851 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
852 }
853 }
854
855 rxptr = rxptr->next_rx_desc;
856 }
857
858 db->rx_ready_ptr = rxptr;
859 }
860
861
862 /*
863 * Get statistics from driver.
864 */
865
866 static struct net_device_stats * uli526x_get_stats(struct net_device *dev)
867 {
868 struct uli526x_board_info *db = netdev_priv(dev);
869
870 ULI526X_DBUG(0, "uli526x_get_stats", 0);
871 return &db->stats;
872 }
873
874
875 /*
876 * Set ULI526X multicast address
877 */
878
879 static void uli526x_set_filter_mode(struct net_device * dev)
880 {
881 struct uli526x_board_info *db = dev->priv;
882 unsigned long flags;
883
884 ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
885 spin_lock_irqsave(&db->lock, flags);
886
887 if (dev->flags & IFF_PROMISC) {
888 ULI526X_DBUG(0, "Enable PROM Mode", 0);
889 db->cr6_data |= CR6_PM | CR6_PBF;
890 update_cr6(db->cr6_data, db->ioaddr);
891 spin_unlock_irqrestore(&db->lock, flags);
892 return;
893 }
894
895 if (dev->flags & IFF_ALLMULTI || dev->mc_count > ULI5261_MAX_MULTICAST) {
896 ULI526X_DBUG(0, "Pass all multicast address", dev->mc_count);
897 db->cr6_data &= ~(CR6_PM | CR6_PBF);
898 db->cr6_data |= CR6_PAM;
899 spin_unlock_irqrestore(&db->lock, flags);
900 return;
901 }
902
903 ULI526X_DBUG(0, "Set multicast address", dev->mc_count);
904 send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */
905 spin_unlock_irqrestore(&db->lock, flags);
906 }
907
908 static void
909 ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd)
910 {
911 ecmd->supported = (SUPPORTED_10baseT_Half |
912 SUPPORTED_10baseT_Full |
913 SUPPORTED_100baseT_Half |
914 SUPPORTED_100baseT_Full |
915 SUPPORTED_Autoneg |
916 SUPPORTED_MII);
917
918 ecmd->advertising = (ADVERTISED_10baseT_Half |
919 ADVERTISED_10baseT_Full |
920 ADVERTISED_100baseT_Half |
921 ADVERTISED_100baseT_Full |
922 ADVERTISED_Autoneg |
923 ADVERTISED_MII);
924
925
926 ecmd->port = PORT_MII;
927 ecmd->phy_address = db->phy_addr;
928
929 ecmd->transceiver = XCVR_EXTERNAL;
930
931 ecmd->speed = 10;
932 ecmd->duplex = DUPLEX_HALF;
933
934 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
935 {
936 ecmd->speed = 100;
937 }
938 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
939 {
940 ecmd->duplex = DUPLEX_FULL;
941 }
942 if(db->link_failed)
943 {
944 ecmd->speed = -1;
945 ecmd->duplex = -1;
946 }
947
948 if (db->media_mode & ULI526X_AUTO)
949 {
950 ecmd->autoneg = AUTONEG_ENABLE;
951 }
952 }
953
954 static void netdev_get_drvinfo(struct net_device *dev,
955 struct ethtool_drvinfo *info)
956 {
957 struct uli526x_board_info *np = netdev_priv(dev);
958
959 strcpy(info->driver, DRV_NAME);
960 strcpy(info->version, DRV_VERSION);
961 if (np->pdev)
962 strcpy(info->bus_info, pci_name(np->pdev));
963 else
964 sprintf(info->bus_info, "EISA 0x%lx %d",
965 dev->base_addr, dev->irq);
966 }
967
968 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) {
969 struct uli526x_board_info *np = netdev_priv(dev);
970
971 ULi_ethtool_gset(np, cmd);
972
973 return 0;
974 }
975
976 static u32 netdev_get_link(struct net_device *dev) {
977 struct uli526x_board_info *np = netdev_priv(dev);
978
979 if(np->link_failed)
980 return 0;
981 else
982 return 1;
983 }
984
985 static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
986 {
987 wol->supported = WAKE_PHY | WAKE_MAGIC;
988 wol->wolopts = 0;
989 }
990
991 static const struct ethtool_ops netdev_ethtool_ops = {
992 .get_drvinfo = netdev_get_drvinfo,
993 .get_settings = netdev_get_settings,
994 .get_link = netdev_get_link,
995 .get_wol = uli526x_get_wol,
996 };
997
998 /*
999 * A periodic timer routine
1000 * Dynamic media sense, allocate Rx buffer...
1001 */
1002
1003 static void uli526x_timer(unsigned long data)
1004 {
1005 u32 tmp_cr8;
1006 unsigned char tmp_cr12=0;
1007 struct net_device *dev = (struct net_device *) data;
1008 struct uli526x_board_info *db = netdev_priv(dev);
1009 unsigned long flags;
1010 u8 TmpSpeed=10;
1011
1012 //ULI526X_DBUG(0, "uli526x_timer()", 0);
1013 spin_lock_irqsave(&db->lock, flags);
1014
1015
1016 /* Dynamic reset ULI526X : system error or transmit time-out */
1017 tmp_cr8 = inl(db->ioaddr + DCR8);
1018 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1019 db->reset_cr8++;
1020 db->wait_reset = 1;
1021 }
1022 db->interval_rx_cnt = 0;
1023
1024 /* TX polling kick monitor */
1025 if ( db->tx_packet_cnt &&
1026 time_after(jiffies, dev->trans_start + ULI526X_TX_KICK) ) {
1027 outl(0x1, dev->base_addr + DCR1); // Tx polling again
1028
1029 // TX Timeout
1030 if ( time_after(jiffies, dev->trans_start + ULI526X_TX_TIMEOUT) ) {
1031 db->reset_TXtimeout++;
1032 db->wait_reset = 1;
1033 printk( "%s: Tx timeout - resetting\n",
1034 dev->name);
1035 }
1036 }
1037
1038 if (db->wait_reset) {
1039 ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1040 db->reset_count++;
1041 uli526x_dynamic_reset(dev);
1042 db->timer.expires = ULI526X_TIMER_WUT;
1043 add_timer(&db->timer);
1044 spin_unlock_irqrestore(&db->lock, flags);
1045 return;
1046 }
1047
1048 /* Link status check, Dynamic media type change */
1049 if((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)!=0)
1050 tmp_cr12 = 3;
1051
1052 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1053 /* Link Failed */
1054 ULI526X_DBUG(0, "Link Failed", tmp_cr12);
1055 netif_carrier_off(dev);
1056 printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name);
1057 db->link_failed = 1;
1058
1059 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1060 /* AUTO don't need */
1061 if ( !(db->media_mode & 0x8) )
1062 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1063
1064 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1065 if (db->media_mode & ULI526X_AUTO) {
1066 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1067 update_cr6(db->cr6_data, db->ioaddr);
1068 }
1069 } else
1070 if ((tmp_cr12 & 0x3) && db->link_failed) {
1071 ULI526X_DBUG(0, "Link link OK", tmp_cr12);
1072 db->link_failed = 0;
1073
1074 /* Auto Sense Speed */
1075 if ( (db->media_mode & ULI526X_AUTO) &&
1076 uli526x_sense_speed(db) )
1077 db->link_failed = 1;
1078 uli526x_process_mode(db);
1079
1080 if(db->link_failed==0)
1081 {
1082 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
1083 {
1084 TmpSpeed = 100;
1085 }
1086 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
1087 {
1088 printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Full duplex\n",dev->name,TmpSpeed);
1089 }
1090 else
1091 {
1092 printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Half duplex\n",dev->name,TmpSpeed);
1093 }
1094 netif_carrier_on(dev);
1095 }
1096 /* SHOW_MEDIA_TYPE(db->op_mode); */
1097 }
1098 else if(!(tmp_cr12 & 0x3) && db->link_failed)
1099 {
1100 if(db->init==1)
1101 {
1102 printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name);
1103 netif_carrier_off(dev);
1104 }
1105 }
1106 db->init=0;
1107
1108 /* Timer active again */
1109 db->timer.expires = ULI526X_TIMER_WUT;
1110 add_timer(&db->timer);
1111 spin_unlock_irqrestore(&db->lock, flags);
1112 }
1113
1114
1115 /*
1116 * Stop ULI526X board
1117 * Free Tx/Rx allocated memory
1118 * Init system variable
1119 */
1120
1121 static void uli526x_reset_prepare(struct net_device *dev)
1122 {
1123 struct uli526x_board_info *db = netdev_priv(dev);
1124
1125 /* Sopt MAC controller */
1126 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1127 update_cr6(db->cr6_data, dev->base_addr);
1128 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1129 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1130
1131 /* Disable upper layer interface */
1132 netif_stop_queue(dev);
1133
1134 /* Free Rx Allocate buffer */
1135 uli526x_free_rxbuffer(db);
1136
1137 /* system variable init */
1138 db->tx_packet_cnt = 0;
1139 db->rx_avail_cnt = 0;
1140 db->link_failed = 1;
1141 db->init=1;
1142 db->wait_reset = 0;
1143 }
1144
1145
1146 /*
1147 * Dynamic reset the ULI526X board
1148 * Stop ULI526X board
1149 * Free Tx/Rx allocated memory
1150 * Reset ULI526X board
1151 * Re-initialize ULI526X board
1152 */
1153
1154 static void uli526x_dynamic_reset(struct net_device *dev)
1155 {
1156 ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1157
1158 uli526x_reset_prepare(dev);
1159
1160 /* Re-initialize ULI526X board */
1161 uli526x_init(dev);
1162
1163 /* Restart upper layer interface */
1164 netif_wake_queue(dev);
1165 }
1166
1167
1168 #ifdef CONFIG_PM
1169
1170 /*
1171 * Suspend the interface.
1172 */
1173
1174 static int uli526x_suspend(struct pci_dev *pdev, pm_message_t state)
1175 {
1176 struct net_device *dev = pci_get_drvdata(pdev);
1177 pci_power_t power_state;
1178 int err;
1179
1180 ULI526X_DBUG(0, "uli526x_suspend", 0);
1181
1182 if (!netdev_priv(dev))
1183 return 0;
1184
1185 pci_save_state(pdev);
1186
1187 if (!netif_running(dev))
1188 return 0;
1189
1190 netif_device_detach(dev);
1191 uli526x_reset_prepare(dev);
1192
1193 power_state = pci_choose_state(pdev, state);
1194 pci_enable_wake(pdev, power_state, 0);
1195 err = pci_set_power_state(pdev, power_state);
1196 if (err) {
1197 netif_device_attach(dev);
1198 /* Re-initialize ULI526X board */
1199 uli526x_init(dev);
1200 /* Restart upper layer interface */
1201 netif_wake_queue(dev);
1202 }
1203
1204 return err;
1205 }
1206
1207 /*
1208 * Resume the interface.
1209 */
1210
1211 static int uli526x_resume(struct pci_dev *pdev)
1212 {
1213 struct net_device *dev = pci_get_drvdata(pdev);
1214 int err;
1215
1216 ULI526X_DBUG(0, "uli526x_resume", 0);
1217
1218 if (!netdev_priv(dev))
1219 return 0;
1220
1221 pci_restore_state(pdev);
1222
1223 if (!netif_running(dev))
1224 return 0;
1225
1226 err = pci_set_power_state(pdev, PCI_D0);
1227 if (err) {
1228 printk(KERN_WARNING "%s: Could not put device into D0\n",
1229 dev->name);
1230 return err;
1231 }
1232
1233 netif_device_attach(dev);
1234 /* Re-initialize ULI526X board */
1235 uli526x_init(dev);
1236 /* Restart upper layer interface */
1237 netif_wake_queue(dev);
1238
1239 return 0;
1240 }
1241
1242 #else /* !CONFIG_PM */
1243
1244 #define uli526x_suspend NULL
1245 #define uli526x_resume NULL
1246
1247 #endif /* !CONFIG_PM */
1248
1249
1250 /*
1251 * free all allocated rx buffer
1252 */
1253
1254 static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1255 {
1256 ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1257
1258 /* free allocated rx buffer */
1259 while (db->rx_avail_cnt) {
1260 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1261 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1262 db->rx_avail_cnt--;
1263 }
1264 }
1265
1266
1267 /*
1268 * Reuse the SK buffer
1269 */
1270
1271 static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1272 {
1273 struct rx_desc *rxptr = db->rx_insert_ptr;
1274
1275 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1276 rxptr->rx_skb_ptr = skb;
1277 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1278 skb_tail_pointer(skb),
1279 RX_ALLOC_SIZE,
1280 PCI_DMA_FROMDEVICE));
1281 wmb();
1282 rxptr->rdes0 = cpu_to_le32(0x80000000);
1283 db->rx_avail_cnt++;
1284 db->rx_insert_ptr = rxptr->next_rx_desc;
1285 } else
1286 ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1287 }
1288
1289
1290 /*
1291 * Initialize transmit/Receive descriptor
1292 * Using Chain structure, and allocate Tx/Rx buffer
1293 */
1294
1295 static void uli526x_descriptor_init(struct uli526x_board_info *db, unsigned long ioaddr)
1296 {
1297 struct tx_desc *tmp_tx;
1298 struct rx_desc *tmp_rx;
1299 unsigned char *tmp_buf;
1300 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1301 dma_addr_t tmp_buf_dma;
1302 int i;
1303
1304 ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1305
1306 /* tx descriptor start pointer */
1307 db->tx_insert_ptr = db->first_tx_desc;
1308 db->tx_remove_ptr = db->first_tx_desc;
1309 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1310
1311 /* rx descriptor start pointer */
1312 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1313 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1314 db->rx_insert_ptr = db->first_rx_desc;
1315 db->rx_ready_ptr = db->first_rx_desc;
1316 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1317
1318 /* Init Transmit chain */
1319 tmp_buf = db->buf_pool_start;
1320 tmp_buf_dma = db->buf_pool_dma_start;
1321 tmp_tx_dma = db->first_tx_desc_dma;
1322 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1323 tmp_tx->tx_buf_ptr = tmp_buf;
1324 tmp_tx->tdes0 = cpu_to_le32(0);
1325 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1326 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1327 tmp_tx_dma += sizeof(struct tx_desc);
1328 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1329 tmp_tx->next_tx_desc = tmp_tx + 1;
1330 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1331 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1332 }
1333 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1334 tmp_tx->next_tx_desc = db->first_tx_desc;
1335
1336 /* Init Receive descriptor chain */
1337 tmp_rx_dma=db->first_rx_desc_dma;
1338 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1339 tmp_rx->rdes0 = cpu_to_le32(0);
1340 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1341 tmp_rx_dma += sizeof(struct rx_desc);
1342 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1343 tmp_rx->next_rx_desc = tmp_rx + 1;
1344 }
1345 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1346 tmp_rx->next_rx_desc = db->first_rx_desc;
1347
1348 /* pre-allocate Rx buffer */
1349 allocate_rx_buffer(db);
1350 }
1351
1352
1353 /*
1354 * Update CR6 value
1355 * Firstly stop ULI526X, then written value and start
1356 */
1357
1358 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1359 {
1360
1361 outl(cr6_data, ioaddr + DCR6);
1362 udelay(5);
1363 }
1364
1365
1366 /*
1367 * Send a setup frame for M5261/M5263
1368 * This setup frame initialize ULI526X address filter mode
1369 */
1370
1371 #ifdef __BIG_ENDIAN
1372 #define FLT_SHIFT 16
1373 #else
1374 #define FLT_SHIFT 0
1375 #endif
1376
1377 static void send_filter_frame(struct net_device *dev, int mc_cnt)
1378 {
1379 struct uli526x_board_info *db = netdev_priv(dev);
1380 struct dev_mc_list *mcptr;
1381 struct tx_desc *txptr;
1382 u16 * addrptr;
1383 u32 * suptr;
1384 int i;
1385
1386 ULI526X_DBUG(0, "send_filter_frame()", 0);
1387
1388 txptr = db->tx_insert_ptr;
1389 suptr = (u32 *) txptr->tx_buf_ptr;
1390
1391 /* Node address */
1392 addrptr = (u16 *) dev->dev_addr;
1393 *suptr++ = addrptr[0] << FLT_SHIFT;
1394 *suptr++ = addrptr[1] << FLT_SHIFT;
1395 *suptr++ = addrptr[2] << FLT_SHIFT;
1396
1397 /* broadcast address */
1398 *suptr++ = 0xffff << FLT_SHIFT;
1399 *suptr++ = 0xffff << FLT_SHIFT;
1400 *suptr++ = 0xffff << FLT_SHIFT;
1401
1402 /* fit the multicast address */
1403 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1404 addrptr = (u16 *) mcptr->dmi_addr;
1405 *suptr++ = addrptr[0] << FLT_SHIFT;
1406 *suptr++ = addrptr[1] << FLT_SHIFT;
1407 *suptr++ = addrptr[2] << FLT_SHIFT;
1408 }
1409
1410 for (; i<14; i++) {
1411 *suptr++ = 0xffff << FLT_SHIFT;
1412 *suptr++ = 0xffff << FLT_SHIFT;
1413 *suptr++ = 0xffff << FLT_SHIFT;
1414 }
1415
1416 /* prepare the setup frame */
1417 db->tx_insert_ptr = txptr->next_tx_desc;
1418 txptr->tdes1 = cpu_to_le32(0x890000c0);
1419
1420 /* Resource Check and Send the setup packet */
1421 if (db->tx_packet_cnt < TX_DESC_CNT) {
1422 /* Resource Empty */
1423 db->tx_packet_cnt++;
1424 txptr->tdes0 = cpu_to_le32(0x80000000);
1425 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1426 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1427 update_cr6(db->cr6_data, dev->base_addr);
1428 dev->trans_start = jiffies;
1429 } else
1430 printk(KERN_ERR DRV_NAME ": No Tx resource - Send_filter_frame!\n");
1431 }
1432
1433
1434 /*
1435 * Allocate rx buffer,
1436 * As possible as allocate maxiumn Rx buffer
1437 */
1438
1439 static void allocate_rx_buffer(struct uli526x_board_info *db)
1440 {
1441 struct rx_desc *rxptr;
1442 struct sk_buff *skb;
1443
1444 rxptr = db->rx_insert_ptr;
1445
1446 while(db->rx_avail_cnt < RX_DESC_CNT) {
1447 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1448 break;
1449 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1450 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1451 skb_tail_pointer(skb),
1452 RX_ALLOC_SIZE,
1453 PCI_DMA_FROMDEVICE));
1454 wmb();
1455 rxptr->rdes0 = cpu_to_le32(0x80000000);
1456 rxptr = rxptr->next_rx_desc;
1457 db->rx_avail_cnt++;
1458 }
1459
1460 db->rx_insert_ptr = rxptr;
1461 }
1462
1463
1464 /*
1465 * Read one word data from the serial ROM
1466 */
1467
1468 static u16 read_srom_word(long ioaddr, int offset)
1469 {
1470 int i;
1471 u16 srom_data = 0;
1472 long cr9_ioaddr = ioaddr + DCR9;
1473
1474 outl(CR9_SROM_READ, cr9_ioaddr);
1475 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1476
1477 /* Send the Read Command 110b */
1478 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1479 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1480 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1481
1482 /* Send the offset */
1483 for (i = 5; i >= 0; i--) {
1484 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1485 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1486 }
1487
1488 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1489
1490 for (i = 16; i > 0; i--) {
1491 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1492 udelay(5);
1493 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1494 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1495 udelay(5);
1496 }
1497
1498 outl(CR9_SROM_READ, cr9_ioaddr);
1499 return srom_data;
1500 }
1501
1502
1503 /*
1504 * Auto sense the media mode
1505 */
1506
1507 static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1508 {
1509 u8 ErrFlag = 0;
1510 u16 phy_mode;
1511
1512 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1513 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1514
1515 if ( (phy_mode & 0x24) == 0x24 ) {
1516
1517 phy_mode = ((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)<<7);
1518 if(phy_mode&0x8000)
1519 phy_mode = 0x8000;
1520 else if(phy_mode&0x4000)
1521 phy_mode = 0x4000;
1522 else if(phy_mode&0x2000)
1523 phy_mode = 0x2000;
1524 else
1525 phy_mode = 0x1000;
1526
1527 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1528 switch (phy_mode) {
1529 case 0x1000: db->op_mode = ULI526X_10MHF; break;
1530 case 0x2000: db->op_mode = ULI526X_10MFD; break;
1531 case 0x4000: db->op_mode = ULI526X_100MHF; break;
1532 case 0x8000: db->op_mode = ULI526X_100MFD; break;
1533 default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1534 }
1535 } else {
1536 db->op_mode = ULI526X_10MHF;
1537 ULI526X_DBUG(0, "Link Failed :", phy_mode);
1538 ErrFlag = 1;
1539 }
1540
1541 return ErrFlag;
1542 }
1543
1544
1545 /*
1546 * Set 10/100 phyxcer capability
1547 * AUTO mode : phyxcer register4 is NIC capability
1548 * Force mode: phyxcer register4 is the force media
1549 */
1550
1551 static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1552 {
1553 u16 phy_reg;
1554
1555 /* Phyxcer capability setting */
1556 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1557
1558 if (db->media_mode & ULI526X_AUTO) {
1559 /* AUTO Mode */
1560 phy_reg |= db->PHY_reg4;
1561 } else {
1562 /* Force Mode */
1563 switch(db->media_mode) {
1564 case ULI526X_10MHF: phy_reg |= 0x20; break;
1565 case ULI526X_10MFD: phy_reg |= 0x40; break;
1566 case ULI526X_100MHF: phy_reg |= 0x80; break;
1567 case ULI526X_100MFD: phy_reg |= 0x100; break;
1568 }
1569
1570 }
1571
1572 /* Write new capability to Phyxcer Reg4 */
1573 if ( !(phy_reg & 0x01e0)) {
1574 phy_reg|=db->PHY_reg4;
1575 db->media_mode|=ULI526X_AUTO;
1576 }
1577 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1578
1579 /* Restart Auto-Negotiation */
1580 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1581 udelay(50);
1582 }
1583
1584
1585 /*
1586 * Process op-mode
1587 AUTO mode : PHY controller in Auto-negotiation Mode
1588 * Force mode: PHY controller in force mode with HUB
1589 * N-way force capability with SWITCH
1590 */
1591
1592 static void uli526x_process_mode(struct uli526x_board_info *db)
1593 {
1594 u16 phy_reg;
1595
1596 /* Full Duplex Mode Check */
1597 if (db->op_mode & 0x4)
1598 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1599 else
1600 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1601
1602 update_cr6(db->cr6_data, db->ioaddr);
1603
1604 /* 10/100M phyxcer force mode need */
1605 if ( !(db->media_mode & 0x8)) {
1606 /* Forece Mode */
1607 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1608 if ( !(phy_reg & 0x1) ) {
1609 /* parter without N-Way capability */
1610 phy_reg = 0x0;
1611 switch(db->op_mode) {
1612 case ULI526X_10MHF: phy_reg = 0x0; break;
1613 case ULI526X_10MFD: phy_reg = 0x100; break;
1614 case ULI526X_100MHF: phy_reg = 0x2000; break;
1615 case ULI526X_100MFD: phy_reg = 0x2100; break;
1616 }
1617 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1618 }
1619 }
1620 }
1621
1622
1623 /*
1624 * Write a word to Phy register
1625 */
1626
1627 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
1628 {
1629 u16 i;
1630 unsigned long ioaddr;
1631
1632 if(chip_id == PCI_ULI5263_ID)
1633 {
1634 phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
1635 return;
1636 }
1637 /* M5261/M5263 Chip */
1638 ioaddr = iobase + DCR9;
1639
1640 /* Send 33 synchronization clock to Phy controller */
1641 for (i = 0; i < 35; i++)
1642 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1643
1644 /* Send start command(01) to Phy */
1645 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1646 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1647
1648 /* Send write command(01) to Phy */
1649 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1650 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1651
1652 /* Send Phy address */
1653 for (i = 0x10; i > 0; i = i >> 1)
1654 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1655
1656 /* Send register address */
1657 for (i = 0x10; i > 0; i = i >> 1)
1658 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1659
1660 /* written trasnition */
1661 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1662 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1663
1664 /* Write a word data to PHY controller */
1665 for ( i = 0x8000; i > 0; i >>= 1)
1666 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1667
1668 }
1669
1670
1671 /*
1672 * Read a word data from phy register
1673 */
1674
1675 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1676 {
1677 int i;
1678 u16 phy_data;
1679 unsigned long ioaddr;
1680
1681 if(chip_id == PCI_ULI5263_ID)
1682 return phy_readby_cr10(iobase, phy_addr, offset);
1683 /* M5261/M5263 Chip */
1684 ioaddr = iobase + DCR9;
1685
1686 /* Send 33 synchronization clock to Phy controller */
1687 for (i = 0; i < 35; i++)
1688 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1689
1690 /* Send start command(01) to Phy */
1691 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1692 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1693
1694 /* Send read command(10) to Phy */
1695 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1696 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1697
1698 /* Send Phy address */
1699 for (i = 0x10; i > 0; i = i >> 1)
1700 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1701
1702 /* Send register address */
1703 for (i = 0x10; i > 0; i = i >> 1)
1704 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1705
1706 /* Skip transition state */
1707 phy_read_1bit(ioaddr, chip_id);
1708
1709 /* read 16bit data */
1710 for (phy_data = 0, i = 0; i < 16; i++) {
1711 phy_data <<= 1;
1712 phy_data |= phy_read_1bit(ioaddr, chip_id);
1713 }
1714
1715 return phy_data;
1716 }
1717
1718 static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
1719 {
1720 unsigned long ioaddr,cr10_value;
1721
1722 ioaddr = iobase + DCR10;
1723 cr10_value = phy_addr;
1724 cr10_value = (cr10_value<<5) + offset;
1725 cr10_value = (cr10_value<<16) + 0x08000000;
1726 outl(cr10_value,ioaddr);
1727 udelay(1);
1728 while(1)
1729 {
1730 cr10_value = inl(ioaddr);
1731 if(cr10_value&0x10000000)
1732 break;
1733 }
1734 return (cr10_value&0x0ffff);
1735 }
1736
1737 static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data)
1738 {
1739 unsigned long ioaddr,cr10_value;
1740
1741 ioaddr = iobase + DCR10;
1742 cr10_value = phy_addr;
1743 cr10_value = (cr10_value<<5) + offset;
1744 cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
1745 outl(cr10_value,ioaddr);
1746 udelay(1);
1747 }
1748 /*
1749 * Write one bit data to Phy Controller
1750 */
1751
1752 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
1753 {
1754 outl(phy_data , ioaddr); /* MII Clock Low */
1755 udelay(1);
1756 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1757 udelay(1);
1758 outl(phy_data , ioaddr); /* MII Clock Low */
1759 udelay(1);
1760 }
1761
1762
1763 /*
1764 * Read one bit phy data from PHY controller
1765 */
1766
1767 static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
1768 {
1769 u16 phy_data;
1770
1771 outl(0x50000 , ioaddr);
1772 udelay(1);
1773 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1774 outl(0x40000 , ioaddr);
1775 udelay(1);
1776
1777 return phy_data;
1778 }
1779
1780
1781 static struct pci_device_id uli526x_pci_tbl[] = {
1782 { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
1783 { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
1784 { 0, }
1785 };
1786 MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl);
1787
1788
1789 static struct pci_driver uli526x_driver = {
1790 .name = "uli526x",
1791 .id_table = uli526x_pci_tbl,
1792 .probe = uli526x_init_one,
1793 .remove = __devexit_p(uli526x_remove_one),
1794 .suspend = uli526x_suspend,
1795 .resume = uli526x_resume,
1796 };
1797
1798 MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1799 MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1800 MODULE_LICENSE("GPL");
1801
1802 module_param(debug, int, 0644);
1803 module_param(mode, int, 0);
1804 module_param(cr6set, int, 0);
1805 MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
1806 MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1807
1808 /* Description:
1809 * when user used insmod to add module, system invoked init_module()
1810 * to register the services.
1811 */
1812
1813 static int __init uli526x_init_module(void)
1814 {
1815
1816 printk(version);
1817 printed_version = 1;
1818
1819 ULI526X_DBUG(0, "init_module() ", debug);
1820
1821 if (debug)
1822 uli526x_debug = debug; /* set debug flag */
1823 if (cr6set)
1824 uli526x_cr6_user_set = cr6set;
1825
1826 switch (mode) {
1827 case ULI526X_10MHF:
1828 case ULI526X_100MHF:
1829 case ULI526X_10MFD:
1830 case ULI526X_100MFD:
1831 uli526x_media_mode = mode;
1832 break;
1833 default:
1834 uli526x_media_mode = ULI526X_AUTO;
1835 break;
1836 }
1837
1838 return pci_register_driver(&uli526x_driver);
1839 }
1840
1841
1842 /*
1843 * Description:
1844 * when user used rmmod to delete module, system invoked clean_module()
1845 * to un-register all registered services.
1846 */
1847
1848 static void __exit uli526x_cleanup_module(void)
1849 {
1850 ULI526X_DBUG(0, "uli526x_clean_module() ", debug);
1851 pci_unregister_driver(&uli526x_driver);
1852 }
1853
1854 module_init(uli526x_init_module);
1855 module_exit(uli526x_cleanup_module);
x86 "subsystem" repository