drivers/net/sfc/mdio_10g.h

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2006-2008 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9
  10 #ifndef EFX_MDIO_10G_H
  11 #define EFX_MDIO_10G_H
  12
  13 /*
  14  * Definitions needed for doing 10G MDIO as specified in clause 45
  15  * MDIO, which do not appear in Linux yet. Also some helper functions.
  16  */
  17
  18 #include "efx.h"
  19 #include "boards.h"
  20
  21 /* Numbering of the MDIO Manageable Devices (MMDs) */
  22 /* Physical Medium Attachment/ Physical Medium Dependent sublayer */
  23 #define MDIO_MMD_PMAPMD (1)
  24 /* WAN Interface Sublayer */
  25 #define MDIO_MMD_WIS    (2)
  26 /* Physical Coding Sublayer */
  27 #define MDIO_MMD_PCS    (3)
  28 /* PHY Extender Sublayer */
  29 #define MDIO_MMD_PHYXS  (4)
  30 /* Extender Sublayer */
  31 #define MDIO_MMD_DTEXS  (5)
  32 /* Transmission convergence */
  33 #define MDIO_MMD_TC     (6)
  34 /* Auto negotiation */
  35 #define MDIO_MMD_AN     (7)
  36
  37 /* Generic register locations */
  38 #define MDIO_MMDREG_CTRL1       (0)
  39 #define MDIO_MMDREG_STAT1       (1)
  40 #define MDIO_MMDREG_IDHI        (2)
  41 #define MDIO_MMDREG_IDLOW       (3)
  42 #define MDIO_MMDREG_SPEED       (4)
  43 #define MDIO_MMDREG_DEVS0       (5)
  44 #define MDIO_MMDREG_DEVS1       (6)
  45 #define MDIO_MMDREG_CTRL2       (7)
  46 #define MDIO_MMDREG_STAT2       (8)
  47
  48 /* Bits in MMDREG_CTRL1 */
  49 /* Reset */
  50 #define MDIO_MMDREG_CTRL1_RESET_LBN     (15)
  51 #define MDIO_MMDREG_CTRL1_RESET_WIDTH   (1)
  52
  53 /* Bits in MMDREG_STAT1 */
  54 #define MDIO_MMDREG_STAT1_FAULT_LBN     (7)
  55 #define MDIO_MMDREG_STAT1_FAULT_WIDTH   (1)
  56 /* Link state */
  57 #define MDIO_MMDREG_STAT1_LINK_LBN      (2)
  58 #define MDIO_MMDREG_STAT1_LINK_WIDTH    (1)
  59
  60 /* Bits in ID reg */
  61 #define MDIO_ID_REV(_id32)      (_id32 & 0xf)
  62 #define MDIO_ID_MODEL(_id32)    ((_id32 >> 4) & 0x3f)
  63 #define MDIO_ID_OUI(_id32)      (_id32 >> 10)
  64
  65 /* Bits in MMDREG_DEVS0. Someone thoughtfully layed things out
  66  * so the 'bit present' bit number of an MMD is the number of
  67  * that MMD */
  68 #define DEV_PRESENT_BIT(_b) (1 << _b)
  69
  70 #define MDIO_MMDREG_DEVS0_PHYXS  DEV_PRESENT_BIT(MDIO_MMD_PHYXS)
  71 #define MDIO_MMDREG_DEVS0_PCS    DEV_PRESENT_BIT(MDIO_MMD_PCS)
  72 #define MDIO_MMDREG_DEVS0_PMAPMD DEV_PRESENT_BIT(MDIO_MMD_PMAPMD)
  73
  74 /* Bits in MMDREG_STAT2 */
  75 #define MDIO_MMDREG_STAT2_PRESENT_VAL   (2)
  76 #define MDIO_MMDREG_STAT2_PRESENT_LBN   (14)
  77 #define MDIO_MMDREG_STAT2_PRESENT_WIDTH (2)
  78
  79 /* PMA type (4 bits) */
  80 #define MDIO_PMAPMD_CTRL2_10G_CX4       (0x0)
  81 #define MDIO_PMAPMD_CTRL2_10G_EW        (0x1)
  82 #define MDIO_PMAPMD_CTRL2_10G_LW        (0x2)
  83 #define MDIO_PMAPMD_CTRL2_10G_SW        (0x3)
  84 #define MDIO_PMAPMD_CTRL2_10G_LX4       (0x4)
  85 #define MDIO_PMAPMD_CTRL2_10G_ER        (0x5)
  86 #define MDIO_PMAPMD_CTRL2_10G_LR        (0x6)
  87 #define MDIO_PMAPMD_CTRL2_10G_SR        (0x7)
  88 /* Reserved */
  89 #define MDIO_PMAPMD_CTRL2_10G_BT        (0x9)
  90 /* Reserved */
  91 /* Reserved */
  92 #define MDIO_PMAPMD_CTRL2_1G_BT         (0xc)
  93 /* Reserved */
  94 #define MDIO_PMAPMD_CTRL2_100_BT        (0xe)
  95 #define MDIO_PMAPMD_CTRL2_10_BT         (0xf)
  96 #define MDIO_PMAPMD_CTRL2_TYPE_MASK     (0xf)
  97
  98 /* PHY XGXS lane state */
  99 #define MDIO_PHYXS_LANE_STATE           (0x18)
 100 #define MDIO_PHYXS_LANE_ALIGNED_LBN     (12)
 101
 102 /* AN registers */
 103 #define MDIO_AN_STATUS                  (1)
 104 #define MDIO_AN_STATUS_XNP_LBN          (7)
 105 #define MDIO_AN_STATUS_PAGE_LBN         (6)
 106 #define MDIO_AN_STATUS_AN_DONE_LBN      (5)
 107 #define MDIO_AN_STATUS_LP_AN_CAP_LBN    (0)
 108
 109 #define MDIO_AN_10GBT_STATUS            (33)
 110 #define MDIO_AN_10GBT_STATUS_MS_FLT_LBN (15) /* MASTER/SLAVE config fault */
 111 #define MDIO_AN_10GBT_STATUS_MS_LBN     (14) /* MASTER/SLAVE config */
 112 #define MDIO_AN_10GBT_STATUS_LOC_OK_LBN (13) /* Local OK */
 113 #define MDIO_AN_10GBT_STATUS_REM_OK_LBN (12) /* Remote OK */
 114 #define MDIO_AN_10GBT_STATUS_LP_10G_LBN (11) /* Link partner is 10GBT capable */
 115 #define MDIO_AN_10GBT_STATUS_LP_LTA_LBN (10) /* LP loop timing ability */
 116 #define MDIO_AN_10GBT_STATUS_LP_TRR_LBN (9)  /* LP Training Reset Request */
 117
 118
 119 /* Packing of the prt and dev arguments of clause 45 style MDIO into a
 120  * single int so they can be passed into the mdio_read/write functions
 121  * that currently exist. Note that as Falcon is the only current user,
 122  * the packed form is chosen to match what Falcon needs to write into
 123  * a register. This is checked at compile-time so do not change it. If
 124  * your target chip needs things layed out differently you will need
 125  * to unpack the arguments in your chip-specific mdio functions.
 126  */
 127  /* These are defined by the standard. */
 128 #define MDIO45_PRT_ID_WIDTH  (5)
 129 #define MDIO45_DEV_ID_WIDTH  (5)
 130
 131 /* The prt ID is just packed in immediately to the left of the dev ID */
 132 #define MDIO45_PRT_DEV_WIDTH (MDIO45_PRT_ID_WIDTH + MDIO45_DEV_ID_WIDTH)
 133
 134 #define MDIO45_PRT_ID_MASK   ((1 << MDIO45_PRT_DEV_WIDTH) - 1)
 135 /* This is the prt + dev extended by 1 bit to hold the 'is clause 45' flag. */
 136 #define MDIO45_XPRT_ID_WIDTH   (MDIO45_PRT_DEV_WIDTH + 1)
 137 #define MDIO45_XPRT_ID_MASK   ((1 << MDIO45_XPRT_ID_WIDTH) - 1)
 138 #define MDIO45_XPRT_ID_IS10G   (1 << (MDIO45_XPRT_ID_WIDTH - 1))
 139
 140
 141 #define MDIO45_PRT_ID_COMP_LBN   MDIO45_DEV_ID_WIDTH
 142 #define MDIO45_PRT_ID_COMP_WIDTH  MDIO45_PRT_ID_WIDTH
 143 #define MDIO45_DEV_ID_COMP_LBN    0
 144 #define MDIO45_DEV_ID_COMP_WIDTH  MDIO45_DEV_ID_WIDTH
 145
 146 /* Compose port and device into a phy_id */
 147 static inline int mdio_clause45_pack(u8 prt, u8 dev)
 148 {
 149         efx_dword_t phy_id;
 150         EFX_POPULATE_DWORD_2(phy_id, MDIO45_PRT_ID_COMP, prt,
 151                              MDIO45_DEV_ID_COMP, dev);
 152         return MDIO45_XPRT_ID_IS10G | EFX_DWORD_VAL(phy_id);
 153 }
 154
 155 static inline void mdio_clause45_unpack(u32 val, u8 *prt, u8 *dev)
 156 {
 157         efx_dword_t phy_id;
 158         EFX_POPULATE_DWORD_1(phy_id, EFX_DWORD_0, val);
 159         *prt = EFX_DWORD_FIELD(phy_id, MDIO45_PRT_ID_COMP);
 160         *dev = EFX_DWORD_FIELD(phy_id, MDIO45_DEV_ID_COMP);
 161 }
 162
 163 static inline int mdio_clause45_read(struct efx_nic *efx,
 164                                      u8 prt, u8 dev, u16 addr)
 165 {
 166         return efx->mii.mdio_read(efx->net_dev,
 167                                   mdio_clause45_pack(prt, dev), addr);
 168 }
 169
 170 static inline void mdio_clause45_write(struct efx_nic *efx,
 171                                        u8 prt, u8 dev, u16 addr, int value)
 172 {
 173         efx->mii.mdio_write(efx->net_dev,
 174                             mdio_clause45_pack(prt, dev), addr, value);
 175 }
 176
 177
 178 static inline u32 mdio_clause45_read_id(struct efx_nic *efx, int mmd)
 179 {
 180         int phy_id = efx->mii.phy_id;
 181         u16 id_low = mdio_clause45_read(efx, phy_id, mmd, MDIO_MMDREG_IDLOW);
 182         u16 id_hi = mdio_clause45_read(efx, phy_id, mmd, MDIO_MMDREG_IDHI);
 183         return (id_hi << 16) | (id_low);
 184 }
 185
 186 static inline int mdio_clause45_phyxgxs_lane_sync(struct efx_nic *efx)
 187 {
 188         int i, sync, lane_status;
 189
 190         for (i = 0; i < 2; ++i)
 191                 lane_status = mdio_clause45_read(efx, efx->mii.phy_id,
 192                                                  MDIO_MMD_PHYXS,
 193                                                  MDIO_PHYXS_LANE_STATE);
 194
 195         sync = (lane_status & (1 << MDIO_PHYXS_LANE_ALIGNED_LBN)) != 0;
 196         if (!sync)
 197                 EFX_INFO(efx, "XGXS lane status: %x\n", lane_status);
 198         return sync;
 199 }
 200
 201 extern const char *mdio_clause45_mmd_name(int mmd);
 202
 203 /*
 204  * Reset a specific MMD and wait for reset to clear.
 205  * Return number of spins left (>0) on success, -%ETIMEDOUT on failure.
 206  *
 207  * This function will sleep
 208  */
 209 extern int mdio_clause45_reset_mmd(struct efx_nic *efx, int mmd,
 210                                    int spins, int spintime);
 211
 212 /* As mdio_clause45_check_mmd but for multiple MMDs */
 213 int mdio_clause45_check_mmds(struct efx_nic *efx,
 214                              unsigned int mmd_mask, unsigned int fatal_mask);
 215
 216 /* Check the link status of specified mmds in bit mask */
 217 extern int mdio_clause45_links_ok(struct efx_nic *efx,
 218                                   unsigned int mmd_mask);
 219
 220 /* Read (some of) the PHY settings over MDIO */
 221 extern void mdio_clause45_get_settings(struct efx_nic *efx,
 222                                        struct ethtool_cmd *ecmd);
 223
 224 /* Set (some of) the PHY settings over MDIO */
 225 extern int mdio_clause45_set_settings(struct efx_nic *efx,
 226                                       struct ethtool_cmd *ecmd);
 227
 228 /* Wait for specified MMDs to exit reset within a timeout */
 229 extern int mdio_clause45_wait_reset_mmds(struct efx_nic *efx,
 230                                          unsigned int mmd_mask);
 231
 232 #endif /* EFX_MDIO_10G_H */