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mm: fix proc_dointvec_userhz_jiffies "breakage"
[linux-2.6/x86.git] / drivers / ata / sata_mv.c
bloba377226b81c8954005f37cfaac9aeb69ebff1677
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
7 *
8 * Originally written by Brett Russ.
9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
10 *
11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
28 /*
29 * sata_mv TODO list:
30 *
31 * --> More errata workarounds for PCI-X.
32 *
33 * --> Complete a full errata audit for all chipsets to identify others.
34 *
35 * --> Develop a low-power-consumption strategy, and implement it.
36 *
37 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
38 *
39 * --> [Experiment, Marvell value added] Is it possible to use target
40 * mode to cross-connect two Linux boxes with Marvell cards? If so,
41 * creating LibATA target mode support would be very interesting.
42 *
43 * Target mode, for those without docs, is the ability to directly
44 * connect two SATA ports.
45 */
46
47 #include <linux/kernel.h>
48 #include <linux/module.h>
49 #include <linux/pci.h>
50 #include <linux/init.h>
51 #include <linux/blkdev.h>
52 #include <linux/delay.h>
53 #include <linux/interrupt.h>
54 #include <linux/dmapool.h>
55 #include <linux/dma-mapping.h>
56 #include <linux/device.h>
57 #include <linux/platform_device.h>
58 #include <linux/ata_platform.h>
59 #include <linux/mbus.h>
60 #include <linux/bitops.h>
61 #include <scsi/scsi_host.h>
62 #include <scsi/scsi_cmnd.h>
63 #include <scsi/scsi_device.h>
64 #include <linux/libata.h>
65
66 #define DRV_NAME "sata_mv"
67 #define DRV_VERSION "1.27"
68
69 /*
70 * module options
71 */
72
73 static int msi;
74 #ifdef CONFIG_PCI
75 module_param(msi, int, S_IRUGO);
76 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
77 #endif
78
79 static int irq_coalescing_io_count;
80 module_param(irq_coalescing_io_count, int, S_IRUGO);
81 MODULE_PARM_DESC(irq_coalescing_io_count,
82 "IRQ coalescing I/O count threshold (0..255)");
83
84 static int irq_coalescing_usecs;
85 module_param(irq_coalescing_usecs, int, S_IRUGO);
86 MODULE_PARM_DESC(irq_coalescing_usecs,
87 "IRQ coalescing time threshold in usecs");
88
89 enum {
90 /* BAR's are enumerated in terms of pci_resource_start() terms */
91 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
92 MV_IO_BAR = 2, /* offset 0x18: IO space */
93 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
94
95 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
96 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
97
98 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
99 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
100 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
101 MAX_COAL_IO_COUNT = 255, /* completed I/O count */
102
103 MV_PCI_REG_BASE = 0,
104
105 /*
106 * Per-chip ("all ports") interrupt coalescing feature.
107 * This is only for GEN_II / GEN_IIE hardware.
108 *
109 * Coalescing defers the interrupt until either the IO_THRESHOLD
110 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
111 */
112 MV_COAL_REG_BASE = 0x18000,
113 MV_IRQ_COAL_CAUSE = (MV_COAL_REG_BASE + 0x08),
114 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
115
116 MV_IRQ_COAL_IO_THRESHOLD = (MV_COAL_REG_BASE + 0xcc),
117 MV_IRQ_COAL_TIME_THRESHOLD = (MV_COAL_REG_BASE + 0xd0),
118
119 /*
120 * Registers for the (unused here) transaction coalescing feature:
121 */
122 MV_TRAN_COAL_CAUSE_LO = (MV_COAL_REG_BASE + 0x88),
123 MV_TRAN_COAL_CAUSE_HI = (MV_COAL_REG_BASE + 0x8c),
124
125 MV_SATAHC0_REG_BASE = 0x20000,
126 MV_FLASH_CTL_OFS = 0x1046c,
127 MV_GPIO_PORT_CTL_OFS = 0x104f0,
128 MV_RESET_CFG_OFS = 0x180d8,
129
130 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
131 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
132 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
133 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
134
135 MV_MAX_Q_DEPTH = 32,
136 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
137
138 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
139 * CRPB needs alignment on a 256B boundary. Size == 256B
140 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
141 */
142 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
143 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
144 MV_MAX_SG_CT = 256,
145 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
146
147 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
148 MV_PORT_HC_SHIFT = 2,
149 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
150 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
151 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
152
153 /* Host Flags */
154 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
155
156 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
157 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
158
159 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
160
161 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
162 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
163
164 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
165
166 CRQB_FLAG_READ = (1 << 0),
167 CRQB_TAG_SHIFT = 1,
168 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
169 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
170 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
171 CRQB_CMD_ADDR_SHIFT = 8,
172 CRQB_CMD_CS = (0x2 << 11),
173 CRQB_CMD_LAST = (1 << 15),
174
175 CRPB_FLAG_STATUS_SHIFT = 8,
176 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
177 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
178
179 EPRD_FLAG_END_OF_TBL = (1 << 31),
180
181 /* PCI interface registers */
182
183 PCI_COMMAND_OFS = 0xc00,
184 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
185
186 PCI_MAIN_CMD_STS_OFS = 0xd30,
187 STOP_PCI_MASTER = (1 << 2),
188 PCI_MASTER_EMPTY = (1 << 3),
189 GLOB_SFT_RST = (1 << 4),
190
191 MV_PCI_MODE_OFS = 0xd00,
192 MV_PCI_MODE_MASK = 0x30,
193
194 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
195 MV_PCI_DISC_TIMER = 0xd04,
196 MV_PCI_MSI_TRIGGER = 0xc38,
197 MV_PCI_SERR_MASK = 0xc28,
198 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
199 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
200 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
201 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
202 MV_PCI_ERR_COMMAND = 0x1d50,
203
204 PCI_IRQ_CAUSE_OFS = 0x1d58,
205 PCI_IRQ_MASK_OFS = 0x1d5c,
206 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
207
208 PCIE_IRQ_CAUSE_OFS = 0x1900,
209 PCIE_IRQ_MASK_OFS = 0x1910,
210 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
211
212 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
213 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
214 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
215 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
216 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
217 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
218 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
219 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
220 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
221 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
222 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
223 PCI_ERR = (1 << 18),
224 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
225 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
226 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
227 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
228 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
229 GPIO_INT = (1 << 22),
230 SELF_INT = (1 << 23),
231 TWSI_INT = (1 << 24),
232 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
233 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
234 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
235
236 /* SATAHC registers */
237 HC_CFG_OFS = 0,
238
239 HC_IRQ_CAUSE_OFS = 0x14,
240 DMA_IRQ = (1 << 0), /* shift by port # */
241 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
242 DEV_IRQ = (1 << 8), /* shift by port # */
243
244 /*
245 * Per-HC (Host-Controller) interrupt coalescing feature.
246 * This is present on all chip generations.
247 *
248 * Coalescing defers the interrupt until either the IO_THRESHOLD
249 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
250 */
251 HC_IRQ_COAL_IO_THRESHOLD_OFS = 0x000c,
252 HC_IRQ_COAL_TIME_THRESHOLD_OFS = 0x0010,
253
254 SOC_LED_CTRL_OFS = 0x2c,
255 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
256 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
257 /* with dev activity LED */
258
259 /* Shadow block registers */
260 SHD_BLK_OFS = 0x100,
261 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
262
263 /* SATA registers */
264 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
265 SATA_ACTIVE_OFS = 0x350,
266 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
267 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
268
269 LTMODE_OFS = 0x30c,
270 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
271
272 PHY_MODE3 = 0x310,
273 PHY_MODE4 = 0x314,
274 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
275 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
276 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
277 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
278
279 PHY_MODE2 = 0x330,
280 SATA_IFCTL_OFS = 0x344,
281 SATA_TESTCTL_OFS = 0x348,
282 SATA_IFSTAT_OFS = 0x34c,
283 VENDOR_UNIQUE_FIS_OFS = 0x35c,
284
285 FISCFG_OFS = 0x360,
286 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
287 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
288
289 MV5_PHY_MODE = 0x74,
290 MV5_LTMODE_OFS = 0x30,
291 MV5_PHY_CTL_OFS = 0x0C,
292 SATA_INTERFACE_CFG_OFS = 0x050,
293
294 MV_M2_PREAMP_MASK = 0x7e0,
295
296 /* Port registers */
297 EDMA_CFG_OFS = 0,
298 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
299 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
300 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
301 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
302 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
303 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
304 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
305
306 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
307 EDMA_ERR_IRQ_MASK_OFS = 0xc,
308 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
309 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
310 EDMA_ERR_DEV = (1 << 2), /* device error */
311 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
312 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
313 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
314 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
315 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
316 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
317 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
318 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
319 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
320 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
321 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
322
323 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
324 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
325 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
326 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
327 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
328
329 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
330
331 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
332 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
333 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
334 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
335 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
336 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
337
338 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
339
340 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
341 EDMA_ERR_OVERRUN_5 = (1 << 5),
342 EDMA_ERR_UNDERRUN_5 = (1 << 6),
343
344 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
345 EDMA_ERR_LNK_CTRL_RX_1 |
346 EDMA_ERR_LNK_CTRL_RX_3 |
347 EDMA_ERR_LNK_CTRL_TX,
348
349 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
350 EDMA_ERR_PRD_PAR |
351 EDMA_ERR_DEV_DCON |
352 EDMA_ERR_DEV_CON |
353 EDMA_ERR_SERR |
354 EDMA_ERR_SELF_DIS |
355 EDMA_ERR_CRQB_PAR |
356 EDMA_ERR_CRPB_PAR |
357 EDMA_ERR_INTRL_PAR |
358 EDMA_ERR_IORDY |
359 EDMA_ERR_LNK_CTRL_RX_2 |
360 EDMA_ERR_LNK_DATA_RX |
361 EDMA_ERR_LNK_DATA_TX |
362 EDMA_ERR_TRANS_PROTO,
363
364 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
365 EDMA_ERR_PRD_PAR |
366 EDMA_ERR_DEV_DCON |
367 EDMA_ERR_DEV_CON |
368 EDMA_ERR_OVERRUN_5 |
369 EDMA_ERR_UNDERRUN_5 |
370 EDMA_ERR_SELF_DIS_5 |
371 EDMA_ERR_CRQB_PAR |
372 EDMA_ERR_CRPB_PAR |
373 EDMA_ERR_INTRL_PAR |
374 EDMA_ERR_IORDY,
375
376 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
377 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
378
379 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
380 EDMA_REQ_Q_PTR_SHIFT = 5,
381
382 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
383 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
384 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
385 EDMA_RSP_Q_PTR_SHIFT = 3,
386
387 EDMA_CMD_OFS = 0x28, /* EDMA command register */
388 EDMA_EN = (1 << 0), /* enable EDMA */
389 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
390 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
391
392 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
393 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
394 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
395
396 EDMA_IORDY_TMOUT_OFS = 0x34,
397 EDMA_ARB_CFG_OFS = 0x38,
398
399 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
400 EDMA_UNKNOWN_RSVD_OFS = 0x6C, /* GenIIe unknown/reserved */
401
402 BMDMA_CMD_OFS = 0x224, /* bmdma command register */
403 BMDMA_STATUS_OFS = 0x228, /* bmdma status register */
404 BMDMA_PRD_LOW_OFS = 0x22c, /* bmdma PRD addr 31:0 */
405 BMDMA_PRD_HIGH_OFS = 0x230, /* bmdma PRD addr 63:32 */
406
407 /* Host private flags (hp_flags) */
408 MV_HP_FLAG_MSI = (1 << 0),
409 MV_HP_ERRATA_50XXB0 = (1 << 1),
410 MV_HP_ERRATA_50XXB2 = (1 << 2),
411 MV_HP_ERRATA_60X1B2 = (1 << 3),
412 MV_HP_ERRATA_60X1C0 = (1 << 4),
413 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
414 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
415 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
416 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
417 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
418 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
419 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
420
421 /* Port private flags (pp_flags) */
422 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
423 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
424 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
425 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
426 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
427 };
428
429 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
430 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
431 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
432 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
433 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
434
435 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
436 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
437
438 enum {
439 /* DMA boundary 0xffff is required by the s/g splitting
440 * we need on /length/ in mv_fill-sg().
441 */
442 MV_DMA_BOUNDARY = 0xffffU,
443
444 /* mask of register bits containing lower 32 bits
445 * of EDMA request queue DMA address
446 */
447 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
448
449 /* ditto, for response queue */
450 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
451 };
452
453 enum chip_type {
454 chip_504x,
455 chip_508x,
456 chip_5080,
457 chip_604x,
458 chip_608x,
459 chip_6042,
460 chip_7042,
461 chip_soc,
462 };
463
464 /* Command ReQuest Block: 32B */
465 struct mv_crqb {
466 __le32 sg_addr;
467 __le32 sg_addr_hi;
468 __le16 ctrl_flags;
469 __le16 ata_cmd[11];
470 };
471
472 struct mv_crqb_iie {
473 __le32 addr;
474 __le32 addr_hi;
475 __le32 flags;
476 __le32 len;
477 __le32 ata_cmd[4];
478 };
479
480 /* Command ResPonse Block: 8B */
481 struct mv_crpb {
482 __le16 id;
483 __le16 flags;
484 __le32 tmstmp;
485 };
486
487 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
488 struct mv_sg {
489 __le32 addr;
490 __le32 flags_size;
491 __le32 addr_hi;
492 __le32 reserved;
493 };
494
495 /*
496 * We keep a local cache of a few frequently accessed port
497 * registers here, to avoid having to read them (very slow)
498 * when switching between EDMA and non-EDMA modes.
499 */
500 struct mv_cached_regs {
501 u32 fiscfg;
502 u32 ltmode;
503 u32 haltcond;
504 u32 unknown_rsvd;
505 };
506
507 struct mv_port_priv {
508 struct mv_crqb *crqb;
509 dma_addr_t crqb_dma;
510 struct mv_crpb *crpb;
511 dma_addr_t crpb_dma;
512 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
513 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
514
515 unsigned int req_idx;
516 unsigned int resp_idx;
517
518 u32 pp_flags;
519 struct mv_cached_regs cached;
520 unsigned int delayed_eh_pmp_map;
521 };
522
523 struct mv_port_signal {
524 u32 amps;
525 u32 pre;
526 };
527
528 struct mv_host_priv {
529 u32 hp_flags;
530 u32 main_irq_mask;
531 struct mv_port_signal signal[8];
532 const struct mv_hw_ops *ops;
533 int n_ports;
534 void __iomem *base;
535 void __iomem *main_irq_cause_addr;
536 void __iomem *main_irq_mask_addr;
537 u32 irq_cause_ofs;
538 u32 irq_mask_ofs;
539 u32 unmask_all_irqs;
540 /*
541 * These consistent DMA memory pools give us guaranteed
542 * alignment for hardware-accessed data structures,
543 * and less memory waste in accomplishing the alignment.
544 */
545 struct dma_pool *crqb_pool;
546 struct dma_pool *crpb_pool;
547 struct dma_pool *sg_tbl_pool;
548 };
549
550 struct mv_hw_ops {
551 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
552 unsigned int port);
553 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
554 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
555 void __iomem *mmio);
556 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
557 unsigned int n_hc);
558 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
559 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
560 };
561
562 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
563 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
564 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
565 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
566 static int mv_port_start(struct ata_port *ap);
567 static void mv_port_stop(struct ata_port *ap);
568 static int mv_qc_defer(struct ata_queued_cmd *qc);
569 static void mv_qc_prep(struct ata_queued_cmd *qc);
570 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
571 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
572 static int mv_hardreset(struct ata_link *link, unsigned int *class,
573 unsigned long deadline);
574 static void mv_eh_freeze(struct ata_port *ap);
575 static void mv_eh_thaw(struct ata_port *ap);
576 static void mv6_dev_config(struct ata_device *dev);
577
578 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
579 unsigned int port);
580 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
581 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
582 void __iomem *mmio);
583 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
584 unsigned int n_hc);
585 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
586 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
587
588 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
589 unsigned int port);
590 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
591 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
592 void __iomem *mmio);
593 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
594 unsigned int n_hc);
595 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
596 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
597 void __iomem *mmio);
598 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
599 void __iomem *mmio);
600 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
601 void __iomem *mmio, unsigned int n_hc);
602 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
603 void __iomem *mmio);
604 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
605 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
606 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
607 unsigned int port_no);
608 static int mv_stop_edma(struct ata_port *ap);
609 static int mv_stop_edma_engine(void __iomem *port_mmio);
610 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
611
612 static void mv_pmp_select(struct ata_port *ap, int pmp);
613 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
614 unsigned long deadline);
615 static int mv_softreset(struct ata_link *link, unsigned int *class,
616 unsigned long deadline);
617 static void mv_pmp_error_handler(struct ata_port *ap);
618 static void mv_process_crpb_entries(struct ata_port *ap,
619 struct mv_port_priv *pp);
620
621 static void mv_sff_irq_clear(struct ata_port *ap);
622 static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
623 static void mv_bmdma_setup(struct ata_queued_cmd *qc);
624 static void mv_bmdma_start(struct ata_queued_cmd *qc);
625 static void mv_bmdma_stop(struct ata_queued_cmd *qc);
626 static u8 mv_bmdma_status(struct ata_port *ap);
627 static u8 mv_sff_check_status(struct ata_port *ap);
628
629 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
630 * because we have to allow room for worst case splitting of
631 * PRDs for 64K boundaries in mv_fill_sg().
632 */
633 static struct scsi_host_template mv5_sht = {
634 ATA_BASE_SHT(DRV_NAME),
635 .sg_tablesize = MV_MAX_SG_CT / 2,
636 .dma_boundary = MV_DMA_BOUNDARY,
637 };
638
639 static struct scsi_host_template mv6_sht = {
640 ATA_NCQ_SHT(DRV_NAME),
641 .can_queue = MV_MAX_Q_DEPTH - 1,
642 .sg_tablesize = MV_MAX_SG_CT / 2,
643 .dma_boundary = MV_DMA_BOUNDARY,
644 };
645
646 static struct ata_port_operations mv5_ops = {
647 .inherits = &ata_sff_port_ops,
648
649 .lost_interrupt = ATA_OP_NULL,
650
651 .qc_defer = mv_qc_defer,
652 .qc_prep = mv_qc_prep,
653 .qc_issue = mv_qc_issue,
654
655 .freeze = mv_eh_freeze,
656 .thaw = mv_eh_thaw,
657 .hardreset = mv_hardreset,
658 .error_handler = ata_std_error_handler, /* avoid SFF EH */
659 .post_internal_cmd = ATA_OP_NULL,
660
661 .scr_read = mv5_scr_read,
662 .scr_write = mv5_scr_write,
663
664 .port_start = mv_port_start,
665 .port_stop = mv_port_stop,
666 };
667
668 static struct ata_port_operations mv6_ops = {
669 .inherits = &mv5_ops,
670 .dev_config = mv6_dev_config,
671 .scr_read = mv_scr_read,
672 .scr_write = mv_scr_write,
673
674 .pmp_hardreset = mv_pmp_hardreset,
675 .pmp_softreset = mv_softreset,
676 .softreset = mv_softreset,
677 .error_handler = mv_pmp_error_handler,
678
679 .sff_check_status = mv_sff_check_status,
680 .sff_irq_clear = mv_sff_irq_clear,
681 .check_atapi_dma = mv_check_atapi_dma,
682 .bmdma_setup = mv_bmdma_setup,
683 .bmdma_start = mv_bmdma_start,
684 .bmdma_stop = mv_bmdma_stop,
685 .bmdma_status = mv_bmdma_status,
686 };
687
688 static struct ata_port_operations mv_iie_ops = {
689 .inherits = &mv6_ops,
690 .dev_config = ATA_OP_NULL,
691 .qc_prep = mv_qc_prep_iie,
692 };
693
694 static const struct ata_port_info mv_port_info[] = {
695 { /* chip_504x */
696 .flags = MV_GEN_I_FLAGS,
697 .pio_mask = 0x1f, /* pio0-4 */
698 .udma_mask = ATA_UDMA6,
699 .port_ops = &mv5_ops,
700 },
701 { /* chip_508x */
702 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
703 .pio_mask = 0x1f, /* pio0-4 */
704 .udma_mask = ATA_UDMA6,
705 .port_ops = &mv5_ops,
706 },
707 { /* chip_5080 */
708 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
709 .pio_mask = 0x1f, /* pio0-4 */
710 .udma_mask = ATA_UDMA6,
711 .port_ops = &mv5_ops,
712 },
713 { /* chip_604x */
714 .flags = MV_GEN_II_FLAGS,
715 .pio_mask = 0x1f, /* pio0-4 */
716 .udma_mask = ATA_UDMA6,
717 .port_ops = &mv6_ops,
718 },
719 { /* chip_608x */
720 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
721 .pio_mask = 0x1f, /* pio0-4 */
722 .udma_mask = ATA_UDMA6,
723 .port_ops = &mv6_ops,
724 },
725 { /* chip_6042 */
726 .flags = MV_GEN_IIE_FLAGS,
727 .pio_mask = 0x1f, /* pio0-4 */
728 .udma_mask = ATA_UDMA6,
729 .port_ops = &mv_iie_ops,
730 },
731 { /* chip_7042 */
732 .flags = MV_GEN_IIE_FLAGS,
733 .pio_mask = 0x1f, /* pio0-4 */
734 .udma_mask = ATA_UDMA6,
735 .port_ops = &mv_iie_ops,
736 },
737 { /* chip_soc */
738 .flags = MV_GEN_IIE_FLAGS,
739 .pio_mask = 0x1f, /* pio0-4 */
740 .udma_mask = ATA_UDMA6,
741 .port_ops = &mv_iie_ops,
742 },
743 };
744
745 static const struct pci_device_id mv_pci_tbl[] = {
746 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
747 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
748 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
749 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
750 /* RocketRAID 1720/174x have different identifiers */
751 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
752 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
753 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
754
755 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
756 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
757 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
758 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
759 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
760
761 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
762
763 /* Adaptec 1430SA */
764 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
765
766 /* Marvell 7042 support */
767 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
768
769 /* Highpoint RocketRAID PCIe series */
770 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
771 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
772
773 { } /* terminate list */
774 };
775
776 static const struct mv_hw_ops mv5xxx_ops = {
777 .phy_errata = mv5_phy_errata,
778 .enable_leds = mv5_enable_leds,
779 .read_preamp = mv5_read_preamp,
780 .reset_hc = mv5_reset_hc,
781 .reset_flash = mv5_reset_flash,
782 .reset_bus = mv5_reset_bus,
783 };
784
785 static const struct mv_hw_ops mv6xxx_ops = {
786 .phy_errata = mv6_phy_errata,
787 .enable_leds = mv6_enable_leds,
788 .read_preamp = mv6_read_preamp,
789 .reset_hc = mv6_reset_hc,
790 .reset_flash = mv6_reset_flash,
791 .reset_bus = mv_reset_pci_bus,
792 };
793
794 static const struct mv_hw_ops mv_soc_ops = {
795 .phy_errata = mv6_phy_errata,
796 .enable_leds = mv_soc_enable_leds,
797 .read_preamp = mv_soc_read_preamp,
798 .reset_hc = mv_soc_reset_hc,
799 .reset_flash = mv_soc_reset_flash,
800 .reset_bus = mv_soc_reset_bus,
801 };
802
803 /*
804 * Functions
805 */
806
807 static inline void writelfl(unsigned long data, void __iomem *addr)
808 {
809 writel(data, addr);
810 (void) readl(addr); /* flush to avoid PCI posted write */
811 }
812
813 static inline unsigned int mv_hc_from_port(unsigned int port)
814 {
815 return port >> MV_PORT_HC_SHIFT;
816 }
817
818 static inline unsigned int mv_hardport_from_port(unsigned int port)
819 {
820 return port & MV_PORT_MASK;
821 }
822
823 /*
824 * Consolidate some rather tricky bit shift calculations.
825 * This is hot-path stuff, so not a function.
826 * Simple code, with two return values, so macro rather than inline.
827 *
828 * port is the sole input, in range 0..7.
829 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
830 * hardport is the other output, in range 0..3.
831 *
832 * Note that port and hardport may be the same variable in some cases.
833 */
834 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
835 { \
836 shift = mv_hc_from_port(port) * HC_SHIFT; \
837 hardport = mv_hardport_from_port(port); \
838 shift += hardport * 2; \
839 }
840
841 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
842 {
843 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
844 }
845
846 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
847 unsigned int port)
848 {
849 return mv_hc_base(base, mv_hc_from_port(port));
850 }
851
852 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
853 {
854 return mv_hc_base_from_port(base, port) +
855 MV_SATAHC_ARBTR_REG_SZ +
856 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
857 }
858
859 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
860 {
861 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
862 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
863
864 return hc_mmio + ofs;
865 }
866
867 static inline void __iomem *mv_host_base(struct ata_host *host)
868 {
869 struct mv_host_priv *hpriv = host->private_data;
870 return hpriv->base;
871 }
872
873 static inline void __iomem *mv_ap_base(struct ata_port *ap)
874 {
875 return mv_port_base(mv_host_base(ap->host), ap->port_no);
876 }
877
878 static inline int mv_get_hc_count(unsigned long port_flags)
879 {
880 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
881 }
882
883 /**
884 * mv_save_cached_regs - (re-)initialize cached port registers
885 * @ap: the port whose registers we are caching
886 *
887 * Initialize the local cache of port registers,
888 * so that reading them over and over again can
889 * be avoided on the hotter paths of this driver.
890 * This saves a few microseconds each time we switch
891 * to/from EDMA mode to perform (eg.) a drive cache flush.
892 */
893 static void mv_save_cached_regs(struct ata_port *ap)
894 {
895 void __iomem *port_mmio = mv_ap_base(ap);
896 struct mv_port_priv *pp = ap->private_data;
897
898 pp->cached.fiscfg = readl(port_mmio + FISCFG_OFS);
899 pp->cached.ltmode = readl(port_mmio + LTMODE_OFS);
900 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
901 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD_OFS);
902 }
903
904 /**
905 * mv_write_cached_reg - write to a cached port register
906 * @addr: hardware address of the register
907 * @old: pointer to cached value of the register
908 * @new: new value for the register
909 *
910 * Write a new value to a cached register,
911 * but only if the value is different from before.
912 */
913 static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
914 {
915 if (new != *old) {
916 *old = new;
917 writel(new, addr);
918 }
919 }
920
921 static void mv_set_edma_ptrs(void __iomem *port_mmio,
922 struct mv_host_priv *hpriv,
923 struct mv_port_priv *pp)
924 {
925 u32 index;
926
927 /*
928 * initialize request queue
929 */
930 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
931 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
932
933 WARN_ON(pp->crqb_dma & 0x3ff);
934 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
935 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
936 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
937 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
938
939 /*
940 * initialize response queue
941 */
942 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
943 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
944
945 WARN_ON(pp->crpb_dma & 0xff);
946 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
947 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
948 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
949 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
950 }
951
952 static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
953 {
954 /*
955 * When writing to the main_irq_mask in hardware,
956 * we must ensure exclusivity between the interrupt coalescing bits
957 * and the corresponding individual port DONE_IRQ bits.
958 *
959 * Note that this register is really an "IRQ enable" register,
960 * not an "IRQ mask" register as Marvell's naming might suggest.
961 */
962 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
963 mask &= ~DONE_IRQ_0_3;
964 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
965 mask &= ~DONE_IRQ_4_7;
966 writelfl(mask, hpriv->main_irq_mask_addr);
967 }
968
969 static void mv_set_main_irq_mask(struct ata_host *host,
970 u32 disable_bits, u32 enable_bits)
971 {
972 struct mv_host_priv *hpriv = host->private_data;
973 u32 old_mask, new_mask;
974
975 old_mask = hpriv->main_irq_mask;
976 new_mask = (old_mask & ~disable_bits) | enable_bits;
977 if (new_mask != old_mask) {
978 hpriv->main_irq_mask = new_mask;
979 mv_write_main_irq_mask(new_mask, hpriv);
980 }
981 }
982
983 static void mv_enable_port_irqs(struct ata_port *ap,
984 unsigned int port_bits)
985 {
986 unsigned int shift, hardport, port = ap->port_no;
987 u32 disable_bits, enable_bits;
988
989 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
990
991 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
992 enable_bits = port_bits << shift;
993 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
994 }
995
996 static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
997 void __iomem *port_mmio,
998 unsigned int port_irqs)
999 {
1000 struct mv_host_priv *hpriv = ap->host->private_data;
1001 int hardport = mv_hardport_from_port(ap->port_no);
1002 void __iomem *hc_mmio = mv_hc_base_from_port(
1003 mv_host_base(ap->host), ap->port_no);
1004 u32 hc_irq_cause;
1005
1006 /* clear EDMA event indicators, if any */
1007 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1008
1009 /* clear pending irq events */
1010 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
1011 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1012
1013 /* clear FIS IRQ Cause */
1014 if (IS_GEN_IIE(hpriv))
1015 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1016
1017 mv_enable_port_irqs(ap, port_irqs);
1018 }
1019
1020 static void mv_set_irq_coalescing(struct ata_host *host,
1021 unsigned int count, unsigned int usecs)
1022 {
1023 struct mv_host_priv *hpriv = host->private_data;
1024 void __iomem *mmio = hpriv->base, *hc_mmio;
1025 u32 coal_enable = 0;
1026 unsigned long flags;
1027 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
1028 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
1029 ALL_PORTS_COAL_DONE;
1030
1031 /* Disable IRQ coalescing if either threshold is zero */
1032 if (!usecs || !count) {
1033 clks = count = 0;
1034 } else {
1035 /* Respect maximum limits of the hardware */
1036 clks = usecs * COAL_CLOCKS_PER_USEC;
1037 if (clks > MAX_COAL_TIME_THRESHOLD)
1038 clks = MAX_COAL_TIME_THRESHOLD;
1039 if (count > MAX_COAL_IO_COUNT)
1040 count = MAX_COAL_IO_COUNT;
1041 }
1042
1043 spin_lock_irqsave(&host->lock, flags);
1044 mv_set_main_irq_mask(host, coal_disable, 0);
1045
1046 if (is_dual_hc && !IS_GEN_I(hpriv)) {
1047 /*
1048 * GEN_II/GEN_IIE with dual host controllers:
1049 * one set of global thresholds for the entire chip.
1050 */
1051 writel(clks, mmio + MV_IRQ_COAL_TIME_THRESHOLD);
1052 writel(count, mmio + MV_IRQ_COAL_IO_THRESHOLD);
1053 /* clear leftover coal IRQ bit */
1054 writel(~ALL_PORTS_COAL_IRQ, mmio + MV_IRQ_COAL_CAUSE);
1055 if (count)
1056 coal_enable = ALL_PORTS_COAL_DONE;
1057 clks = count = 0; /* force clearing of regular regs below */
1058 }
1059
1060 /*
1061 * All chips: independent thresholds for each HC on the chip.
1062 */
1063 hc_mmio = mv_hc_base_from_port(mmio, 0);
1064 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD_OFS);
1065 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD_OFS);
1066 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE_OFS);
1067 if (count)
1068 coal_enable |= PORTS_0_3_COAL_DONE;
1069 if (is_dual_hc) {
1070 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
1071 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD_OFS);
1072 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD_OFS);
1073 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE_OFS);
1074 if (count)
1075 coal_enable |= PORTS_4_7_COAL_DONE;
1076 }
1077
1078 mv_set_main_irq_mask(host, 0, coal_enable);
1079 spin_unlock_irqrestore(&host->lock, flags);
1080 }
1081
1082 /**
1083 * mv_start_edma - Enable eDMA engine
1084 * @base: port base address
1085 * @pp: port private data
1086 *
1087 * Verify the local cache of the eDMA state is accurate with a
1088 * WARN_ON.
1089 *
1090 * LOCKING:
1091 * Inherited from caller.
1092 */
1093 static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
1094 struct mv_port_priv *pp, u8 protocol)
1095 {
1096 int want_ncq = (protocol == ATA_PROT_NCQ);
1097
1098 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1099 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
1100 if (want_ncq != using_ncq)
1101 mv_stop_edma(ap);
1102 }
1103 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
1104 struct mv_host_priv *hpriv = ap->host->private_data;
1105
1106 mv_edma_cfg(ap, want_ncq, 1);
1107
1108 mv_set_edma_ptrs(port_mmio, hpriv, pp);
1109 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
1110
1111 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
1112 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
1113 }
1114 }
1115
1116 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
1117 {
1118 void __iomem *port_mmio = mv_ap_base(ap);
1119 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
1120 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
1121 int i;
1122
1123 /*
1124 * Wait for the EDMA engine to finish transactions in progress.
1125 * No idea what a good "timeout" value might be, but measurements
1126 * indicate that it often requires hundreds of microseconds
1127 * with two drives in-use. So we use the 15msec value above
1128 * as a rough guess at what even more drives might require.
1129 */
1130 for (i = 0; i < timeout; ++i) {
1131 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
1132 if ((edma_stat & empty_idle) == empty_idle)
1133 break;
1134 udelay(per_loop);
1135 }
1136 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
1137 }
1138
1139 /**
1140 * mv_stop_edma_engine - Disable eDMA engine
1141 * @port_mmio: io base address
1142 *
1143 * LOCKING:
1144 * Inherited from caller.
1145 */
1146 static int mv_stop_edma_engine(void __iomem *port_mmio)
1147 {
1148 int i;
1149
1150 /* Disable eDMA. The disable bit auto clears. */
1151 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1152
1153 /* Wait for the chip to confirm eDMA is off. */
1154 for (i = 10000; i > 0; i--) {
1155 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
1156 if (!(reg & EDMA_EN))
1157 return 0;
1158 udelay(10);
1159 }
1160 return -EIO;
1161 }
1162
1163 static int mv_stop_edma(struct ata_port *ap)
1164 {
1165 void __iomem *port_mmio = mv_ap_base(ap);
1166 struct mv_port_priv *pp = ap->private_data;
1167 int err = 0;
1168
1169 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1170 return 0;
1171 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1172 mv_wait_for_edma_empty_idle(ap);
1173 if (mv_stop_edma_engine(port_mmio)) {
1174 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
1175 err = -EIO;
1176 }
1177 mv_edma_cfg(ap, 0, 0);
1178 return err;
1179 }
1180
1181 #ifdef ATA_DEBUG
1182 static void mv_dump_mem(void __iomem *start, unsigned bytes)
1183 {
1184 int b, w;
1185 for (b = 0; b < bytes; ) {
1186 DPRINTK("%p: ", start + b);
1187 for (w = 0; b < bytes && w < 4; w++) {
1188 printk("%08x ", readl(start + b));
1189 b += sizeof(u32);
1190 }
1191 printk("\n");
1192 }
1193 }
1194 #endif
1195
1196 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1197 {
1198 #ifdef ATA_DEBUG
1199 int b, w;
1200 u32 dw;
1201 for (b = 0; b < bytes; ) {
1202 DPRINTK("%02x: ", b);
1203 for (w = 0; b < bytes && w < 4; w++) {
1204 (void) pci_read_config_dword(pdev, b, &dw);
1205 printk("%08x ", dw);
1206 b += sizeof(u32);
1207 }
1208 printk("\n");
1209 }
1210 #endif
1211 }
1212 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1213 struct pci_dev *pdev)
1214 {
1215 #ifdef ATA_DEBUG
1216 void __iomem *hc_base = mv_hc_base(mmio_base,
1217 port >> MV_PORT_HC_SHIFT);
1218 void __iomem *port_base;
1219 int start_port, num_ports, p, start_hc, num_hcs, hc;
1220
1221 if (0 > port) {
1222 start_hc = start_port = 0;
1223 num_ports = 8; /* shld be benign for 4 port devs */
1224 num_hcs = 2;
1225 } else {
1226 start_hc = port >> MV_PORT_HC_SHIFT;
1227 start_port = port;
1228 num_ports = num_hcs = 1;
1229 }
1230 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1231 num_ports > 1 ? num_ports - 1 : start_port);
1232
1233 if (NULL != pdev) {
1234 DPRINTK("PCI config space regs:\n");
1235 mv_dump_pci_cfg(pdev, 0x68);
1236 }
1237 DPRINTK("PCI regs:\n");
1238 mv_dump_mem(mmio_base+0xc00, 0x3c);
1239 mv_dump_mem(mmio_base+0xd00, 0x34);
1240 mv_dump_mem(mmio_base+0xf00, 0x4);
1241 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1242 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1243 hc_base = mv_hc_base(mmio_base, hc);
1244 DPRINTK("HC regs (HC %i):\n", hc);
1245 mv_dump_mem(hc_base, 0x1c);
1246 }
1247 for (p = start_port; p < start_port + num_ports; p++) {
1248 port_base = mv_port_base(mmio_base, p);
1249 DPRINTK("EDMA regs (port %i):\n", p);
1250 mv_dump_mem(port_base, 0x54);
1251 DPRINTK("SATA regs (port %i):\n", p);
1252 mv_dump_mem(port_base+0x300, 0x60);
1253 }
1254 #endif
1255 }
1256
1257 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1258 {
1259 unsigned int ofs;
1260
1261 switch (sc_reg_in) {
1262 case SCR_STATUS:
1263 case SCR_CONTROL:
1264 case SCR_ERROR:
1265 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1266 break;
1267 case SCR_ACTIVE:
1268 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1269 break;
1270 default:
1271 ofs = 0xffffffffU;
1272 break;
1273 }
1274 return ofs;
1275 }
1276
1277 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
1278 {
1279 unsigned int ofs = mv_scr_offset(sc_reg_in);
1280
1281 if (ofs != 0xffffffffU) {
1282 *val = readl(mv_ap_base(link->ap) + ofs);
1283 return 0;
1284 } else
1285 return -EINVAL;
1286 }
1287
1288 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
1289 {
1290 unsigned int ofs = mv_scr_offset(sc_reg_in);
1291
1292 if (ofs != 0xffffffffU) {
1293 writelfl(val, mv_ap_base(link->ap) + ofs);
1294 return 0;
1295 } else
1296 return -EINVAL;
1297 }
1298
1299 static void mv6_dev_config(struct ata_device *adev)
1300 {
1301 /*
1302 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1303 *
1304 * Gen-II does not support NCQ over a port multiplier
1305 * (no FIS-based switching).
1306 */
1307 if (adev->flags & ATA_DFLAG_NCQ) {
1308 if (sata_pmp_attached(adev->link->ap)) {
1309 adev->flags &= ~ATA_DFLAG_NCQ;
1310 ata_dev_printk(adev, KERN_INFO,
1311 "NCQ disabled for command-based switching\n");
1312 }
1313 }
1314 }
1315
1316 static int mv_qc_defer(struct ata_queued_cmd *qc)
1317 {
1318 struct ata_link *link = qc->dev->link;
1319 struct ata_port *ap = link->ap;
1320 struct mv_port_priv *pp = ap->private_data;
1321
1322 /*
1323 * Don't allow new commands if we're in a delayed EH state
1324 * for NCQ and/or FIS-based switching.
1325 */
1326 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1327 return ATA_DEFER_PORT;
1328 /*
1329 * If the port is completely idle, then allow the new qc.
1330 */
1331 if (ap->nr_active_links == 0)
1332 return 0;
1333
1334 /*
1335 * The port is operating in host queuing mode (EDMA) with NCQ
1336 * enabled, allow multiple NCQ commands. EDMA also allows
1337 * queueing multiple DMA commands but libata core currently
1338 * doesn't allow it.
1339 */
1340 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1341 (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol))
1342 return 0;
1343
1344 return ATA_DEFER_PORT;
1345 }
1346
1347 static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
1348 {
1349 struct mv_port_priv *pp = ap->private_data;
1350 void __iomem *port_mmio;
1351
1352 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1353 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1354 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
1355
1356 ltmode = *old_ltmode & ~LTMODE_BIT8;
1357 haltcond = *old_haltcond | EDMA_ERR_DEV;
1358
1359 if (want_fbs) {
1360 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1361 ltmode = *old_ltmode | LTMODE_BIT8;
1362 if (want_ncq)
1363 haltcond &= ~EDMA_ERR_DEV;
1364 else
1365 fiscfg |= FISCFG_WAIT_DEV_ERR;
1366 } else {
1367 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1368 }
1369
1370 port_mmio = mv_ap_base(ap);
1371 mv_write_cached_reg(port_mmio + FISCFG_OFS, old_fiscfg, fiscfg);
1372 mv_write_cached_reg(port_mmio + LTMODE_OFS, old_ltmode, ltmode);
1373 mv_write_cached_reg(port_mmio + EDMA_HALTCOND_OFS, old_haltcond, haltcond);
1374 }
1375
1376 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1377 {
1378 struct mv_host_priv *hpriv = ap->host->private_data;
1379 u32 old, new;
1380
1381 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1382 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1383 if (want_ncq)
1384 new = old | (1 << 22);
1385 else
1386 new = old & ~(1 << 22);
1387 if (new != old)
1388 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1389 }
1390
1391 /**
1392 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1393 * @ap: Port being initialized
1394 *
1395 * There are two DMA modes on these chips: basic DMA, and EDMA.
1396 *
1397 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1398 * of basic DMA on the GEN_IIE versions of the chips.
1399 *
1400 * This bit survives EDMA resets, and must be set for basic DMA
1401 * to function, and should be cleared when EDMA is active.
1402 */
1403 static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1404 {
1405 struct mv_port_priv *pp = ap->private_data;
1406 u32 new, *old = &pp->cached.unknown_rsvd;
1407
1408 if (enable_bmdma)
1409 new = *old | 1;
1410 else
1411 new = *old & ~1;
1412 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD_OFS, old, new);
1413 }
1414
1415 /*
1416 * SOC chips have an issue whereby the HDD LEDs don't always blink
1417 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1418 * of the SOC takes care of it, generating a steady blink rate when
1419 * any drive on the chip is active.
1420 *
1421 * Unfortunately, the blink mode is a global hardware setting for the SOC,
1422 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1423 *
1424 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1425 * LED operation works then, and provides better (more accurate) feedback.
1426 *
1427 * Note that this code assumes that an SOC never has more than one HC onboard.
1428 */
1429 static void mv_soc_led_blink_enable(struct ata_port *ap)
1430 {
1431 struct ata_host *host = ap->host;
1432 struct mv_host_priv *hpriv = host->private_data;
1433 void __iomem *hc_mmio;
1434 u32 led_ctrl;
1435
1436 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1437 return;
1438 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1439 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1440 led_ctrl = readl(hc_mmio + SOC_LED_CTRL_OFS);
1441 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL_OFS);
1442 }
1443
1444 static void mv_soc_led_blink_disable(struct ata_port *ap)
1445 {
1446 struct ata_host *host = ap->host;
1447 struct mv_host_priv *hpriv = host->private_data;
1448 void __iomem *hc_mmio;
1449 u32 led_ctrl;
1450 unsigned int port;
1451
1452 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1453 return;
1454
1455 /* disable led-blink only if no ports are using NCQ */
1456 for (port = 0; port < hpriv->n_ports; port++) {
1457 struct ata_port *this_ap = host->ports[port];
1458 struct mv_port_priv *pp = this_ap->private_data;
1459
1460 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1461 return;
1462 }
1463
1464 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1465 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1466 led_ctrl = readl(hc_mmio + SOC_LED_CTRL_OFS);
1467 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL_OFS);
1468 }
1469
1470 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
1471 {
1472 u32 cfg;
1473 struct mv_port_priv *pp = ap->private_data;
1474 struct mv_host_priv *hpriv = ap->host->private_data;
1475 void __iomem *port_mmio = mv_ap_base(ap);
1476
1477 /* set up non-NCQ EDMA configuration */
1478 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1479 pp->pp_flags &=
1480 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
1481
1482 if (IS_GEN_I(hpriv))
1483 cfg |= (1 << 8); /* enab config burst size mask */
1484
1485 else if (IS_GEN_II(hpriv)) {
1486 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1487 mv_60x1_errata_sata25(ap, want_ncq);
1488
1489 } else if (IS_GEN_IIE(hpriv)) {
1490 int want_fbs = sata_pmp_attached(ap);
1491 /*
1492 * Possible future enhancement:
1493 *
1494 * The chip can use FBS with non-NCQ, if we allow it,
1495 * But first we need to have the error handling in place
1496 * for this mode (datasheet section 7.3.15.4.2.3).
1497 * So disallow non-NCQ FBS for now.
1498 */
1499 want_fbs &= want_ncq;
1500
1501 mv_config_fbs(ap, want_ncq, want_fbs);
1502
1503 if (want_fbs) {
1504 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1505 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1506 }
1507
1508 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1509 if (want_edma) {
1510 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1511 if (!IS_SOC(hpriv))
1512 cfg |= (1 << 18); /* enab early completion */
1513 }
1514 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1515 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1516 mv_bmdma_enable_iie(ap, !want_edma);
1517
1518 if (IS_SOC(hpriv)) {
1519 if (want_ncq)
1520 mv_soc_led_blink_enable(ap);
1521 else
1522 mv_soc_led_blink_disable(ap);
1523 }
1524 }
1525
1526 if (want_ncq) {
1527 cfg |= EDMA_CFG_NCQ;
1528 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1529 }
1530
1531 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1532 }
1533
1534 static void mv_port_free_dma_mem(struct ata_port *ap)
1535 {
1536 struct mv_host_priv *hpriv = ap->host->private_data;
1537 struct mv_port_priv *pp = ap->private_data;
1538 int tag;
1539
1540 if (pp->crqb) {
1541 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1542 pp->crqb = NULL;
1543 }
1544 if (pp->crpb) {
1545 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1546 pp->crpb = NULL;
1547 }
1548 /*
1549 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1550 * For later hardware, we have one unique sg_tbl per NCQ tag.
1551 */
1552 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1553 if (pp->sg_tbl[tag]) {
1554 if (tag == 0 || !IS_GEN_I(hpriv))
1555 dma_pool_free(hpriv->sg_tbl_pool,
1556 pp->sg_tbl[tag],
1557 pp->sg_tbl_dma[tag]);
1558 pp->sg_tbl[tag] = NULL;
1559 }
1560 }
1561 }
1562
1563 /**
1564 * mv_port_start - Port specific init/start routine.
1565 * @ap: ATA channel to manipulate
1566 *
1567 * Allocate and point to DMA memory, init port private memory,
1568 * zero indices.
1569 *
1570 * LOCKING:
1571 * Inherited from caller.
1572 */
1573 static int mv_port_start(struct ata_port *ap)
1574 {
1575 struct device *dev = ap->host->dev;
1576 struct mv_host_priv *hpriv = ap->host->private_data;
1577 struct mv_port_priv *pp;
1578 int tag;
1579
1580 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1581 if (!pp)
1582 return -ENOMEM;
1583 ap->private_data = pp;
1584
1585 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1586 if (!pp->crqb)
1587 return -ENOMEM;
1588 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1589
1590 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1591 if (!pp->crpb)
1592 goto out_port_free_dma_mem;
1593 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1594
1595 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1596 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1597 ap->flags |= ATA_FLAG_AN;
1598 /*
1599 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1600 * For later hardware, we need one unique sg_tbl per NCQ tag.
1601 */
1602 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1603 if (tag == 0 || !IS_GEN_I(hpriv)) {
1604 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1605 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1606 if (!pp->sg_tbl[tag])
1607 goto out_port_free_dma_mem;
1608 } else {
1609 pp->sg_tbl[tag] = pp->sg_tbl[0];
1610 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1611 }
1612 }
1613 mv_save_cached_regs(ap);
1614 mv_edma_cfg(ap, 0, 0);
1615 return 0;
1616
1617 out_port_free_dma_mem:
1618 mv_port_free_dma_mem(ap);
1619 return -ENOMEM;
1620 }
1621
1622 /**
1623 * mv_port_stop - Port specific cleanup/stop routine.
1624 * @ap: ATA channel to manipulate
1625 *
1626 * Stop DMA, cleanup port memory.
1627 *
1628 * LOCKING:
1629 * This routine uses the host lock to protect the DMA stop.
1630 */
1631 static void mv_port_stop(struct ata_port *ap)
1632 {
1633 mv_stop_edma(ap);
1634 mv_enable_port_irqs(ap, 0);
1635 mv_port_free_dma_mem(ap);
1636 }
1637
1638 /**
1639 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1640 * @qc: queued command whose SG list to source from
1641 *
1642 * Populate the SG list and mark the last entry.
1643 *
1644 * LOCKING:
1645 * Inherited from caller.
1646 */
1647 static void mv_fill_sg(struct ata_queued_cmd *qc)
1648 {
1649 struct mv_port_priv *pp = qc->ap->private_data;
1650 struct scatterlist *sg;
1651 struct mv_sg *mv_sg, *last_sg = NULL;
1652 unsigned int si;
1653
1654 mv_sg = pp->sg_tbl[qc->tag];
1655 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1656 dma_addr_t addr = sg_dma_address(sg);
1657 u32 sg_len = sg_dma_len(sg);
1658
1659 while (sg_len) {
1660 u32 offset = addr & 0xffff;
1661 u32 len = sg_len;
1662
1663 if (offset + len > 0x10000)
1664 len = 0x10000 - offset;
1665
1666 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1667 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1668 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1669 mv_sg->reserved = 0;
1670
1671 sg_len -= len;
1672 addr += len;
1673
1674 last_sg = mv_sg;
1675 mv_sg++;
1676 }
1677 }
1678
1679 if (likely(last_sg))
1680 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1681 mb(); /* ensure data structure is visible to the chipset */
1682 }
1683
1684 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1685 {
1686 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1687 (last ? CRQB_CMD_LAST : 0);
1688 *cmdw = cpu_to_le16(tmp);
1689 }
1690
1691 /**
1692 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1693 * @ap: Port associated with this ATA transaction.
1694 *
1695 * We need this only for ATAPI bmdma transactions,
1696 * as otherwise we experience spurious interrupts
1697 * after libata-sff handles the bmdma interrupts.
1698 */
1699 static void mv_sff_irq_clear(struct ata_port *ap)
1700 {
1701 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1702 }
1703
1704 /**
1705 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1706 * @qc: queued command to check for chipset/DMA compatibility.
1707 *
1708 * The bmdma engines cannot handle speculative data sizes
1709 * (bytecount under/over flow). So only allow DMA for
1710 * data transfer commands with known data sizes.
1711 *
1712 * LOCKING:
1713 * Inherited from caller.
1714 */
1715 static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1716 {
1717 struct scsi_cmnd *scmd = qc->scsicmd;
1718
1719 if (scmd) {
1720 switch (scmd->cmnd[0]) {
1721 case READ_6:
1722 case READ_10:
1723 case READ_12:
1724 case WRITE_6:
1725 case WRITE_10:
1726 case WRITE_12:
1727 case GPCMD_READ_CD:
1728 case GPCMD_SEND_DVD_STRUCTURE:
1729 case GPCMD_SEND_CUE_SHEET:
1730 return 0; /* DMA is safe */
1731 }
1732 }
1733 return -EOPNOTSUPP; /* use PIO instead */
1734 }
1735
1736 /**
1737 * mv_bmdma_setup - Set up BMDMA transaction
1738 * @qc: queued command to prepare DMA for.
1739 *
1740 * LOCKING:
1741 * Inherited from caller.
1742 */
1743 static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1744 {
1745 struct ata_port *ap = qc->ap;
1746 void __iomem *port_mmio = mv_ap_base(ap);
1747 struct mv_port_priv *pp = ap->private_data;
1748
1749 mv_fill_sg(qc);
1750
1751 /* clear all DMA cmd bits */
1752 writel(0, port_mmio + BMDMA_CMD_OFS);
1753
1754 /* load PRD table addr. */
1755 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
1756 port_mmio + BMDMA_PRD_HIGH_OFS);
1757 writelfl(pp->sg_tbl_dma[qc->tag],
1758 port_mmio + BMDMA_PRD_LOW_OFS);
1759
1760 /* issue r/w command */
1761 ap->ops->sff_exec_command(ap, &qc->tf);
1762 }
1763
1764 /**
1765 * mv_bmdma_start - Start a BMDMA transaction
1766 * @qc: queued command to start DMA on.
1767 *
1768 * LOCKING:
1769 * Inherited from caller.
1770 */
1771 static void mv_bmdma_start(struct ata_queued_cmd *qc)
1772 {
1773 struct ata_port *ap = qc->ap;
1774 void __iomem *port_mmio = mv_ap_base(ap);
1775 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1776 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1777
1778 /* start host DMA transaction */
1779 writelfl(cmd, port_mmio + BMDMA_CMD_OFS);
1780 }
1781
1782 /**
1783 * mv_bmdma_stop - Stop BMDMA transfer
1784 * @qc: queued command to stop DMA on.
1785 *
1786 * Clears the ATA_DMA_START flag in the bmdma control register
1787 *
1788 * LOCKING:
1789 * Inherited from caller.
1790 */
1791 static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1792 {
1793 struct ata_port *ap = qc->ap;
1794 void __iomem *port_mmio = mv_ap_base(ap);
1795 u32 cmd;
1796
1797 /* clear start/stop bit */
1798 cmd = readl(port_mmio + BMDMA_CMD_OFS);
1799 cmd &= ~ATA_DMA_START;
1800 writelfl(cmd, port_mmio + BMDMA_CMD_OFS);
1801
1802 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1803 ata_sff_dma_pause(ap);
1804 }
1805
1806 /**
1807 * mv_bmdma_status - Read BMDMA status
1808 * @ap: port for which to retrieve DMA status.
1809 *
1810 * Read and return equivalent of the sff BMDMA status register.
1811 *
1812 * LOCKING:
1813 * Inherited from caller.
1814 */
1815 static u8 mv_bmdma_status(struct ata_port *ap)
1816 {
1817 void __iomem *port_mmio = mv_ap_base(ap);
1818 u32 reg, status;
1819
1820 /*
1821 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1822 * and the ATA_DMA_INTR bit doesn't exist.
1823 */
1824 reg = readl(port_mmio + BMDMA_STATUS_OFS);
1825 if (reg & ATA_DMA_ACTIVE)
1826 status = ATA_DMA_ACTIVE;
1827 else
1828 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
1829 return status;
1830 }
1831
1832 /**
1833 * mv_qc_prep - Host specific command preparation.
1834 * @qc: queued command to prepare
1835 *
1836 * This routine simply redirects to the general purpose routine
1837 * if command is not DMA. Else, it handles prep of the CRQB
1838 * (command request block), does some sanity checking, and calls
1839 * the SG load routine.
1840 *
1841 * LOCKING:
1842 * Inherited from caller.
1843 */
1844 static void mv_qc_prep(struct ata_queued_cmd *qc)
1845 {
1846 struct ata_port *ap = qc->ap;
1847 struct mv_port_priv *pp = ap->private_data;
1848 __le16 *cw;
1849 struct ata_taskfile *tf;
1850 u16 flags = 0;
1851 unsigned in_index;
1852
1853 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1854 (qc->tf.protocol != ATA_PROT_NCQ))
1855 return;
1856
1857 /* Fill in command request block
1858 */
1859 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1860 flags |= CRQB_FLAG_READ;
1861 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1862 flags |= qc->tag << CRQB_TAG_SHIFT;
1863 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1864
1865 /* get current queue index from software */
1866 in_index = pp->req_idx;
1867
1868 pp->crqb[in_index].sg_addr =
1869 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1870 pp->crqb[in_index].sg_addr_hi =
1871 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1872 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1873
1874 cw = &pp->crqb[in_index].ata_cmd[0];
1875 tf = &qc->tf;
1876
1877 /* Sadly, the CRQB cannot accomodate all registers--there are
1878 * only 11 bytes...so we must pick and choose required
1879 * registers based on the command. So, we drop feature and
1880 * hob_feature for [RW] DMA commands, but they are needed for
1881 * NCQ. NCQ will drop hob_nsect, which is not needed there
1882 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
1883 */
1884 switch (tf->command) {
1885 case ATA_CMD_READ:
1886 case ATA_CMD_READ_EXT:
1887 case ATA_CMD_WRITE:
1888 case ATA_CMD_WRITE_EXT:
1889 case ATA_CMD_WRITE_FUA_EXT:
1890 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1891 break;
1892 case ATA_CMD_FPDMA_READ:
1893 case ATA_CMD_FPDMA_WRITE:
1894 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1895 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1896 break;
1897 default:
1898 /* The only other commands EDMA supports in non-queued and
1899 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1900 * of which are defined/used by Linux. If we get here, this
1901 * driver needs work.
1902 *
1903 * FIXME: modify libata to give qc_prep a return value and
1904 * return error here.
1905 */
1906 BUG_ON(tf->command);
1907 break;
1908 }
1909 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1910 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1911 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1912 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1913 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1914 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1915 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1916 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1917 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1918
1919 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1920 return;
1921 mv_fill_sg(qc);
1922 }
1923
1924 /**
1925 * mv_qc_prep_iie - Host specific command preparation.
1926 * @qc: queued command to prepare
1927 *
1928 * This routine simply redirects to the general purpose routine
1929 * if command is not DMA. Else, it handles prep of the CRQB
1930 * (command request block), does some sanity checking, and calls
1931 * the SG load routine.
1932 *
1933 * LOCKING:
1934 * Inherited from caller.
1935 */
1936 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1937 {
1938 struct ata_port *ap = qc->ap;
1939 struct mv_port_priv *pp = ap->private_data;
1940 struct mv_crqb_iie *crqb;
1941 struct ata_taskfile *tf;
1942 unsigned in_index;
1943 u32 flags = 0;
1944
1945 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1946 (qc->tf.protocol != ATA_PROT_NCQ))
1947 return;
1948
1949 /* Fill in Gen IIE command request block */
1950 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1951 flags |= CRQB_FLAG_READ;
1952
1953 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1954 flags |= qc->tag << CRQB_TAG_SHIFT;
1955 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
1956 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1957
1958 /* get current queue index from software */
1959 in_index = pp->req_idx;
1960
1961 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
1962 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1963 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1964 crqb->flags = cpu_to_le32(flags);
1965
1966 tf = &qc->tf;
1967 crqb->ata_cmd[0] = cpu_to_le32(
1968 (tf->command << 16) |
1969 (tf->feature << 24)
1970 );
1971 crqb->ata_cmd[1] = cpu_to_le32(
1972 (tf->lbal << 0) |
1973 (tf->lbam << 8) |
1974 (tf->lbah << 16) |
1975 (tf->device << 24)
1976 );
1977 crqb->ata_cmd[2] = cpu_to_le32(
1978 (tf->hob_lbal << 0) |
1979 (tf->hob_lbam << 8) |
1980 (tf->hob_lbah << 16) |
1981 (tf->hob_feature << 24)
1982 );
1983 crqb->ata_cmd[3] = cpu_to_le32(
1984 (tf->nsect << 0) |
1985 (tf->hob_nsect << 8)
1986 );
1987
1988 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1989 return;
1990 mv_fill_sg(qc);
1991 }
1992
1993 /**
1994 * mv_sff_check_status - fetch device status, if valid
1995 * @ap: ATA port to fetch status from
1996 *
1997 * When using command issue via mv_qc_issue_fis(),
1998 * the initial ATA_BUSY state does not show up in the
1999 * ATA status (shadow) register. This can confuse libata!
2000 *
2001 * So we have a hook here to fake ATA_BUSY for that situation,
2002 * until the first time a BUSY, DRQ, or ERR bit is seen.
2003 *
2004 * The rest of the time, it simply returns the ATA status register.
2005 */
2006 static u8 mv_sff_check_status(struct ata_port *ap)
2007 {
2008 u8 stat = ioread8(ap->ioaddr.status_addr);
2009 struct mv_port_priv *pp = ap->private_data;
2010
2011 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
2012 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
2013 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
2014 else
2015 stat = ATA_BUSY;
2016 }
2017 return stat;
2018 }
2019
2020 /**
2021 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2022 * @fis: fis to be sent
2023 * @nwords: number of 32-bit words in the fis
2024 */
2025 static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
2026 {
2027 void __iomem *port_mmio = mv_ap_base(ap);
2028 u32 ifctl, old_ifctl, ifstat;
2029 int i, timeout = 200, final_word = nwords - 1;
2030
2031 /* Initiate FIS transmission mode */
2032 old_ifctl = readl(port_mmio + SATA_IFCTL_OFS);
2033 ifctl = 0x100 | (old_ifctl & 0xf);
2034 writelfl(ifctl, port_mmio + SATA_IFCTL_OFS);
2035
2036 /* Send all words of the FIS except for the final word */
2037 for (i = 0; i < final_word; ++i)
2038 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS_OFS);
2039
2040 /* Flag end-of-transmission, and then send the final word */
2041 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL_OFS);
2042 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS_OFS);
2043
2044 /*
2045 * Wait for FIS transmission to complete.
2046 * This typically takes just a single iteration.
2047 */
2048 do {
2049 ifstat = readl(port_mmio + SATA_IFSTAT_OFS);
2050 } while (!(ifstat & 0x1000) && --timeout);
2051
2052 /* Restore original port configuration */
2053 writelfl(old_ifctl, port_mmio + SATA_IFCTL_OFS);
2054
2055 /* See if it worked */
2056 if ((ifstat & 0x3000) != 0x1000) {
2057 ata_port_printk(ap, KERN_WARNING,
2058 "%s transmission error, ifstat=%08x\n",
2059 __func__, ifstat);
2060 return AC_ERR_OTHER;
2061 }
2062 return 0;
2063 }
2064
2065 /**
2066 * mv_qc_issue_fis - Issue a command directly as a FIS
2067 * @qc: queued command to start
2068 *
2069 * Note that the ATA shadow registers are not updated
2070 * after command issue, so the device will appear "READY"
2071 * if polled, even while it is BUSY processing the command.
2072 *
2073 * So we use a status hook to fake ATA_BUSY until the drive changes state.
2074 *
2075 * Note: we don't get updated shadow regs on *completion*
2076 * of non-data commands. So avoid sending them via this function,
2077 * as they will appear to have completed immediately.
2078 *
2079 * GEN_IIE has special registers that we could get the result tf from,
2080 * but earlier chipsets do not. For now, we ignore those registers.
2081 */
2082 static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
2083 {
2084 struct ata_port *ap = qc->ap;
2085 struct mv_port_priv *pp = ap->private_data;
2086 struct ata_link *link = qc->dev->link;
2087 u32 fis[5];
2088 int err = 0;
2089
2090 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
2091 err = mv_send_fis(ap, fis, sizeof(fis) / sizeof(fis[0]));
2092 if (err)
2093 return err;
2094
2095 switch (qc->tf.protocol) {
2096 case ATAPI_PROT_PIO:
2097 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2098 /* fall through */
2099 case ATAPI_PROT_NODATA:
2100 ap->hsm_task_state = HSM_ST_FIRST;
2101 break;
2102 case ATA_PROT_PIO:
2103 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2104 if (qc->tf.flags & ATA_TFLAG_WRITE)
2105 ap->hsm_task_state = HSM_ST_FIRST;
2106 else
2107 ap->hsm_task_state = HSM_ST;
2108 break;
2109 default:
2110 ap->hsm_task_state = HSM_ST_LAST;
2111 break;
2112 }
2113
2114 if (qc->tf.flags & ATA_TFLAG_POLLING)
2115 ata_pio_queue_task(ap, qc, 0);
2116 return 0;
2117 }
2118
2119 /**
2120 * mv_qc_issue - Initiate a command to the host
2121 * @qc: queued command to start
2122 *
2123 * This routine simply redirects to the general purpose routine
2124 * if command is not DMA. Else, it sanity checks our local
2125 * caches of the request producer/consumer indices then enables
2126 * DMA and bumps the request producer index.
2127 *
2128 * LOCKING:
2129 * Inherited from caller.
2130 */
2131 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
2132 {
2133 static int limit_warnings = 10;
2134 struct ata_port *ap = qc->ap;
2135 void __iomem *port_mmio = mv_ap_base(ap);
2136 struct mv_port_priv *pp = ap->private_data;
2137 u32 in_index;
2138 unsigned int port_irqs;
2139
2140 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
2141
2142 switch (qc->tf.protocol) {
2143 case ATA_PROT_DMA:
2144 case ATA_PROT_NCQ:
2145 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2146 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2147 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
2148
2149 /* Write the request in pointer to kick the EDMA to life */
2150 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
2151 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
2152 return 0;
2153
2154 case ATA_PROT_PIO:
2155 /*
2156 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2157 *
2158 * Someday, we might implement special polling workarounds
2159 * for these, but it all seems rather unnecessary since we
2160 * normally use only DMA for commands which transfer more
2161 * than a single block of data.
2162 *
2163 * Much of the time, this could just work regardless.
2164 * So for now, just log the incident, and allow the attempt.
2165 */
2166 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
2167 --limit_warnings;
2168 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
2169 ": attempting PIO w/multiple DRQ: "
2170 "this may fail due to h/w errata\n");
2171 }
2172 /* drop through */
2173 case ATA_PROT_NODATA:
2174 case ATAPI_PROT_PIO:
2175 case ATAPI_PROT_NODATA:
2176 if (ap->flags & ATA_FLAG_PIO_POLLING)
2177 qc->tf.flags |= ATA_TFLAG_POLLING;
2178 break;
2179 }
2180
2181 if (qc->tf.flags & ATA_TFLAG_POLLING)
2182 port_irqs = ERR_IRQ; /* mask device interrupt when polling */
2183 else
2184 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
2185
2186 /*
2187 * We're about to send a non-EDMA capable command to the
2188 * port. Turn off EDMA so there won't be problems accessing
2189 * shadow block, etc registers.
2190 */
2191 mv_stop_edma(ap);
2192 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2193 mv_pmp_select(ap, qc->dev->link->pmp);
2194
2195 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2196 struct mv_host_priv *hpriv = ap->host->private_data;
2197 /*
2198 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
2199 *
2200 * After any NCQ error, the READ_LOG_EXT command
2201 * from libata-eh *must* use mv_qc_issue_fis().
2202 * Otherwise it might fail, due to chip errata.
2203 *
2204 * Rather than special-case it, we'll just *always*
2205 * use this method here for READ_LOG_EXT, making for
2206 * easier testing.
2207 */
2208 if (IS_GEN_II(hpriv))
2209 return mv_qc_issue_fis(qc);
2210 }
2211 return ata_sff_qc_issue(qc);
2212 }
2213
2214 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
2215 {
2216 struct mv_port_priv *pp = ap->private_data;
2217 struct ata_queued_cmd *qc;
2218
2219 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2220 return NULL;
2221 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2222 if (qc) {
2223 if (qc->tf.flags & ATA_TFLAG_POLLING)
2224 qc = NULL;
2225 else if (!(qc->flags & ATA_QCFLAG_ACTIVE))
2226 qc = NULL;
2227 }
2228 return qc;
2229 }
2230
2231 static void mv_pmp_error_handler(struct ata_port *ap)
2232 {
2233 unsigned int pmp, pmp_map;
2234 struct mv_port_priv *pp = ap->private_data;
2235
2236 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2237 /*
2238 * Perform NCQ error analysis on failed PMPs
2239 * before we freeze the port entirely.
2240 *
2241 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2242 */
2243 pmp_map = pp->delayed_eh_pmp_map;
2244 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2245 for (pmp = 0; pmp_map != 0; pmp++) {
2246 unsigned int this_pmp = (1 << pmp);
2247 if (pmp_map & this_pmp) {
2248 struct ata_link *link = &ap->pmp_link[pmp];
2249 pmp_map &= ~this_pmp;
2250 ata_eh_analyze_ncq_error(link);
2251 }
2252 }
2253 ata_port_freeze(ap);
2254 }
2255 sata_pmp_error_handler(ap);
2256 }
2257
2258 static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2259 {
2260 void __iomem *port_mmio = mv_ap_base(ap);
2261
2262 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
2263 }
2264
2265 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2266 {
2267 struct ata_eh_info *ehi;
2268 unsigned int pmp;
2269
2270 /*
2271 * Initialize EH info for PMPs which saw device errors
2272 */
2273 ehi = &ap->link.eh_info;
2274 for (pmp = 0; pmp_map != 0; pmp++) {
2275 unsigned int this_pmp = (1 << pmp);
2276 if (pmp_map & this_pmp) {
2277 struct ata_link *link = &ap->pmp_link[pmp];
2278
2279 pmp_map &= ~this_pmp;
2280 ehi = &link->eh_info;
2281 ata_ehi_clear_desc(ehi);
2282 ata_ehi_push_desc(ehi, "dev err");
2283 ehi->err_mask |= AC_ERR_DEV;
2284 ehi->action |= ATA_EH_RESET;
2285 ata_link_abort(link);
2286 }
2287 }
2288 }
2289
2290 static int mv_req_q_empty(struct ata_port *ap)
2291 {
2292 void __iomem *port_mmio = mv_ap_base(ap);
2293 u32 in_ptr, out_ptr;
2294
2295 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS)
2296 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2297 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
2298 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2299 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
2300 }
2301
2302 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2303 {
2304 struct mv_port_priv *pp = ap->private_data;
2305 int failed_links;
2306 unsigned int old_map, new_map;
2307
2308 /*
2309 * Device error during FBS+NCQ operation:
2310 *
2311 * Set a port flag to prevent further I/O being enqueued.
2312 * Leave the EDMA running to drain outstanding commands from this port.
2313 * Perform the post-mortem/EH only when all responses are complete.
2314 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2315 */
2316 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2317 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2318 pp->delayed_eh_pmp_map = 0;
2319 }
2320 old_map = pp->delayed_eh_pmp_map;
2321 new_map = old_map | mv_get_err_pmp_map(ap);
2322
2323 if (old_map != new_map) {
2324 pp->delayed_eh_pmp_map = new_map;
2325 mv_pmp_eh_prep(ap, new_map & ~old_map);
2326 }
2327 failed_links = hweight16(new_map);
2328
2329 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
2330 "failed_links=%d nr_active_links=%d\n",
2331 __func__, pp->delayed_eh_pmp_map,
2332 ap->qc_active, failed_links,
2333 ap->nr_active_links);
2334
2335 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
2336 mv_process_crpb_entries(ap, pp);
2337 mv_stop_edma(ap);
2338 mv_eh_freeze(ap);
2339 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
2340 return 1; /* handled */
2341 }
2342 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
2343 return 1; /* handled */
2344 }
2345
2346 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2347 {
2348 /*
2349 * Possible future enhancement:
2350 *
2351 * FBS+non-NCQ operation is not yet implemented.
2352 * See related notes in mv_edma_cfg().
2353 *
2354 * Device error during FBS+non-NCQ operation:
2355 *
2356 * We need to snapshot the shadow registers for each failed command.
2357 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2358 */
2359 return 0; /* not handled */
2360 }
2361
2362 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2363 {
2364 struct mv_port_priv *pp = ap->private_data;
2365
2366 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2367 return 0; /* EDMA was not active: not handled */
2368 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2369 return 0; /* FBS was not active: not handled */
2370
2371 if (!(edma_err_cause & EDMA_ERR_DEV))
2372 return 0; /* non DEV error: not handled */
2373 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2374 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2375 return 0; /* other problems: not handled */
2376
2377 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2378 /*
2379 * EDMA should NOT have self-disabled for this case.
2380 * If it did, then something is wrong elsewhere,
2381 * and we cannot handle it here.
2382 */
2383 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2384 ata_port_printk(ap, KERN_WARNING,
2385 "%s: err_cause=0x%x pp_flags=0x%x\n",
2386 __func__, edma_err_cause, pp->pp_flags);
2387 return 0; /* not handled */
2388 }
2389 return mv_handle_fbs_ncq_dev_err(ap);
2390 } else {
2391 /*
2392 * EDMA should have self-disabled for this case.
2393 * If it did not, then something is wrong elsewhere,
2394 * and we cannot handle it here.
2395 */
2396 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
2397 ata_port_printk(ap, KERN_WARNING,
2398 "%s: err_cause=0x%x pp_flags=0x%x\n",
2399 __func__, edma_err_cause, pp->pp_flags);
2400 return 0; /* not handled */
2401 }
2402 return mv_handle_fbs_non_ncq_dev_err(ap);
2403 }
2404 return 0; /* not handled */
2405 }
2406
2407 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
2408 {
2409 struct ata_eh_info *ehi = &ap->link.eh_info;
2410 char *when = "idle";
2411
2412 ata_ehi_clear_desc(ehi);
2413 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2414 when = "disabled";
2415 } else if (edma_was_enabled) {
2416 when = "EDMA enabled";
2417 } else {
2418 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2419 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
2420 when = "polling";
2421 }
2422 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
2423 ehi->err_mask |= AC_ERR_OTHER;
2424 ehi->action |= ATA_EH_RESET;
2425 ata_port_freeze(ap);
2426 }
2427
2428 /**
2429 * mv_err_intr - Handle error interrupts on the port
2430 * @ap: ATA channel to manipulate
2431 *
2432 * Most cases require a full reset of the chip's state machine,
2433 * which also performs a COMRESET.
2434 * Also, if the port disabled DMA, update our cached copy to match.
2435 *
2436 * LOCKING:
2437 * Inherited from caller.
2438 */
2439 static void mv_err_intr(struct ata_port *ap)
2440 {
2441 void __iomem *port_mmio = mv_ap_base(ap);
2442 u32 edma_err_cause, eh_freeze_mask, serr = 0;
2443 u32 fis_cause = 0;
2444 struct mv_port_priv *pp = ap->private_data;
2445 struct mv_host_priv *hpriv = ap->host->private_data;
2446 unsigned int action = 0, err_mask = 0;
2447 struct ata_eh_info *ehi = &ap->link.eh_info;
2448 struct ata_queued_cmd *qc;
2449 int abort = 0;
2450
2451 /*
2452 * Read and clear the SError and err_cause bits.
2453 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2454 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
2455 */
2456 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2457 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2458
2459 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2460 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2461 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
2462 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
2463 }
2464 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2465
2466 if (edma_err_cause & EDMA_ERR_DEV) {
2467 /*
2468 * Device errors during FIS-based switching operation
2469 * require special handling.
2470 */
2471 if (mv_handle_dev_err(ap, edma_err_cause))
2472 return;
2473 }
2474
2475 qc = mv_get_active_qc(ap);
2476 ata_ehi_clear_desc(ehi);
2477 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2478 edma_err_cause, pp->pp_flags);
2479
2480 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2481 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
2482 if (fis_cause & SATA_FIS_IRQ_AN) {
2483 u32 ec = edma_err_cause &
2484 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2485 sata_async_notification(ap);
2486 if (!ec)
2487 return; /* Just an AN; no need for the nukes */
2488 ata_ehi_push_desc(ehi, "SDB notify");
2489 }
2490 }
2491 /*
2492 * All generations share these EDMA error cause bits:
2493 */
2494 if (edma_err_cause & EDMA_ERR_DEV) {
2495 err_mask |= AC_ERR_DEV;
2496 action |= ATA_EH_RESET;
2497 ata_ehi_push_desc(ehi, "dev error");
2498 }
2499 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
2500 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
2501 EDMA_ERR_INTRL_PAR)) {
2502 err_mask |= AC_ERR_ATA_BUS;
2503 action |= ATA_EH_RESET;
2504 ata_ehi_push_desc(ehi, "parity error");
2505 }
2506 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2507 ata_ehi_hotplugged(ehi);
2508 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
2509 "dev disconnect" : "dev connect");
2510 action |= ATA_EH_RESET;
2511 }
2512
2513 /*
2514 * Gen-I has a different SELF_DIS bit,
2515 * different FREEZE bits, and no SERR bit:
2516 */
2517 if (IS_GEN_I(hpriv)) {
2518 eh_freeze_mask = EDMA_EH_FREEZE_5;
2519 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
2520 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2521 ata_ehi_push_desc(ehi, "EDMA self-disable");
2522 }
2523 } else {
2524 eh_freeze_mask = EDMA_EH_FREEZE;
2525 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2526 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2527 ata_ehi_push_desc(ehi, "EDMA self-disable");
2528 }
2529 if (edma_err_cause & EDMA_ERR_SERR) {
2530 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2531 err_mask |= AC_ERR_ATA_BUS;
2532 action |= ATA_EH_RESET;
2533 }
2534 }
2535
2536 if (!err_mask) {
2537 err_mask = AC_ERR_OTHER;
2538 action |= ATA_EH_RESET;
2539 }
2540
2541 ehi->serror |= serr;
2542 ehi->action |= action;
2543
2544 if (qc)
2545 qc->err_mask |= err_mask;
2546 else
2547 ehi->err_mask |= err_mask;
2548
2549 if (err_mask == AC_ERR_DEV) {
2550 /*
2551 * Cannot do ata_port_freeze() here,
2552 * because it would kill PIO access,
2553 * which is needed for further diagnosis.
2554 */
2555 mv_eh_freeze(ap);
2556 abort = 1;
2557 } else if (edma_err_cause & eh_freeze_mask) {
2558 /*
2559 * Note to self: ata_port_freeze() calls ata_port_abort()
2560 */
2561 ata_port_freeze(ap);
2562 } else {
2563 abort = 1;
2564 }
2565
2566 if (abort) {
2567 if (qc)
2568 ata_link_abort(qc->dev->link);
2569 else
2570 ata_port_abort(ap);
2571 }
2572 }
2573
2574 static void mv_process_crpb_response(struct ata_port *ap,
2575 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2576 {
2577 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
2578
2579 if (qc) {
2580 u8 ata_status;
2581 u16 edma_status = le16_to_cpu(response->flags);
2582 /*
2583 * edma_status from a response queue entry:
2584 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
2585 * MSB is saved ATA status from command completion.
2586 */
2587 if (!ncq_enabled) {
2588 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2589 if (err_cause) {
2590 /*
2591 * Error will be seen/handled by mv_err_intr().
2592 * So do nothing at all here.
2593 */
2594 return;
2595 }
2596 }
2597 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2598 if (!ac_err_mask(ata_status))
2599 ata_qc_complete(qc);
2600 /* else: leave it for mv_err_intr() */
2601 } else {
2602 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2603 __func__, tag);
2604 }
2605 }
2606
2607 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
2608 {
2609 void __iomem *port_mmio = mv_ap_base(ap);
2610 struct mv_host_priv *hpriv = ap->host->private_data;
2611 u32 in_index;
2612 bool work_done = false;
2613 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
2614
2615 /* Get the hardware queue position index */
2616 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
2617 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2618
2619 /* Process new responses from since the last time we looked */
2620 while (in_index != pp->resp_idx) {
2621 unsigned int tag;
2622 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
2623
2624 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2625
2626 if (IS_GEN_I(hpriv)) {
2627 /* 50xx: no NCQ, only one command active at a time */
2628 tag = ap->link.active_tag;
2629 } else {
2630 /* Gen II/IIE: get command tag from CRPB entry */
2631 tag = le16_to_cpu(response->id) & 0x1f;
2632 }
2633 mv_process_crpb_response(ap, response, tag, ncq_enabled);
2634 work_done = true;
2635 }
2636
2637 /* Update the software queue position index in hardware */
2638 if (work_done)
2639 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
2640 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
2641 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
2642 }
2643
2644 static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2645 {
2646 struct mv_port_priv *pp;
2647 int edma_was_enabled;
2648
2649 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2650 mv_unexpected_intr(ap, 0);
2651 return;
2652 }
2653 /*
2654 * Grab a snapshot of the EDMA_EN flag setting,
2655 * so that we have a consistent view for this port,
2656 * even if something we call of our routines changes it.
2657 */
2658 pp = ap->private_data;
2659 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2660 /*
2661 * Process completed CRPB response(s) before other events.
2662 */
2663 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2664 mv_process_crpb_entries(ap, pp);
2665 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2666 mv_handle_fbs_ncq_dev_err(ap);
2667 }
2668 /*
2669 * Handle chip-reported errors, or continue on to handle PIO.
2670 */
2671 if (unlikely(port_cause & ERR_IRQ)) {
2672 mv_err_intr(ap);
2673 } else if (!edma_was_enabled) {
2674 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2675 if (qc)
2676 ata_sff_host_intr(ap, qc);
2677 else
2678 mv_unexpected_intr(ap, edma_was_enabled);
2679 }
2680 }
2681
2682 /**
2683 * mv_host_intr - Handle all interrupts on the given host controller
2684 * @host: host specific structure
2685 * @main_irq_cause: Main interrupt cause register for the chip.
2686 *
2687 * LOCKING:
2688 * Inherited from caller.
2689 */
2690 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2691 {
2692 struct mv_host_priv *hpriv = host->private_data;
2693 void __iomem *mmio = hpriv->base, *hc_mmio;
2694 unsigned int handled = 0, port;
2695
2696 /* If asserted, clear the "all ports" IRQ coalescing bit */
2697 if (main_irq_cause & ALL_PORTS_COAL_DONE)
2698 writel(~ALL_PORTS_COAL_IRQ, mmio + MV_IRQ_COAL_CAUSE);
2699
2700 for (port = 0; port < hpriv->n_ports; port++) {
2701 struct ata_port *ap = host->ports[port];
2702 unsigned int p, shift, hardport, port_cause;
2703
2704 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2705 /*
2706 * Each hc within the host has its own hc_irq_cause register,
2707 * where the interrupting ports bits get ack'd.
2708 */
2709 if (hardport == 0) { /* first port on this hc ? */
2710 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2711 u32 port_mask, ack_irqs;
2712 /*
2713 * Skip this entire hc if nothing pending for any ports
2714 */
2715 if (!hc_cause) {
2716 port += MV_PORTS_PER_HC - 1;
2717 continue;
2718 }
2719 /*
2720 * We don't need/want to read the hc_irq_cause register,
2721 * because doing so hurts performance, and
2722 * main_irq_cause already gives us everything we need.
2723 *
2724 * But we do have to *write* to the hc_irq_cause to ack
2725 * the ports that we are handling this time through.
2726 *
2727 * This requires that we create a bitmap for those
2728 * ports which interrupted us, and use that bitmap
2729 * to ack (only) those ports via hc_irq_cause.
2730 */
2731 ack_irqs = 0;
2732 if (hc_cause & PORTS_0_3_COAL_DONE)
2733 ack_irqs = HC_COAL_IRQ;
2734 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2735 if ((port + p) >= hpriv->n_ports)
2736 break;
2737 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2738 if (hc_cause & port_mask)
2739 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2740 }
2741 hc_mmio = mv_hc_base_from_port(mmio, port);
2742 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
2743 handled = 1;
2744 }
2745 /*
2746 * Handle interrupts signalled for this port:
2747 */
2748 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2749 if (port_cause)
2750 mv_port_intr(ap, port_cause);
2751 }
2752 return handled;
2753 }
2754
2755 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
2756 {
2757 struct mv_host_priv *hpriv = host->private_data;
2758 struct ata_port *ap;
2759 struct ata_queued_cmd *qc;
2760 struct ata_eh_info *ehi;
2761 unsigned int i, err_mask, printed = 0;
2762 u32 err_cause;
2763
2764 err_cause = readl(mmio + hpriv->irq_cause_ofs);
2765
2766 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2767 err_cause);
2768
2769 DPRINTK("All regs @ PCI error\n");
2770 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2771
2772 writelfl(0, mmio + hpriv->irq_cause_ofs);
2773
2774 for (i = 0; i < host->n_ports; i++) {
2775 ap = host->ports[i];
2776 if (!ata_link_offline(&ap->link)) {
2777 ehi = &ap->link.eh_info;
2778 ata_ehi_clear_desc(ehi);
2779 if (!printed++)
2780 ata_ehi_push_desc(ehi,
2781 "PCI err cause 0x%08x", err_cause);
2782 err_mask = AC_ERR_HOST_BUS;
2783 ehi->action = ATA_EH_RESET;
2784 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2785 if (qc)
2786 qc->err_mask |= err_mask;
2787 else
2788 ehi->err_mask |= err_mask;
2789
2790 ata_port_freeze(ap);
2791 }
2792 }
2793 return 1; /* handled */
2794 }
2795
2796 /**
2797 * mv_interrupt - Main interrupt event handler
2798 * @irq: unused
2799 * @dev_instance: private data; in this case the host structure
2800 *
2801 * Read the read only register to determine if any host
2802 * controllers have pending interrupts. If so, call lower level
2803 * routine to handle. Also check for PCI errors which are only
2804 * reported here.
2805 *
2806 * LOCKING:
2807 * This routine holds the host lock while processing pending
2808 * interrupts.
2809 */
2810 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2811 {
2812 struct ata_host *host = dev_instance;
2813 struct mv_host_priv *hpriv = host->private_data;
2814 unsigned int handled = 0;
2815 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
2816 u32 main_irq_cause, pending_irqs;
2817
2818 spin_lock(&host->lock);
2819
2820 /* for MSI: block new interrupts while in here */
2821 if (using_msi)
2822 mv_write_main_irq_mask(0, hpriv);
2823
2824 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2825 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
2826 /*
2827 * Deal with cases where we either have nothing pending, or have read
2828 * a bogus register value which can indicate HW removal or PCI fault.
2829 */
2830 if (pending_irqs && main_irq_cause != 0xffffffffU) {
2831 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
2832 handled = mv_pci_error(host, hpriv->base);
2833 else
2834 handled = mv_host_intr(host, pending_irqs);
2835 }
2836
2837 /* for MSI: unmask; interrupt cause bits will retrigger now */
2838 if (using_msi)
2839 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
2840
2841 spin_unlock(&host->lock);
2842
2843 return IRQ_RETVAL(handled);
2844 }
2845
2846 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2847 {
2848 unsigned int ofs;
2849
2850 switch (sc_reg_in) {
2851 case SCR_STATUS:
2852 case SCR_ERROR:
2853 case SCR_CONTROL:
2854 ofs = sc_reg_in * sizeof(u32);
2855 break;
2856 default:
2857 ofs = 0xffffffffU;
2858 break;
2859 }
2860 return ofs;
2861 }
2862
2863 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
2864 {
2865 struct mv_host_priv *hpriv = link->ap->host->private_data;
2866 void __iomem *mmio = hpriv->base;
2867 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
2868 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2869
2870 if (ofs != 0xffffffffU) {
2871 *val = readl(addr + ofs);
2872 return 0;
2873 } else
2874 return -EINVAL;
2875 }
2876
2877 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
2878 {
2879 struct mv_host_priv *hpriv = link->ap->host->private_data;
2880 void __iomem *mmio = hpriv->base;
2881 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
2882 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2883
2884 if (ofs != 0xffffffffU) {
2885 writelfl(val, addr + ofs);
2886 return 0;
2887 } else
2888 return -EINVAL;
2889 }
2890
2891 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
2892 {
2893 struct pci_dev *pdev = to_pci_dev(host->dev);
2894 int early_5080;
2895
2896 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
2897
2898 if (!early_5080) {
2899 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2900 tmp |= (1 << 0);
2901 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2902 }
2903
2904 mv_reset_pci_bus(host, mmio);
2905 }
2906
2907 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2908 {
2909 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
2910 }
2911
2912 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
2913 void __iomem *mmio)
2914 {
2915 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2916 u32 tmp;
2917
2918 tmp = readl(phy_mmio + MV5_PHY_MODE);
2919
2920 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2921 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
2922 }
2923
2924 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2925 {
2926 u32 tmp;
2927
2928 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
2929
2930 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2931
2932 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2933 tmp |= ~(1 << 0);
2934 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2935 }
2936
2937 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2938 unsigned int port)
2939 {
2940 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2941 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2942 u32 tmp;
2943 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2944
2945 if (fix_apm_sq) {
2946 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
2947 tmp |= (1 << 19);
2948 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
2949
2950 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
2951 tmp &= ~0x3;
2952 tmp |= 0x1;
2953 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
2954 }
2955
2956 tmp = readl(phy_mmio + MV5_PHY_MODE);
2957 tmp &= ~mask;
2958 tmp |= hpriv->signal[port].pre;
2959 tmp |= hpriv->signal[port].amps;
2960 writel(tmp, phy_mmio + MV5_PHY_MODE);
2961 }
2962
2963
2964 #undef ZERO
2965 #define ZERO(reg) writel(0, port_mmio + (reg))
2966 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2967 unsigned int port)
2968 {
2969 void __iomem *port_mmio = mv_port_base(mmio, port);
2970
2971 mv_reset_channel(hpriv, mmio, port);
2972
2973 ZERO(0x028); /* command */
2974 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2975 ZERO(0x004); /* timer */
2976 ZERO(0x008); /* irq err cause */
2977 ZERO(0x00c); /* irq err mask */
2978 ZERO(0x010); /* rq bah */
2979 ZERO(0x014); /* rq inp */
2980 ZERO(0x018); /* rq outp */
2981 ZERO(0x01c); /* respq bah */
2982 ZERO(0x024); /* respq outp */
2983 ZERO(0x020); /* respq inp */
2984 ZERO(0x02c); /* test control */
2985 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2986 }
2987 #undef ZERO
2988
2989 #define ZERO(reg) writel(0, hc_mmio + (reg))
2990 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2991 unsigned int hc)
2992 {
2993 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2994 u32 tmp;
2995
2996 ZERO(0x00c);
2997 ZERO(0x010);
2998 ZERO(0x014);
2999 ZERO(0x018);
3000
3001 tmp = readl(hc_mmio + 0x20);
3002 tmp &= 0x1c1c1c1c;
3003 tmp |= 0x03030303;
3004 writel(tmp, hc_mmio + 0x20);
3005 }
3006 #undef ZERO
3007
3008 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3009 unsigned int n_hc)
3010 {
3011 unsigned int hc, port;
3012
3013 for (hc = 0; hc < n_hc; hc++) {
3014 for (port = 0; port < MV_PORTS_PER_HC; port++)
3015 mv5_reset_hc_port(hpriv, mmio,
3016 (hc * MV_PORTS_PER_HC) + port);
3017
3018 mv5_reset_one_hc(hpriv, mmio, hc);
3019 }
3020
3021 return 0;
3022 }
3023
3024 #undef ZERO
3025 #define ZERO(reg) writel(0, mmio + (reg))
3026 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
3027 {
3028 struct mv_host_priv *hpriv = host->private_data;
3029 u32 tmp;
3030
3031 tmp = readl(mmio + MV_PCI_MODE_OFS);
3032 tmp &= 0xff00ffff;
3033 writel(tmp, mmio + MV_PCI_MODE_OFS);
3034
3035 ZERO(MV_PCI_DISC_TIMER);
3036 ZERO(MV_PCI_MSI_TRIGGER);
3037 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
3038 ZERO(MV_PCI_SERR_MASK);
3039 ZERO(hpriv->irq_cause_ofs);
3040 ZERO(hpriv->irq_mask_ofs);
3041 ZERO(MV_PCI_ERR_LOW_ADDRESS);
3042 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
3043 ZERO(MV_PCI_ERR_ATTRIBUTE);
3044 ZERO(MV_PCI_ERR_COMMAND);
3045 }
3046 #undef ZERO
3047
3048 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3049 {
3050 u32 tmp;
3051
3052 mv5_reset_flash(hpriv, mmio);
3053
3054 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
3055 tmp &= 0x3;
3056 tmp |= (1 << 5) | (1 << 6);
3057 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
3058 }
3059
3060 /**
3061 * mv6_reset_hc - Perform the 6xxx global soft reset
3062 * @mmio: base address of the HBA
3063 *
3064 * This routine only applies to 6xxx parts.
3065 *
3066 * LOCKING:
3067 * Inherited from caller.
3068 */
3069 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3070 unsigned int n_hc)
3071 {
3072 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
3073 int i, rc = 0;
3074 u32 t;
3075
3076 /* Following procedure defined in PCI "main command and status
3077 * register" table.
3078 */
3079 t = readl(reg);
3080 writel(t | STOP_PCI_MASTER, reg);
3081
3082 for (i = 0; i < 1000; i++) {
3083 udelay(1);
3084 t = readl(reg);
3085 if (PCI_MASTER_EMPTY & t)
3086 break;
3087 }
3088 if (!(PCI_MASTER_EMPTY & t)) {
3089 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
3090 rc = 1;
3091 goto done;
3092 }
3093
3094 /* set reset */
3095 i = 5;
3096 do {
3097 writel(t | GLOB_SFT_RST, reg);
3098 t = readl(reg);
3099 udelay(1);
3100 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
3101
3102 if (!(GLOB_SFT_RST & t)) {
3103 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
3104 rc = 1;
3105 goto done;
3106 }
3107
3108 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
3109 i = 5;
3110 do {
3111 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
3112 t = readl(reg);
3113 udelay(1);
3114 } while ((GLOB_SFT_RST & t) && (i-- > 0));
3115
3116 if (GLOB_SFT_RST & t) {
3117 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
3118 rc = 1;
3119 }
3120 done:
3121 return rc;
3122 }
3123
3124 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
3125 void __iomem *mmio)
3126 {
3127 void __iomem *port_mmio;
3128 u32 tmp;
3129
3130 tmp = readl(mmio + MV_RESET_CFG_OFS);
3131 if ((tmp & (1 << 0)) == 0) {
3132 hpriv->signal[idx].amps = 0x7 << 8;
3133 hpriv->signal[idx].pre = 0x1 << 5;
3134 return;
3135 }
3136
3137 port_mmio = mv_port_base(mmio, idx);
3138 tmp = readl(port_mmio + PHY_MODE2);
3139
3140 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3141 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3142 }
3143
3144 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3145 {
3146 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
3147 }
3148
3149 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3150 unsigned int port)
3151 {
3152 void __iomem *port_mmio = mv_port_base(mmio, port);
3153
3154 u32 hp_flags = hpriv->hp_flags;
3155 int fix_phy_mode2 =
3156 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3157 int fix_phy_mode4 =
3158 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
3159 u32 m2, m3;
3160
3161 if (fix_phy_mode2) {
3162 m2 = readl(port_mmio + PHY_MODE2);
3163 m2 &= ~(1 << 16);
3164 m2 |= (1 << 31);
3165 writel(m2, port_mmio + PHY_MODE2);
3166
3167 udelay(200);
3168
3169 m2 = readl(port_mmio + PHY_MODE2);
3170 m2 &= ~((1 << 16) | (1 << 31));
3171 writel(m2, port_mmio + PHY_MODE2);
3172
3173 udelay(200);
3174 }
3175
3176 /*
3177 * Gen-II/IIe PHY_MODE3 errata RM#2:
3178 * Achieves better receiver noise performance than the h/w default:
3179 */
3180 m3 = readl(port_mmio + PHY_MODE3);
3181 m3 = (m3 & 0x1f) | (0x5555601 << 5);
3182
3183 /* Guideline 88F5182 (GL# SATA-S11) */
3184 if (IS_SOC(hpriv))
3185 m3 &= ~0x1c;
3186
3187 if (fix_phy_mode4) {
3188 u32 m4 = readl(port_mmio + PHY_MODE4);
3189 /*
3190 * Enforce reserved-bit restrictions on GenIIe devices only.
3191 * For earlier chipsets, force only the internal config field
3192 * (workaround for errata FEr SATA#10 part 1).
3193 */
3194 if (IS_GEN_IIE(hpriv))
3195 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
3196 else
3197 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
3198 writel(m4, port_mmio + PHY_MODE4);
3199 }
3200 /*
3201 * Workaround for 60x1-B2 errata SATA#13:
3202 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3203 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
3204 */
3205 writel(m3, port_mmio + PHY_MODE3);
3206
3207 /* Revert values of pre-emphasis and signal amps to the saved ones */
3208 m2 = readl(port_mmio + PHY_MODE2);
3209
3210 m2 &= ~MV_M2_PREAMP_MASK;
3211 m2 |= hpriv->signal[port].amps;
3212 m2 |= hpriv->signal[port].pre;
3213 m2 &= ~(1 << 16);
3214
3215 /* according to mvSata 3.6.1, some IIE values are fixed */
3216 if (IS_GEN_IIE(hpriv)) {
3217 m2 &= ~0xC30FF01F;
3218 m2 |= 0x0000900F;
3219 }
3220
3221 writel(m2, port_mmio + PHY_MODE2);
3222 }
3223
3224 /* TODO: use the generic LED interface to configure the SATA Presence */
3225 /* & Acitivy LEDs on the board */
3226 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3227 void __iomem *mmio)
3228 {
3229 return;
3230 }
3231
3232 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3233 void __iomem *mmio)
3234 {
3235 void __iomem *port_mmio;
3236 u32 tmp;
3237
3238 port_mmio = mv_port_base(mmio, idx);
3239 tmp = readl(port_mmio + PHY_MODE2);
3240
3241 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3242 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3243 }
3244
3245 #undef ZERO
3246 #define ZERO(reg) writel(0, port_mmio + (reg))
3247 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3248 void __iomem *mmio, unsigned int port)
3249 {
3250 void __iomem *port_mmio = mv_port_base(mmio, port);
3251
3252 mv_reset_channel(hpriv, mmio, port);
3253
3254 ZERO(0x028); /* command */
3255 writel(0x101f, port_mmio + EDMA_CFG_OFS);
3256 ZERO(0x004); /* timer */
3257 ZERO(0x008); /* irq err cause */
3258 ZERO(0x00c); /* irq err mask */
3259 ZERO(0x010); /* rq bah */
3260 ZERO(0x014); /* rq inp */
3261 ZERO(0x018); /* rq outp */
3262 ZERO(0x01c); /* respq bah */
3263 ZERO(0x024); /* respq outp */
3264 ZERO(0x020); /* respq inp */
3265 ZERO(0x02c); /* test control */
3266 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
3267 }
3268
3269 #undef ZERO
3270
3271 #define ZERO(reg) writel(0, hc_mmio + (reg))
3272 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3273 void __iomem *mmio)
3274 {
3275 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3276
3277 ZERO(0x00c);
3278 ZERO(0x010);
3279 ZERO(0x014);
3280
3281 }
3282
3283 #undef ZERO
3284
3285 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3286 void __iomem *mmio, unsigned int n_hc)
3287 {
3288 unsigned int port;
3289
3290 for (port = 0; port < hpriv->n_ports; port++)
3291 mv_soc_reset_hc_port(hpriv, mmio, port);
3292
3293 mv_soc_reset_one_hc(hpriv, mmio);
3294
3295 return 0;
3296 }
3297
3298 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3299 void __iomem *mmio)
3300 {
3301 return;
3302 }
3303
3304 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3305 {
3306 return;
3307 }
3308
3309 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
3310 {
3311 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
3312
3313 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
3314 if (want_gen2i)
3315 ifcfg |= (1 << 7); /* enable gen2i speed */
3316 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
3317 }
3318
3319 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
3320 unsigned int port_no)
3321 {
3322 void __iomem *port_mmio = mv_port_base(mmio, port_no);
3323
3324 /*
3325 * The datasheet warns against setting EDMA_RESET when EDMA is active
3326 * (but doesn't say what the problem might be). So we first try
3327 * to disable the EDMA engine before doing the EDMA_RESET operation.
3328 */
3329 mv_stop_edma_engine(port_mmio);
3330 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
3331
3332 if (!IS_GEN_I(hpriv)) {
3333 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3334 mv_setup_ifcfg(port_mmio, 1);
3335 }
3336 /*
3337 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
3338 * link, and physical layers. It resets all SATA interface registers
3339 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
3340 */
3341 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
3342 udelay(25); /* allow reset propagation */
3343 writelfl(0, port_mmio + EDMA_CMD_OFS);
3344
3345 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3346
3347 if (IS_GEN_I(hpriv))
3348 mdelay(1);
3349 }
3350
3351 static void mv_pmp_select(struct ata_port *ap, int pmp)
3352 {
3353 if (sata_pmp_supported(ap)) {
3354 void __iomem *port_mmio = mv_ap_base(ap);
3355 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
3356 int old = reg & 0xf;
3357
3358 if (old != pmp) {
3359 reg = (reg & ~0xf) | pmp;
3360 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
3361 }
3362 }
3363 }
3364
3365 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3366 unsigned long deadline)
3367 {
3368 mv_pmp_select(link->ap, sata_srst_pmp(link));
3369 return sata_std_hardreset(link, class, deadline);
3370 }
3371
3372 static int mv_softreset(struct ata_link *link, unsigned int *class,
3373 unsigned long deadline)
3374 {
3375 mv_pmp_select(link->ap, sata_srst_pmp(link));
3376 return ata_sff_softreset(link, class, deadline);
3377 }
3378
3379 static int mv_hardreset(struct ata_link *link, unsigned int *class,
3380 unsigned long deadline)
3381 {
3382 struct ata_port *ap = link->ap;
3383 struct mv_host_priv *hpriv = ap->host->private_data;
3384 struct mv_port_priv *pp = ap->private_data;
3385 void __iomem *mmio = hpriv->base;
3386 int rc, attempts = 0, extra = 0;
3387 u32 sstatus;
3388 bool online;
3389
3390 mv_reset_channel(hpriv, mmio, ap->port_no);
3391 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
3392 pp->pp_flags &=
3393 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
3394
3395 /* Workaround for errata FEr SATA#10 (part 2) */
3396 do {
3397 const unsigned long *timing =
3398 sata_ehc_deb_timing(&link->eh_context);
3399
3400 rc = sata_link_hardreset(link, timing, deadline + extra,
3401 &online, NULL);
3402 rc = online ? -EAGAIN : rc;
3403 if (rc)
3404 return rc;
3405 sata_scr_read(link, SCR_STATUS, &sstatus);
3406 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3407 /* Force 1.5gb/s link speed and try again */
3408 mv_setup_ifcfg(mv_ap_base(ap), 0);
3409 if (time_after(jiffies + HZ, deadline))
3410 extra = HZ; /* only extend it once, max */
3411 }
3412 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
3413 mv_save_cached_regs(ap);
3414 mv_edma_cfg(ap, 0, 0);
3415
3416 return rc;
3417 }
3418
3419 static void mv_eh_freeze(struct ata_port *ap)
3420 {
3421 mv_stop_edma(ap);
3422 mv_enable_port_irqs(ap, 0);
3423 }
3424
3425 static void mv_eh_thaw(struct ata_port *ap)
3426 {
3427 struct mv_host_priv *hpriv = ap->host->private_data;
3428 unsigned int port = ap->port_no;
3429 unsigned int hardport = mv_hardport_from_port(port);
3430 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
3431 void __iomem *port_mmio = mv_ap_base(ap);
3432 u32 hc_irq_cause;
3433
3434 /* clear EDMA errors on this port */
3435 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
3436
3437 /* clear pending irq events */
3438 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
3439 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
3440
3441 mv_enable_port_irqs(ap, ERR_IRQ);
3442 }
3443
3444 /**
3445 * mv_port_init - Perform some early initialization on a single port.
3446 * @port: libata data structure storing shadow register addresses
3447 * @port_mmio: base address of the port
3448 *
3449 * Initialize shadow register mmio addresses, clear outstanding
3450 * interrupts on the port, and unmask interrupts for the future
3451 * start of the port.
3452 *
3453 * LOCKING:
3454 * Inherited from caller.
3455 */
3456 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
3457 {
3458 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
3459 unsigned serr_ofs;
3460
3461 /* PIO related setup
3462 */
3463 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
3464 port->error_addr =
3465 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3466 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3467 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3468 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3469 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3470 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
3471 port->status_addr =
3472 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3473 /* special case: control/altstatus doesn't have ATA_REG_ address */
3474 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
3475
3476 /* unused: */
3477 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
3478
3479 /* Clear any currently outstanding port interrupt conditions */
3480 serr_ofs = mv_scr_offset(SCR_ERROR);
3481 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
3482 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
3483
3484 /* unmask all non-transient EDMA error interrupts */
3485 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
3486
3487 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
3488 readl(port_mmio + EDMA_CFG_OFS),
3489 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
3490 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
3491 }
3492
3493 static unsigned int mv_in_pcix_mode(struct ata_host *host)
3494 {
3495 struct mv_host_priv *hpriv = host->private_data;
3496 void __iomem *mmio = hpriv->base;
3497 u32 reg;
3498
3499 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
3500 return 0; /* not PCI-X capable */
3501 reg = readl(mmio + MV_PCI_MODE_OFS);
3502 if ((reg & MV_PCI_MODE_MASK) == 0)
3503 return 0; /* conventional PCI mode */
3504 return 1; /* chip is in PCI-X mode */
3505 }
3506
3507 static int mv_pci_cut_through_okay(struct ata_host *host)
3508 {
3509 struct mv_host_priv *hpriv = host->private_data;
3510 void __iomem *mmio = hpriv->base;
3511 u32 reg;
3512
3513 if (!mv_in_pcix_mode(host)) {
3514 reg = readl(mmio + PCI_COMMAND_OFS);
3515 if (reg & PCI_COMMAND_MRDTRIG)
3516 return 0; /* not okay */
3517 }
3518 return 1; /* okay */
3519 }
3520
3521 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
3522 {
3523 struct pci_dev *pdev = to_pci_dev(host->dev);
3524 struct mv_host_priv *hpriv = host->private_data;
3525 u32 hp_flags = hpriv->hp_flags;
3526
3527 switch (board_idx) {
3528 case chip_5080:
3529 hpriv->ops = &mv5xxx_ops;
3530 hp_flags |= MV_HP_GEN_I;
3531
3532 switch (pdev->revision) {
3533 case 0x1:
3534 hp_flags |= MV_HP_ERRATA_50XXB0;
3535 break;
3536 case 0x3:
3537 hp_flags |= MV_HP_ERRATA_50XXB2;
3538 break;
3539 default:
3540 dev_printk(KERN_WARNING, &pdev->dev,
3541 "Applying 50XXB2 workarounds to unknown rev\n");
3542 hp_flags |= MV_HP_ERRATA_50XXB2;
3543 break;
3544 }
3545 break;
3546
3547 case chip_504x:
3548 case chip_508x:
3549 hpriv->ops = &mv5xxx_ops;
3550 hp_flags |= MV_HP_GEN_I;
3551
3552 switch (pdev->revision) {
3553 case 0x0:
3554 hp_flags |= MV_HP_ERRATA_50XXB0;
3555 break;
3556 case 0x3:
3557 hp_flags |= MV_HP_ERRATA_50XXB2;
3558 break;
3559 default:
3560 dev_printk(KERN_WARNING, &pdev->dev,
3561 "Applying B2 workarounds to unknown rev\n");
3562 hp_flags |= MV_HP_ERRATA_50XXB2;
3563 break;
3564 }
3565 break;
3566
3567 case chip_604x:
3568 case chip_608x:
3569 hpriv->ops = &mv6xxx_ops;
3570 hp_flags |= MV_HP_GEN_II;
3571
3572 switch (pdev->revision) {
3573 case 0x7:
3574 hp_flags |= MV_HP_ERRATA_60X1B2;
3575 break;
3576 case 0x9:
3577 hp_flags |= MV_HP_ERRATA_60X1C0;
3578 break;
3579 default:
3580 dev_printk(KERN_WARNING, &pdev->dev,
3581 "Applying B2 workarounds to unknown rev\n");
3582 hp_flags |= MV_HP_ERRATA_60X1B2;
3583 break;
3584 }
3585 break;
3586
3587 case chip_7042:
3588 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
3589 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3590 (pdev->device == 0x2300 || pdev->device == 0x2310))
3591 {
3592 /*
3593 * Highpoint RocketRAID PCIe 23xx series cards:
3594 *
3595 * Unconfigured drives are treated as "Legacy"
3596 * by the BIOS, and it overwrites sector 8 with
3597 * a "Lgcy" metadata block prior to Linux boot.
3598 *
3599 * Configured drives (RAID or JBOD) leave sector 8
3600 * alone, but instead overwrite a high numbered
3601 * sector for the RAID metadata. This sector can
3602 * be determined exactly, by truncating the physical
3603 * drive capacity to a nice even GB value.
3604 *
3605 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3606 *
3607 * Warn the user, lest they think we're just buggy.
3608 */
3609 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3610 " BIOS CORRUPTS DATA on all attached drives,"
3611 " regardless of if/how they are configured."
3612 " BEWARE!\n");
3613 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3614 " use sectors 8-9 on \"Legacy\" drives,"
3615 " and avoid the final two gigabytes on"
3616 " all RocketRAID BIOS initialized drives.\n");
3617 }
3618 /* drop through */
3619 case chip_6042:
3620 hpriv->ops = &mv6xxx_ops;
3621 hp_flags |= MV_HP_GEN_IIE;
3622 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3623 hp_flags |= MV_HP_CUT_THROUGH;
3624
3625 switch (pdev->revision) {
3626 case 0x2: /* Rev.B0: the first/only public release */
3627 hp_flags |= MV_HP_ERRATA_60X1C0;
3628 break;
3629 default:
3630 dev_printk(KERN_WARNING, &pdev->dev,
3631 "Applying 60X1C0 workarounds to unknown rev\n");
3632 hp_flags |= MV_HP_ERRATA_60X1C0;
3633 break;
3634 }
3635 break;
3636 case chip_soc:
3637 hpriv->ops = &mv_soc_ops;
3638 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3639 MV_HP_ERRATA_60X1C0;
3640 break;
3641
3642 default:
3643 dev_printk(KERN_ERR, host->dev,
3644 "BUG: invalid board index %u\n", board_idx);
3645 return 1;
3646 }
3647
3648 hpriv->hp_flags = hp_flags;
3649 if (hp_flags & MV_HP_PCIE) {
3650 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3651 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3652 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3653 } else {
3654 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3655 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3656 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3657 }
3658
3659 return 0;
3660 }
3661
3662 /**
3663 * mv_init_host - Perform some early initialization of the host.
3664 * @host: ATA host to initialize
3665 * @board_idx: controller index
3666 *
3667 * If possible, do an early global reset of the host. Then do
3668 * our port init and clear/unmask all/relevant host interrupts.
3669 *
3670 * LOCKING:
3671 * Inherited from caller.
3672 */
3673 static int mv_init_host(struct ata_host *host, unsigned int board_idx)
3674 {
3675 int rc = 0, n_hc, port, hc;
3676 struct mv_host_priv *hpriv = host->private_data;
3677 void __iomem *mmio = hpriv->base;
3678
3679 rc = mv_chip_id(host, board_idx);
3680 if (rc)
3681 goto done;
3682
3683 if (IS_SOC(hpriv)) {
3684 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3685 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
3686 } else {
3687 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3688 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
3689 }
3690
3691 /* initialize shadow irq mask with register's value */
3692 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3693
3694 /* global interrupt mask: 0 == mask everything */
3695 mv_set_main_irq_mask(host, ~0, 0);
3696
3697 n_hc = mv_get_hc_count(host->ports[0]->flags);
3698
3699 for (port = 0; port < host->n_ports; port++)
3700 hpriv->ops->read_preamp(hpriv, port, mmio);
3701
3702 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3703 if (rc)
3704 goto done;
3705
3706 hpriv->ops->reset_flash(hpriv, mmio);
3707 hpriv->ops->reset_bus(host, mmio);
3708 hpriv->ops->enable_leds(hpriv, mmio);
3709
3710 for (port = 0; port < host->n_ports; port++) {
3711 struct ata_port *ap = host->ports[port];
3712 void __iomem *port_mmio = mv_port_base(mmio, port);
3713
3714 mv_port_init(&ap->ioaddr, port_mmio);
3715
3716 #ifdef CONFIG_PCI
3717 if (!IS_SOC(hpriv)) {
3718 unsigned int offset = port_mmio - mmio;
3719 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3720 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3721 }
3722 #endif
3723 }
3724
3725 for (hc = 0; hc < n_hc; hc++) {
3726 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3727
3728 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3729 "(before clear)=0x%08x\n", hc,
3730 readl(hc_mmio + HC_CFG_OFS),
3731 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3732
3733 /* Clear any currently outstanding hc interrupt conditions */
3734 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
3735 }
3736
3737 /* Clear any currently outstanding host interrupt conditions */
3738 writelfl(0, mmio + hpriv->irq_cause_ofs);
3739
3740 /* and unmask interrupt generation for host regs */
3741 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
3742
3743 /*
3744 * enable only global host interrupts for now.
3745 * The per-port interrupts get done later as ports are set up.
3746 */
3747 mv_set_main_irq_mask(host, 0, PCI_ERR);
3748 mv_set_irq_coalescing(host, irq_coalescing_io_count,
3749 irq_coalescing_usecs);
3750 done:
3751 return rc;
3752 }
3753
3754 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3755 {
3756 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3757 MV_CRQB_Q_SZ, 0);
3758 if (!hpriv->crqb_pool)
3759 return -ENOMEM;
3760
3761 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3762 MV_CRPB_Q_SZ, 0);
3763 if (!hpriv->crpb_pool)
3764 return -ENOMEM;
3765
3766 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3767 MV_SG_TBL_SZ, 0);
3768 if (!hpriv->sg_tbl_pool)
3769 return -ENOMEM;
3770
3771 return 0;
3772 }
3773
3774 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3775 struct mbus_dram_target_info *dram)
3776 {
3777 int i;
3778
3779 for (i = 0; i < 4; i++) {
3780 writel(0, hpriv->base + WINDOW_CTRL(i));
3781 writel(0, hpriv->base + WINDOW_BASE(i));
3782 }
3783
3784 for (i = 0; i < dram->num_cs; i++) {
3785 struct mbus_dram_window *cs = dram->cs + i;
3786
3787 writel(((cs->size - 1) & 0xffff0000) |
3788 (cs->mbus_attr << 8) |
3789 (dram->mbus_dram_target_id << 4) | 1,
3790 hpriv->base + WINDOW_CTRL(i));
3791 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3792 }
3793 }
3794
3795 /**
3796 * mv_platform_probe - handle a positive probe of an soc Marvell
3797 * host
3798 * @pdev: platform device found
3799 *
3800 * LOCKING:
3801 * Inherited from caller.
3802 */
3803 static int mv_platform_probe(struct platform_device *pdev)
3804 {
3805 static int printed_version;
3806 const struct mv_sata_platform_data *mv_platform_data;
3807 const struct ata_port_info *ppi[] =
3808 { &mv_port_info[chip_soc], NULL };
3809 struct ata_host *host;
3810 struct mv_host_priv *hpriv;
3811 struct resource *res;
3812 int n_ports, rc;
3813
3814 if (!printed_version++)
3815 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3816
3817 /*
3818 * Simple resource validation ..
3819 */
3820 if (unlikely(pdev->num_resources != 2)) {
3821 dev_err(&pdev->dev, "invalid number of resources\n");
3822 return -EINVAL;
3823 }
3824
3825 /*
3826 * Get the register base first
3827 */
3828 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3829 if (res == NULL)
3830 return -EINVAL;
3831
3832 /* allocate host */
3833 mv_platform_data = pdev->dev.platform_data;
3834 n_ports = mv_platform_data->n_ports;
3835
3836 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3837 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3838
3839 if (!host || !hpriv)
3840 return -ENOMEM;
3841 host->private_data = hpriv;
3842 hpriv->n_ports = n_ports;
3843
3844 host->iomap = NULL;
3845 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3846 res->end - res->start + 1);
3847 hpriv->base -= MV_SATAHC0_REG_BASE;
3848
3849 /*
3850 * (Re-)program MBUS remapping windows if we are asked to.
3851 */
3852 if (mv_platform_data->dram != NULL)
3853 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3854
3855 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3856 if (rc)
3857 return rc;
3858
3859 /* initialize adapter */
3860 rc = mv_init_host(host, chip_soc);
3861 if (rc)
3862 return rc;
3863
3864 dev_printk(KERN_INFO, &pdev->dev,
3865 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3866 host->n_ports);
3867
3868 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3869 IRQF_SHARED, &mv6_sht);
3870 }
3871
3872 /*
3873 *
3874 * mv_platform_remove - unplug a platform interface
3875 * @pdev: platform device
3876 *
3877 * A platform bus SATA device has been unplugged. Perform the needed
3878 * cleanup. Also called on module unload for any active devices.
3879 */
3880 static int __devexit mv_platform_remove(struct platform_device *pdev)
3881 {
3882 struct device *dev = &pdev->dev;
3883 struct ata_host *host = dev_get_drvdata(dev);
3884
3885 ata_host_detach(host);
3886 return 0;
3887 }
3888
3889 static struct platform_driver mv_platform_driver = {
3890 .probe = mv_platform_probe,
3891 .remove = __devexit_p(mv_platform_remove),
3892 .driver = {
3893 .name = DRV_NAME,
3894 .owner = THIS_MODULE,
3895 },
3896 };
3897
3898
3899 #ifdef CONFIG_PCI
3900 static int mv_pci_init_one(struct pci_dev *pdev,
3901 const struct pci_device_id *ent);
3902
3903
3904 static struct pci_driver mv_pci_driver = {
3905 .name = DRV_NAME,
3906 .id_table = mv_pci_tbl,
3907 .probe = mv_pci_init_one,
3908 .remove = ata_pci_remove_one,
3909 };
3910
3911 /* move to PCI layer or libata core? */
3912 static int pci_go_64(struct pci_dev *pdev)
3913 {
3914 int rc;
3915
3916 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3917 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3918 if (rc) {
3919 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3920 if (rc) {
3921 dev_printk(KERN_ERR, &pdev->dev,
3922 "64-bit DMA enable failed\n");
3923 return rc;
3924 }
3925 }
3926 } else {
3927 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3928 if (rc) {
3929 dev_printk(KERN_ERR, &pdev->dev,
3930 "32-bit DMA enable failed\n");
3931 return rc;
3932 }
3933 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3934 if (rc) {
3935 dev_printk(KERN_ERR, &pdev->dev,
3936 "32-bit consistent DMA enable failed\n");
3937 return rc;
3938 }
3939 }
3940
3941 return rc;
3942 }
3943
3944 /**
3945 * mv_print_info - Dump key info to kernel log for perusal.
3946 * @host: ATA host to print info about
3947 *
3948 * FIXME: complete this.
3949 *
3950 * LOCKING:
3951 * Inherited from caller.
3952 */
3953 static void mv_print_info(struct ata_host *host)
3954 {
3955 struct pci_dev *pdev = to_pci_dev(host->dev);
3956 struct mv_host_priv *hpriv = host->private_data;
3957 u8 scc;
3958 const char *scc_s, *gen;
3959
3960 /* Use this to determine the HW stepping of the chip so we know
3961 * what errata to workaround
3962 */
3963 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3964 if (scc == 0)
3965 scc_s = "SCSI";
3966 else if (scc == 0x01)
3967 scc_s = "RAID";
3968 else
3969 scc_s = "?";
3970
3971 if (IS_GEN_I(hpriv))
3972 gen = "I";
3973 else if (IS_GEN_II(hpriv))
3974 gen = "II";
3975 else if (IS_GEN_IIE(hpriv))
3976 gen = "IIE";
3977 else
3978 gen = "?";
3979
3980 dev_printk(KERN_INFO, &pdev->dev,
3981 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3982 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
3983 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3984 }
3985
3986 /**
3987 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
3988 * @pdev: PCI device found
3989 * @ent: PCI device ID entry for the matched host
3990 *
3991 * LOCKING:
3992 * Inherited from caller.
3993 */
3994 static int mv_pci_init_one(struct pci_dev *pdev,
3995 const struct pci_device_id *ent)
3996 {
3997 static int printed_version;
3998 unsigned int board_idx = (unsigned int)ent->driver_data;
3999 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
4000 struct ata_host *host;
4001 struct mv_host_priv *hpriv;
4002 int n_ports, rc;
4003
4004 if (!printed_version++)
4005 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
4006
4007 /* allocate host */
4008 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
4009
4010 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4011 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4012 if (!host || !hpriv)
4013 return -ENOMEM;
4014 host->private_data = hpriv;
4015 hpriv->n_ports = n_ports;
4016
4017 /* acquire resources */
4018 rc = pcim_enable_device(pdev);
4019 if (rc)
4020 return rc;
4021
4022 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
4023 if (rc == -EBUSY)
4024 pcim_pin_device(pdev);
4025 if (rc)
4026 return rc;
4027 host->iomap = pcim_iomap_table(pdev);
4028 hpriv->base = host->iomap[MV_PRIMARY_BAR];
4029
4030 rc = pci_go_64(pdev);
4031 if (rc)
4032 return rc;
4033
4034 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4035 if (rc)
4036 return rc;
4037
4038 /* initialize adapter */
4039 rc = mv_init_host(host, board_idx);
4040 if (rc)
4041 return rc;
4042
4043 /* Enable message-switched interrupts, if requested */
4044 if (msi && pci_enable_msi(pdev) == 0)
4045 hpriv->hp_flags |= MV_HP_FLAG_MSI;
4046
4047 mv_dump_pci_cfg(pdev, 0x68);
4048 mv_print_info(host);
4049
4050 pci_set_master(pdev);
4051 pci_try_set_mwi(pdev);
4052 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
4053 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
4054 }
4055 #endif
4056
4057 static int mv_platform_probe(struct platform_device *pdev);
4058 static int __devexit mv_platform_remove(struct platform_device *pdev);
4059
4060 static int __init mv_init(void)
4061 {
4062 int rc = -ENODEV;
4063 #ifdef CONFIG_PCI
4064 rc = pci_register_driver(&mv_pci_driver);
4065 if (rc < 0)
4066 return rc;
4067 #endif
4068 rc = platform_driver_register(&mv_platform_driver);
4069
4070 #ifdef CONFIG_PCI
4071 if (rc < 0)
4072 pci_unregister_driver(&mv_pci_driver);
4073 #endif
4074 return rc;
4075 }
4076
4077 static void __exit mv_exit(void)
4078 {
4079 #ifdef CONFIG_PCI
4080 pci_unregister_driver(&mv_pci_driver);
4081 #endif
4082 platform_driver_unregister(&mv_platform_driver);
4083 }
4084
4085 MODULE_AUTHOR("Brett Russ");
4086 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4087 MODULE_LICENSE("GPL");
4088 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
4089 MODULE_VERSION(DRV_VERSION);
4090 MODULE_ALIAS("platform:" DRV_NAME);
4091
4092 module_init(mv_init);
4093 module_exit(mv_exit);
x86 "subsystem" repository