2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/bootmem.h>
15 #include <linux/mman.h>
16 #include <linux/nodemask.h>
18 #include <asm/cputype.h>
19 #include <asm/mach-types.h>
20 #include <asm/setup.h>
21 #include <asm/sizes.h>
24 #include <asm/mach/arch.h>
25 #include <asm/mach/map.h>
29 DEFINE_PER_CPU(struct mmu_gather
, mmu_gathers
);
32 * empty_zero_page is a special page that is used for
33 * zero-initialized data and COW.
35 struct page
*empty_zero_page
;
36 EXPORT_SYMBOL(empty_zero_page
);
39 * The pmd table for the upper-most set of pages.
43 #define CPOLICY_UNCACHED 0
44 #define CPOLICY_BUFFERED 1
45 #define CPOLICY_WRITETHROUGH 2
46 #define CPOLICY_WRITEBACK 3
47 #define CPOLICY_WRITEALLOC 4
49 static unsigned int cachepolicy __initdata
= CPOLICY_WRITEBACK
;
50 static unsigned int ecc_mask __initdata
= 0;
52 pgprot_t pgprot_kernel
;
54 EXPORT_SYMBOL(pgprot_user
);
55 EXPORT_SYMBOL(pgprot_kernel
);
58 const char policy
[16];
64 static struct cachepolicy cache_policies
[] __initdata
= {
68 .pmd
= PMD_SECT_UNCACHED
,
73 .pmd
= PMD_SECT_BUFFERED
,
74 .pte
= PTE_BUFFERABLE
,
76 .policy
= "writethrough",
81 .policy
= "writeback",
84 .pte
= PTE_BUFFERABLE
|PTE_CACHEABLE
,
86 .policy
= "writealloc",
89 .pte
= PTE_BUFFERABLE
|PTE_CACHEABLE
,
94 * These are useful for identifying cache coherency
95 * problems by allowing the cache or the cache and
96 * writebuffer to be turned off. (Note: the write
97 * buffer should not be on and the cache off).
99 static void __init
early_cachepolicy(char **p
)
103 for (i
= 0; i
< ARRAY_SIZE(cache_policies
); i
++) {
104 int len
= strlen(cache_policies
[i
].policy
);
106 if (memcmp(*p
, cache_policies
[i
].policy
, len
) == 0) {
108 cr_alignment
&= ~cache_policies
[i
].cr_mask
;
109 cr_no_alignment
&= ~cache_policies
[i
].cr_mask
;
114 if (i
== ARRAY_SIZE(cache_policies
))
115 printk(KERN_ERR
"ERROR: unknown or unsupported cache policy\n");
116 if (cpu_architecture() >= CPU_ARCH_ARMv6
) {
117 printk(KERN_WARNING
"Only cachepolicy=writeback supported on ARMv6 and later\n");
118 cachepolicy
= CPOLICY_WRITEBACK
;
121 set_cr(cr_alignment
);
123 __early_param("cachepolicy=", early_cachepolicy
);
125 static void __init
early_nocache(char **__unused
)
127 char *p
= "buffered";
128 printk(KERN_WARNING
"nocache is deprecated; use cachepolicy=%s\n", p
);
129 early_cachepolicy(&p
);
131 __early_param("nocache", early_nocache
);
133 static void __init
early_nowrite(char **__unused
)
135 char *p
= "uncached";
136 printk(KERN_WARNING
"nowb is deprecated; use cachepolicy=%s\n", p
);
137 early_cachepolicy(&p
);
139 __early_param("nowb", early_nowrite
);
141 static void __init
early_ecc(char **p
)
143 if (memcmp(*p
, "on", 2) == 0) {
144 ecc_mask
= PMD_PROTECTION
;
146 } else if (memcmp(*p
, "off", 3) == 0) {
151 __early_param("ecc=", early_ecc
);
153 static int __init
noalign_setup(char *__unused
)
155 cr_alignment
&= ~CR_A
;
156 cr_no_alignment
&= ~CR_A
;
157 set_cr(cr_alignment
);
160 __setup("noalign", noalign_setup
);
163 void adjust_cr(unsigned long mask
, unsigned long set
)
171 local_irq_save(flags
);
173 cr_no_alignment
= (cr_no_alignment
& ~mask
) | set
;
174 cr_alignment
= (cr_alignment
& ~mask
) | set
;
176 set_cr((get_cr() & ~mask
) | set
);
178 local_irq_restore(flags
);
182 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE
183 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_XN|PMD_SECT_AP_WRITE
185 static struct mem_type mem_types
[] = {
186 [MT_DEVICE
] = { /* Strongly ordered / ARMv6 shared device */
187 .prot_pte
= PROT_PTE_DEVICE
,
188 .prot_l1
= PMD_TYPE_TABLE
,
189 .prot_sect
= PROT_SECT_DEVICE
| PMD_SECT_UNCACHED
,
192 [MT_DEVICE_NONSHARED
] = { /* ARMv6 non-shared device */
193 .prot_pte
= PROT_PTE_DEVICE
,
194 .prot_pte_ext
= PTE_EXT_TEX(2),
195 .prot_l1
= PMD_TYPE_TABLE
,
196 .prot_sect
= PROT_SECT_DEVICE
| PMD_SECT_TEX(2),
199 [MT_DEVICE_CACHED
] = { /* ioremap_cached */
200 .prot_pte
= PROT_PTE_DEVICE
| L_PTE_CACHEABLE
| L_PTE_BUFFERABLE
,
201 .prot_l1
= PMD_TYPE_TABLE
,
202 .prot_sect
= PROT_SECT_DEVICE
| PMD_SECT_WB
,
205 [MT_DEVICE_IXP2000
] = { /* IXP2400 requires XCB=101 for on-chip I/O */
206 .prot_pte
= PROT_PTE_DEVICE
,
207 .prot_l1
= PMD_TYPE_TABLE
,
208 .prot_sect
= PROT_SECT_DEVICE
| PMD_SECT_BUFFERABLE
|
213 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_XN
,
214 .domain
= DOMAIN_KERNEL
,
217 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_XN
| PMD_SECT_MINICACHE
,
218 .domain
= DOMAIN_KERNEL
,
221 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
223 .prot_l1
= PMD_TYPE_TABLE
,
224 .domain
= DOMAIN_USER
,
226 [MT_HIGH_VECTORS
] = {
227 .prot_pte
= L_PTE_PRESENT
| L_PTE_YOUNG
| L_PTE_DIRTY
|
228 L_PTE_USER
| L_PTE_EXEC
,
229 .prot_l1
= PMD_TYPE_TABLE
,
230 .domain
= DOMAIN_USER
,
233 .prot_sect
= PMD_TYPE_SECT
| PMD_SECT_AP_WRITE
,
234 .domain
= DOMAIN_KERNEL
,
237 .prot_sect
= PMD_TYPE_SECT
,
238 .domain
= DOMAIN_KERNEL
,
242 const struct mem_type
*get_mem_type(unsigned int type
)
244 return type
< ARRAY_SIZE(mem_types
) ? &mem_types
[type
] : NULL
;
248 * Adjust the PMD section entries according to the CPU in use.
250 static void __init
build_mem_type_table(void)
252 struct cachepolicy
*cp
;
253 unsigned int cr
= get_cr();
254 unsigned int user_pgprot
, kern_pgprot
;
255 int cpu_arch
= cpu_architecture();
258 if (cpu_arch
< CPU_ARCH_ARMv6
) {
259 #if defined(CONFIG_CPU_DCACHE_DISABLE)
260 if (cachepolicy
> CPOLICY_BUFFERED
)
261 cachepolicy
= CPOLICY_BUFFERED
;
262 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
263 if (cachepolicy
> CPOLICY_WRITETHROUGH
)
264 cachepolicy
= CPOLICY_WRITETHROUGH
;
267 if (cpu_arch
< CPU_ARCH_ARMv5
) {
268 if (cachepolicy
>= CPOLICY_WRITEALLOC
)
269 cachepolicy
= CPOLICY_WRITEBACK
;
274 * ARMv5 and lower, bit 4 must be set for page tables.
275 * (was: cache "update-able on write" bit on ARM610)
276 * However, Xscale cores require this bit to be cleared.
278 if (cpu_is_xscale()) {
279 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++) {
280 mem_types
[i
].prot_sect
&= ~PMD_BIT4
;
281 mem_types
[i
].prot_l1
&= ~PMD_BIT4
;
283 } else if (cpu_arch
< CPU_ARCH_ARMv6
) {
284 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++) {
285 if (mem_types
[i
].prot_l1
)
286 mem_types
[i
].prot_l1
|= PMD_BIT4
;
287 if (mem_types
[i
].prot_sect
)
288 mem_types
[i
].prot_sect
|= PMD_BIT4
;
292 cp
= &cache_policies
[cachepolicy
];
293 kern_pgprot
= user_pgprot
= cp
->pte
;
296 * Enable CPU-specific coherency if supported.
297 * (Only available on XSC3 at the moment.)
299 if (arch_is_coherent()) {
301 mem_types
[MT_MEMORY
].prot_sect
|= PMD_SECT_S
;
302 mem_types
[MT_MEMORY
].prot_pte
|= L_PTE_SHARED
;
307 * ARMv6 and above have extended page tables.
309 if (cpu_arch
>= CPU_ARCH_ARMv6
&& (cr
& CR_XP
)) {
311 * Mark cache clean areas and XIP ROM read only
312 * from SVC mode and no access from userspace.
314 mem_types
[MT_ROM
].prot_sect
|= PMD_SECT_APX
|PMD_SECT_AP_WRITE
;
315 mem_types
[MT_MINICLEAN
].prot_sect
|= PMD_SECT_APX
|PMD_SECT_AP_WRITE
;
316 mem_types
[MT_CACHECLEAN
].prot_sect
|= PMD_SECT_APX
|PMD_SECT_AP_WRITE
;
319 * Mark the device area as "shared device"
321 mem_types
[MT_DEVICE
].prot_pte
|= L_PTE_BUFFERABLE
;
322 mem_types
[MT_DEVICE
].prot_sect
|= PMD_SECT_BUFFERED
;
326 * Mark memory with the "shared" attribute for SMP systems
328 user_pgprot
|= L_PTE_SHARED
;
329 kern_pgprot
|= L_PTE_SHARED
;
330 mem_types
[MT_MEMORY
].prot_sect
|= PMD_SECT_S
;
334 for (i
= 0; i
< 16; i
++) {
335 unsigned long v
= pgprot_val(protection_map
[i
]);
336 v
= (v
& ~(L_PTE_BUFFERABLE
|L_PTE_CACHEABLE
)) | user_pgprot
;
337 protection_map
[i
] = __pgprot(v
);
340 mem_types
[MT_LOW_VECTORS
].prot_pte
|= kern_pgprot
;
341 mem_types
[MT_HIGH_VECTORS
].prot_pte
|= kern_pgprot
;
343 if (cpu_arch
>= CPU_ARCH_ARMv5
) {
346 * Only use write-through for non-SMP systems
348 mem_types
[MT_LOW_VECTORS
].prot_pte
&= ~L_PTE_BUFFERABLE
;
349 mem_types
[MT_HIGH_VECTORS
].prot_pte
&= ~L_PTE_BUFFERABLE
;
352 mem_types
[MT_MINICLEAN
].prot_sect
&= ~PMD_SECT_TEX(1);
355 pgprot_user
= __pgprot(L_PTE_PRESENT
| L_PTE_YOUNG
| user_pgprot
);
356 pgprot_kernel
= __pgprot(L_PTE_PRESENT
| L_PTE_YOUNG
|
357 L_PTE_DIRTY
| L_PTE_WRITE
|
358 L_PTE_EXEC
| kern_pgprot
);
360 mem_types
[MT_LOW_VECTORS
].prot_l1
|= ecc_mask
;
361 mem_types
[MT_HIGH_VECTORS
].prot_l1
|= ecc_mask
;
362 mem_types
[MT_MEMORY
].prot_sect
|= ecc_mask
| cp
->pmd
;
363 mem_types
[MT_ROM
].prot_sect
|= cp
->pmd
;
367 mem_types
[MT_CACHECLEAN
].prot_sect
|= PMD_SECT_WT
;
371 mem_types
[MT_CACHECLEAN
].prot_sect
|= PMD_SECT_WB
;
374 printk("Memory policy: ECC %sabled, Data cache %s\n",
375 ecc_mask
? "en" : "dis", cp
->policy
);
377 for (i
= 0; i
< ARRAY_SIZE(mem_types
); i
++) {
378 struct mem_type
*t
= &mem_types
[i
];
380 t
->prot_l1
|= PMD_DOMAIN(t
->domain
);
382 t
->prot_sect
|= PMD_DOMAIN(t
->domain
);
386 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
388 static void __init
alloc_init_pte(pmd_t
*pmd
, unsigned long addr
,
389 unsigned long end
, unsigned long pfn
,
390 const struct mem_type
*type
)
394 if (pmd_none(*pmd
)) {
395 pte
= alloc_bootmem_low_pages(2 * PTRS_PER_PTE
* sizeof(pte_t
));
396 __pmd_populate(pmd
, __pa(pte
) | type
->prot_l1
);
399 pte
= pte_offset_kernel(pmd
, addr
);
401 set_pte_ext(pte
, pfn_pte(pfn
, __pgprot(type
->prot_pte
)),
404 } while (pte
++, addr
+= PAGE_SIZE
, addr
!= end
);
407 static void __init
alloc_init_section(pgd_t
*pgd
, unsigned long addr
,
408 unsigned long end
, unsigned long phys
,
409 const struct mem_type
*type
)
411 pmd_t
*pmd
= pmd_offset(pgd
, addr
);
414 * Try a section mapping - end, addr and phys must all be aligned
415 * to a section boundary. Note that PMDs refer to the individual
416 * L1 entries, whereas PGDs refer to a group of L1 entries making
417 * up one logical pointer to an L2 table.
419 if (((addr
| end
| phys
) & ~SECTION_MASK
) == 0) {
422 if (addr
& SECTION_SIZE
)
426 *pmd
= __pmd(phys
| type
->prot_sect
);
427 phys
+= SECTION_SIZE
;
428 } while (pmd
++, addr
+= SECTION_SIZE
, addr
!= end
);
433 * No need to loop; pte's aren't interested in the
434 * individual L1 entries.
436 alloc_init_pte(pmd
, addr
, end
, __phys_to_pfn(phys
), type
);
440 static void __init
create_36bit_mapping(struct map_desc
*md
,
441 const struct mem_type
*type
)
443 unsigned long phys
, addr
, length
, end
;
447 phys
= (unsigned long)__pfn_to_phys(md
->pfn
);
448 length
= PAGE_ALIGN(md
->length
);
450 if (!(cpu_architecture() >= CPU_ARCH_ARMv6
|| cpu_is_xsc3())) {
451 printk(KERN_ERR
"MM: CPU does not support supersection "
452 "mapping for 0x%08llx at 0x%08lx\n",
453 __pfn_to_phys((u64
)md
->pfn
), addr
);
457 /* N.B. ARMv6 supersections are only defined to work with domain 0.
458 * Since domain assignments can in fact be arbitrary, the
459 * 'domain == 0' check below is required to insure that ARMv6
460 * supersections are only allocated for domain 0 regardless
461 * of the actual domain assignments in use.
464 printk(KERN_ERR
"MM: invalid domain in supersection "
465 "mapping for 0x%08llx at 0x%08lx\n",
466 __pfn_to_phys((u64
)md
->pfn
), addr
);
470 if ((addr
| length
| __pfn_to_phys(md
->pfn
)) & ~SUPERSECTION_MASK
) {
471 printk(KERN_ERR
"MM: cannot create mapping for "
472 "0x%08llx at 0x%08lx invalid alignment\n",
473 __pfn_to_phys((u64
)md
->pfn
), addr
);
478 * Shift bits [35:32] of address into bits [23:20] of PMD
481 phys
|= (((md
->pfn
>> (32 - PAGE_SHIFT
)) & 0xF) << 20);
483 pgd
= pgd_offset_k(addr
);
486 pmd_t
*pmd
= pmd_offset(pgd
, addr
);
489 for (i
= 0; i
< 16; i
++)
490 *pmd
++ = __pmd(phys
| type
->prot_sect
| PMD_SECT_SUPER
);
492 addr
+= SUPERSECTION_SIZE
;
493 phys
+= SUPERSECTION_SIZE
;
494 pgd
+= SUPERSECTION_SIZE
>> PGDIR_SHIFT
;
495 } while (addr
!= end
);
499 * Create the page directory entries and any necessary
500 * page tables for the mapping specified by `md'. We
501 * are able to cope here with varying sizes and address
502 * offsets, and we take full advantage of sections and
505 void __init
create_mapping(struct map_desc
*md
)
507 unsigned long phys
, addr
, length
, end
;
508 const struct mem_type
*type
;
511 if (md
->virtual != vectors_base() && md
->virtual < TASK_SIZE
) {
512 printk(KERN_WARNING
"BUG: not creating mapping for "
513 "0x%08llx at 0x%08lx in user region\n",
514 __pfn_to_phys((u64
)md
->pfn
), md
->virtual);
518 if ((md
->type
== MT_DEVICE
|| md
->type
== MT_ROM
) &&
519 md
->virtual >= PAGE_OFFSET
&& md
->virtual < VMALLOC_END
) {
520 printk(KERN_WARNING
"BUG: mapping for 0x%08llx at 0x%08lx "
521 "overlaps vmalloc space\n",
522 __pfn_to_phys((u64
)md
->pfn
), md
->virtual);
525 type
= &mem_types
[md
->type
];
528 * Catch 36-bit addresses
530 if (md
->pfn
>= 0x100000) {
531 create_36bit_mapping(md
, type
);
535 addr
= md
->virtual & PAGE_MASK
;
536 phys
= (unsigned long)__pfn_to_phys(md
->pfn
);
537 length
= PAGE_ALIGN(md
->length
+ (md
->virtual & ~PAGE_MASK
));
539 if (type
->prot_l1
== 0 && ((addr
| phys
| length
) & ~SECTION_MASK
)) {
540 printk(KERN_WARNING
"BUG: map for 0x%08lx at 0x%08lx can not "
541 "be mapped using pages, ignoring.\n",
542 __pfn_to_phys(md
->pfn
), addr
);
546 pgd
= pgd_offset_k(addr
);
549 unsigned long next
= pgd_addr_end(addr
, end
);
551 alloc_init_section(pgd
, addr
, next
, phys
, type
);
555 } while (pgd
++, addr
!= end
);
559 * Create the architecture specific mappings
561 void __init
iotable_init(struct map_desc
*io_desc
, int nr
)
565 for (i
= 0; i
< nr
; i
++)
566 create_mapping(io_desc
+ i
);
569 static unsigned long __initdata vmalloc_reserve
= SZ_128M
;
572 * vmalloc=size forces the vmalloc area to be exactly 'size'
573 * bytes. This can be used to increase (or decrease) the vmalloc
574 * area - the default is 128m.
576 static void __init
early_vmalloc(char **arg
)
578 vmalloc_reserve
= memparse(*arg
, arg
);
580 if (vmalloc_reserve
< SZ_16M
) {
581 vmalloc_reserve
= SZ_16M
;
583 "vmalloc area too small, limiting to %luMB\n",
584 vmalloc_reserve
>> 20);
587 __early_param("vmalloc=", early_vmalloc
);
589 #define VMALLOC_MIN (void *)(VMALLOC_END - vmalloc_reserve)
591 static int __init
check_membank_valid(struct membank
*mb
)
594 * Check whether this memory region has non-zero size or
595 * invalid node number.
597 if (mb
->size
== 0 || mb
->node
>= MAX_NUMNODES
)
601 * Check whether this memory region would entirely overlap
604 if (phys_to_virt(mb
->start
) >= VMALLOC_MIN
) {
605 printk(KERN_NOTICE
"Ignoring RAM at %.8lx-%.8lx "
606 "(vmalloc region overlap).\n",
607 mb
->start
, mb
->start
+ mb
->size
- 1);
612 * Check whether this memory region would partially overlap
615 if (phys_to_virt(mb
->start
+ mb
->size
) < phys_to_virt(mb
->start
) ||
616 phys_to_virt(mb
->start
+ mb
->size
) > VMALLOC_MIN
) {
617 unsigned long newsize
= VMALLOC_MIN
- phys_to_virt(mb
->start
);
619 printk(KERN_NOTICE
"Truncating RAM at %.8lx-%.8lx "
620 "to -%.8lx (vmalloc region overlap).\n",
621 mb
->start
, mb
->start
+ mb
->size
- 1,
622 mb
->start
+ newsize
- 1);
629 static void __init
sanity_check_meminfo(struct meminfo
*mi
)
633 for (i
= 0, j
= 0; i
< mi
->nr_banks
; i
++) {
634 if (check_membank_valid(&mi
->bank
[i
]))
635 mi
->bank
[j
++] = mi
->bank
[i
];
640 static inline void prepare_page_table(struct meminfo
*mi
)
645 * Clear out all the mappings below the kernel image.
647 for (addr
= 0; addr
< MODULE_START
; addr
+= PGDIR_SIZE
)
648 pmd_clear(pmd_off_k(addr
));
650 #ifdef CONFIG_XIP_KERNEL
651 /* The XIP kernel is mapped in the module area -- skip over it */
652 addr
= ((unsigned long)&_etext
+ PGDIR_SIZE
- 1) & PGDIR_MASK
;
654 for ( ; addr
< PAGE_OFFSET
; addr
+= PGDIR_SIZE
)
655 pmd_clear(pmd_off_k(addr
));
658 * Clear out all the kernel space mappings, except for the first
659 * memory bank, up to the end of the vmalloc region.
661 for (addr
= __phys_to_virt(mi
->bank
[0].start
+ mi
->bank
[0].size
);
662 addr
< VMALLOC_END
; addr
+= PGDIR_SIZE
)
663 pmd_clear(pmd_off_k(addr
));
667 * Reserve the various regions of node 0
669 void __init
reserve_node_zero(pg_data_t
*pgdat
)
671 unsigned long res_size
= 0;
674 * Register the kernel text and data with bootmem.
675 * Note that this can only be in node 0.
677 #ifdef CONFIG_XIP_KERNEL
678 reserve_bootmem_node(pgdat
, __pa(&__data_start
), &_end
- &__data_start
,
681 reserve_bootmem_node(pgdat
, __pa(&_stext
), &_end
- &_stext
,
686 * Reserve the page tables. These are already in use,
687 * and can only be in node 0.
689 reserve_bootmem_node(pgdat
, __pa(swapper_pg_dir
),
690 PTRS_PER_PGD
* sizeof(pgd_t
), BOOTMEM_DEFAULT
);
693 * Hmm... This should go elsewhere, but we really really need to
694 * stop things allocating the low memory; ideally we need a better
695 * implementation of GFP_DMA which does not assume that DMA-able
696 * memory starts at zero.
698 if (machine_is_integrator() || machine_is_cintegrator())
699 res_size
= __pa(swapper_pg_dir
) - PHYS_OFFSET
;
702 * These should likewise go elsewhere. They pre-reserve the
703 * screen memory region at the start of main system memory.
705 if (machine_is_edb7211())
706 res_size
= 0x00020000;
707 if (machine_is_p720t())
708 res_size
= 0x00014000;
710 /* H1940 and RX3715 need to reserve this for suspend */
712 if (machine_is_h1940() || machine_is_rx3715()) {
713 reserve_bootmem_node(pgdat
, 0x30003000, 0x1000,
715 reserve_bootmem_node(pgdat
, 0x30081000, 0x1000,
721 * Because of the SA1111 DMA bug, we want to preserve our
722 * precious DMA-able memory...
724 res_size
= __pa(swapper_pg_dir
) - PHYS_OFFSET
;
727 reserve_bootmem_node(pgdat
, PHYS_OFFSET
, res_size
,
732 * Set up device the mappings. Since we clear out the page tables for all
733 * mappings above VMALLOC_END, we will remove any debug device mappings.
734 * This means you have to be careful how you debug this function, or any
735 * called function. This means you can't use any function or debugging
736 * method which may touch any device, otherwise the kernel _will_ crash.
738 static void __init
devicemaps_init(struct machine_desc
*mdesc
)
745 * Allocate the vector page early.
747 vectors
= alloc_bootmem_low_pages(PAGE_SIZE
);
750 for (addr
= VMALLOC_END
; addr
; addr
+= PGDIR_SIZE
)
751 pmd_clear(pmd_off_k(addr
));
754 * Map the kernel if it is XIP.
755 * It is always first in the modulearea.
757 #ifdef CONFIG_XIP_KERNEL
758 map
.pfn
= __phys_to_pfn(CONFIG_XIP_PHYS_ADDR
& SECTION_MASK
);
759 map
.virtual = MODULE_START
;
760 map
.length
= ((unsigned long)&_etext
- map
.virtual + ~SECTION_MASK
) & SECTION_MASK
;
762 create_mapping(&map
);
766 * Map the cache flushing regions.
769 map
.pfn
= __phys_to_pfn(FLUSH_BASE_PHYS
);
770 map
.virtual = FLUSH_BASE
;
772 map
.type
= MT_CACHECLEAN
;
773 create_mapping(&map
);
775 #ifdef FLUSH_BASE_MINICACHE
776 map
.pfn
= __phys_to_pfn(FLUSH_BASE_PHYS
+ SZ_1M
);
777 map
.virtual = FLUSH_BASE_MINICACHE
;
779 map
.type
= MT_MINICLEAN
;
780 create_mapping(&map
);
784 * Create a mapping for the machine vectors at the high-vectors
785 * location (0xffff0000). If we aren't using high-vectors, also
786 * create a mapping at the low-vectors virtual address.
788 map
.pfn
= __phys_to_pfn(virt_to_phys(vectors
));
789 map
.virtual = 0xffff0000;
790 map
.length
= PAGE_SIZE
;
791 map
.type
= MT_HIGH_VECTORS
;
792 create_mapping(&map
);
794 if (!vectors_high()) {
796 map
.type
= MT_LOW_VECTORS
;
797 create_mapping(&map
);
801 * Ask the machine support to map in the statically mapped devices.
807 * Finally flush the caches and tlb to ensure that we're in a
808 * consistent state wrt the writebuffer. This also ensures that
809 * any write-allocated cache lines in the vector page are written
810 * back. After this point, we can start to touch devices again.
812 local_flush_tlb_all();
817 * paging_init() sets up the page tables, initialises the zone memory
818 * maps, and sets up the zero page, bad page and bad page tables.
820 void __init
paging_init(struct meminfo
*mi
, struct machine_desc
*mdesc
)
824 build_mem_type_table();
825 sanity_check_meminfo(mi
);
826 prepare_page_table(mi
);
828 devicemaps_init(mdesc
);
830 top_pmd
= pmd_off_k(0xffff0000);
833 * allocate the zero page. Note that we count on this going ok.
835 zero_page
= alloc_bootmem_low_pages(PAGE_SIZE
);
836 memzero(zero_page
, PAGE_SIZE
);
837 empty_zero_page
= virt_to_page(zero_page
);
838 flush_dcache_page(empty_zero_page
);
842 * In order to soft-boot, we need to insert a 1:1 mapping in place of
843 * the user-mode pages. This will then ensure that we have predictable
844 * results when turning the mmu off
846 void setup_mm_for_reboot(char mode
)
848 unsigned long base_pmdval
;
852 if (current
->mm
&& current
->mm
->pgd
)
853 pgd
= current
->mm
->pgd
;
857 base_pmdval
= PMD_SECT_AP_WRITE
| PMD_SECT_AP_READ
| PMD_TYPE_SECT
;
858 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ
&& !cpu_is_xscale())
859 base_pmdval
|= PMD_BIT4
;
861 for (i
= 0; i
< FIRST_USER_PGD_NR
+ USER_PTRS_PER_PGD
; i
++, pgd
++) {
862 unsigned long pmdval
= (i
<< PGDIR_SHIFT
) | base_pmdval
;
865 pmd
= pmd_off(pgd
, i
<< PGDIR_SHIFT
);
866 pmd
[0] = __pmd(pmdval
);
867 pmd
[1] = __pmd(pmdval
+ (1 << (PGDIR_SHIFT
- 1)));
868 flush_pmd_entry(pmd
);