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libata: implement and use SHT initializers
[linux-2.6/x86.git] / drivers / ata / sata_sis.c
blob4becb7fde5e76b019f1866c9d8a46137bc7dd07d
1 /*
2 * sata_sis.c - Silicon Integrated Systems SATA
3 *
4 * Maintained by: Uwe Koziolek
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004 Uwe Koziolek
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware documentation available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/device.h>
41 #include <scsi/scsi_host.h>
42 #include <linux/libata.h>
43 #include "sis.h"
44
45 #define DRV_NAME "sata_sis"
46 #define DRV_VERSION "1.0"
47
48 enum {
49 sis_180 = 0,
50 SIS_SCR_PCI_BAR = 5,
51
52 /* PCI configuration registers */
53 SIS_GENCTL = 0x54, /* IDE General Control register */
54 SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
55 SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
56 SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
57 SIS_PMR = 0x90, /* port mapping register */
58 SIS_PMR_COMBINED = 0x30,
59
60 /* random bits */
61 SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
62
63 GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
64 };
65
66 static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
67 static int sis_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
68 static int sis_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
69
70 static const struct pci_device_id sis_pci_tbl[] = {
71 { PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */
72 { PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */
73 { PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */
74 { PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */
75 { PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/680 */
76 { PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L/968/680 */
77
78 { } /* terminate list */
79 };
80
81 static struct pci_driver sis_pci_driver = {
82 .name = DRV_NAME,
83 .id_table = sis_pci_tbl,
84 .probe = sis_init_one,
85 .remove = ata_pci_remove_one,
86 };
87
88 static struct scsi_host_template sis_sht = {
89 ATA_BMDMA_SHT(DRV_NAME),
90 };
91
92 static const struct ata_port_operations sis_ops = {
93 .tf_load = ata_tf_load,
94 .tf_read = ata_tf_read,
95 .check_status = ata_check_status,
96 .exec_command = ata_exec_command,
97 .dev_select = ata_std_dev_select,
98 .bmdma_setup = ata_bmdma_setup,
99 .bmdma_start = ata_bmdma_start,
100 .bmdma_stop = ata_bmdma_stop,
101 .bmdma_status = ata_bmdma_status,
102 .qc_prep = ata_qc_prep,
103 .qc_issue = ata_qc_issue_prot,
104 .data_xfer = ata_data_xfer,
105 .mode_filter = ata_pci_default_filter,
106 .freeze = ata_bmdma_freeze,
107 .thaw = ata_bmdma_thaw,
108 .error_handler = ata_bmdma_error_handler,
109 .post_internal_cmd = ata_bmdma_post_internal_cmd,
110 .irq_clear = ata_bmdma_irq_clear,
111 .irq_on = ata_irq_on,
112 .scr_read = sis_scr_read,
113 .scr_write = sis_scr_write,
114 .port_start = ata_sff_port_start,
115 };
116
117 static const struct ata_port_info sis_port_info = {
118 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
119 .pio_mask = 0x1f,
120 .mwdma_mask = 0x7,
121 .udma_mask = ATA_UDMA6,
122 .port_ops = &sis_ops,
123 };
124
125 MODULE_AUTHOR("Uwe Koziolek");
126 MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
127 MODULE_LICENSE("GPL");
128 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
129 MODULE_VERSION(DRV_VERSION);
130
131 static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
132 {
133 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
134 unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
135 u8 pmr;
136
137 if (ap->port_no) {
138 switch (pdev->device) {
139 case 0x0180:
140 case 0x0181:
141 pci_read_config_byte(pdev, SIS_PMR, &pmr);
142 if ((pmr & SIS_PMR_COMBINED) == 0)
143 addr += SIS180_SATA1_OFS;
144 break;
145
146 case 0x0182:
147 case 0x0183:
148 case 0x1182:
149 addr += SIS182_SATA1_OFS;
150 break;
151 }
152 }
153 return addr;
154 }
155
156 static u32 sis_scr_cfg_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
157 {
158 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
159 unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
160 u32 val2 = 0;
161 u8 pmr;
162
163 if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
164 return 0xffffffff;
165
166 pci_read_config_byte(pdev, SIS_PMR, &pmr);
167
168 pci_read_config_dword(pdev, cfg_addr, val);
169
170 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
171 (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
172 pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
173
174 *val |= val2;
175 *val &= 0xfffffffb; /* avoid problems with powerdowned ports */
176
177 return 0;
178 }
179
180 static void sis_scr_cfg_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
181 {
182 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
183 unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
184 u8 pmr;
185
186 if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
187 return;
188
189 pci_read_config_byte(pdev, SIS_PMR, &pmr);
190
191 pci_write_config_dword(pdev, cfg_addr, val);
192
193 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
194 (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
195 pci_write_config_dword(pdev, cfg_addr+0x10, val);
196 }
197
198 static int sis_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
199 {
200 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
201 u8 pmr;
202
203 if (sc_reg > SCR_CONTROL)
204 return -EINVAL;
205
206 if (ap->flags & SIS_FLAG_CFGSCR)
207 return sis_scr_cfg_read(ap, sc_reg, val);
208
209 pci_read_config_byte(pdev, SIS_PMR, &pmr);
210
211 *val = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4));
212
213 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
214 (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
215 *val |= ioread32(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);
216
217 *val &= 0xfffffffb;
218
219 return 0;
220 }
221
222 static int sis_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
223 {
224 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
225 u8 pmr;
226
227 if (sc_reg > SCR_CONTROL)
228 return -EINVAL;
229
230 pci_read_config_byte(pdev, SIS_PMR, &pmr);
231
232 if (ap->flags & SIS_FLAG_CFGSCR)
233 sis_scr_cfg_write(ap, sc_reg, val);
234 else {
235 iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
236 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) ||
237 (pdev->device == 0x1182) || (pmr & SIS_PMR_COMBINED))
238 iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
239 }
240 return 0;
241 }
242
243 static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
244 {
245 static int printed_version;
246 struct ata_port_info pi = sis_port_info;
247 const struct ata_port_info *ppi[] = { &pi, &pi };
248 struct ata_host *host;
249 u32 genctl, val;
250 u8 pmr;
251 u8 port2_start = 0x20;
252 int rc;
253
254 if (!printed_version++)
255 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
256
257 rc = pcim_enable_device(pdev);
258 if (rc)
259 return rc;
260
261 /* check and see if the SCRs are in IO space or PCI cfg space */
262 pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
263 if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
264 pi.flags |= SIS_FLAG_CFGSCR;
265
266 /* if hardware thinks SCRs are in IO space, but there are
267 * no IO resources assigned, change to PCI cfg space.
268 */
269 if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
270 ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
271 (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
272 genctl &= ~GENCTL_IOMAPPED_SCR;
273 pci_write_config_dword(pdev, SIS_GENCTL, genctl);
274 pi.flags |= SIS_FLAG_CFGSCR;
275 }
276
277 pci_read_config_byte(pdev, SIS_PMR, &pmr);
278 switch (ent->device) {
279 case 0x0180:
280 case 0x0181:
281
282 /* The PATA-handling is provided by pata_sis */
283 switch (pmr & 0x30) {
284 case 0x10:
285 ppi[1] = &sis_info133_for_sata;
286 break;
287
288 case 0x30:
289 ppi[0] = &sis_info133_for_sata;
290 break;
291 }
292 if ((pmr & SIS_PMR_COMBINED) == 0) {
293 dev_printk(KERN_INFO, &pdev->dev,
294 "Detected SiS 180/181/964 chipset in SATA mode\n");
295 port2_start = 64;
296 } else {
297 dev_printk(KERN_INFO, &pdev->dev,
298 "Detected SiS 180/181 chipset in combined mode\n");
299 port2_start = 0;
300 pi.flags |= ATA_FLAG_SLAVE_POSS;
301 }
302 break;
303
304 case 0x0182:
305 case 0x0183:
306 pci_read_config_dword(pdev, 0x6C, &val);
307 if (val & (1L << 31)) {
308 dev_printk(KERN_INFO, &pdev->dev,
309 "Detected SiS 182/965 chipset\n");
310 pi.flags |= ATA_FLAG_SLAVE_POSS;
311 } else {
312 dev_printk(KERN_INFO, &pdev->dev,
313 "Detected SiS 182/965L chipset\n");
314 }
315 break;
316
317 case 0x1182:
318 dev_printk(KERN_INFO, &pdev->dev,
319 "Detected SiS 1182/966/680 SATA controller\n");
320 pi.flags |= ATA_FLAG_SLAVE_POSS;
321 break;
322
323 case 0x1183:
324 dev_printk(KERN_INFO, &pdev->dev,
325 "Detected SiS 1183/966/966L/968/680 controller in PATA mode\n");
326 ppi[0] = &sis_info133_for_sata;
327 ppi[1] = &sis_info133_for_sata;
328 break;
329 }
330
331 rc = ata_pci_prepare_sff_host(pdev, ppi, &host);
332 if (rc)
333 return rc;
334
335 if (!(pi.flags & SIS_FLAG_CFGSCR)) {
336 void __iomem *mmio;
337
338 rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
339 if (rc)
340 return rc;
341 mmio = host->iomap[SIS_SCR_PCI_BAR];
342
343 host->ports[0]->ioaddr.scr_addr = mmio;
344 host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
345 }
346
347 pci_set_master(pdev);
348 pci_intx(pdev, 1);
349 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
350 &sis_sht);
351 }
352
353 static int __init sis_init(void)
354 {
355 return pci_register_driver(&sis_pci_driver);
356 }
357
358 static void __exit sis_exit(void)
359 {
360 pci_unregister_driver(&sis_pci_driver);
361 }
362
363 module_init(sis_init);
364 module_exit(sis_exit);
x86 "subsystem" repository