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libata: implement and use SHT initializers
[linux-2.6/x86.git] / drivers / ata / sata_sil.c
blob738c1a8ae3b6e7d5cf4f66f753648e713dc0f869
1 /*
2 * sata_sil.c - Silicon Image SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2005 Red Hat, Inc.
9 * Copyright 2003 Benjamin Herrenschmidt
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Documentation for SiI 3112:
31 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
32 *
33 * Other errata and documentation available under NDA.
34 *
35 */
36
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/init.h>
41 #include <linux/blkdev.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <linux/libata.h>
47
48 #define DRV_NAME "sata_sil"
49 #define DRV_VERSION "2.3"
50
51 enum {
52 SIL_MMIO_BAR = 5,
53
54 /*
55 * host flags
56 */
57 SIL_FLAG_NO_SATA_IRQ = (1 << 28),
58 SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29),
59 SIL_FLAG_MOD15WRITE = (1 << 30),
60
61 SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
62 ATA_FLAG_MMIO,
63
64 /*
65 * Controller IDs
66 */
67 sil_3112 = 0,
68 sil_3112_no_sata_irq = 1,
69 sil_3512 = 2,
70 sil_3114 = 3,
71
72 /*
73 * Register offsets
74 */
75 SIL_SYSCFG = 0x48,
76
77 /*
78 * Register bits
79 */
80 /* SYSCFG */
81 SIL_MASK_IDE0_INT = (1 << 22),
82 SIL_MASK_IDE1_INT = (1 << 23),
83 SIL_MASK_IDE2_INT = (1 << 24),
84 SIL_MASK_IDE3_INT = (1 << 25),
85 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
86 SIL_MASK_4PORT = SIL_MASK_2PORT |
87 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
88
89 /* BMDMA/BMDMA2 */
90 SIL_INTR_STEERING = (1 << 1),
91
92 SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */
93 SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */
94 SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */
95 SIL_DMA_ACTIVE = (1 << 16), /* DMA running */
96 SIL_DMA_ERROR = (1 << 17), /* PCI bus error */
97 SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */
98 SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */
99 SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */
100 SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */
101 SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */
102
103 /* SIEN */
104 SIL_SIEN_N = (1 << 16), /* triggered by SError.N */
105
106 /*
107 * Others
108 */
109 SIL_QUIRK_MOD15WRITE = (1 << 0),
110 SIL_QUIRK_UDMA5MAX = (1 << 1),
111 };
112
113 static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
114 #ifdef CONFIG_PM
115 static int sil_pci_device_resume(struct pci_dev *pdev);
116 #endif
117 static void sil_dev_config(struct ata_device *dev);
118 static int sil_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
119 static int sil_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
120 static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed);
121 static void sil_freeze(struct ata_port *ap);
122 static void sil_thaw(struct ata_port *ap);
123
124
125 static const struct pci_device_id sil_pci_tbl[] = {
126 { PCI_VDEVICE(CMD, 0x3112), sil_3112 },
127 { PCI_VDEVICE(CMD, 0x0240), sil_3112 },
128 { PCI_VDEVICE(CMD, 0x3512), sil_3512 },
129 { PCI_VDEVICE(CMD, 0x3114), sil_3114 },
130 { PCI_VDEVICE(ATI, 0x436e), sil_3112 },
131 { PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq },
132 { PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq },
133
134 { } /* terminate list */
135 };
136
137
138 /* TODO firmware versions should be added - eric */
139 static const struct sil_drivelist {
140 const char *product;
141 unsigned int quirk;
142 } sil_blacklist [] = {
143 { "ST320012AS", SIL_QUIRK_MOD15WRITE },
144 { "ST330013AS", SIL_QUIRK_MOD15WRITE },
145 { "ST340017AS", SIL_QUIRK_MOD15WRITE },
146 { "ST360015AS", SIL_QUIRK_MOD15WRITE },
147 { "ST380023AS", SIL_QUIRK_MOD15WRITE },
148 { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
149 { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
150 { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
151 { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
152 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
153 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
154 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
155 { }
156 };
157
158 static struct pci_driver sil_pci_driver = {
159 .name = DRV_NAME,
160 .id_table = sil_pci_tbl,
161 .probe = sil_init_one,
162 .remove = ata_pci_remove_one,
163 #ifdef CONFIG_PM
164 .suspend = ata_pci_device_suspend,
165 .resume = sil_pci_device_resume,
166 #endif
167 };
168
169 static struct scsi_host_template sil_sht = {
170 ATA_BMDMA_SHT(DRV_NAME),
171 };
172
173 static const struct ata_port_operations sil_ops = {
174 .dev_config = sil_dev_config,
175 .tf_load = ata_tf_load,
176 .tf_read = ata_tf_read,
177 .check_status = ata_check_status,
178 .exec_command = ata_exec_command,
179 .dev_select = ata_std_dev_select,
180 .set_mode = sil_set_mode,
181 .mode_filter = ata_pci_default_filter,
182 .bmdma_setup = ata_bmdma_setup,
183 .bmdma_start = ata_bmdma_start,
184 .bmdma_stop = ata_bmdma_stop,
185 .bmdma_status = ata_bmdma_status,
186 .qc_prep = ata_qc_prep,
187 .qc_issue = ata_qc_issue_prot,
188 .data_xfer = ata_data_xfer,
189 .freeze = sil_freeze,
190 .thaw = sil_thaw,
191 .error_handler = ata_bmdma_error_handler,
192 .post_internal_cmd = ata_bmdma_post_internal_cmd,
193 .irq_clear = ata_bmdma_irq_clear,
194 .irq_on = ata_irq_on,
195 .scr_read = sil_scr_read,
196 .scr_write = sil_scr_write,
197 .port_start = ata_sff_port_start,
198 };
199
200 static const struct ata_port_info sil_port_info[] = {
201 /* sil_3112 */
202 {
203 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE,
204 .pio_mask = 0x1f, /* pio0-4 */
205 .mwdma_mask = 0x07, /* mwdma0-2 */
206 .udma_mask = ATA_UDMA5,
207 .port_ops = &sil_ops,
208 },
209 /* sil_3112_no_sata_irq */
210 {
211 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE |
212 SIL_FLAG_NO_SATA_IRQ,
213 .pio_mask = 0x1f, /* pio0-4 */
214 .mwdma_mask = 0x07, /* mwdma0-2 */
215 .udma_mask = ATA_UDMA5,
216 .port_ops = &sil_ops,
217 },
218 /* sil_3512 */
219 {
220 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
221 .pio_mask = 0x1f, /* pio0-4 */
222 .mwdma_mask = 0x07, /* mwdma0-2 */
223 .udma_mask = ATA_UDMA5,
224 .port_ops = &sil_ops,
225 },
226 /* sil_3114 */
227 {
228 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
229 .pio_mask = 0x1f, /* pio0-4 */
230 .mwdma_mask = 0x07, /* mwdma0-2 */
231 .udma_mask = ATA_UDMA5,
232 .port_ops = &sil_ops,
233 },
234 };
235
236 /* per-port register offsets */
237 /* TODO: we can probably calculate rather than use a table */
238 static const struct {
239 unsigned long tf; /* ATA taskfile register block */
240 unsigned long ctl; /* ATA control/altstatus register block */
241 unsigned long bmdma; /* DMA register block */
242 unsigned long bmdma2; /* DMA register block #2 */
243 unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */
244 unsigned long scr; /* SATA control register block */
245 unsigned long sien; /* SATA Interrupt Enable register */
246 unsigned long xfer_mode;/* data transfer mode register */
247 unsigned long sfis_cfg; /* SATA FIS reception config register */
248 } sil_port[] = {
249 /* port 0 ... */
250 /* tf ctl bmdma bmdma2 fifo scr sien mode sfis */
251 { 0x80, 0x8A, 0x0, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c },
252 { 0xC0, 0xCA, 0x8, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
253 { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
254 { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
255 /* ... port 3 */
256 };
257
258 MODULE_AUTHOR("Jeff Garzik");
259 MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
260 MODULE_LICENSE("GPL");
261 MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
262 MODULE_VERSION(DRV_VERSION);
263
264 static int slow_down;
265 module_param(slow_down, int, 0444);
266 MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
267
268
269 static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
270 {
271 u8 cache_line = 0;
272 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
273 return cache_line;
274 }
275
276 /**
277 * sil_set_mode - wrap set_mode functions
278 * @link: link to set up
279 * @r_failed: returned device when we fail
280 *
281 * Wrap the libata method for device setup as after the setup we need
282 * to inspect the results and do some configuration work
283 */
284
285 static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed)
286 {
287 struct ata_port *ap = link->ap;
288 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
289 void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode;
290 struct ata_device *dev;
291 u32 tmp, dev_mode[2] = { };
292 int rc;
293
294 rc = ata_do_set_mode(link, r_failed);
295 if (rc)
296 return rc;
297
298 ata_link_for_each_dev(dev, link) {
299 if (!ata_dev_enabled(dev))
300 dev_mode[dev->devno] = 0; /* PIO0/1/2 */
301 else if (dev->flags & ATA_DFLAG_PIO)
302 dev_mode[dev->devno] = 1; /* PIO3/4 */
303 else
304 dev_mode[dev->devno] = 3; /* UDMA */
305 /* value 2 indicates MDMA */
306 }
307
308 tmp = readl(addr);
309 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
310 tmp |= dev_mode[0];
311 tmp |= (dev_mode[1] << 4);
312 writel(tmp, addr);
313 readl(addr); /* flush */
314 return 0;
315 }
316
317 static inline void __iomem *sil_scr_addr(struct ata_port *ap,
318 unsigned int sc_reg)
319 {
320 void __iomem *offset = ap->ioaddr.scr_addr;
321
322 switch (sc_reg) {
323 case SCR_STATUS:
324 return offset + 4;
325 case SCR_ERROR:
326 return offset + 8;
327 case SCR_CONTROL:
328 return offset;
329 default:
330 /* do nothing */
331 break;
332 }
333
334 return NULL;
335 }
336
337 static int sil_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
338 {
339 void __iomem *mmio = sil_scr_addr(ap, sc_reg);
340
341 if (mmio) {
342 *val = readl(mmio);
343 return 0;
344 }
345 return -EINVAL;
346 }
347
348 static int sil_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
349 {
350 void __iomem *mmio = sil_scr_addr(ap, sc_reg);
351
352 if (mmio) {
353 writel(val, mmio);
354 return 0;
355 }
356 return -EINVAL;
357 }
358
359 static void sil_host_intr(struct ata_port *ap, u32 bmdma2)
360 {
361 struct ata_eh_info *ehi = &ap->link.eh_info;
362 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
363 u8 status;
364
365 if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) {
366 u32 serror;
367
368 /* SIEN doesn't mask SATA IRQs on some 3112s. Those
369 * controllers continue to assert IRQ as long as
370 * SError bits are pending. Clear SError immediately.
371 */
372 sil_scr_read(ap, SCR_ERROR, &serror);
373 sil_scr_write(ap, SCR_ERROR, serror);
374
375 /* Sometimes spurious interrupts occur, double check
376 * it's PHYRDY CHG.
377 */
378 if (serror & SERR_PHYRDY_CHG) {
379 ap->link.eh_info.serror |= serror;
380 goto freeze;
381 }
382
383 if (!(bmdma2 & SIL_DMA_COMPLETE))
384 return;
385 }
386
387 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
388 /* this sometimes happens, just clear IRQ */
389 ata_chk_status(ap);
390 return;
391 }
392
393 /* Check whether we are expecting interrupt in this state */
394 switch (ap->hsm_task_state) {
395 case HSM_ST_FIRST:
396 /* Some pre-ATAPI-4 devices assert INTRQ
397 * at this state when ready to receive CDB.
398 */
399
400 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
401 * The flag was turned on only for atapi devices. No
402 * need to check ata_is_atapi(qc->tf.protocol) again.
403 */
404 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
405 goto err_hsm;
406 break;
407 case HSM_ST_LAST:
408 if (ata_is_dma(qc->tf.protocol)) {
409 /* clear DMA-Start bit */
410 ap->ops->bmdma_stop(qc);
411
412 if (bmdma2 & SIL_DMA_ERROR) {
413 qc->err_mask |= AC_ERR_HOST_BUS;
414 ap->hsm_task_state = HSM_ST_ERR;
415 }
416 }
417 break;
418 case HSM_ST:
419 break;
420 default:
421 goto err_hsm;
422 }
423
424 /* check main status, clearing INTRQ */
425 status = ata_chk_status(ap);
426 if (unlikely(status & ATA_BUSY))
427 goto err_hsm;
428
429 /* ack bmdma irq events */
430 ata_bmdma_irq_clear(ap);
431
432 /* kick HSM in the ass */
433 ata_hsm_move(ap, qc, status, 0);
434
435 if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
436 ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2);
437
438 return;
439
440 err_hsm:
441 qc->err_mask |= AC_ERR_HSM;
442 freeze:
443 ata_port_freeze(ap);
444 }
445
446 static irqreturn_t sil_interrupt(int irq, void *dev_instance)
447 {
448 struct ata_host *host = dev_instance;
449 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
450 int handled = 0;
451 int i;
452
453 spin_lock(&host->lock);
454
455 for (i = 0; i < host->n_ports; i++) {
456 struct ata_port *ap = host->ports[i];
457 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2);
458
459 if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED))
460 continue;
461
462 /* turn off SATA_IRQ if not supported */
463 if (ap->flags & SIL_FLAG_NO_SATA_IRQ)
464 bmdma2 &= ~SIL_DMA_SATA_IRQ;
465
466 if (bmdma2 == 0xffffffff ||
467 !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ)))
468 continue;
469
470 sil_host_intr(ap, bmdma2);
471 handled = 1;
472 }
473
474 spin_unlock(&host->lock);
475
476 return IRQ_RETVAL(handled);
477 }
478
479 static void sil_freeze(struct ata_port *ap)
480 {
481 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
482 u32 tmp;
483
484 /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */
485 writel(0, mmio_base + sil_port[ap->port_no].sien);
486
487 /* plug IRQ */
488 tmp = readl(mmio_base + SIL_SYSCFG);
489 tmp |= SIL_MASK_IDE0_INT << ap->port_no;
490 writel(tmp, mmio_base + SIL_SYSCFG);
491 readl(mmio_base + SIL_SYSCFG); /* flush */
492 }
493
494 static void sil_thaw(struct ata_port *ap)
495 {
496 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
497 u32 tmp;
498
499 /* clear IRQ */
500 ata_chk_status(ap);
501 ata_bmdma_irq_clear(ap);
502
503 /* turn on SATA IRQ if supported */
504 if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ))
505 writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien);
506
507 /* turn on IRQ */
508 tmp = readl(mmio_base + SIL_SYSCFG);
509 tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no);
510 writel(tmp, mmio_base + SIL_SYSCFG);
511 }
512
513 /**
514 * sil_dev_config - Apply device/host-specific errata fixups
515 * @dev: Device to be examined
516 *
517 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
518 * device is known to be present, this function is called.
519 * We apply two errata fixups which are specific to Silicon Image,
520 * a Seagate and a Maxtor fixup.
521 *
522 * For certain Seagate devices, we must limit the maximum sectors
523 * to under 8K.
524 *
525 * For certain Maxtor devices, we must not program the drive
526 * beyond udma5.
527 *
528 * Both fixups are unfairly pessimistic. As soon as I get more
529 * information on these errata, I will create a more exhaustive
530 * list, and apply the fixups to only the specific
531 * devices/hosts/firmwares that need it.
532 *
533 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
534 * The Maxtor quirk is in the blacklist, but I'm keeping the original
535 * pessimistic fix for the following reasons...
536 * - There seems to be less info on it, only one device gleaned off the
537 * Windows driver, maybe only one is affected. More info would be greatly
538 * appreciated.
539 * - But then again UDMA5 is hardly anything to complain about
540 */
541 static void sil_dev_config(struct ata_device *dev)
542 {
543 struct ata_port *ap = dev->link->ap;
544 int print_info = ap->link.eh_context.i.flags & ATA_EHI_PRINTINFO;
545 unsigned int n, quirks = 0;
546 unsigned char model_num[ATA_ID_PROD_LEN + 1];
547
548 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
549
550 for (n = 0; sil_blacklist[n].product; n++)
551 if (!strcmp(sil_blacklist[n].product, model_num)) {
552 quirks = sil_blacklist[n].quirk;
553 break;
554 }
555
556 /* limit requests to 15 sectors */
557 if (slow_down ||
558 ((ap->flags & SIL_FLAG_MOD15WRITE) &&
559 (quirks & SIL_QUIRK_MOD15WRITE))) {
560 if (print_info)
561 ata_dev_printk(dev, KERN_INFO, "applying Seagate "
562 "errata fix (mod15write workaround)\n");
563 dev->max_sectors = 15;
564 return;
565 }
566
567 /* limit to udma5 */
568 if (quirks & SIL_QUIRK_UDMA5MAX) {
569 if (print_info)
570 ata_dev_printk(dev, KERN_INFO, "applying Maxtor "
571 "errata fix %s\n", model_num);
572 dev->udma_mask &= ATA_UDMA5;
573 return;
574 }
575 }
576
577 static void sil_init_controller(struct ata_host *host)
578 {
579 struct pci_dev *pdev = to_pci_dev(host->dev);
580 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
581 u8 cls;
582 u32 tmp;
583 int i;
584
585 /* Initialize FIFO PCI bus arbitration */
586 cls = sil_get_device_cache_line(pdev);
587 if (cls) {
588 cls >>= 3;
589 cls++; /* cls = (line_size/8)+1 */
590 for (i = 0; i < host->n_ports; i++)
591 writew(cls << 8 | cls,
592 mmio_base + sil_port[i].fifo_cfg);
593 } else
594 dev_printk(KERN_WARNING, &pdev->dev,
595 "cache line size not set. Driver may not function\n");
596
597 /* Apply R_ERR on DMA activate FIS errata workaround */
598 if (host->ports[0]->flags & SIL_FLAG_RERR_ON_DMA_ACT) {
599 int cnt;
600
601 for (i = 0, cnt = 0; i < host->n_ports; i++) {
602 tmp = readl(mmio_base + sil_port[i].sfis_cfg);
603 if ((tmp & 0x3) != 0x01)
604 continue;
605 if (!cnt)
606 dev_printk(KERN_INFO, &pdev->dev,
607 "Applying R_ERR on DMA activate "
608 "FIS errata fix\n");
609 writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
610 cnt++;
611 }
612 }
613
614 if (host->n_ports == 4) {
615 /* flip the magic "make 4 ports work" bit */
616 tmp = readl(mmio_base + sil_port[2].bmdma);
617 if ((tmp & SIL_INTR_STEERING) == 0)
618 writel(tmp | SIL_INTR_STEERING,
619 mmio_base + sil_port[2].bmdma);
620 }
621 }
622
623 static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
624 {
625 static int printed_version;
626 int board_id = ent->driver_data;
627 const struct ata_port_info *ppi[] = { &sil_port_info[board_id], NULL };
628 struct ata_host *host;
629 void __iomem *mmio_base;
630 int n_ports, rc;
631 unsigned int i;
632
633 if (!printed_version++)
634 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
635
636 /* allocate host */
637 n_ports = 2;
638 if (board_id == sil_3114)
639 n_ports = 4;
640
641 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
642 if (!host)
643 return -ENOMEM;
644
645 /* acquire resources and fill host */
646 rc = pcim_enable_device(pdev);
647 if (rc)
648 return rc;
649
650 rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME);
651 if (rc == -EBUSY)
652 pcim_pin_device(pdev);
653 if (rc)
654 return rc;
655 host->iomap = pcim_iomap_table(pdev);
656
657 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
658 if (rc)
659 return rc;
660 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
661 if (rc)
662 return rc;
663
664 mmio_base = host->iomap[SIL_MMIO_BAR];
665
666 for (i = 0; i < host->n_ports; i++) {
667 struct ata_port *ap = host->ports[i];
668 struct ata_ioports *ioaddr = &ap->ioaddr;
669
670 ioaddr->cmd_addr = mmio_base + sil_port[i].tf;
671 ioaddr->altstatus_addr =
672 ioaddr->ctl_addr = mmio_base + sil_port[i].ctl;
673 ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma;
674 ioaddr->scr_addr = mmio_base + sil_port[i].scr;
675 ata_std_ports(ioaddr);
676
677 ata_port_pbar_desc(ap, SIL_MMIO_BAR, -1, "mmio");
678 ata_port_pbar_desc(ap, SIL_MMIO_BAR, sil_port[i].tf, "tf");
679 }
680
681 /* initialize and activate */
682 sil_init_controller(host);
683
684 pci_set_master(pdev);
685 return ata_host_activate(host, pdev->irq, sil_interrupt, IRQF_SHARED,
686 &sil_sht);
687 }
688
689 #ifdef CONFIG_PM
690 static int sil_pci_device_resume(struct pci_dev *pdev)
691 {
692 struct ata_host *host = dev_get_drvdata(&pdev->dev);
693 int rc;
694
695 rc = ata_pci_device_do_resume(pdev);
696 if (rc)
697 return rc;
698
699 sil_init_controller(host);
700 ata_host_resume(host);
701
702 return 0;
703 }
704 #endif
705
706 static int __init sil_init(void)
707 {
708 return pci_register_driver(&sil_pci_driver);
709 }
710
711 static void __exit sil_exit(void)
712 {
713 pci_unregister_driver(&sil_pci_driver);
714 }
715
716
717 module_init(sil_init);
718 module_exit(sil_exit);
x86 "subsystem" repository