2 * pdc_adma.c - Pacific Digital Corporation ADMA
4 * Maintained by: Mark Lord <mlord@pobox.com>
6 * Copyright 2005 Mark Lord
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
27 * Supports ATA disks in single-packet ADMA mode.
28 * Uses PIO for everything else.
30 * TODO: Use ADMA transfers for ATAPI devices, when possible.
31 * This requires careful attention to a number of quirks of the chip.
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <linux/libata.h>
46 #define DRV_NAME "pdc_adma"
47 #define DRV_VERSION "1.0"
49 /* macro to calculate base address for ATA regs */
50 #define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40))
52 /* macro to calculate base address for ADMA regs */
53 #define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20))
55 /* macro to obtain addresses from ata_port */
56 #define ADMA_PORT_REGS(ap) \
57 ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
64 ADMA_PRD_BYTES
= LIBATA_MAX_PRD
* 16,
65 ADMA_PKT_BYTES
= ADMA_CPB_BYTES
+ ADMA_PRD_BYTES
,
67 ADMA_DMA_BOUNDARY
= 0xffffffff,
69 /* global register offsets */
70 ADMA_MODE_LOCK
= 0x00c7,
72 /* per-channel register offsets */
73 ADMA_CONTROL
= 0x0000, /* ADMA control */
74 ADMA_STATUS
= 0x0002, /* ADMA status */
75 ADMA_CPB_COUNT
= 0x0004, /* CPB count */
76 ADMA_CPB_CURRENT
= 0x000c, /* current CPB address */
77 ADMA_CPB_NEXT
= 0x000c, /* next CPB address */
78 ADMA_CPB_LOOKUP
= 0x0010, /* CPB lookup table */
79 ADMA_FIFO_IN
= 0x0014, /* input FIFO threshold */
80 ADMA_FIFO_OUT
= 0x0016, /* output FIFO threshold */
82 /* ADMA_CONTROL register bits */
83 aNIEN
= (1 << 8), /* irq mask: 1==masked */
84 aGO
= (1 << 7), /* packet trigger ("Go!") */
85 aRSTADM
= (1 << 5), /* ADMA logic reset */
86 aPIOMD4
= 0x0003, /* PIO mode 4 */
88 /* ADMA_STATUS register bits */
106 /* ATA register flags */
110 /* ATA register addresses */
111 ADMA_REGS_CONTROL
= 0x0e,
112 ADMA_REGS_SECTOR_COUNT
= 0x12,
113 ADMA_REGS_LBA_LOW
= 0x13,
114 ADMA_REGS_LBA_MID
= 0x14,
115 ADMA_REGS_LBA_HIGH
= 0x15,
116 ADMA_REGS_DEVICE
= 0x16,
117 ADMA_REGS_COMMAND
= 0x17,
120 board_1841_idx
= 0, /* ADMA 2-port controller */
123 typedef enum { adma_state_idle
, adma_state_pkt
, adma_state_mmio
} adma_state_t
;
125 struct adma_port_priv
{
131 static int adma_ata_init_one(struct pci_dev
*pdev
,
132 const struct pci_device_id
*ent
);
133 static int adma_port_start(struct ata_port
*ap
);
134 static void adma_host_stop(struct ata_host
*host
);
135 static void adma_port_stop(struct ata_port
*ap
);
136 static void adma_qc_prep(struct ata_queued_cmd
*qc
);
137 static unsigned int adma_qc_issue(struct ata_queued_cmd
*qc
);
138 static int adma_check_atapi_dma(struct ata_queued_cmd
*qc
);
139 static void adma_bmdma_stop(struct ata_queued_cmd
*qc
);
140 static u8
adma_bmdma_status(struct ata_port
*ap
);
141 static void adma_freeze(struct ata_port
*ap
);
142 static void adma_thaw(struct ata_port
*ap
);
143 static void adma_error_handler(struct ata_port
*ap
);
145 static struct scsi_host_template adma_ata_sht
= {
146 ATA_BASE_SHT(DRV_NAME
),
147 .sg_tablesize
= LIBATA_MAX_PRD
,
148 .dma_boundary
= ADMA_DMA_BOUNDARY
,
151 static const struct ata_port_operations adma_ata_ops
= {
152 .tf_load
= ata_tf_load
,
153 .tf_read
= ata_tf_read
,
154 .exec_command
= ata_exec_command
,
155 .check_status
= ata_check_status
,
156 .dev_select
= ata_std_dev_select
,
157 .check_atapi_dma
= adma_check_atapi_dma
,
158 .data_xfer
= ata_data_xfer
,
159 .qc_prep
= adma_qc_prep
,
160 .qc_issue
= adma_qc_issue
,
161 .freeze
= adma_freeze
,
163 .error_handler
= adma_error_handler
,
164 .irq_clear
= ata_noop_irq_clear
,
165 .irq_on
= ata_irq_on
,
166 .port_start
= adma_port_start
,
167 .port_stop
= adma_port_stop
,
168 .host_stop
= adma_host_stop
,
169 .bmdma_stop
= adma_bmdma_stop
,
170 .bmdma_status
= adma_bmdma_status
,
173 static struct ata_port_info adma_port_info
[] = {
176 .flags
= ATA_FLAG_SLAVE_POSS
|
177 ATA_FLAG_NO_LEGACY
| ATA_FLAG_MMIO
|
178 ATA_FLAG_PIO_POLLING
,
179 .pio_mask
= 0x10, /* pio4 */
180 .udma_mask
= ATA_UDMA4
,
181 .port_ops
= &adma_ata_ops
,
185 static const struct pci_device_id adma_ata_pci_tbl
[] = {
186 { PCI_VDEVICE(PDC
, 0x1841), board_1841_idx
},
188 { } /* terminate list */
191 static struct pci_driver adma_ata_pci_driver
= {
193 .id_table
= adma_ata_pci_tbl
,
194 .probe
= adma_ata_init_one
,
195 .remove
= ata_pci_remove_one
,
198 static int adma_check_atapi_dma(struct ata_queued_cmd
*qc
)
200 return 1; /* ATAPI DMA not yet supported */
203 static void adma_bmdma_stop(struct ata_queued_cmd
*qc
)
208 static u8
adma_bmdma_status(struct ata_port
*ap
)
213 static void adma_reset_engine(struct ata_port
*ap
)
215 void __iomem
*chan
= ADMA_PORT_REGS(ap
);
217 /* reset ADMA to idle state */
218 writew(aPIOMD4
| aNIEN
| aRSTADM
, chan
+ ADMA_CONTROL
);
220 writew(aPIOMD4
, chan
+ ADMA_CONTROL
);
224 static void adma_reinit_engine(struct ata_port
*ap
)
226 struct adma_port_priv
*pp
= ap
->private_data
;
227 void __iomem
*chan
= ADMA_PORT_REGS(ap
);
229 /* mask/clear ATA interrupts */
230 writeb(ATA_NIEN
, ap
->ioaddr
.ctl_addr
);
231 ata_check_status(ap
);
233 /* reset the ADMA engine */
234 adma_reset_engine(ap
);
236 /* set in-FIFO threshold to 0x100 */
237 writew(0x100, chan
+ ADMA_FIFO_IN
);
239 /* set CPB pointer */
240 writel((u32
)pp
->pkt_dma
, chan
+ ADMA_CPB_NEXT
);
242 /* set out-FIFO threshold to 0x100 */
243 writew(0x100, chan
+ ADMA_FIFO_OUT
);
246 writew(1, chan
+ ADMA_CPB_COUNT
);
248 /* read/discard ADMA status */
249 readb(chan
+ ADMA_STATUS
);
252 static inline void adma_enter_reg_mode(struct ata_port
*ap
)
254 void __iomem
*chan
= ADMA_PORT_REGS(ap
);
256 writew(aPIOMD4
, chan
+ ADMA_CONTROL
);
257 readb(chan
+ ADMA_STATUS
); /* flush */
260 static void adma_freeze(struct ata_port
*ap
)
262 void __iomem
*chan
= ADMA_PORT_REGS(ap
);
264 /* mask/clear ATA interrupts */
265 writeb(ATA_NIEN
, ap
->ioaddr
.ctl_addr
);
266 ata_check_status(ap
);
268 /* reset ADMA to idle state */
269 writew(aPIOMD4
| aNIEN
| aRSTADM
, chan
+ ADMA_CONTROL
);
271 writew(aPIOMD4
| aNIEN
, chan
+ ADMA_CONTROL
);
275 static void adma_thaw(struct ata_port
*ap
)
277 adma_reinit_engine(ap
);
280 static int adma_prereset(struct ata_link
*link
, unsigned long deadline
)
282 struct ata_port
*ap
= link
->ap
;
283 struct adma_port_priv
*pp
= ap
->private_data
;
285 if (pp
->state
!= adma_state_idle
) /* healthy paranoia */
286 pp
->state
= adma_state_mmio
;
287 adma_reinit_engine(ap
);
289 return ata_std_prereset(link
, deadline
);
292 static void adma_error_handler(struct ata_port
*ap
)
294 ata_do_eh(ap
, adma_prereset
, ata_std_softreset
, NULL
,
298 static int adma_fill_sg(struct ata_queued_cmd
*qc
)
300 struct scatterlist
*sg
;
301 struct ata_port
*ap
= qc
->ap
;
302 struct adma_port_priv
*pp
= ap
->private_data
;
303 u8
*buf
= pp
->pkt
, *last_buf
= NULL
;
304 int i
= (2 + buf
[3]) * 8;
305 u8 pFLAGS
= pORD
| ((qc
->tf
.flags
& ATA_TFLAG_WRITE
) ? pDIRO
: 0);
308 for_each_sg(qc
->sg
, sg
, qc
->n_elem
, si
) {
312 addr
= (u32
)sg_dma_address(sg
);
313 *(__le32
*)(buf
+ i
) = cpu_to_le32(addr
);
316 len
= sg_dma_len(sg
) >> 3;
317 *(__le32
*)(buf
+ i
) = cpu_to_le32(len
);
322 buf
[i
++] = qc
->dev
->dma_mode
& 0xf;
323 buf
[i
++] = 0; /* pPKLW */
324 buf
[i
++] = 0; /* reserved */
326 *(__le32
*)(buf
+ i
) =
327 (pFLAGS
& pEND
) ? 0 : cpu_to_le32(pp
->pkt_dma
+ i
+ 4);
330 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i
/4,
331 (unsigned long)addr
, len
);
334 if (likely(last_buf
))
340 static void adma_qc_prep(struct ata_queued_cmd
*qc
)
342 struct adma_port_priv
*pp
= qc
->ap
->private_data
;
344 u32 pkt_dma
= (u32
)pp
->pkt_dma
;
349 adma_enter_reg_mode(qc
->ap
);
350 if (qc
->tf
.protocol
!= ATA_PROT_DMA
) {
355 buf
[i
++] = 0; /* Response flags */
356 buf
[i
++] = 0; /* reserved */
357 buf
[i
++] = cVLD
| cDAT
| cIEN
;
358 i
++; /* cLEN, gets filled in below */
360 *(__le32
*)(buf
+i
) = cpu_to_le32(pkt_dma
); /* cNCPB */
362 i
+= 4; /* cPRD, gets filled in below */
364 buf
[i
++] = 0; /* reserved */
365 buf
[i
++] = 0; /* reserved */
366 buf
[i
++] = 0; /* reserved */
367 buf
[i
++] = 0; /* reserved */
369 /* ATA registers; must be a multiple of 4 */
370 buf
[i
++] = qc
->tf
.device
;
371 buf
[i
++] = ADMA_REGS_DEVICE
;
372 if ((qc
->tf
.flags
& ATA_TFLAG_LBA48
)) {
373 buf
[i
++] = qc
->tf
.hob_nsect
;
374 buf
[i
++] = ADMA_REGS_SECTOR_COUNT
;
375 buf
[i
++] = qc
->tf
.hob_lbal
;
376 buf
[i
++] = ADMA_REGS_LBA_LOW
;
377 buf
[i
++] = qc
->tf
.hob_lbam
;
378 buf
[i
++] = ADMA_REGS_LBA_MID
;
379 buf
[i
++] = qc
->tf
.hob_lbah
;
380 buf
[i
++] = ADMA_REGS_LBA_HIGH
;
382 buf
[i
++] = qc
->tf
.nsect
;
383 buf
[i
++] = ADMA_REGS_SECTOR_COUNT
;
384 buf
[i
++] = qc
->tf
.lbal
;
385 buf
[i
++] = ADMA_REGS_LBA_LOW
;
386 buf
[i
++] = qc
->tf
.lbam
;
387 buf
[i
++] = ADMA_REGS_LBA_MID
;
388 buf
[i
++] = qc
->tf
.lbah
;
389 buf
[i
++] = ADMA_REGS_LBA_HIGH
;
391 buf
[i
++] = ADMA_REGS_CONTROL
;
394 buf
[i
++] = qc
->tf
.command
;
395 buf
[i
++] = ADMA_REGS_COMMAND
| rEND
;
397 buf
[3] = (i
>> 3) - 2; /* cLEN */
398 *(__le32
*)(buf
+8) = cpu_to_le32(pkt_dma
+ i
); /* cPRD */
400 i
= adma_fill_sg(qc
);
401 wmb(); /* flush PRDs and pkt to memory */
403 /* dump out CPB + PRDs for debug */
406 static char obuf
[2048];
407 for (j
= 0; j
< i
; ++j
) {
408 len
+= sprintf(obuf
+len
, "%02x ", buf
[j
]);
410 printk("%s\n", obuf
);
415 printk("%s\n", obuf
);
420 static inline void adma_packet_start(struct ata_queued_cmd
*qc
)
422 struct ata_port
*ap
= qc
->ap
;
423 void __iomem
*chan
= ADMA_PORT_REGS(ap
);
425 VPRINTK("ENTER, ap %p\n", ap
);
427 /* fire up the ADMA engine */
428 writew(aPIOMD4
| aGO
, chan
+ ADMA_CONTROL
);
431 static unsigned int adma_qc_issue(struct ata_queued_cmd
*qc
)
433 struct adma_port_priv
*pp
= qc
->ap
->private_data
;
435 switch (qc
->tf
.protocol
) {
437 pp
->state
= adma_state_pkt
;
438 adma_packet_start(qc
);
449 pp
->state
= adma_state_mmio
;
450 return ata_qc_issue_prot(qc
);
453 static inline unsigned int adma_intr_pkt(struct ata_host
*host
)
455 unsigned int handled
= 0, port_no
;
457 for (port_no
= 0; port_no
< host
->n_ports
; ++port_no
) {
458 struct ata_port
*ap
= host
->ports
[port_no
];
459 struct adma_port_priv
*pp
;
460 struct ata_queued_cmd
*qc
;
461 void __iomem
*chan
= ADMA_PORT_REGS(ap
);
462 u8 status
= readb(chan
+ ADMA_STATUS
);
467 adma_enter_reg_mode(ap
);
468 if (ap
->flags
& ATA_FLAG_DISABLED
)
470 pp
= ap
->private_data
;
471 if (!pp
|| pp
->state
!= adma_state_pkt
)
473 qc
= ata_qc_from_tag(ap
, ap
->link
.active_tag
);
474 if (qc
&& (!(qc
->tf
.flags
& ATA_TFLAG_POLLING
))) {
476 qc
->err_mask
|= AC_ERR_HOST_BUS
;
477 else if ((status
& (aPSD
| aUIRQ
)))
478 qc
->err_mask
|= AC_ERR_OTHER
;
480 if (pp
->pkt
[0] & cATERR
)
481 qc
->err_mask
|= AC_ERR_DEV
;
482 else if (pp
->pkt
[0] != cDONE
)
483 qc
->err_mask
|= AC_ERR_OTHER
;
488 struct ata_eh_info
*ehi
= &ap
->link
.eh_info
;
489 ata_ehi_clear_desc(ehi
);
490 ata_ehi_push_desc(ehi
,
491 "ADMA-status 0x%02X", status
);
492 ata_ehi_push_desc(ehi
,
493 "pkt[0] 0x%02X", pp
->pkt
[0]);
495 if (qc
->err_mask
== AC_ERR_DEV
)
505 static inline unsigned int adma_intr_mmio(struct ata_host
*host
)
507 unsigned int handled
= 0, port_no
;
509 for (port_no
= 0; port_no
< host
->n_ports
; ++port_no
) {
511 ap
= host
->ports
[port_no
];
512 if (ap
&& (!(ap
->flags
& ATA_FLAG_DISABLED
))) {
513 struct ata_queued_cmd
*qc
;
514 struct adma_port_priv
*pp
= ap
->private_data
;
515 if (!pp
|| pp
->state
!= adma_state_mmio
)
517 qc
= ata_qc_from_tag(ap
, ap
->link
.active_tag
);
518 if (qc
&& (!(qc
->tf
.flags
& ATA_TFLAG_POLLING
))) {
520 /* check main status, clearing INTRQ */
521 u8 status
= ata_check_status(ap
);
522 if ((status
& ATA_BUSY
))
524 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
525 ap
->print_id
, qc
->tf
.protocol
, status
);
527 /* complete taskfile transaction */
528 pp
->state
= adma_state_idle
;
529 qc
->err_mask
|= ac_err_mask(status
);
533 struct ata_eh_info
*ehi
=
535 ata_ehi_clear_desc(ehi
);
536 ata_ehi_push_desc(ehi
,
537 "status 0x%02X", status
);
539 if (qc
->err_mask
== AC_ERR_DEV
)
551 static irqreturn_t
adma_intr(int irq
, void *dev_instance
)
553 struct ata_host
*host
= dev_instance
;
554 unsigned int handled
= 0;
558 spin_lock(&host
->lock
);
559 handled
= adma_intr_pkt(host
) | adma_intr_mmio(host
);
560 spin_unlock(&host
->lock
);
564 return IRQ_RETVAL(handled
);
567 static void adma_ata_setup_port(struct ata_ioports
*port
, void __iomem
*base
)
570 port
->data_addr
= base
+ 0x000;
572 port
->feature_addr
= base
+ 0x004;
573 port
->nsect_addr
= base
+ 0x008;
574 port
->lbal_addr
= base
+ 0x00c;
575 port
->lbam_addr
= base
+ 0x010;
576 port
->lbah_addr
= base
+ 0x014;
577 port
->device_addr
= base
+ 0x018;
579 port
->command_addr
= base
+ 0x01c;
580 port
->altstatus_addr
=
581 port
->ctl_addr
= base
+ 0x038;
584 static int adma_port_start(struct ata_port
*ap
)
586 struct device
*dev
= ap
->host
->dev
;
587 struct adma_port_priv
*pp
;
590 rc
= ata_port_start(ap
);
593 adma_enter_reg_mode(ap
);
594 pp
= devm_kzalloc(dev
, sizeof(*pp
), GFP_KERNEL
);
597 pp
->pkt
= dmam_alloc_coherent(dev
, ADMA_PKT_BYTES
, &pp
->pkt_dma
,
602 if ((pp
->pkt_dma
& 7) != 0) {
603 printk(KERN_ERR
"bad alignment for pp->pkt_dma: %08x\n",
607 memset(pp
->pkt
, 0, ADMA_PKT_BYTES
);
608 ap
->private_data
= pp
;
609 adma_reinit_engine(ap
);
613 static void adma_port_stop(struct ata_port
*ap
)
615 adma_reset_engine(ap
);
618 static void adma_host_stop(struct ata_host
*host
)
620 unsigned int port_no
;
622 for (port_no
= 0; port_no
< ADMA_PORTS
; ++port_no
)
623 adma_reset_engine(host
->ports
[port_no
]);
626 static void adma_host_init(struct ata_host
*host
, unsigned int chip_id
)
628 unsigned int port_no
;
630 /* enable/lock aGO operation */
631 writeb(7, host
->iomap
[ADMA_MMIO_BAR
] + ADMA_MODE_LOCK
);
633 /* reset the ADMA logic */
634 for (port_no
= 0; port_no
< ADMA_PORTS
; ++port_no
)
635 adma_reset_engine(host
->ports
[port_no
]);
638 static int adma_set_dma_masks(struct pci_dev
*pdev
, void __iomem
*mmio_base
)
642 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
644 dev_printk(KERN_ERR
, &pdev
->dev
,
645 "32-bit DMA enable failed\n");
648 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
650 dev_printk(KERN_ERR
, &pdev
->dev
,
651 "32-bit consistent DMA enable failed\n");
657 static int adma_ata_init_one(struct pci_dev
*pdev
,
658 const struct pci_device_id
*ent
)
660 static int printed_version
;
661 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
662 const struct ata_port_info
*ppi
[] = { &adma_port_info
[board_idx
], NULL
};
663 struct ata_host
*host
;
664 void __iomem
*mmio_base
;
667 if (!printed_version
++)
668 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
671 host
= ata_host_alloc_pinfo(&pdev
->dev
, ppi
, ADMA_PORTS
);
675 /* acquire resources and fill host */
676 rc
= pcim_enable_device(pdev
);
680 if ((pci_resource_flags(pdev
, 4) & IORESOURCE_MEM
) == 0)
683 rc
= pcim_iomap_regions(pdev
, 1 << ADMA_MMIO_BAR
, DRV_NAME
);
686 host
->iomap
= pcim_iomap_table(pdev
);
687 mmio_base
= host
->iomap
[ADMA_MMIO_BAR
];
689 rc
= adma_set_dma_masks(pdev
, mmio_base
);
693 for (port_no
= 0; port_no
< ADMA_PORTS
; ++port_no
) {
694 struct ata_port
*ap
= host
->ports
[port_no
];
695 void __iomem
*port_base
= ADMA_ATA_REGS(mmio_base
, port_no
);
696 unsigned int offset
= port_base
- mmio_base
;
698 adma_ata_setup_port(&ap
->ioaddr
, port_base
);
700 ata_port_pbar_desc(ap
, ADMA_MMIO_BAR
, -1, "mmio");
701 ata_port_pbar_desc(ap
, ADMA_MMIO_BAR
, offset
, "port");
704 /* initialize adapter */
705 adma_host_init(host
, board_idx
);
707 pci_set_master(pdev
);
708 return ata_host_activate(host
, pdev
->irq
, adma_intr
, IRQF_SHARED
,
712 static int __init
adma_ata_init(void)
714 return pci_register_driver(&adma_ata_pci_driver
);
717 static void __exit
adma_ata_exit(void)
719 pci_unregister_driver(&adma_ata_pci_driver
);
722 MODULE_AUTHOR("Mark Lord");
723 MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
724 MODULE_LICENSE("GPL");
725 MODULE_DEVICE_TABLE(pci
, adma_ata_pci_tbl
);
726 MODULE_VERSION(DRV_VERSION
);
728 module_init(adma_ata_init
);
729 module_exit(adma_ata_exit
);