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[PATCH] ppc-opc NULL noise removal
[linux-2.6/x86.git] / arch / ppc64 / xmon / ppc-opc.c
blob5ee8fc32f824143550cf9556bfebf42daea16a1c
1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
5
6 This file is part of GDB, GAS, and the GNU binutils.
7
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
12
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
23 #include <linux/stddef.h>
24 #include "nonstdio.h"
25 #include "ppc.h"
26
27 #define ATTRIBUTE_UNUSED
28 #define _(x) x
29
30 /* This file holds the PowerPC opcode table. The opcode table
31 includes almost all of the extended instruction mnemonics. This
32 permits the disassembler to use them, and simplifies the assembler
33 logic, at the cost of increasing the table size. The table is
34 strictly constant data, so the compiler should be able to put it in
35 the .text section.
36
37 This file also holds the operand table. All knowledge about
38 inserting operands into instructions and vice-versa is kept in this
39 file. */
40 \f
41 /* Local insertion and extraction functions. */
42
43 static unsigned long insert_bat (unsigned long, long, int, const char **);
44 static long extract_bat (unsigned long, int, int *);
45 static unsigned long insert_bba (unsigned long, long, int, const char **);
46 static long extract_bba (unsigned long, int, int *);
47 static unsigned long insert_bd (unsigned long, long, int, const char **);
48 static long extract_bd (unsigned long, int, int *);
49 static unsigned long insert_bdm (unsigned long, long, int, const char **);
50 static long extract_bdm (unsigned long, int, int *);
51 static unsigned long insert_bdp (unsigned long, long, int, const char **);
52 static long extract_bdp (unsigned long, int, int *);
53 static unsigned long insert_bo (unsigned long, long, int, const char **);
54 static long extract_bo (unsigned long, int, int *);
55 static unsigned long insert_boe (unsigned long, long, int, const char **);
56 static long extract_boe (unsigned long, int, int *);
57 static unsigned long insert_dq (unsigned long, long, int, const char **);
58 static long extract_dq (unsigned long, int, int *);
59 static unsigned long insert_ds (unsigned long, long, int, const char **);
60 static long extract_ds (unsigned long, int, int *);
61 static unsigned long insert_de (unsigned long, long, int, const char **);
62 static long extract_de (unsigned long, int, int *);
63 static unsigned long insert_des (unsigned long, long, int, const char **);
64 static long extract_des (unsigned long, int, int *);
65 static unsigned long insert_fxm (unsigned long, long, int, const char **);
66 static long extract_fxm (unsigned long, int, int *);
67 static unsigned long insert_li (unsigned long, long, int, const char **);
68 static long extract_li (unsigned long, int, int *);
69 static unsigned long insert_mbe (unsigned long, long, int, const char **);
70 static long extract_mbe (unsigned long, int, int *);
71 static unsigned long insert_mb6 (unsigned long, long, int, const char **);
72 static long extract_mb6 (unsigned long, int, int *);
73 static unsigned long insert_nb (unsigned long, long, int, const char **);
74 static long extract_nb (unsigned long, int, int *);
75 static unsigned long insert_nsi (unsigned long, long, int, const char **);
76 static long extract_nsi (unsigned long, int, int *);
77 static unsigned long insert_ral (unsigned long, long, int, const char **);
78 static unsigned long insert_ram (unsigned long, long, int, const char **);
79 static unsigned long insert_raq (unsigned long, long, int, const char **);
80 static unsigned long insert_ras (unsigned long, long, int, const char **);
81 static unsigned long insert_rbs (unsigned long, long, int, const char **);
82 static long extract_rbs (unsigned long, int, int *);
83 static unsigned long insert_rsq (unsigned long, long, int, const char **);
84 static unsigned long insert_rtq (unsigned long, long, int, const char **);
85 static unsigned long insert_sh6 (unsigned long, long, int, const char **);
86 static long extract_sh6 (unsigned long, int, int *);
87 static unsigned long insert_spr (unsigned long, long, int, const char **);
88 static long extract_spr (unsigned long, int, int *);
89 static unsigned long insert_tbr (unsigned long, long, int, const char **);
90 static long extract_tbr (unsigned long, int, int *);
91 static unsigned long insert_ev2 (unsigned long, long, int, const char **);
92 static long extract_ev2 (unsigned long, int, int *);
93 static unsigned long insert_ev4 (unsigned long, long, int, const char **);
94 static long extract_ev4 (unsigned long, int, int *);
95 static unsigned long insert_ev8 (unsigned long, long, int, const char **);
96 static long extract_ev8 (unsigned long, int, int *);
97 \f
98 /* The operands table.
99
100 The fields are bits, shift, insert, extract, flags.
101
102 We used to put parens around the various additions, like the one
103 for BA just below. However, that caused trouble with feeble
104 compilers with a limit on depth of a parenthesized expression, like
105 (reportedly) the compiler in Microsoft Developer Studio 5. So we
106 omit the parens, since the macros are never used in a context where
107 the addition will be ambiguous. */
108
109 const struct powerpc_operand powerpc_operands[] =
110 {
111 /* The zero index is used to indicate the end of the list of
112 operands. */
113 #define UNUSED 0
114 { 0, 0, NULL, NULL, 0 },
115
116 /* The BA field in an XL form instruction. */
117 #define BA UNUSED + 1
118 #define BA_MASK (0x1f << 16)
119 { 5, 16, NULL, NULL, PPC_OPERAND_CR },
120
121 /* The BA field in an XL form instruction when it must be the same
122 as the BT field in the same instruction. */
123 #define BAT BA + 1
124 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
125
126 /* The BB field in an XL form instruction. */
127 #define BB BAT + 1
128 #define BB_MASK (0x1f << 11)
129 { 5, 11, NULL, NULL, PPC_OPERAND_CR },
130
131 /* The BB field in an XL form instruction when it must be the same
132 as the BA field in the same instruction. */
133 #define BBA BB + 1
134 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
135
136 /* The BD field in a B form instruction. The lower two bits are
137 forced to zero. */
138 #define BD BBA + 1
139 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
140
141 /* The BD field in a B form instruction when absolute addressing is
142 used. */
143 #define BDA BD + 1
144 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
145
146 /* The BD field in a B form instruction when the - modifier is used.
147 This sets the y bit of the BO field appropriately. */
148 #define BDM BDA + 1
149 { 16, 0, insert_bdm, extract_bdm,
150 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
151
152 /* The BD field in a B form instruction when the - modifier is used
153 and absolute address is used. */
154 #define BDMA BDM + 1
155 { 16, 0, insert_bdm, extract_bdm,
156 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
157
158 /* The BD field in a B form instruction when the + modifier is used.
159 This sets the y bit of the BO field appropriately. */
160 #define BDP BDMA + 1
161 { 16, 0, insert_bdp, extract_bdp,
162 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
163
164 /* The BD field in a B form instruction when the + modifier is used
165 and absolute addressing is used. */
166 #define BDPA BDP + 1
167 { 16, 0, insert_bdp, extract_bdp,
168 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
169
170 /* The BF field in an X or XL form instruction. */
171 #define BF BDPA + 1
172 { 3, 23, NULL, NULL, PPC_OPERAND_CR },
173
174 /* An optional BF field. This is used for comparison instructions,
175 in which an omitted BF field is taken as zero. */
176 #define OBF BF + 1
177 { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
178
179 /* The BFA field in an X or XL form instruction. */
180 #define BFA OBF + 1
181 { 3, 18, NULL, NULL, PPC_OPERAND_CR },
182
183 /* The BI field in a B form or XL form instruction. */
184 #define BI BFA + 1
185 #define BI_MASK (0x1f << 16)
186 { 5, 16, NULL, NULL, PPC_OPERAND_CR },
187
188 /* The BO field in a B form instruction. Certain values are
189 illegal. */
190 #define BO BI + 1
191 #define BO_MASK (0x1f << 21)
192 { 5, 21, insert_bo, extract_bo, 0 },
193
194 /* The BO field in a B form instruction when the + or - modifier is
195 used. This is like the BO field, but it must be even. */
196 #define BOE BO + 1
197 { 5, 21, insert_boe, extract_boe, 0 },
198
199 /* The BT field in an X or XL form instruction. */
200 #define BT BOE + 1
201 { 5, 21, NULL, NULL, PPC_OPERAND_CR },
202
203 /* The condition register number portion of the BI field in a B form
204 or XL form instruction. This is used for the extended
205 conditional branch mnemonics, which set the lower two bits of the
206 BI field. This field is optional. */
207 #define CR BT + 1
208 { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
209
210 /* The CRB field in an X form instruction. */
211 #define CRB CR + 1
212 { 5, 6, NULL, NULL, 0 },
213
214 /* The CRFD field in an X form instruction. */
215 #define CRFD CRB + 1
216 { 3, 23, NULL, NULL, PPC_OPERAND_CR },
217
218 /* The CRFS field in an X form instruction. */
219 #define CRFS CRFD + 1
220 { 3, 0, NULL, NULL, PPC_OPERAND_CR },
221
222 /* The CT field in an X form instruction. */
223 #define CT CRFS + 1
224 { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
225
226 /* The D field in a D form instruction. This is a displacement off
227 a register, and implies that the next operand is a register in
228 parentheses. */
229 #define D CT + 1
230 { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
231
232 /* The DE field in a DE form instruction. This is like D, but is 12
233 bits only. */
234 #define DE D + 1
235 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
236
237 /* The DES field in a DES form instruction. This is like DS, but is 14
238 bits only (12 stored.) */
239 #define DES DE + 1
240 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
241
242 /* The DQ field in a DQ form instruction. This is like D, but the
243 lower four bits are forced to zero. */
244 #define DQ DES + 1
245 { 16, 0, insert_dq, extract_dq,
246 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
247
248 /* The DS field in a DS form instruction. This is like D, but the
249 lower two bits are forced to zero. */
250 #define DS DQ + 1
251 { 16, 0, insert_ds, extract_ds,
252 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
253
254 /* The E field in a wrteei instruction. */
255 #define E DS + 1
256 { 1, 15, NULL, NULL, 0 },
257
258 /* The FL1 field in a POWER SC form instruction. */
259 #define FL1 E + 1
260 { 4, 12, NULL, NULL, 0 },
261
262 /* The FL2 field in a POWER SC form instruction. */
263 #define FL2 FL1 + 1
264 { 3, 2, NULL, NULL, 0 },
265
266 /* The FLM field in an XFL form instruction. */
267 #define FLM FL2 + 1
268 { 8, 17, NULL, NULL, 0 },
269
270 /* The FRA field in an X or A form instruction. */
271 #define FRA FLM + 1
272 #define FRA_MASK (0x1f << 16)
273 { 5, 16, NULL, NULL, PPC_OPERAND_FPR },
274
275 /* The FRB field in an X or A form instruction. */
276 #define FRB FRA + 1
277 #define FRB_MASK (0x1f << 11)
278 { 5, 11, NULL, NULL, PPC_OPERAND_FPR },
279
280 /* The FRC field in an A form instruction. */
281 #define FRC FRB + 1
282 #define FRC_MASK (0x1f << 6)
283 { 5, 6, NULL, NULL, PPC_OPERAND_FPR },
284
285 /* The FRS field in an X form instruction or the FRT field in a D, X
286 or A form instruction. */
287 #define FRS FRC + 1
288 #define FRT FRS
289 { 5, 21, NULL, NULL, PPC_OPERAND_FPR },
290
291 /* The FXM field in an XFX instruction. */
292 #define FXM FRS + 1
293 #define FXM_MASK (0xff << 12)
294 { 8, 12, insert_fxm, extract_fxm, 0 },
295
296 /* Power4 version for mfcr. */
297 #define FXM4 FXM + 1
298 { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
299
300 /* The L field in a D or X form instruction. */
301 #define L FXM4 + 1
302 { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
303
304 /* The LEV field in a POWER SC form instruction. */
305 #define LEV L + 1
306 { 7, 5, NULL, NULL, 0 },
307
308 /* The LI field in an I form instruction. The lower two bits are
309 forced to zero. */
310 #define LI LEV + 1
311 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
312
313 /* The LI field in an I form instruction when used as an absolute
314 address. */
315 #define LIA LI + 1
316 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
317
318 /* The LS field in an X (sync) form instruction. */
319 #define LS LIA + 1
320 { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
321
322 /* The MB field in an M form instruction. */
323 #define MB LS + 1
324 #define MB_MASK (0x1f << 6)
325 { 5, 6, NULL, NULL, 0 },
326
327 /* The ME field in an M form instruction. */
328 #define ME MB + 1
329 #define ME_MASK (0x1f << 1)
330 { 5, 1, NULL, NULL, 0 },
331
332 /* The MB and ME fields in an M form instruction expressed a single
333 operand which is a bitmask indicating which bits to select. This
334 is a two operand form using PPC_OPERAND_NEXT. See the
335 description in opcode/ppc.h for what this means. */
336 #define MBE ME + 1
337 { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
338 { 32, 0, insert_mbe, extract_mbe, 0 },
339
340 /* The MB or ME field in an MD or MDS form instruction. The high
341 bit is wrapped to the low end. */
342 #define MB6 MBE + 2
343 #define ME6 MB6
344 #define MB6_MASK (0x3f << 5)
345 { 6, 5, insert_mb6, extract_mb6, 0 },
346
347 /* The MO field in an mbar instruction. */
348 #define MO MB6 + 1
349 { 5, 21, NULL, NULL, 0 },
350
351 /* The NB field in an X form instruction. The value 32 is stored as
352 0. */
353 #define NB MO + 1
354 { 6, 11, insert_nb, extract_nb, 0 },
355
356 /* The NSI field in a D form instruction. This is the same as the
357 SI field, only negated. */
358 #define NSI NB + 1
359 { 16, 0, insert_nsi, extract_nsi,
360 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
361
362 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
363 #define RA NSI + 1
364 #define RA_MASK (0x1f << 16)
365 { 5, 16, NULL, NULL, PPC_OPERAND_GPR },
366
367 /* The RA field in the DQ form lq instruction, which has special
368 value restrictions. */
369 #define RAQ RA + 1
370 { 5, 16, insert_raq, NULL, PPC_OPERAND_GPR },
371
372 /* The RA field in a D or X form instruction which is an updating
373 load, which means that the RA field may not be zero and may not
374 equal the RT field. */
375 #define RAL RAQ + 1
376 { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR },
377
378 /* The RA field in an lmw instruction, which has special value
379 restrictions. */
380 #define RAM RAL + 1
381 { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR },
382
383 /* The RA field in a D or X form instruction which is an updating
384 store or an updating floating point load, which means that the RA
385 field may not be zero. */
386 #define RAS RAM + 1
387 { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR },
388
389 /* The RB field in an X, XO, M, or MDS form instruction. */
390 #define RB RAS + 1
391 #define RB_MASK (0x1f << 11)
392 { 5, 11, NULL, NULL, PPC_OPERAND_GPR },
393
394 /* The RB field in an X form instruction when it must be the same as
395 the RS field in the instruction. This is used for extended
396 mnemonics like mr. */
397 #define RBS RB + 1
398 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
399
400 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
401 instruction or the RT field in a D, DS, X, XFX or XO form
402 instruction. */
403 #define RS RBS + 1
404 #define RT RS
405 #define RT_MASK (0x1f << 21)
406 { 5, 21, NULL, NULL, PPC_OPERAND_GPR },
407
408 /* The RS field of the DS form stq instruction, which has special
409 value restrictions. */
410 #define RSQ RS + 1
411 { 5, 21, insert_rsq, NULL, PPC_OPERAND_GPR },
412
413 /* The RT field of the DQ form lq instruction, which has special
414 value restrictions. */
415 #define RTQ RSQ + 1
416 { 5, 21, insert_rtq, NULL, PPC_OPERAND_GPR },
417
418 /* The SH field in an X or M form instruction. */
419 #define SH RTQ + 1
420 #define SH_MASK (0x1f << 11)
421 { 5, 11, NULL, NULL, 0 },
422
423 /* The SH field in an MD form instruction. This is split. */
424 #define SH6 SH + 1
425 #define SH6_MASK ((0x1f << 11) | (1 << 1))
426 { 6, 1, insert_sh6, extract_sh6, 0 },
427
428 /* The SI field in a D form instruction. */
429 #define SI SH6 + 1
430 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED },
431
432 /* The SI field in a D form instruction when we accept a wide range
433 of positive values. */
434 #define SISIGNOPT SI + 1
435 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
436
437 /* The SPR field in an XFX form instruction. This is flipped--the
438 lower 5 bits are stored in the upper 5 and vice- versa. */
439 #define SPR SISIGNOPT + 1
440 #define PMR SPR
441 #define SPR_MASK (0x3ff << 11)
442 { 10, 11, insert_spr, extract_spr, 0 },
443
444 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
445 #define SPRBAT SPR + 1
446 #define SPRBAT_MASK (0x3 << 17)
447 { 2, 17, NULL, NULL, 0 },
448
449 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
450 #define SPRG SPRBAT + 1
451 #define SPRG_MASK (0x3 << 16)
452 { 2, 16, NULL, NULL, 0 },
453
454 /* The SR field in an X form instruction. */
455 #define SR SPRG + 1
456 { 4, 16, NULL, NULL, 0 },
457
458 /* The STRM field in an X AltiVec form instruction. */
459 #define STRM SR + 1
460 #define STRM_MASK (0x3 << 21)
461 { 2, 21, NULL, NULL, 0 },
462
463 /* The SV field in a POWER SC form instruction. */
464 #define SV STRM + 1
465 { 14, 2, NULL, NULL, 0 },
466
467 /* The TBR field in an XFX form instruction. This is like the SPR
468 field, but it is optional. */
469 #define TBR SV + 1
470 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
471
472 /* The TO field in a D or X form instruction. */
473 #define TO TBR + 1
474 #define TO_MASK (0x1f << 21)
475 { 5, 21, NULL, NULL, 0 },
476
477 /* The U field in an X form instruction. */
478 #define U TO + 1
479 { 4, 12, NULL, NULL, 0 },
480
481 /* The UI field in a D form instruction. */
482 #define UI U + 1
483 { 16, 0, NULL, NULL, 0 },
484
485 /* The VA field in a VA, VX or VXR form instruction. */
486 #define VA UI + 1
487 #define VA_MASK (0x1f << 16)
488 { 5, 16, NULL, NULL, PPC_OPERAND_VR },
489
490 /* The VB field in a VA, VX or VXR form instruction. */
491 #define VB VA + 1
492 #define VB_MASK (0x1f << 11)
493 { 5, 11, NULL, NULL, PPC_OPERAND_VR },
494
495 /* The VC field in a VA form instruction. */
496 #define VC VB + 1
497 #define VC_MASK (0x1f << 6)
498 { 5, 6, NULL, NULL, PPC_OPERAND_VR },
499
500 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
501 #define VD VC + 1
502 #define VS VD
503 #define VD_MASK (0x1f << 21)
504 { 5, 21, NULL, NULL, PPC_OPERAND_VR },
505
506 /* The SIMM field in a VX form instruction. */
507 #define SIMM VD + 1
508 { 5, 16, NULL, NULL, PPC_OPERAND_SIGNED},
509
510 /* The UIMM field in a VX form instruction. */
511 #define UIMM SIMM + 1
512 { 5, 16, NULL, NULL, 0 },
513
514 /* The SHB field in a VA form instruction. */
515 #define SHB UIMM + 1
516 { 4, 6, NULL, NULL, 0 },
517
518 /* The other UIMM field in a EVX form instruction. */
519 #define EVUIMM SHB + 1
520 { 5, 11, NULL, NULL, 0 },
521
522 /* The other UIMM field in a half word EVX form instruction. */
523 #define EVUIMM_2 EVUIMM + 1
524 { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
525
526 /* The other UIMM field in a word EVX form instruction. */
527 #define EVUIMM_4 EVUIMM_2 + 1
528 { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
529
530 /* The other UIMM field in a double EVX form instruction. */
531 #define EVUIMM_8 EVUIMM_4 + 1
532 { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
533
534 /* The WS field. */
535 #define WS EVUIMM_8 + 1
536 #define WS_MASK (0x7 << 11)
537 { 3, 11, NULL, NULL, 0 },
538
539 /* The L field in an mtmsrd instruction */
540 #define MTMSRD_L WS + 1
541 { 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
542
543 };
544
545 /* The functions used to insert and extract complicated operands. */
546
547 /* The BA field in an XL form instruction when it must be the same as
548 the BT field in the same instruction. This operand is marked FAKE.
549 The insertion function just copies the BT field into the BA field,
550 and the extraction function just checks that the fields are the
551 same. */
552
553 /*ARGSUSED*/
554 static unsigned long
555 insert_bat (unsigned long insn,
556 long value ATTRIBUTE_UNUSED,
557 int dialect ATTRIBUTE_UNUSED,
558 const char **errmsg ATTRIBUTE_UNUSED)
559 {
560 return insn | (((insn >> 21) & 0x1f) << 16);
561 }
562
563 static long
564 extract_bat (unsigned long insn,
565 int dialect ATTRIBUTE_UNUSED,
566 int *invalid)
567 {
568 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
569 *invalid = 1;
570 return 0;
571 }
572
573 /* The BB field in an XL form instruction when it must be the same as
574 the BA field in the same instruction. This operand is marked FAKE.
575 The insertion function just copies the BA field into the BB field,
576 and the extraction function just checks that the fields are the
577 same. */
578
579 /*ARGSUSED*/
580 static unsigned long
581 insert_bba (unsigned long insn,
582 long value ATTRIBUTE_UNUSED,
583 int dialect ATTRIBUTE_UNUSED,
584 const char **errmsg ATTRIBUTE_UNUSED)
585 {
586 return insn | (((insn >> 16) & 0x1f) << 11);
587 }
588
589 static long
590 extract_bba (unsigned long insn,
591 int dialect ATTRIBUTE_UNUSED,
592 int *invalid)
593 {
594 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
595 *invalid = 1;
596 return 0;
597 }
598
599 /* The BD field in a B form instruction. The lower two bits are
600 forced to zero. */
601
602 /*ARGSUSED*/
603 static unsigned long
604 insert_bd (unsigned long insn,
605 long value,
606 int dialect ATTRIBUTE_UNUSED,
607 const char **errmsg ATTRIBUTE_UNUSED)
608 {
609 return insn | (value & 0xfffc);
610 }
611
612 /*ARGSUSED*/
613 static long
614 extract_bd (unsigned long insn,
615 int dialect ATTRIBUTE_UNUSED,
616 int *invalid ATTRIBUTE_UNUSED)
617 {
618 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
619 }
620
621 /* The BD field in a B form instruction when the - modifier is used.
622 This modifier means that the branch is not expected to be taken.
623 For chips built to versions of the architecture prior to version 2
624 (ie. not Power4 compatible), we set the y bit of the BO field to 1
625 if the offset is negative. When extracting, we require that the y
626 bit be 1 and that the offset be positive, since if the y bit is 0
627 we just want to print the normal form of the instruction.
628 Power4 compatible targets use two bits, "a", and "t", instead of
629 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
630 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
631 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
632 for branch on CTR. We only handle the taken/not-taken hint here. */
633
634 /*ARGSUSED*/
635 static unsigned long
636 insert_bdm (unsigned long insn,
637 long value,
638 int dialect,
639 const char **errmsg ATTRIBUTE_UNUSED)
640 {
641 if ((dialect & PPC_OPCODE_POWER4) == 0)
642 {
643 if ((value & 0x8000) != 0)
644 insn |= 1 << 21;
645 }
646 else
647 {
648 if ((insn & (0x14 << 21)) == (0x04 << 21))
649 insn |= 0x02 << 21;
650 else if ((insn & (0x14 << 21)) == (0x10 << 21))
651 insn |= 0x08 << 21;
652 }
653 return insn | (value & 0xfffc);
654 }
655
656 static long
657 extract_bdm (unsigned long insn,
658 int dialect,
659 int *invalid)
660 {
661 if ((dialect & PPC_OPCODE_POWER4) == 0)
662 {
663 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
664 *invalid = 1;
665 }
666 else
667 {
668 if ((insn & (0x17 << 21)) != (0x06 << 21)
669 && (insn & (0x1d << 21)) != (0x18 << 21))
670 *invalid = 1;
671 }
672
673 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
674 }
675
676 /* The BD field in a B form instruction when the + modifier is used.
677 This is like BDM, above, except that the branch is expected to be
678 taken. */
679
680 /*ARGSUSED*/
681 static unsigned long
682 insert_bdp (unsigned long insn,
683 long value,
684 int dialect,
685 const char **errmsg ATTRIBUTE_UNUSED)
686 {
687 if ((dialect & PPC_OPCODE_POWER4) == 0)
688 {
689 if ((value & 0x8000) == 0)
690 insn |= 1 << 21;
691 }
692 else
693 {
694 if ((insn & (0x14 << 21)) == (0x04 << 21))
695 insn |= 0x03 << 21;
696 else if ((insn & (0x14 << 21)) == (0x10 << 21))
697 insn |= 0x09 << 21;
698 }
699 return insn | (value & 0xfffc);
700 }
701
702 static long
703 extract_bdp (unsigned long insn,
704 int dialect,
705 int *invalid)
706 {
707 if ((dialect & PPC_OPCODE_POWER4) == 0)
708 {
709 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
710 *invalid = 1;
711 }
712 else
713 {
714 if ((insn & (0x17 << 21)) != (0x07 << 21)
715 && (insn & (0x1d << 21)) != (0x19 << 21))
716 *invalid = 1;
717 }
718
719 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
720 }
721
722 /* Check for legal values of a BO field. */
723
724 static int
725 valid_bo (long value, int dialect)
726 {
727 if ((dialect & PPC_OPCODE_POWER4) == 0)
728 {
729 /* Certain encodings have bits that are required to be zero.
730 These are (z must be zero, y may be anything):
731 001zy
732 011zy
733 1z00y
734 1z01y
735 1z1zz
736 */
737 switch (value & 0x14)
738 {
739 default:
740 case 0:
741 return 1;
742 case 0x4:
743 return (value & 0x2) == 0;
744 case 0x10:
745 return (value & 0x8) == 0;
746 case 0x14:
747 return value == 0x14;
748 }
749 }
750 else
751 {
752 /* Certain encodings have bits that are required to be zero.
753 These are (z must be zero, a & t may be anything):
754 0000z
755 0001z
756 0100z
757 0101z
758 001at
759 011at
760 1a00t
761 1a01t
762 1z1zz
763 */
764 if ((value & 0x14) == 0)
765 return (value & 0x1) == 0;
766 else if ((value & 0x14) == 0x14)
767 return value == 0x14;
768 else
769 return 1;
770 }
771 }
772
773 /* The BO field in a B form instruction. Warn about attempts to set
774 the field to an illegal value. */
775
776 static unsigned long
777 insert_bo (unsigned long insn,
778 long value,
779 int dialect,
780 const char **errmsg)
781 {
782 if (!valid_bo (value, dialect))
783 *errmsg = _("invalid conditional option");
784 return insn | ((value & 0x1f) << 21);
785 }
786
787 static long
788 extract_bo (unsigned long insn,
789 int dialect,
790 int *invalid)
791 {
792 long value;
793
794 value = (insn >> 21) & 0x1f;
795 if (!valid_bo (value, dialect))
796 *invalid = 1;
797 return value;
798 }
799
800 /* The BO field in a B form instruction when the + or - modifier is
801 used. This is like the BO field, but it must be even. When
802 extracting it, we force it to be even. */
803
804 static unsigned long
805 insert_boe (unsigned long insn,
806 long value,
807 int dialect,
808 const char **errmsg)
809 {
810 if (!valid_bo (value, dialect))
811 *errmsg = _("invalid conditional option");
812 else if ((value & 1) != 0)
813 *errmsg = _("attempt to set y bit when using + or - modifier");
814
815 return insn | ((value & 0x1f) << 21);
816 }
817
818 static long
819 extract_boe (unsigned long insn,
820 int dialect,
821 int *invalid)
822 {
823 long value;
824
825 value = (insn >> 21) & 0x1f;
826 if (!valid_bo (value, dialect))
827 *invalid = 1;
828 return value & 0x1e;
829 }
830
831 /* The DQ field in a DQ form instruction. This is like D, but the
832 lower four bits are forced to zero. */
833
834 /*ARGSUSED*/
835 static unsigned long
836 insert_dq (unsigned long insn,
837 long value,
838 int dialect ATTRIBUTE_UNUSED,
839 const char **errmsg)
840 {
841 if ((value & 0xf) != 0)
842 *errmsg = _("offset not a multiple of 16");
843 return insn | (value & 0xfff0);
844 }
845
846 /*ARGSUSED*/
847 static long
848 extract_dq (unsigned long insn,
849 int dialect ATTRIBUTE_UNUSED,
850 int *invalid ATTRIBUTE_UNUSED)
851 {
852 return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
853 }
854
855 static unsigned long
856 insert_ev2 (unsigned long insn,
857 long value,
858 int dialect ATTRIBUTE_UNUSED,
859 const char **errmsg)
860 {
861 if ((value & 1) != 0)
862 *errmsg = _("offset not a multiple of 2");
863 if ((value > 62) != 0)
864 *errmsg = _("offset greater than 62");
865 return insn | ((value & 0x3e) << 10);
866 }
867
868 static long
869 extract_ev2 (unsigned long insn,
870 int dialect ATTRIBUTE_UNUSED,
871 int *invalid ATTRIBUTE_UNUSED)
872 {
873 return (insn >> 10) & 0x3e;
874 }
875
876 static unsigned long
877 insert_ev4 (unsigned long insn,
878 long value,
879 int dialect ATTRIBUTE_UNUSED,
880 const char **errmsg)
881 {
882 if ((value & 3) != 0)
883 *errmsg = _("offset not a multiple of 4");
884 if ((value > 124) != 0)
885 *errmsg = _("offset greater than 124");
886 return insn | ((value & 0x7c) << 9);
887 }
888
889 static long
890 extract_ev4 (unsigned long insn,
891 int dialect ATTRIBUTE_UNUSED,
892 int *invalid ATTRIBUTE_UNUSED)
893 {
894 return (insn >> 9) & 0x7c;
895 }
896
897 static unsigned long
898 insert_ev8 (unsigned long insn,
899 long value,
900 int dialect ATTRIBUTE_UNUSED,
901 const char **errmsg)
902 {
903 if ((value & 7) != 0)
904 *errmsg = _("offset not a multiple of 8");
905 if ((value > 248) != 0)
906 *errmsg = _("offset greater than 248");
907 return insn | ((value & 0xf8) << 8);
908 }
909
910 static long
911 extract_ev8 (unsigned long insn,
912 int dialect ATTRIBUTE_UNUSED,
913 int *invalid ATTRIBUTE_UNUSED)
914 {
915 return (insn >> 8) & 0xf8;
916 }
917
918 /* The DS field in a DS form instruction. This is like D, but the
919 lower two bits are forced to zero. */
920
921 /*ARGSUSED*/
922 static unsigned long
923 insert_ds (unsigned long insn,
924 long value,
925 int dialect ATTRIBUTE_UNUSED,
926 const char **errmsg)
927 {
928 if ((value & 3) != 0)
929 *errmsg = _("offset not a multiple of 4");
930 return insn | (value & 0xfffc);
931 }
932
933 /*ARGSUSED*/
934 static long
935 extract_ds (unsigned long insn,
936 int dialect ATTRIBUTE_UNUSED,
937 int *invalid ATTRIBUTE_UNUSED)
938 {
939 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
940 }
941
942 /* The DE field in a DE form instruction. */
943
944 /*ARGSUSED*/
945 static unsigned long
946 insert_de (unsigned long insn,
947 long value,
948 int dialect ATTRIBUTE_UNUSED,
949 const char **errmsg)
950 {
951 if (value > 2047 || value < -2048)
952 *errmsg = _("offset not between -2048 and 2047");
953 return insn | ((value << 4) & 0xfff0);
954 }
955
956 /*ARGSUSED*/
957 static long
958 extract_de (unsigned long insn,
959 int dialect ATTRIBUTE_UNUSED,
960 int *invalid ATTRIBUTE_UNUSED)
961 {
962 return (insn & 0xfff0) >> 4;
963 }
964
965 /* The DES field in a DES form instruction. */
966
967 /*ARGSUSED*/
968 static unsigned long
969 insert_des (unsigned long insn,
970 long value,
971 int dialect ATTRIBUTE_UNUSED,
972 const char **errmsg)
973 {
974 if (value > 8191 || value < -8192)
975 *errmsg = _("offset not between -8192 and 8191");
976 else if ((value & 3) != 0)
977 *errmsg = _("offset not a multiple of 4");
978 return insn | ((value << 2) & 0xfff0);
979 }
980
981 /*ARGSUSED*/
982 static long
983 extract_des (unsigned long insn,
984 int dialect ATTRIBUTE_UNUSED,
985 int *invalid ATTRIBUTE_UNUSED)
986 {
987 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
988 }
989
990 /* FXM mask in mfcr and mtcrf instructions. */
991
992 static unsigned long
993 insert_fxm (unsigned long insn,
994 long value,
995 int dialect,
996 const char **errmsg)
997 {
998 /* If the optional field on mfcr is missing that means we want to use
999 the old form of the instruction that moves the whole cr. In that
1000 case we'll have VALUE zero. There doesn't seem to be a way to
1001 distinguish this from the case where someone writes mfcr %r3,0. */
1002 if (value == 0)
1003 ;
1004
1005 /* If only one bit of the FXM field is set, we can use the new form
1006 of the instruction, which is faster. Unlike the Power4 branch hint
1007 encoding, this is not backward compatible. */
1008 else if ((dialect & PPC_OPCODE_POWER4) != 0 && (value & -value) == value)
1009 insn |= 1 << 20;
1010
1011 /* Any other value on mfcr is an error. */
1012 else if ((insn & (0x3ff << 1)) == 19 << 1)
1013 {
1014 *errmsg = _("ignoring invalid mfcr mask");
1015 value = 0;
1016 }
1017
1018 return insn | ((value & 0xff) << 12);
1019 }
1020
1021 static long
1022 extract_fxm (unsigned long insn,
1023 int dialect,
1024 int *invalid)
1025 {
1026 long mask = (insn >> 12) & 0xff;
1027
1028 /* Is this a Power4 insn? */
1029 if ((insn & (1 << 20)) != 0)
1030 {
1031 if ((dialect & PPC_OPCODE_POWER4) == 0)
1032 *invalid = 1;
1033 else
1034 {
1035 /* Exactly one bit of MASK should be set. */
1036 if (mask == 0 || (mask & -mask) != mask)
1037 *invalid = 1;
1038 }
1039 }
1040
1041 /* Check that non-power4 form of mfcr has a zero MASK. */
1042 else if ((insn & (0x3ff << 1)) == 19 << 1)
1043 {
1044 if (mask != 0)
1045 *invalid = 1;
1046 }
1047
1048 return mask;
1049 }
1050
1051 /* The LI field in an I form instruction. The lower two bits are
1052 forced to zero. */
1053
1054 /*ARGSUSED*/
1055 static unsigned long
1056 insert_li (unsigned long insn,
1057 long value,
1058 int dialect ATTRIBUTE_UNUSED,
1059 const char **errmsg)
1060 {
1061 if ((value & 3) != 0)
1062 *errmsg = _("ignoring least significant bits in branch offset");
1063 return insn | (value & 0x3fffffc);
1064 }
1065
1066 /*ARGSUSED*/
1067 static long
1068 extract_li (unsigned long insn,
1069 int dialect ATTRIBUTE_UNUSED,
1070 int *invalid ATTRIBUTE_UNUSED)
1071 {
1072 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
1073 }
1074
1075 /* The MB and ME fields in an M form instruction expressed as a single
1076 operand which is itself a bitmask. The extraction function always
1077 marks it as invalid, since we never want to recognize an
1078 instruction which uses a field of this type. */
1079
1080 static unsigned long
1081 insert_mbe (unsigned long insn,
1082 long value,
1083 int dialect ATTRIBUTE_UNUSED,
1084 const char **errmsg)
1085 {
1086 unsigned long uval, mask;
1087 int mb, me, mx, count, last;
1088
1089 uval = value;
1090
1091 if (uval == 0)
1092 {
1093 *errmsg = _("illegal bitmask");
1094 return insn;
1095 }
1096
1097 mb = 0;
1098 me = 32;
1099 if ((uval & 1) != 0)
1100 last = 1;
1101 else
1102 last = 0;
1103 count = 0;
1104
1105 /* mb: location of last 0->1 transition */
1106 /* me: location of last 1->0 transition */
1107 /* count: # transitions */
1108
1109 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1110 {
1111 if ((uval & mask) && !last)
1112 {
1113 ++count;
1114 mb = mx;
1115 last = 1;
1116 }
1117 else if (!(uval & mask) && last)
1118 {
1119 ++count;
1120 me = mx;
1121 last = 0;
1122 }
1123 }
1124 if (me == 0)
1125 me = 32;
1126
1127 if (count != 2 && (count != 0 || ! last))
1128 *errmsg = _("illegal bitmask");
1129
1130 return insn | (mb << 6) | ((me - 1) << 1);
1131 }
1132
1133 static long
1134 extract_mbe (unsigned long insn,
1135 int dialect ATTRIBUTE_UNUSED,
1136 int *invalid)
1137 {
1138 long ret;
1139 int mb, me;
1140 int i;
1141
1142 *invalid = 1;
1143
1144 mb = (insn >> 6) & 0x1f;
1145 me = (insn >> 1) & 0x1f;
1146 if (mb < me + 1)
1147 {
1148 ret = 0;
1149 for (i = mb; i <= me; i++)
1150 ret |= 1L << (31 - i);
1151 }
1152 else if (mb == me + 1)
1153 ret = ~0;
1154 else /* (mb > me + 1) */
1155 {
1156 ret = ~0;
1157 for (i = me + 1; i < mb; i++)
1158 ret &= ~(1L << (31 - i));
1159 }
1160 return ret;
1161 }
1162
1163 /* The MB or ME field in an MD or MDS form instruction. The high bit
1164 is wrapped to the low end. */
1165
1166 /*ARGSUSED*/
1167 static unsigned long
1168 insert_mb6 (unsigned long insn,
1169 long value,
1170 int dialect ATTRIBUTE_UNUSED,
1171 const char **errmsg ATTRIBUTE_UNUSED)
1172 {
1173 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1174 }
1175
1176 /*ARGSUSED*/
1177 static long
1178 extract_mb6 (unsigned long insn,
1179 int dialect ATTRIBUTE_UNUSED,
1180 int *invalid ATTRIBUTE_UNUSED)
1181 {
1182 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1183 }
1184
1185 /* The NB field in an X form instruction. The value 32 is stored as
1186 0. */
1187
1188 static unsigned long
1189 insert_nb (unsigned long insn,
1190 long value,
1191 int dialect ATTRIBUTE_UNUSED,
1192 const char **errmsg)
1193 {
1194 if (value < 0 || value > 32)
1195 *errmsg = _("value out of range");
1196 if (value == 32)
1197 value = 0;
1198 return insn | ((value & 0x1f) << 11);
1199 }
1200
1201 /*ARGSUSED*/
1202 static long
1203 extract_nb (unsigned long insn,
1204 int dialect ATTRIBUTE_UNUSED,
1205 int *invalid ATTRIBUTE_UNUSED)
1206 {
1207 long ret;
1208
1209 ret = (insn >> 11) & 0x1f;
1210 if (ret == 0)
1211 ret = 32;
1212 return ret;
1213 }
1214
1215 /* The NSI field in a D form instruction. This is the same as the SI
1216 field, only negated. The extraction function always marks it as
1217 invalid, since we never want to recognize an instruction which uses
1218 a field of this type. */
1219
1220 /*ARGSUSED*/
1221 static unsigned long
1222 insert_nsi (unsigned long insn,
1223 long value,
1224 int dialect ATTRIBUTE_UNUSED,
1225 const char **errmsg ATTRIBUTE_UNUSED)
1226 {
1227 return insn | (-value & 0xffff);
1228 }
1229
1230 static long
1231 extract_nsi (unsigned long insn,
1232 int dialect ATTRIBUTE_UNUSED,
1233 int *invalid)
1234 {
1235 *invalid = 1;
1236 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1237 }
1238
1239 /* The RA field in a D or X form instruction which is an updating
1240 load, which means that the RA field may not be zero and may not
1241 equal the RT field. */
1242
1243 static unsigned long
1244 insert_ral (unsigned long insn,
1245 long value,
1246 int dialect ATTRIBUTE_UNUSED,
1247 const char **errmsg)
1248 {
1249 if (value == 0
1250 || (unsigned long) value == ((insn >> 21) & 0x1f))
1251 *errmsg = "invalid register operand when updating";
1252 return insn | ((value & 0x1f) << 16);
1253 }
1254
1255 /* The RA field in an lmw instruction, which has special value
1256 restrictions. */
1257
1258 static unsigned long
1259 insert_ram (unsigned long insn,
1260 long value,
1261 int dialect ATTRIBUTE_UNUSED,
1262 const char **errmsg)
1263 {
1264 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1265 *errmsg = _("index register in load range");
1266 return insn | ((value & 0x1f) << 16);
1267 }
1268
1269 /* The RA field in the DQ form lq instruction, which has special
1270 value restrictions. */
1271
1272 /*ARGSUSED*/
1273 static unsigned long
1274 insert_raq (unsigned long insn,
1275 long value,
1276 int dialect ATTRIBUTE_UNUSED,
1277 const char **errmsg)
1278 {
1279 long rtvalue = (insn & RT_MASK) >> 21;
1280
1281 if (value == rtvalue)
1282 *errmsg = _("source and target register operands must be different");
1283 return insn | ((value & 0x1f) << 16);
1284 }
1285
1286 /* The RA field in a D or X form instruction which is an updating
1287 store or an updating floating point load, which means that the RA
1288 field may not be zero. */
1289
1290 static unsigned long
1291 insert_ras (unsigned long insn,
1292 long value,
1293 int dialect ATTRIBUTE_UNUSED,
1294 const char **errmsg)
1295 {
1296 if (value == 0)
1297 *errmsg = _("invalid register operand when updating");
1298 return insn | ((value & 0x1f) << 16);
1299 }
1300
1301 /* The RB field in an X form instruction when it must be the same as
1302 the RS field in the instruction. This is used for extended
1303 mnemonics like mr. This operand is marked FAKE. The insertion
1304 function just copies the BT field into the BA field, and the
1305 extraction function just checks that the fields are the same. */
1306
1307 /*ARGSUSED*/
1308 static unsigned long
1309 insert_rbs (unsigned long insn,
1310 long value ATTRIBUTE_UNUSED,
1311 int dialect ATTRIBUTE_UNUSED,
1312 const char **errmsg ATTRIBUTE_UNUSED)
1313 {
1314 return insn | (((insn >> 21) & 0x1f) << 11);
1315 }
1316
1317 static long
1318 extract_rbs (unsigned long insn,
1319 int dialect ATTRIBUTE_UNUSED,
1320 int *invalid)
1321 {
1322 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1323 *invalid = 1;
1324 return 0;
1325 }
1326
1327 /* The RT field of the DQ form lq instruction, which has special
1328 value restrictions. */
1329
1330 /*ARGSUSED*/
1331 static unsigned long
1332 insert_rtq (unsigned long insn,
1333 long value,
1334 int dialect ATTRIBUTE_UNUSED,
1335 const char **errmsg)
1336 {
1337 if ((value & 1) != 0)
1338 *errmsg = _("target register operand must be even");
1339 return insn | ((value & 0x1f) << 21);
1340 }
1341
1342 /* The RS field of the DS form stq instruction, which has special
1343 value restrictions. */
1344
1345 /*ARGSUSED*/
1346 static unsigned long
1347 insert_rsq (unsigned long insn,
1348 long value ATTRIBUTE_UNUSED,
1349 int dialect ATTRIBUTE_UNUSED,
1350 const char **errmsg)
1351 {
1352 if ((value & 1) != 0)
1353 *errmsg = _("source register operand must be even");
1354 return insn | ((value & 0x1f) << 21);
1355 }
1356
1357 /* The SH field in an MD form instruction. This is split. */
1358
1359 /*ARGSUSED*/
1360 static unsigned long
1361 insert_sh6 (unsigned long insn,
1362 long value,
1363 int dialect ATTRIBUTE_UNUSED,
1364 const char **errmsg ATTRIBUTE_UNUSED)
1365 {
1366 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1367 }
1368
1369 /*ARGSUSED*/
1370 static long
1371 extract_sh6 (unsigned long insn,
1372 int dialect ATTRIBUTE_UNUSED,
1373 int *invalid ATTRIBUTE_UNUSED)
1374 {
1375 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1376 }
1377
1378 /* The SPR field in an XFX form instruction. This is flipped--the
1379 lower 5 bits are stored in the upper 5 and vice- versa. */
1380
1381 static unsigned long
1382 insert_spr (unsigned long insn,
1383 long value,
1384 int dialect ATTRIBUTE_UNUSED,
1385 const char **errmsg ATTRIBUTE_UNUSED)
1386 {
1387 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1388 }
1389
1390 static long
1391 extract_spr (unsigned long insn,
1392 int dialect ATTRIBUTE_UNUSED,
1393 int *invalid ATTRIBUTE_UNUSED)
1394 {
1395 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1396 }
1397
1398 /* The TBR field in an XFX instruction. This is just like SPR, but it
1399 is optional. When TBR is omitted, it must be inserted as 268 (the
1400 magic number of the TB register). These functions treat 0
1401 (indicating an omitted optional operand) as 268. This means that
1402 ``mftb 4,0'' is not handled correctly. This does not matter very
1403 much, since the architecture manual does not define mftb as
1404 accepting any values other than 268 or 269. */
1405
1406 #define TB (268)
1407
1408 static unsigned long
1409 insert_tbr (unsigned long insn,
1410 long value,
1411 int dialect ATTRIBUTE_UNUSED,
1412 const char **errmsg ATTRIBUTE_UNUSED)
1413 {
1414 if (value == 0)
1415 value = TB;
1416 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1417 }
1418
1419 static long
1420 extract_tbr (unsigned long insn,
1421 int dialect ATTRIBUTE_UNUSED,
1422 int *invalid ATTRIBUTE_UNUSED)
1423 {
1424 long ret;
1425
1426 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1427 if (ret == TB)
1428 ret = 0;
1429 return ret;
1430 }
1431 \f
1432 /* Macros used to form opcodes. */
1433
1434 /* The main opcode. */
1435 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1436 #define OP_MASK OP (0x3f)
1437
1438 /* The main opcode combined with a trap code in the TO field of a D
1439 form instruction. Used for extended mnemonics for the trap
1440 instructions. */
1441 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1442 #define OPTO_MASK (OP_MASK | TO_MASK)
1443
1444 /* The main opcode combined with a comparison size bit in the L field
1445 of a D form or X form instruction. Used for extended mnemonics for
1446 the comparison instructions. */
1447 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1448 #define OPL_MASK OPL (0x3f,1)
1449
1450 /* An A form instruction. */
1451 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1452 #define A_MASK A (0x3f, 0x1f, 1)
1453
1454 /* An A_MASK with the FRB field fixed. */
1455 #define AFRB_MASK (A_MASK | FRB_MASK)
1456
1457 /* An A_MASK with the FRC field fixed. */
1458 #define AFRC_MASK (A_MASK | FRC_MASK)
1459
1460 /* An A_MASK with the FRA and FRC fields fixed. */
1461 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1462
1463 /* A B form instruction. */
1464 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1465 #define B_MASK B (0x3f, 1, 1)
1466
1467 /* A B form instruction setting the BO field. */
1468 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1469 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1470
1471 /* A BBO_MASK with the y bit of the BO field removed. This permits
1472 matching a conditional branch regardless of the setting of the y
1473 bit. Similarly for the 'at' bits used for power4 branch hints. */
1474 #define Y_MASK (((unsigned long) 1) << 21)
1475 #define AT1_MASK (((unsigned long) 3) << 21)
1476 #define AT2_MASK (((unsigned long) 9) << 21)
1477 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1478 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1479
1480 /* A B form instruction setting the BO field and the condition bits of
1481 the BI field. */
1482 #define BBOCB(op, bo, cb, aa, lk) \
1483 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1484 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1485
1486 /* A BBOCB_MASK with the y bit of the BO field removed. */
1487 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1488 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1489 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1490
1491 /* A BBOYCB_MASK in which the BI field is fixed. */
1492 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1493 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1494
1495 /* An Context form instruction. */
1496 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1497 #define CTX_MASK CTX(0x3f, 0x7)
1498
1499 /* An User Context form instruction. */
1500 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1501 #define UCTX_MASK UCTX(0x3f, 0x1f)
1502
1503 /* The main opcode mask with the RA field clear. */
1504 #define DRA_MASK (OP_MASK | RA_MASK)
1505
1506 /* A DS form instruction. */
1507 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1508 #define DS_MASK DSO (0x3f, 3)
1509
1510 /* A DE form instruction. */
1511 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1512 #define DE_MASK DEO (0x3e, 0xf)
1513
1514 /* An EVSEL form instruction. */
1515 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1516 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1517
1518 /* An M form instruction. */
1519 #define M(op, rc) (OP (op) | ((rc) & 1))
1520 #define M_MASK M (0x3f, 1)
1521
1522 /* An M form instruction with the ME field specified. */
1523 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1524
1525 /* An M_MASK with the MB and ME fields fixed. */
1526 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1527
1528 /* An M_MASK with the SH and ME fields fixed. */
1529 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1530
1531 /* An MD form instruction. */
1532 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1533 #define MD_MASK MD (0x3f, 0x7, 1)
1534
1535 /* An MD_MASK with the MB field fixed. */
1536 #define MDMB_MASK (MD_MASK | MB6_MASK)
1537
1538 /* An MD_MASK with the SH field fixed. */
1539 #define MDSH_MASK (MD_MASK | SH6_MASK)
1540
1541 /* An MDS form instruction. */
1542 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1543 #define MDS_MASK MDS (0x3f, 0xf, 1)
1544
1545 /* An MDS_MASK with the MB field fixed. */
1546 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1547
1548 /* An SC form instruction. */
1549 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1550 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1551
1552 /* An VX form instruction. */
1553 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1554
1555 /* The mask for an VX form instruction. */
1556 #define VX_MASK VX(0x3f, 0x7ff)
1557
1558 /* An VA form instruction. */
1559 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1560
1561 /* The mask for an VA form instruction. */
1562 #define VXA_MASK VXA(0x3f, 0x3f)
1563
1564 /* An VXR form instruction. */
1565 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1566
1567 /* The mask for a VXR form instruction. */
1568 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1569
1570 /* An X form instruction. */
1571 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1572
1573 /* An X form instruction with the RC bit specified. */
1574 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1575
1576 /* The mask for an X form instruction. */
1577 #define X_MASK XRC (0x3f, 0x3ff, 1)
1578
1579 /* An X_MASK with the RA field fixed. */
1580 #define XRA_MASK (X_MASK | RA_MASK)
1581
1582 /* An X_MASK with the RB field fixed. */
1583 #define XRB_MASK (X_MASK | RB_MASK)
1584
1585 /* An X_MASK with the RT field fixed. */
1586 #define XRT_MASK (X_MASK | RT_MASK)
1587
1588 /* An X_MASK with the RA and RB fields fixed. */
1589 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1590
1591 /* An XRARB_MASK, but with the L bit clear. */
1592 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1593
1594 /* An X_MASK with the RT and RA fields fixed. */
1595 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1596
1597 /* An XRTRA_MASK, but with L bit clear. */
1598 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1599
1600 /* An X form comparison instruction. */
1601 #define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1602
1603 /* The mask for an X form comparison instruction. */
1604 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1605
1606 /* The mask for an X form comparison instruction with the L field
1607 fixed. */
1608 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1609
1610 /* An X form trap instruction with the TO field specified. */
1611 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1612 #define XTO_MASK (X_MASK | TO_MASK)
1613
1614 /* An X form tlb instruction with the SH field specified. */
1615 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1616 #define XTLB_MASK (X_MASK | SH_MASK)
1617
1618 /* An X form sync instruction. */
1619 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1620
1621 /* An X form sync instruction with everything filled in except the LS field. */
1622 #define XSYNC_MASK (0xff9fffff)
1623
1624 /* An X form AltiVec dss instruction. */
1625 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1626 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1627
1628 /* An XFL form instruction. */
1629 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1630 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1631
1632 /* An X form isel instruction. */
1633 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1634 #define XISEL_MASK XISEL(0x3f, 0x1f)
1635
1636 /* An XL form instruction with the LK field set to 0. */
1637 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1638
1639 /* An XL form instruction which uses the LK field. */
1640 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1641
1642 /* The mask for an XL form instruction. */
1643 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1644
1645 /* An XL form instruction which explicitly sets the BO field. */
1646 #define XLO(op, bo, xop, lk) \
1647 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1648 #define XLO_MASK (XL_MASK | BO_MASK)
1649
1650 /* An XL form instruction which explicitly sets the y bit of the BO
1651 field. */
1652 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1653 #define XLYLK_MASK (XL_MASK | Y_MASK)
1654
1655 /* An XL form instruction which sets the BO field and the condition
1656 bits of the BI field. */
1657 #define XLOCB(op, bo, cb, xop, lk) \
1658 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1659 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1660
1661 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1662 #define XLBB_MASK (XL_MASK | BB_MASK)
1663 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1664 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1665
1666 /* An XL_MASK with the BO and BB fields fixed. */
1667 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1668
1669 /* An XL_MASK with the BO, BI and BB fields fixed. */
1670 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1671
1672 /* An XO form instruction. */
1673 #define XO(op, xop, oe, rc) \
1674 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1675 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1676
1677 /* An XO_MASK with the RB field fixed. */
1678 #define XORB_MASK (XO_MASK | RB_MASK)
1679
1680 /* An XS form instruction. */
1681 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1682 #define XS_MASK XS (0x3f, 0x1ff, 1)
1683
1684 /* A mask for the FXM version of an XFX form instruction. */
1685 #define XFXFXM_MASK (X_MASK | (1 << 11))
1686
1687 /* An XFX form instruction with the FXM field filled in. */
1688 #define XFXM(op, xop, fxm) \
1689 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1690
1691 /* An XFX form instruction with the SPR field filled in. */
1692 #define XSPR(op, xop, spr) \
1693 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1694 #define XSPR_MASK (X_MASK | SPR_MASK)
1695
1696 /* An XFX form instruction with the SPR field filled in except for the
1697 SPRBAT field. */
1698 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1699
1700 /* An XFX form instruction with the SPR field filled in except for the
1701 SPRG field. */
1702 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1703
1704 /* An X form instruction with everything filled in except the E field. */
1705 #define XE_MASK (0xffff7fff)
1706
1707 /* An X form user context instruction. */
1708 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1709 #define XUC_MASK XUC(0x3f, 0x1f)
1710
1711 /* The BO encodings used in extended conditional branch mnemonics. */
1712 #define BODNZF (0x0)
1713 #define BODNZFP (0x1)
1714 #define BODZF (0x2)
1715 #define BODZFP (0x3)
1716 #define BODNZT (0x8)
1717 #define BODNZTP (0x9)
1718 #define BODZT (0xa)
1719 #define BODZTP (0xb)
1720
1721 #define BOF (0x4)
1722 #define BOFP (0x5)
1723 #define BOFM4 (0x6)
1724 #define BOFP4 (0x7)
1725 #define BOT (0xc)
1726 #define BOTP (0xd)
1727 #define BOTM4 (0xe)
1728 #define BOTP4 (0xf)
1729
1730 #define BODNZ (0x10)
1731 #define BODNZP (0x11)
1732 #define BODZ (0x12)
1733 #define BODZP (0x13)
1734 #define BODNZM4 (0x18)
1735 #define BODNZP4 (0x19)
1736 #define BODZM4 (0x1a)
1737 #define BODZP4 (0x1b)
1738
1739 #define BOU (0x14)
1740
1741 /* The BI condition bit encodings used in extended conditional branch
1742 mnemonics. */
1743 #define CBLT (0)
1744 #define CBGT (1)
1745 #define CBEQ (2)
1746 #define CBSO (3)
1747
1748 /* The TO encodings used in extended trap mnemonics. */
1749 #define TOLGT (0x1)
1750 #define TOLLT (0x2)
1751 #define TOEQ (0x4)
1752 #define TOLGE (0x5)
1753 #define TOLNL (0x5)
1754 #define TOLLE (0x6)
1755 #define TOLNG (0x6)
1756 #define TOGT (0x8)
1757 #define TOGE (0xc)
1758 #define TONL (0xc)
1759 #define TOLT (0x10)
1760 #define TOLE (0x14)
1761 #define TONG (0x14)
1762 #define TONE (0x18)
1763 #define TOU (0x1f)
1764 \f
1765 /* Smaller names for the flags so each entry in the opcodes table will
1766 fit on a single line. */
1767 #undef PPC
1768 #define PPC PPC_OPCODE_PPC
1769 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1770 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1771 #define POWER4 PPC_OPCODE_POWER4
1772 #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1773 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
1774 #define PPC403 PPC_OPCODE_403
1775 #define PPC405 PPC403
1776 #define PPC440 PPC_OPCODE_440
1777 #define PPC750 PPC
1778 #define PPC860 PPC
1779 #define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_PPC
1780 #define POWER PPC_OPCODE_POWER
1781 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1782 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1783 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1784 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1785 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1786 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1787 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1788 #define MFDEC1 PPC_OPCODE_POWER
1789 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1790 #define BOOKE PPC_OPCODE_BOOKE
1791 #define BOOKE64 PPC_OPCODE_BOOKE64
1792 #define CLASSIC PPC_OPCODE_CLASSIC
1793 #define PPCSPE PPC_OPCODE_SPE
1794 #define PPCISEL PPC_OPCODE_ISEL
1795 #define PPCEFS PPC_OPCODE_EFS
1796 #define PPCBRLK PPC_OPCODE_BRLOCK
1797 #define PPCPMR PPC_OPCODE_PMR
1798 #define PPCCHLK PPC_OPCODE_CACHELCK
1799 #define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1800 #define PPCRFMCI PPC_OPCODE_RFMCI
1801 \f
1802 /* The opcode table.
1803
1804 The format of the opcode table is:
1805
1806 NAME OPCODE MASK FLAGS { OPERANDS }
1807
1808 NAME is the name of the instruction.
1809 OPCODE is the instruction opcode.
1810 MASK is the opcode mask; this is used to tell the disassembler
1811 which bits in the actual opcode must match OPCODE.
1812 FLAGS are flags indicated what processors support the instruction.
1813 OPERANDS is the list of operands.
1814
1815 The disassembler reads the table in order and prints the first
1816 instruction which matches, so this table is sorted to put more
1817 specific instructions before more general instructions. It is also
1818 sorted by major opcode. */
1819
1820 const struct powerpc_opcode powerpc_opcodes[] = {
1821 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
1822 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1823 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1824 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1825 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1826 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1827 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1828 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1829 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1830 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1831 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1832 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1833 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1834 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1835 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1836 { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1837
1838 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1839 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1840 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1841 { "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1842 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1843 { "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1844 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1845 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1846 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1847 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1848 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1849 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1850 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1851 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1852 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1853 { "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1854 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1855 { "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1856 { "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1857 { "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1858 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1859 { "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1860 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1861 { "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1862 { "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1863 { "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1864 { "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1865 { "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1866 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1867 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
1868
1869 { "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1870 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1871 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1872 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1873 { "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1874 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1875 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1876 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1877 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1878 { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1879 { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1880 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1881 { "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1882 { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1883 { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1884 { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1885 { "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1886 { "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1887 { "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1888 { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1889 { "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1890 { "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1891 { "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1892 { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1893 { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1894 { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1895 { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1896 { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1897 { "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1898 { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1899 { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1900 { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1901 { "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1902 { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1903 { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1904 { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1905 { "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1906 { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1907 { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1908 { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1909 { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1910 { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1911 { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1912 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1913 { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1914 { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1915 { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1916 { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1917 { "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1918 { "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1919 { "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1920 { "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1921 { "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1922 { "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1923 { "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1924 { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1925 { "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1926 { "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1927 { "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1928 { "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1929 { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1930 { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1931 { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1932 { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1933 { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1934 { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1935 { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1936 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1937 { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1938 { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1939 { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1940 { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1941 { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1942 { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1943 { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1944 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1945 { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1946 { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1947 { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1948 { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1949 { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1950 { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1951 { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1952 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1953 { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
1954 { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
1955 { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
1956 { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
1957 { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
1958 { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
1959 { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
1960 { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
1961 { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
1962 { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
1963 { "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
1964 { "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
1965 { "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
1966 { "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
1967 { "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
1968 { "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
1969 { "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
1970 { "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
1971 { "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
1972 { "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
1973 { "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
1974 { "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1975 { "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1976 { "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1977 { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1978 { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1979 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1980 { "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1981 { "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1982 { "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1983 { "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1984 { "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1985 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1986 { "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1987 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1988 { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1989 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1990 { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1991 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1992 { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1993 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1994 { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1995 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1996 { "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1997 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1998 { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1999 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2000 { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2001 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2002 { "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2003 { "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2004 { "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
2005 { "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
2006 { "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2007 { "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
2008 { "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
2009 { "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
2010 { "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
2011 { "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
2012 { "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
2013 { "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
2014 { "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2015 { "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2016 { "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
2017 { "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
2018 { "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
2019 { "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
2020 { "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
2021 { "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2022 { "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2023 { "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2024 { "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2025 { "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2026 { "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2027 { "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2028 { "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2029 { "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2030 { "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2031 { "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2032 { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2033 { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2034 { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2035 { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2036 { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2037 { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2038 { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2039 { "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2040 { "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2041 { "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2042 { "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2043 { "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2044 { "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2045 { "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2046 { "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2047 { "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2048 { "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2049 { "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2050 { "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2051 { "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2052 { "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2053 { "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2054 { "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2055 { "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2056 { "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2057 { "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2058 { "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2059 { "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2060 { "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2061 { "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2062 { "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2063 { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2064 { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2065 { "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2066 { "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2067 { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2068 { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2069 { "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2070 { "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2071 { "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
2072 { "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
2073 { "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2074 { "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2075 { "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2076 { "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2077 { "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2078 { "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2079 { "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2080 { "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2081 { "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2082 { "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2083 { "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2084 { "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2085 { "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2086 { "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2087 { "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2088 { "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2089 { "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2090 { "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2091 { "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2092 { "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2093 { "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2094 { "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2095 { "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2096 { "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2097 { "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2098 { "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2099 { "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2100 { "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2101 { "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2102 { "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2103 { "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2104 { "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2105 { "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2106 { "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2107 { "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2108 { "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2109 { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
2110
2111 { "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2112 { "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2113 { "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2114 { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2115 { "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2116 { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2117 { "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2118 { "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2119 { "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2120 { "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2121 { "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2122 { "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2123 { "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2124
2125 { "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2126
2127 { "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2128 { "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2129 { "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2130 { "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2131 { "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2132 { "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2133 { "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2134 { "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2135 { "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2136 { "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2137
2138 { "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2139 { "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2140 { "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2141 { "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2142 { "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2143 { "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2144 { "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2145 { "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2146 { "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2147 { "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
2148 { "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2149 { "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2150 { "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2151 { "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2152
2153 { "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2154 { "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2155 { "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2156 { "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2157 { "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2158 { "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2159
2160 { "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2161 { "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2162 { "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2163 { "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2164 { "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2165 { "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2166 { "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2167 { "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2168 { "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2169 { "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2170 { "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2171 { "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2172 { "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2173 { "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2174 { "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2175 { "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2176 { "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2177 { "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2178 { "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2179 { "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2180 { "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2181 { "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2182
2183 { "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2184 { "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2185 { "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2186 { "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2187 { "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2188 { "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2189 { "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2190 { "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2191 { "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2192 { "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2193 { "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2194 { "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2195 { "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2196 { "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2197
2198 { "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2199 { "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2200 { "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2201 { "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2202 { "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2203 { "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2204 { "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2205 { "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2206 { "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2207 { "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2208 { "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2209 { "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2210 { "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2211 { "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2212 { "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2213 { "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2214 { "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2215 { "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2216 { "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2217 { "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2218 { "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2219 { "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2220 { "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2221
2222 { "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2223 { "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2224 { "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2225 { "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2226 { "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2227 { "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2228 { "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2229 { "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2230 { "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2231 { "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2232 { "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2233 { "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2234 { "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2235 { "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2236 { "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2237 { "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2238 { "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2239 { "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2240 { "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2241 { "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2242 { "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2243 { "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2244 { "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2245
2246 { "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2247 { "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2248 { "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2249 { "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2250 { "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2251 { "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2252 { "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2253 { "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2254 { "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2255 { "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2256 { "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2257 { "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2258 { "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2259 { "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2260 { "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2261 { "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2262
2263 { "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2264 { "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2265 { "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2266 { "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2267 { "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2268 { "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2269 { "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2270 { "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2271 { "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2272 { "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2273 { "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2274 { "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2275
2276 { "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2277 { "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2278 { "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2279 { "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2280 { "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2281 { "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2282 { "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2283 { "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2284 { "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2285 { "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2286 { "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2287 { "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2288
2289 { "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2290 { "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2291 { "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2292 { "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2293 { "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2294 { "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2295
2296 { "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2297 { "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2298 { "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2299 { "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2300 { "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2301 { "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2302
2303 { "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2304 { "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2305 { "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2306 { "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2307 { "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2308 { "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2309 { "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2310 { "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2311
2312 { "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2313 { "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2314
2315 { "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2316 { "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2317 { "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2318 { "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2319
2320 { "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2321 { "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2322 { "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2323 { "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2324
2325 { "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2326 { "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2327 { "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2328 { "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2329 { "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2330 { "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2331 { "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2332 { "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2333
2334 { "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2335 { "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2336 { "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2337 { "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2338
2339 { "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2340 { "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2341 { "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2342 { "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2343
2344 { "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2345 { "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2346 { "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2347 { "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2348
2349 { "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2350 { "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2351 { "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2352 { "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2353
2354 { "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2355
2356 { "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2357 { "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
2358
2359 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2360 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2361
2362 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2363 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2364
2365 { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2366
2367 { "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2368 { "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2369 { "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2370 { "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2371
2372 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2373 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
2374 { "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
2375 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2376
2377 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2378 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
2379 { "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
2380 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2381
2382 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2383 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2384 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2385
2386 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2387 { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2388 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2389
2390 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2391 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2392 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } },
2393 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } },
2394 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } },
2395 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } },
2396
2397 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2398 { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2399 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } },
2400 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } },
2401 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } },
2402
2403 { "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2404 { "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2405 { "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2406 { "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2407 { "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2408 { "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2409 { "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2410 { "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2411 { "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2412 { "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2413 { "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2414 { "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2415 { "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2416 { "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2417 { "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2418 { "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2419 { "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2420 { "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2421 { "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2422 { "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2423 { "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2424 { "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2425 { "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2426 { "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2427 { "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2428 { "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2429 { "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2430 { "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
2431 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2432 { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2433 { "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2434 { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2435 { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2436 { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2437 { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2438 { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2439 { "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2440 { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2441 { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2442 { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2443 { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2444 { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2445 { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2446 { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2447 { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2448 { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2449 { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2450 { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2451 { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2452 { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2453 { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2454 { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2455 { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2456 { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2457 { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2458 { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2459 { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2460 { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2461 { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2462 { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2463 { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2464 { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2465 { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2466 { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2467 { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2468 { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2469 { "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2470 { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2471 { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2472 { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2473 { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2474 { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2475 { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2476 { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2477 { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2478 { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2479 { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2480 { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2481 { "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2482 { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2483 { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2484 { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2485 { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2486 { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2487 { "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2488 { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2489 { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2490 { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2491 { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2492 { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2493 { "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2494 { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2495 { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2496 { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2497 { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2498 { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2499 { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2500 { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2501 { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2502 { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2503 { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2504 { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2505 { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2506 { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2507 { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2508 { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2509 { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2510 { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2511 { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2512 { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2513 { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2514 { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2515 { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2516 { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2517 { "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2518 { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2519 { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2520 { "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2521 { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2522 { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2523 { "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2524 { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2525 { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2526 { "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2527 { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2528 { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2529 { "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2530 { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2531 { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2532 { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2533 { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2534 { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2535 { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2536 { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2537 { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2538 { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2539 { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2540 { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2541 { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2542 { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2543 { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2544 { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2545 { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2546 { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2547 { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2548 { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2549 { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2550 { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2551 { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2552 { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2553 { "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2554 { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2555 { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2556 { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2557 { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2558 { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2559 { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2560 { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2561 { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2562 { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2563 { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2564 { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2565 { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2566 { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2567 { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2568 { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2569 { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2570 { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2571 { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2572 { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2573 { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2574 { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2575 { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2576 { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2577 { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2578 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2579 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2580 { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2581 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2582 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2583 { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2584 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2585 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2586 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2587 { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2588 { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2589 { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2590 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2591 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2592 { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2593 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2594 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2595 { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2596 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2597 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2598 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2599 { "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2600 { "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2601 { "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2602 { "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2603 { "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2604 { "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2605 { "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2606 { "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2607 { "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2608 { "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2609 { "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2610 { "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2611 { "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2612 { "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2613 { "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2614 { "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2615 { "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2616 { "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2617 { "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2618 { "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2619 { "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2620 { "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2621 { "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2622 { "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2623 { "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2624 { "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2625 { "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2626 { "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2627 { "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2628 { "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2629 { "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2630 { "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2631 { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2632 { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2633 { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2634 { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2635 { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2636 { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2637 { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2638 { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2639 { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2640 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2641 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2642 { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2643 { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2644 { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2645 { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2646 { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2647 { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2648 { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2649 { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2650 { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2651 { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2652 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2653 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2654 { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2655 { "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2656 { "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
2657 { "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
2658 { "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2659 { "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
2660 { "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
2661 { "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2662 { "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2663 { "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
2664 { "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2665 { "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2666 { "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2667
2668 { "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
2669 { "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
2670 { "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
2671 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2672 { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2673
2674 { "b", B(18,0,0), B_MASK, COM, { LI } },
2675 { "bl", B(18,0,1), B_MASK, COM, { LI } },
2676 { "ba", B(18,1,0), B_MASK, COM, { LIA } },
2677 { "bla", B(18,1,1), B_MASK, COM, { LIA } },
2678
2679 { "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
2680
2681 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2682 { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2683 { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2684 { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2685 { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2686 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2687 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2688 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2689 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2690 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2691 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2692 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2693 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2694 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2695 { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2696 { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2697 { "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2698 { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2699 { "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2700 { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2701 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2702 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2703 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2704 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2705 { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2706 { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2707 { "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2708 { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2709 { "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2710 { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2711 { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2712 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2713 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2714 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2715 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2716 { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2717 { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2718 { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2719 { "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2720 { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2721 { "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2722 { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2723 { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2724 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2725 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2726 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2727 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2728 { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2729 { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2730 { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2731 { "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2732 { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2733 { "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2734 { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2735 { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2736 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2737 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2738 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2739 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2740 { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2741 { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2742 { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2743 { "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2744 { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2745 { "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2746 { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2747 { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2748 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2749 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2750 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2751 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2752 { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2753 { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2754 { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2755 { "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2756 { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2757 { "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2758 { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2759 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2760 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2761 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2762 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2763 { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2764 { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2765 { "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2766 { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2767 { "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2768 { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2769 { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2770 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2771 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2772 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2773 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2774 { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2775 { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2776 { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2777 { "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2778 { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2779 { "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2780 { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2781 { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2782 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2783 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2784 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2785 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2786 { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2787 { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2788 { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2789 { "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2790 { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2791 { "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2792 { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2793 { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2794 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2795 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2796 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2797 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2798 { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2799 { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2800 { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2801 { "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2802 { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2803 { "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2804 { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2805 { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2806 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2807 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2808 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2809 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2810 { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2811 { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2812 { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2813 { "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2814 { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2815 { "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2816 { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2817 { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2818 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2819 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2820 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2821 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2822 { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2823 { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2824 { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2825 { "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2826 { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2827 { "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2828 { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2829 { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2830 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2831 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2832 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2833 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2834 { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2835 { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2836 { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2837 { "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2838 { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2839 { "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2840 { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2841 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2842 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2843 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2844 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2845 { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2846 { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2847 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2848 { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2849 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2850 { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2851 { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2852 { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2853 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2854 { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2855 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2856 { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2857 { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2858 { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2859 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2860 { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2861 { "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2862 { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2863 { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2864 { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2865 { "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2866 { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2867 { "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2868 { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2869 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2870 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2871 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2872 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2873 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2874 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2875 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2876 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2877 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2878 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2879 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2880 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2881 { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2882 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2883 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2884 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2885 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2886 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2887 { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2888 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2889 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2890 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2891 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2892 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2893 { "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } },
2894 { "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } },
2895 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2896 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2897 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2898 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2899 { "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2900 { "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
2901 { "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
2902 { "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
2903
2904 { "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2905
2906 { "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2907 { "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
2908 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
2909
2910 { "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
2911 { "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } },
2912
2913 { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2914
2915 { "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
2916
2917 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
2918 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
2919
2920 { "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2921 { "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
2922
2923 { "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
2924
2925 { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
2926
2927 { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2928 { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
2929
2930 { "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
2931
2932 { "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
2933 { "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
2934
2935 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
2936 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
2937 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2938 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2939 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2940 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2941 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2942 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2943 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2944 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2945 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2946 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2947 { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2948 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2949 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2950 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2951 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2952 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2953 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2954 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2955 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2956 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2957 { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2958 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2959 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2960 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2961 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2962 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2963 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2964 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2965 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2966 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2967 { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2968 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2969 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2970 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2971 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2972 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2973 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2974 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2975 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2976 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2977 { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2978 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2979 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2980 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2981 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2982 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2983 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2984 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2985 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2986 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2987 { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2988 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2989 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2990 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2991 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2992 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2993 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2994 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2995 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2996 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2997 { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2998 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2999 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3000 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3001 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3002 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3003 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3004 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3005 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3006 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3007 { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3008 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3009 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3010 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3011 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3012 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3013 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3014 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3015 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3016 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3017 { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3018 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3019 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3020 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3021 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3022 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3023 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3024 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3025 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3026 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3027 { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3028 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3029 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3030 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3031 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3032 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3033 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3034 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3035 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3036 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3037 { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3038 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3039 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3040 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3041 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3042 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3043 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3044 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3045 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3046 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3047 { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3048 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3049 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3050 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3051 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3052 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3053 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3054 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3055 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3056 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3057 { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3058 { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3059 { "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3060 { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3061 { "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3062 { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3063 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3064 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3065 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3066 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3067 { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3068 { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3069 { "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3070 { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3071 { "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3072 { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3073 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3074 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3075 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3076 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3077 { "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } },
3078 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3079 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3080 { "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } },
3081 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3082 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3083 { "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3084 { "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
3085 { "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
3086 { "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
3087
3088 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3089 { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3090
3091 { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3092 { "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3093
3094 { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3095 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3096 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3097 { "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3098 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3099 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3100 { "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3101 { "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3102
3103 { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3104 { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3105
3106 { "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
3107 { "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
3108 { "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3109 { "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3110
3111 { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3112 { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3113 { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3114 { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3115 { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3116 { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3117
3118 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3119 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3120 { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3121
3122 { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3123 { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3124
3125 { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3126 { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3127
3128 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3129 { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3130
3131 { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3132 { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3133
3134 { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3135 { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3136
3137 { "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3138 { "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3139 { "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3140 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3141 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3142 { "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3143
3144 { "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3145 { "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3146
3147 { "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3148 { "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3149
3150 { "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3151 { "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3152
3153 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3154 { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3155 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3156 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3157
3158 { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3159 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3160
3161 { "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3162 { "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3163 { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
3164 { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3165
3166 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3167 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3168 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3169 { "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3170 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3171 { "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3172 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3173 { "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3174 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3175 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3176 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3177 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3178 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3179 { "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3180 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3181 { "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3182 { "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3183 { "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3184 { "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3185 { "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3186 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3187 { "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3188 { "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3189 { "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3190 { "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3191 { "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3192 { "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3193 { "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3194 { "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3195 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3196 { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3197
3198 { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3199 { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3200 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3201 { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3202 { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3203 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3204 { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3205 { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3206 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3207 { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3208 { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3209 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3210
3211 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3212 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3213
3214 { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3215 { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3216 { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3217 { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3218 { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3219 { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3220 { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3221 { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3222
3223 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3224 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3225
3226 { "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3227 { "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3228 { "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3229 { "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3230
3231 { "mfcr", X(31,19), XRARB_MASK, NOPOWER4, { RT } },
3232 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3233
3234 { "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
3235
3236 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } },
3237
3238 { "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
3239 { "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3240
3241 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } },
3242 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3243
3244 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3245 { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3246 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3247 { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3248
3249 { "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3250 { "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3251 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3252 { "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3253
3254 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3255 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3256
3257 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3258 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3259
3260 { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3261 { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3262
3263 { "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3264
3265 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA, RB } },
3266
3267 { "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3268 { "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3269 { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
3270 { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3271
3272 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3273 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3274 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3275 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3276 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3277 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3278 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3279 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3280
3281 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3282
3283 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3284
3285 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3286 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3287
3288 { "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3289
3290 { "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3291
3292 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3293 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3294
3295 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3296 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3297
3298 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3299 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3300 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3301 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3302 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3303 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3304 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3305 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3306 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3307 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3308 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3309 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3310 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3311 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3312 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3313
3314 { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3315 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3316
3317 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3318 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3319
3320 { "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3321 { "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3322
3323 { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3324
3325 { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3326
3327 { "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB } },
3328
3329 { "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
3330
3331 { "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } },
3332
3333 { "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3334
3335 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA, RB } },
3336
3337 { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3338 { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3339 { "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3340 { "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3341
3342 { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3343 { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3344 { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3345 { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3346
3347 { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3348
3349 { "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3350
3351 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3352
3353 { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3354 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3355 { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3356 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3357
3358 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA, RB } },
3359
3360 { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3361
3362 { "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
3363
3364 { "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3365
3366 { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3367 { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3368 { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3369 { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3370 { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3371 { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3372 { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3373 { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3374
3375 { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3376 { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3377 { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3378 { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3379 { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3380 { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3381 { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3382 { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3383
3384 { "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3385
3386 { "mtcr", XFXM(31,144,0xff), XRARB_MASK, COM, { RS }},
3387 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3388
3389 { "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3390
3391 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA, RB } },
3392
3393 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
3394
3395 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } },
3396 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3397
3398 { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA, RB } },
3399
3400 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA, RB } },
3401
3402 { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3403 { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3404
3405 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3406 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3407
3408 { "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
3409
3410 { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3411 { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3412
3413 { "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
3414
3415 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3416
3417 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3418 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA, RB } },
3419
3420 { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3421 { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3422
3423 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3424
3425 { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3426 { "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3427 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3428 { "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3429 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3430 { "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3431 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3432 { "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3433
3434 { "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3435 { "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3436 { "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3437 { "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3438 { "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3439 { "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3440 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3441 { "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3442
3443 { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3444
3445 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } },
3446
3447 { "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } },
3448
3449 { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3450 { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3451
3452 { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3453 { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3454
3455 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA, RB } },
3456
3457 { "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3458
3459 { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3460 { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3461 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3462 { "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3463 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3464 { "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3465 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3466 { "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3467
3468 { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3469 { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3470 { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3471 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3472
3473 { "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3474 { "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3475 { "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3476 { "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3477 { "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3478 { "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3479 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3480 { "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3481
3482 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3483 { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3484 { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3485 { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3486 { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3487 { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3488 { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3489 { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3490
3491 { "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3492 { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3493 { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3494
3495 { "dcbtst", X(31,246), XRT_MASK, PPC, { CT, RA, RB } },
3496
3497 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3498
3499 { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3500 { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3501
3502 { "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3503
3504 { "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3505
3506 { "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3507
3508 { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3509 { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3510 { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3511 { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3512
3513 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3514 { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3515 { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3516 { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3517 { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3518 { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3519 { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3520 { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3521
3522 { "tlbiel", X(31,274), XRTRA_MASK, POWER4, { RB } },
3523
3524 { "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3525
3526 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3527 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3528
3529 { "dcbt", X(31,278), XRT_MASK, PPC, { CT, RA, RB } },
3530
3531 { "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } },
3532
3533 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3534 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3535
3536 { "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3537
3538 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA, RB } },
3539
3540 { "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3541 { "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } },
3542
3543 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3544
3545 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3546
3547 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3548 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3549
3550 { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3551
3552 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3553 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3554 { "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3555 { "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3556 { "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3557 { "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3558 { "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3559 { "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3560 { "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3561 { "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3562 { "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3563 { "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3564 { "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3565 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3566 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3567 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3568 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3569 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3570 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3571 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3572 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3573 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3574 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3575 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3576 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3577 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3578 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3579 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3580 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3581 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3582 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3583 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3584 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3585 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3586 { "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
3587
3588 { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3589 { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3590 { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3591 { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3592
3593 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3594
3595 { "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3596 { "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3597 { "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3598 { "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3599 { "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3600 { "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3601 { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3602 { "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3603 { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3604 { "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3605 { "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3606 { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3607 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3608 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3609 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3610 { "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3611 { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3612 { "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3613 { "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3614 { "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3615 { "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3616 { "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3617 { "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3618 { "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3619 { "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3620 { "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3621 { "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3622 { "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3623 { "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3624 { "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3625 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3626 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3627 { "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3628 { "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3629 { "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3630 { "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3631 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3632 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3633 { "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3634 { "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3635 { "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3636 { "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3637 { "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
3638 { "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
3639 { "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
3640 { "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
3641 { "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3642 { "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3643 { "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3644 { "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3645 { "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
3646 { "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3647 { "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
3648 { "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3649 { "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3650 { "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3651 { "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3652 { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3653 { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3654 { "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3655 { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3656 { "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3657 { "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3658 { "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3659 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3660 { "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3661 { "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
3662 { "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3663 { "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3664 { "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3665 { "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3666 { "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3667 { "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3668 { "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3669 { "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3670 { "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3671 { "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3672 { "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3673 { "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3674 { "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3675 { "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3676 { "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3677 { "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3678 { "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
3679 { "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3680 { "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3681 { "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3682 { "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3683 { "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3684 { "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3685 { "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3686 { "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3687 { "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3688 { "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3689 { "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3690 { "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3691 { "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3692 { "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3693 { "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3694 { "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3695 { "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3696 { "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3697 { "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3698 { "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3699 { "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3700 { "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
3701 { "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
3702 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3703 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3704 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3705 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3706 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3707 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3708 { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3709 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3710 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3711 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3712 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3713 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3714 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3715 { "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3716 { "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3717 { "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3718 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3719 { "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3720 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3721 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3722 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3723 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3724 { "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3725 { "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3726 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3727 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3728 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3729 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3730 { "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3731 { "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3732 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3733 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3734 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3735 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3736 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3737 { "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3738 { "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3739 { "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3740 { "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3741 { "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3742 { "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3743 { "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3744 { "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3745 { "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
3746 { "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3747 { "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
3748 { "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
3749 { "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
3750 { "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
3751 { "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
3752 { "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
3753 { "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
3754 { "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
3755 { "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
3756 { "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
3757 { "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
3758 { "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3759 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3760 { "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3761 { "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3762 { "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3763 { "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3764 { "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3765 { "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3766 { "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3767 { "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3768 { "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3769 { "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3770 { "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3771 { "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3772 { "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3773 { "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3774 { "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3775 { "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3776 { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3777
3778 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } },
3779
3780 { "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3781 { "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3782
3783 { "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } },
3784
3785 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA, RB } },
3786
3787 { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3788 { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3789
3790 { "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
3791
3792 { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3793 { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3794 { "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3795 { "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3796
3797 { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3798 { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3799 { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3800 { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3801
3802 { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3803
3804 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3805
3806 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3807
3808 { "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3809
3810 { "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3811
3812 { "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3813
3814 { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3815 { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3816
3817 { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3818 { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3819
3820 { "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
3821
3822 { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3823
3824 { "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } },
3825
3826 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3827
3828 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3829
3830 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3831
3832 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3833
3834 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3835 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3836
3837 { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3838 { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3839
3840 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA, RB } },
3841
3842 { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3843
3844 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3845
3846 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3847
3848 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3849
3850 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3851 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3852 { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3853 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3854
3855 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
3856 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
3857 { "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
3858 { "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
3859 { "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
3860 { "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
3861 { "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
3862 { "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
3863 { "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
3864 { "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
3865 { "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
3866 { "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
3867 { "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
3868 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
3869 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
3870 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
3871 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
3872 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
3873 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
3874 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
3875 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
3876 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
3877 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
3878 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
3879 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
3880 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
3881 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
3882 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
3883 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
3884 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
3885 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
3886 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
3887 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
3888 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
3889 { "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
3890
3891 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3892 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3893
3894 { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3895 { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3896 { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3897 { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3898
3899 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3900 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3901
3902 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
3903 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
3904 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
3905 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
3906
3907 { "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
3908 { "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
3909 { "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
3910 { "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
3911 { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
3912 { "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
3913 { "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
3914 { "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
3915 { "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
3916 { "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
3917 { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
3918 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
3919 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
3920 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
3921 { "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
3922 { "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
3923 { "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
3924 { "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
3925 { "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
3926 { "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
3927 { "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
3928 { "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
3929 { "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
3930 { "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
3931 { "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
3932 { "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
3933 { "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
3934 { "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
3935 { "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
3936 { "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
3937 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
3938 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
3939 { "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
3940 { "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
3941 { "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
3942 { "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
3943 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
3944 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
3945 { "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
3946 { "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
3947 { "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
3948 { "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
3949 { "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } },
3950 { "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
3951 { "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
3952 { "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
3953 { "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
3954 { "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
3955 { "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
3956 { "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
3957 { "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
3958 { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
3959 { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
3960 { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
3961 { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
3962 { "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
3963 { "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
3964 { "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
3965 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
3966 { "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
3967 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
3968 { "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
3969 { "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
3970 { "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
3971 { "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
3972 { "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
3973 { "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
3974 { "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
3975 { "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
3976 { "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
3977 { "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
3978 { "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
3979 { "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
3980 { "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
3981 { "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
3982 { "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
3983 { "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
3984 { "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
3985 { "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
3986 { "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
3987 { "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
3988 { "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
3989 { "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
3990 { "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
3991 { "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
3992 { "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
3993 { "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
3994 { "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
3995 { "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
3996 { "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
3997 { "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
3998 { "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
3999 { "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
4000 { "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
4001 { "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
4002 { "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
4003 { "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
4004 { "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
4005 { "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
4006 { "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
4007 { "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
4008 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4009 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4010 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4011 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4012 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
4013 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
4014 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
4015 { "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
4016 { "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
4017 { "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
4018 { "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
4019 { "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
4020 { "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
4021 { "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
4022 { "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
4023 { "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
4024 { "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
4025 { "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
4026 { "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
4027 { "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
4028 { "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
4029 { "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
4030 { "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
4031 { "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
4032 { "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
4033 { "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
4034 { "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
4035 { "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
4036 { "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
4037 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
4038 { "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
4039 { "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
4040 { "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
4041 { "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
4042 { "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
4043 { "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
4044 { "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
4045 { "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
4046 { "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
4047 { "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
4048 { "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
4049 { "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
4050 { "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
4051 { "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
4052 { "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
4053 { "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
4054 { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
4055
4056 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4057
4058 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4059 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4060
4061 { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4062
4063 { "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4064
4065 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
4066
4067 { "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4068
4069 { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
4070 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4071 { "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4072 { "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
4073 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4074 { "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4075
4076 { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4077 { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4078 { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4079 { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4080
4081 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4082 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4083
4084 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4085 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4086 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4087 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4088
4089 { "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4090
4091 { "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
4092
4093 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4094
4095 { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4096
4097 { "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
4098
4099 { "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
4100 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
4101
4102 { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4103
4104 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } },
4105 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4106
4107 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB } },
4108 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4109
4110 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } },
4111
4112 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4113 { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4114 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4115 { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4116
4117 { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4118 { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4119
4120 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4121 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4122
4123 { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4124 { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4125
4126 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA, RB } },
4127
4128 { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA, RB } },
4129
4130 { "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
4131 { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4132
4133 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4134
4135 { "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4136
4137 { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4138
4139 { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } },
4140 { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } },
4141
4142 { "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } },
4143 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
4144 { "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
4145 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
4146 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4147
4148 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } },
4149
4150 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA, RB } },
4151
4152 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4153
4154 { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4155
4156 { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4157
4158 { "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4159
4160 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4161
4162 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } },
4163 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA, RB } },
4164
4165 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB } },
4166 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA, RB } },
4167
4168 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB } },
4169
4170 { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4171 { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4172
4173 { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4174 { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4175
4176 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA, RB } },
4177
4178 { "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA, RB } },
4179
4180 { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4181
4182 { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4183 { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4184
4185 { "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4186
4187 { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } },
4188 { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } },
4189
4190 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB } },
4191
4192 { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4193 { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4194
4195 { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4196 { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4197
4198 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA, RB } },
4199
4200 { "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
4201
4202 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4203
4204 { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4205 { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4206
4207 { "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4208
4209 { "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4210
4211 { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4212 { "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4213
4214 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } },
4215
4216 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4217 { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4218 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4219 { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4220
4221 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4222 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4223
4224 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA, RB } },
4225
4226 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA, RB } },
4227 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA, RB } },
4228
4229 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4230
4231 { "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
4232 { "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
4233
4234 { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4235 { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4236 { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4237 { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4238
4239 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4240
4241 { "mbar", X(31,854), X_MASK, BOOKE, { MO } },
4242 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4243
4244 { "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
4245 { "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
4246 { "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } },
4247 { "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
4248 { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4249 { "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
4250
4251 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4252
4253 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } },
4254
4255 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4256 { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4257
4258 { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4259 { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4260
4261 { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4262 { "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4263 { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4264 { "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4265
4266 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA, RB } },
4267
4268 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA, RB } },
4269
4270 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4271 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4272 { "tlbre", X(31,946), X_MASK, BOOKE, { 0 } },
4273 { "tlbre", X(31,946), X_MASK, PPC403, { RS, RA, SH } },
4274
4275 { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4276 { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4277
4278 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4279 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4280
4281 { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4282
4283 { "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
4284
4285 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4286 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4287 { "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } },
4288 { "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } },
4289 { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
4290
4291 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4292
4293 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
4294
4295 { "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4296 { "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
4297
4298 { "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
4299
4300 { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4301 { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA, RB } },
4302
4303 { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4304
4305 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4306 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4307
4308 { "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4309
4310 { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4311 { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4312 { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4313 { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4314 { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4315 { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4316 { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4317 { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4318 { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4319 { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4320 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4321 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4322
4323 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } },
4324 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } },
4325
4326 { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4327 { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } },
4328
4329 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA } },
4330
4331 { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4332
4333 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } },
4334 { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } },
4335
4336 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4337 { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } },
4338
4339 { "stb", OP(38), OP_MASK, COM, { RS, D, RA } },
4340
4341 { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4342
4343 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA } },
4344
4345 { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4346
4347 { "lha", OP(42), OP_MASK, COM, { RT, D, RA } },
4348
4349 { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4350
4351 { "sth", OP(44), OP_MASK, COM, { RS, D, RA } },
4352
4353 { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4354
4355 { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4356 { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } },
4357
4358 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } },
4359 { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } },
4360
4361 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } },
4362
4363 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4364
4365 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } },
4366
4367 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4368
4369 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } },
4370
4371 { "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4372
4373 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } },
4374
4375 { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4376
4377 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4378
4379 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
4380
4381 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
4382
4383 { "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA } },
4384 { "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4385 { "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA } },
4386 { "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4387 { "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA } },
4388 { "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4389 { "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA } },
4390 { "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4391 { "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA } },
4392 { "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4393 { "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA } },
4394 { "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4395 { "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA } },
4396 { "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4397
4398 { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA } },
4399
4400 { "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4401
4402 { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } },
4403
4404 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4405 { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4406
4407 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4408 { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4409
4410 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4411 { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4412
4413 { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4414 { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4415
4416 { "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4417 { "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4418
4419 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4420 { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4421
4422 { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4423 { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4424
4425 { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4426 { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4427
4428 { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4429 { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4430
4431 { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4432 { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4433
4434 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4435
4436 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4437
4438 { "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA } },
4439 { "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA } },
4440 { "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA } },
4441 { "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4442 { "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA } },
4443 { "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4444 { "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA } },
4445 { "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4446 { "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA } },
4447 { "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4448 { "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA } },
4449 { "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4450
4451 { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } },
4452
4453 { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
4454
4455 { "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA } },
4456
4457 { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4458
4459 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4460 { "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4461
4462 { "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4463 { "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
4464 { "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4465 { "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4466
4467 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4468 { "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
4469 { "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4470 { "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4471
4472 { "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4473 { "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4474 { "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4475 { "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4476
4477 { "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4478 { "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4479 { "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4480 { "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4481
4482 { "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4483 { "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4484 { "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4485 { "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4486
4487 { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4488 { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4489
4490 { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4491 { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4492
4493 { "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4494 { "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4495 { "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4496 { "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4497
4498 { "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4499 { "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4500
4501 { "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4502 { "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4503 { "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4504 { "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4505
4506 { "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4507 { "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4508 { "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4509 { "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4510
4511 { "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4512 { "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4513 { "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4514 { "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4515
4516 { "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4517 { "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4518 { "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4519 { "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4520
4521 { "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4522
4523 { "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4524 { "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4525
4526 { "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4527 { "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
4528
4529 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4530
4531 { "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4532 { "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4533
4534 { "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4535 { "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4536
4537 { "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4538 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4539
4540 { "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4541 { "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4542
4543 { "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4544 { "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4545
4546 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4547 { "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4548
4549 { "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
4550 { "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
4551
4552 { "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
4553 { "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
4554
4555 { "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
4556 { "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
4557
4558 { "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
4559 { "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
4560
4561 };
4562
4563 const int powerpc_num_opcodes =
4564 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4565 \f
4566 /* The macro table. This is only used by the assembler. */
4567
4568 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4569 when x=0; 32-x when x is between 1 and 31; are negative if x is
4570 negative; and are 32 or more otherwise. This is what you want
4571 when, for instance, you are emulating a right shift by a
4572 rotate-left-and-mask, because the underlying instructions support
4573 shifts of size 0 but not shifts of size 32. By comparison, when
4574 extracting x bits from some word you want to use just 32-x, because
4575 the underlying instructions don't support extracting 0 bits but do
4576 support extracting the whole word (32 bits in this case). */
4577
4578 const struct powerpc_macro powerpc_macros[] = {
4579 { "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
4580 { "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
4581 { "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4582 { "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4583 { "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4584 { "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4585 { "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4586 { "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4587 { "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
4588 { "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
4589 { "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4590 { "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4591 { "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
4592 { "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
4593 { "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
4594 { "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
4595
4596 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
4597 { "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
4598 { "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4599 { "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4600 { "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4601 { "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4602 { "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4603 { "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4604 { "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4605 { "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4606 { "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
4607 { "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
4608 { "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
4609 { "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
4610 { "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4611 { "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4612 { "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4613 { "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4614 { "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
4615 { "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
4616 { "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4617 { "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4618 };
4619
4620 const int powerpc_num_macros =
4621 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
x86 "subsystem" repository