include/asm-powerpc/paca.h

   1 /*
   2  * include/asm-powerpc/paca.h
   3  *
   4  * This control block defines the PACA which defines the processor
   5  * specific data for each logical processor on the system.
   6  * There are some pointers defined that are utilized by PLIC.
   7  *
   8  * C 2001 PPC 64 Team, IBM Corp
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version
  13  * 2 of the License, or (at your option) any later version.
  14  */
  15 #ifndef _ASM_POWERPC_PACA_H
  16 #define _ASM_POWERPC_PACA_H
  17
  18 #include        <linux/config.h>
  19 #include        <asm/types.h>
  20 #include        <asm/lppaca.h>
  21 #include        <asm/iseries/it_lp_reg_save.h>
  22 #include        <asm/mmu.h>
  23
  24 register struct paca_struct *local_paca asm("r13");
  25 #define get_paca()      local_paca
  26
  27 struct task_struct;
  28
  29 /*
  30  * Defines the layout of the paca.
  31  *
  32  * This structure is not directly accessed by firmware or the service
  33  * processor except for the first two pointers that point to the
  34  * lppaca area and the ItLpRegSave area for this CPU.  Both the
  35  * lppaca and ItLpRegSave objects are currently contained within the
  36  * PACA but they do not need to be.
  37  */
  38 struct paca_struct {
  39         /*
  40          * Because hw_cpu_id, unlike other paca fields, is accessed
  41          * routinely from other CPUs (from the IRQ code), we stick to
  42          * read-only (after boot) fields in the first cacheline to
  43          * avoid cacheline bouncing.
  44          */
  45
  46         /*
  47          * MAGIC: These first two pointers can't be moved - they're
  48          * accessed by the firmware
  49          */
  50         struct lppaca *lppaca_ptr;      /* Pointer to LpPaca for PLIC */
  51         struct ItLpRegSave *reg_save_ptr; /* Pointer to LpRegSave for PLIC */
  52
  53         /*
  54          * MAGIC: the spinlock functions in arch/ppc64/lib/locks.c
  55          * load lock_token and paca_index with a single lwz
  56          * instruction.  They must travel together and be properly
  57          * aligned.
  58          */
  59         u16 lock_token;                 /* Constant 0x8000, used in locks */
  60         u16 paca_index;                 /* Logical processor number */
  61
  62         u32 default_decr;               /* Default decrementer value */
  63         u64 kernel_toc;                 /* Kernel TOC address */
  64         u64 stab_real;                  /* Absolute address of segment table */
  65         u64 stab_addr;                  /* Virtual address of segment table */
  66         void *emergency_sp;             /* pointer to emergency stack */
  67         s16 hw_cpu_id;                  /* Physical processor number */
  68         u8 cpu_start;                   /* At startup, processor spins until */
  69                                         /* this becomes non-zero. */
  70
  71         /*
  72          * Now, starting in cacheline 2, the exception save areas
  73          */
  74         /* used for most interrupts/exceptions */
  75         u64 exgen[10] __attribute__((aligned(0x80)));
  76         u64 exmc[10];           /* used for machine checks */
  77         u64 exslb[10];          /* used for SLB/segment table misses
  78                                  * on the linear mapping */
  79 #ifdef CONFIG_PPC_64K_PAGES
  80         pgd_t *pgdir;
  81 #endif /* CONFIG_PPC_64K_PAGES */
  82
  83         mm_context_t context;
  84         u16 slb_cache[SLB_CACHE_ENTRIES];
  85         u16 slb_cache_ptr;
  86
  87         /*
  88          * then miscellaneous read-write fields
  89          */
  90         struct task_struct *__current;  /* Pointer to current */
  91         u64 kstack;                     /* Saved Kernel stack addr */
  92         u64 stab_rr;                    /* stab/slb round-robin counter */
  93         u64 next_jiffy_update_tb;       /* TB value for next jiffy update */
  94         u64 saved_r1;                   /* r1 save for RTAS calls */
  95         u64 saved_msr;                  /* MSR saved here by enter_rtas */
  96         u8 proc_enabled;                /* irq soft-enable flag */
  97
  98         /* not yet used */
  99         u64 exdsi[8];           /* used for linear mapping hash table misses */
 100
 101         /*
 102          * iSeries structure which the hypervisor knows about -
 103          * this structure should not cross a page boundary.
 104          * The vpa_init/register_vpa call is now known to fail if the
 105          * lppaca structure crosses a page boundary.
 106          * The lppaca is also used on POWER5 pSeries boxes.
 107          * The lppaca is 640 bytes long, and cannot readily change
 108          * since the hypervisor knows its layout, so a 1kB
 109          * alignment will suffice to ensure that it doesn't
 110          * cross a page boundary.
 111          */
 112         struct lppaca lppaca __attribute__((__aligned__(0x400)));
 113 #ifdef CONFIG_PPC_ISERIES
 114         struct ItLpRegSave reg_save;
 115 #endif
 116 };
 117
 118 extern struct paca_struct paca[];
 119
 120 #endif /* _ASM_POWERPC_PACA_H */