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clockevents: ARM sp804: allow clockevent name to be specified
[linux-2.6/x86.git] / arch / arm / mach-realview / core.c
blob9f5155507d2760e2e7aa3bbdb6e723f4b27cf549
1 /*
2 * linux/arch/arm/mach-realview/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/amba/bus.h>
27 #include <linux/amba/clcd.h>
28 #include <linux/io.h>
29 #include <linux/smsc911x.h>
30 #include <linux/ata_platform.h>
31 #include <linux/amba/mmci.h>
32 #include <linux/gfp.h>
33 #include <linux/clkdev.h>
34
35 #include <asm/system.h>
36 #include <mach/hardware.h>
37 #include <asm/irq.h>
38 #include <asm/leds.h>
39 #include <asm/mach-types.h>
40 #include <asm/hardware/arm_timer.h>
41 #include <asm/hardware/icst.h>
42
43 #include <asm/mach/arch.h>
44 #include <asm/mach/flash.h>
45 #include <asm/mach/irq.h>
46 #include <asm/mach/map.h>
47
48 #include <asm/hardware/gic.h>
49
50 #include <mach/platform.h>
51 #include <mach/irqs.h>
52 #include <asm/hardware/timer-sp.h>
53
54 #include <plat/clcd.h>
55 #include <plat/sched_clock.h>
56
57 #include "core.h"
58
59 #ifdef CONFIG_ZONE_DMA
60 /*
61 * Adjust the zones if there are restrictions for DMA access.
62 */
63 void __init realview_adjust_zones(unsigned long *size, unsigned long *hole)
64 {
65 unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
66
67 if (!machine_is_realview_pbx() || size[0] <= dma_size)
68 return;
69
70 size[ZONE_NORMAL] = size[0] - dma_size;
71 size[ZONE_DMA] = dma_size;
72 hole[ZONE_NORMAL] = hole[0];
73 hole[ZONE_DMA] = 0;
74 }
75 #endif
76
77
78 #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
79
80 static int realview_flash_init(void)
81 {
82 u32 val;
83
84 val = __raw_readl(REALVIEW_FLASHCTRL);
85 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
86 __raw_writel(val, REALVIEW_FLASHCTRL);
87
88 return 0;
89 }
90
91 static void realview_flash_exit(void)
92 {
93 u32 val;
94
95 val = __raw_readl(REALVIEW_FLASHCTRL);
96 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
97 __raw_writel(val, REALVIEW_FLASHCTRL);
98 }
99
100 static void realview_flash_set_vpp(int on)
101 {
102 u32 val;
103
104 val = __raw_readl(REALVIEW_FLASHCTRL);
105 if (on)
106 val |= REALVIEW_FLASHPROG_FLVPPEN;
107 else
108 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
109 __raw_writel(val, REALVIEW_FLASHCTRL);
110 }
111
112 static struct flash_platform_data realview_flash_data = {
113 .map_name = "cfi_probe",
114 .width = 4,
115 .init = realview_flash_init,
116 .exit = realview_flash_exit,
117 .set_vpp = realview_flash_set_vpp,
118 };
119
120 struct platform_device realview_flash_device = {
121 .name = "armflash",
122 .id = 0,
123 .dev = {
124 .platform_data = &realview_flash_data,
125 },
126 };
127
128 int realview_flash_register(struct resource *res, u32 num)
129 {
130 realview_flash_device.resource = res;
131 realview_flash_device.num_resources = num;
132 return platform_device_register(&realview_flash_device);
133 }
134
135 static struct smsc911x_platform_config smsc911x_config = {
136 .flags = SMSC911X_USE_32BIT,
137 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
138 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
139 .phy_interface = PHY_INTERFACE_MODE_MII,
140 };
141
142 static struct platform_device realview_eth_device = {
143 .name = "smsc911x",
144 .id = 0,
145 .num_resources = 2,
146 };
147
148 int realview_eth_register(const char *name, struct resource *res)
149 {
150 if (name)
151 realview_eth_device.name = name;
152 realview_eth_device.resource = res;
153 if (strcmp(realview_eth_device.name, "smsc911x") == 0)
154 realview_eth_device.dev.platform_data = &smsc911x_config;
155
156 return platform_device_register(&realview_eth_device);
157 }
158
159 struct platform_device realview_usb_device = {
160 .name = "isp1760",
161 .num_resources = 2,
162 };
163
164 int realview_usb_register(struct resource *res)
165 {
166 realview_usb_device.resource = res;
167 return platform_device_register(&realview_usb_device);
168 }
169
170 static struct pata_platform_info pata_platform_data = {
171 .ioport_shift = 1,
172 };
173
174 static struct resource pata_resources[] = {
175 [0] = {
176 .start = REALVIEW_CF_BASE,
177 .end = REALVIEW_CF_BASE + 0xff,
178 .flags = IORESOURCE_MEM,
179 },
180 [1] = {
181 .start = REALVIEW_CF_BASE + 0x100,
182 .end = REALVIEW_CF_BASE + SZ_4K - 1,
183 .flags = IORESOURCE_MEM,
184 },
185 };
186
187 struct platform_device realview_cf_device = {
188 .name = "pata_platform",
189 .id = -1,
190 .num_resources = ARRAY_SIZE(pata_resources),
191 .resource = pata_resources,
192 .dev = {
193 .platform_data = &pata_platform_data,
194 },
195 };
196
197 static struct resource realview_i2c_resource = {
198 .start = REALVIEW_I2C_BASE,
199 .end = REALVIEW_I2C_BASE + SZ_4K - 1,
200 .flags = IORESOURCE_MEM,
201 };
202
203 struct platform_device realview_i2c_device = {
204 .name = "versatile-i2c",
205 .id = 0,
206 .num_resources = 1,
207 .resource = &realview_i2c_resource,
208 };
209
210 static struct i2c_board_info realview_i2c_board_info[] = {
211 {
212 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
213 },
214 };
215
216 static int __init realview_i2c_init(void)
217 {
218 return i2c_register_board_info(0, realview_i2c_board_info,
219 ARRAY_SIZE(realview_i2c_board_info));
220 }
221 arch_initcall(realview_i2c_init);
222
223 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
224
225 /*
226 * This is only used if GPIOLIB support is disabled
227 */
228 static unsigned int realview_mmc_status(struct device *dev)
229 {
230 struct amba_device *adev = container_of(dev, struct amba_device, dev);
231 u32 mask;
232
233 if (machine_is_realview_pb1176()) {
234 static bool inserted = false;
235
236 /*
237 * The PB1176 does not have the status register,
238 * assume it is inserted at startup, then invert
239 * for each call so card insertion/removal will
240 * be detected anyway. This will not be called if
241 * GPIO on PL061 is active, which is the proper
242 * way to do this on the PB1176.
243 */
244 inserted = !inserted;
245 return inserted ? 0 : 1;
246 }
247
248 if (adev->res.start == REALVIEW_MMCI0_BASE)
249 mask = 1;
250 else
251 mask = 2;
252
253 return readl(REALVIEW_SYSMCI) & mask;
254 }
255
256 struct mmci_platform_data realview_mmc0_plat_data = {
257 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
258 .status = realview_mmc_status,
259 .gpio_wp = 17,
260 .gpio_cd = 16,
261 .cd_invert = true,
262 };
263
264 struct mmci_platform_data realview_mmc1_plat_data = {
265 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
266 .status = realview_mmc_status,
267 .gpio_wp = 19,
268 .gpio_cd = 18,
269 .cd_invert = true,
270 };
271
272 /*
273 * Clock handling
274 */
275 static const struct icst_params realview_oscvco_params = {
276 .ref = 24000000,
277 .vco_max = ICST307_VCO_MAX,
278 .vco_min = ICST307_VCO_MIN,
279 .vd_min = 4 + 8,
280 .vd_max = 511 + 8,
281 .rd_min = 1 + 2,
282 .rd_max = 127 + 2,
283 .s2div = icst307_s2div,
284 .idx2s = icst307_idx2s,
285 };
286
287 static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
288 {
289 void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
290 u32 val;
291
292 val = readl(clk->vcoreg) & ~0x7ffff;
293 val |= vco.v | (vco.r << 9) | (vco.s << 16);
294
295 writel(0xa05f, sys_lock);
296 writel(val, clk->vcoreg);
297 writel(0, sys_lock);
298 }
299
300 static const struct clk_ops oscvco_clk_ops = {
301 .round = icst_clk_round,
302 .set = icst_clk_set,
303 .setvco = realview_oscvco_set,
304 };
305
306 static struct clk oscvco_clk = {
307 .ops = &oscvco_clk_ops,
308 .params = &realview_oscvco_params,
309 };
310
311 /*
312 * These are fixed clocks.
313 */
314 static struct clk ref24_clk = {
315 .rate = 24000000,
316 };
317
318 static struct clk sp804_clk = {
319 .rate = 1000000,
320 };
321
322 static struct clk dummy_apb_pclk;
323
324 static struct clk_lookup lookups[] = {
325 { /* Bus clock */
326 .con_id = "apb_pclk",
327 .clk = &dummy_apb_pclk,
328 }, { /* UART0 */
329 .dev_id = "dev:uart0",
330 .clk = &ref24_clk,
331 }, { /* UART1 */
332 .dev_id = "dev:uart1",
333 .clk = &ref24_clk,
334 }, { /* UART2 */
335 .dev_id = "dev:uart2",
336 .clk = &ref24_clk,
337 }, { /* UART3 */
338 .dev_id = "fpga:uart3",
339 .clk = &ref24_clk,
340 }, { /* UART3 is on the dev chip in PB1176 */
341 .dev_id = "dev:uart3",
342 .clk = &ref24_clk,
343 }, { /* UART4 only exists in PB1176 */
344 .dev_id = "fpga:uart4",
345 .clk = &ref24_clk,
346 }, { /* KMI0 */
347 .dev_id = "fpga:kmi0",
348 .clk = &ref24_clk,
349 }, { /* KMI1 */
350 .dev_id = "fpga:kmi1",
351 .clk = &ref24_clk,
352 }, { /* MMC0 */
353 .dev_id = "fpga:mmc0",
354 .clk = &ref24_clk,
355 }, { /* CLCD is in the PB1176 and EB DevChip */
356 .dev_id = "dev:clcd",
357 .clk = &oscvco_clk,
358 }, { /* PB:CLCD */
359 .dev_id = "issp:clcd",
360 .clk = &oscvco_clk,
361 }, { /* SSP */
362 .dev_id = "dev:ssp0",
363 .clk = &ref24_clk,
364 }, { /* SP804 timers */
365 .dev_id = "sp804",
366 .clk = &sp804_clk,
367 },
368 };
369
370 void __init realview_init_early(void)
371 {
372 void __iomem *sys = __io_address(REALVIEW_SYS_BASE);
373
374 if (machine_is_realview_pb1176())
375 oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC0_OFFSET;
376 else
377 oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC4_OFFSET;
378
379 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
380
381 versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000);
382 }
383
384 /*
385 * CLCD support.
386 */
387 #define SYS_CLCD_NLCDIOON (1 << 2)
388 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
389 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
390 #define SYS_CLCD_ID_MASK (0x1f << 8)
391 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
392 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
393 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
394 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
395 #define SYS_CLCD_ID_VGA (0x1f << 8)
396
397 /*
398 * Disable all display connectors on the interface module.
399 */
400 static void realview_clcd_disable(struct clcd_fb *fb)
401 {
402 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
403 u32 val;
404
405 val = readl(sys_clcd);
406 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
407 writel(val, sys_clcd);
408 }
409
410 /*
411 * Enable the relevant connector on the interface module.
412 */
413 static void realview_clcd_enable(struct clcd_fb *fb)
414 {
415 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
416 u32 val;
417
418 /*
419 * Enable the PSUs
420 */
421 val = readl(sys_clcd);
422 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
423 writel(val, sys_clcd);
424 }
425
426 /*
427 * Detect which LCD panel is connected, and return the appropriate
428 * clcd_panel structure. Note: we do not have any information on
429 * the required timings for the 8.4in panel, so we presently assume
430 * VGA timings.
431 */
432 static int realview_clcd_setup(struct clcd_fb *fb)
433 {
434 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
435 const char *panel_name, *vga_panel_name;
436 unsigned long framesize;
437 u32 val;
438
439 if (machine_is_realview_eb()) {
440 /* VGA, 16bpp */
441 framesize = 640 * 480 * 2;
442 vga_panel_name = "VGA";
443 } else {
444 /* XVGA, 16bpp */
445 framesize = 1024 * 768 * 2;
446 vga_panel_name = "XVGA";
447 }
448
449 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
450 if (val == SYS_CLCD_ID_SANYO_3_8)
451 panel_name = "Sanyo TM38QV67A02A";
452 else if (val == SYS_CLCD_ID_SANYO_2_5)
453 panel_name = "Sanyo QVGA Portrait";
454 else if (val == SYS_CLCD_ID_EPSON_2_2)
455 panel_name = "Epson L2F50113T00";
456 else if (val == SYS_CLCD_ID_VGA)
457 panel_name = vga_panel_name;
458 else {
459 pr_err("CLCD: unknown LCD panel ID 0x%08x, using VGA\n", val);
460 panel_name = vga_panel_name;
461 }
462
463 fb->panel = versatile_clcd_get_panel(panel_name);
464 if (!fb->panel)
465 return -EINVAL;
466
467 return versatile_clcd_setup_dma(fb, framesize);
468 }
469
470 struct clcd_board clcd_plat_data = {
471 .name = "RealView",
472 .caps = CLCD_CAP_ALL,
473 .check = clcdfb_check,
474 .decode = clcdfb_decode,
475 .disable = realview_clcd_disable,
476 .enable = realview_clcd_enable,
477 .setup = realview_clcd_setup,
478 .mmap = versatile_clcd_mmap_dma,
479 .remove = versatile_clcd_remove_dma,
480 };
481
482 #ifdef CONFIG_LEDS
483 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
484
485 void realview_leds_event(led_event_t ledevt)
486 {
487 unsigned long flags;
488 u32 val;
489 u32 led = 1 << smp_processor_id();
490
491 local_irq_save(flags);
492 val = readl(VA_LEDS_BASE);
493
494 switch (ledevt) {
495 case led_idle_start:
496 val = val & ~led;
497 break;
498
499 case led_idle_end:
500 val = val | led;
501 break;
502
503 case led_timer:
504 val = val ^ REALVIEW_SYS_LED7;
505 break;
506
507 case led_halted:
508 val = 0;
509 break;
510
511 default:
512 break;
513 }
514
515 writel(val, VA_LEDS_BASE);
516 local_irq_restore(flags);
517 }
518 #endif /* CONFIG_LEDS */
519
520 /*
521 * Where is the timer (VA)?
522 */
523 void __iomem *timer0_va_base;
524 void __iomem *timer1_va_base;
525 void __iomem *timer2_va_base;
526 void __iomem *timer3_va_base;
527
528 /*
529 * Set up the clock source and clock events devices
530 */
531 void __init realview_timer_init(unsigned int timer_irq)
532 {
533 u32 val;
534
535 /*
536 * set clock frequency:
537 * REALVIEW_REFCLK is 32KHz
538 * REALVIEW_TIMCLK is 1MHz
539 */
540 val = readl(__io_address(REALVIEW_SCTL_BASE));
541 writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
542 (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
543 (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
544 (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
545 __io_address(REALVIEW_SCTL_BASE));
546
547 /*
548 * Initialise to a known state (all timers off)
549 */
550 writel(0, timer0_va_base + TIMER_CTRL);
551 writel(0, timer1_va_base + TIMER_CTRL);
552 writel(0, timer2_va_base + TIMER_CTRL);
553 writel(0, timer3_va_base + TIMER_CTRL);
554
555 sp804_clocksource_init(timer3_va_base, "timer3");
556 sp804_clockevents_init(timer0_va_base, timer_irq, "timer0");
557 }
558
559 /*
560 * Setup the memory banks.
561 */
562 void realview_fixup(struct machine_desc *mdesc, struct tag *tags, char **from,
563 struct meminfo *meminfo)
564 {
565 /*
566 * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
567 * Half of this is mirrored at 0.
568 */
569 #ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
570 meminfo->bank[0].start = 0x70000000;
571 meminfo->bank[0].size = SZ_512M;
572 meminfo->nr_banks = 1;
573 #else
574 meminfo->bank[0].start = 0;
575 meminfo->bank[0].size = SZ_256M;
576 meminfo->nr_banks = 1;
577 #endif
578 }
x86 "subsystem" repository