?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[PATCH] genirq: x86_64 irq: make vector_irq per cpu
[linux-2.6/x86.git] / arch / x86_64 / kernel / io_apic.c
blob7d53f66394a7dfc2e07715e112dc8760c82d5613
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/pci.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/acpi.h>
32 #include <linux/sysdev.h>
33 #ifdef CONFIG_ACPI
34 #include <acpi/acpi_bus.h>
35 #endif
36
37 #include <asm/io.h>
38 #include <asm/smp.h>
39 #include <asm/desc.h>
40 #include <asm/proto.h>
41 #include <asm/mach_apic.h>
42 #include <asm/acpi.h>
43 #include <asm/dma.h>
44 #include <asm/nmi.h>
45 #include <asm/msidef.h>
46
47 static int assign_irq_vector(int irq, cpumask_t mask);
48
49 #define __apicdebuginit __init
50
51 int sis_apic_bug; /* not actually supported, dummy for compile */
52
53 static int no_timer_check;
54
55 static int disable_timer_pin_1 __initdata;
56
57 int timer_over_8254 __initdata = 0;
58
59 /* Where if anywhere is the i8259 connect in external int mode */
60 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
61
62 static DEFINE_SPINLOCK(ioapic_lock);
63 static DEFINE_SPINLOCK(vector_lock);
64
65 /*
66 * # of IRQ routing registers
67 */
68 int nr_ioapic_registers[MAX_IO_APICS];
69
70 /*
71 * Rough estimation of how many shared IRQs there are, can
72 * be changed anytime.
73 */
74 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
75 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
76
77 /*
78 * This is performance-critical, we want to do it O(1)
79 *
80 * the indexing order of this array favors 1:1 mappings
81 * between pins and IRQs.
82 */
83
84 static struct irq_pin_list {
85 short apic, pin, next;
86 } irq_2_pin[PIN_MAP_SIZE];
87
88 #define __DO_ACTION(R, ACTION, FINAL) \
89 \
90 { \
91 int pin; \
92 struct irq_pin_list *entry = irq_2_pin + irq; \
93 \
94 BUG_ON(irq >= NR_IRQS); \
95 for (;;) { \
96 unsigned int reg; \
97 pin = entry->pin; \
98 if (pin == -1) \
99 break; \
100 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
101 reg ACTION; \
102 io_apic_modify(entry->apic, reg); \
103 if (!entry->next) \
104 break; \
105 entry = irq_2_pin + entry->next; \
106 } \
107 FINAL; \
108 }
109
110 union entry_union {
111 struct { u32 w1, w2; };
112 struct IO_APIC_route_entry entry;
113 };
114
115 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
116 {
117 union entry_union eu;
118 unsigned long flags;
119 spin_lock_irqsave(&ioapic_lock, flags);
120 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
121 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
122 spin_unlock_irqrestore(&ioapic_lock, flags);
123 return eu.entry;
124 }
125
126 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
127 {
128 unsigned long flags;
129 union entry_union eu;
130 eu.entry = e;
131 spin_lock_irqsave(&ioapic_lock, flags);
132 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
133 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
134 spin_unlock_irqrestore(&ioapic_lock, flags);
135 }
136
137 #ifdef CONFIG_SMP
138 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
139 {
140 int apic, pin;
141 struct irq_pin_list *entry = irq_2_pin + irq;
142
143 BUG_ON(irq >= NR_IRQS);
144 for (;;) {
145 unsigned int reg;
146 apic = entry->apic;
147 pin = entry->pin;
148 if (pin == -1)
149 break;
150 io_apic_write(apic, 0x11 + pin*2, dest);
151 reg = io_apic_read(apic, 0x10 + pin*2);
152 reg &= ~0x000000ff;
153 reg |= vector;
154 io_apic_modify(apic, reg);
155 if (!entry->next)
156 break;
157 entry = irq_2_pin + entry->next;
158 }
159 }
160
161 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
162 {
163 unsigned long flags;
164 unsigned int dest;
165 cpumask_t tmp;
166 int vector;
167
168 cpus_and(tmp, mask, cpu_online_map);
169 if (cpus_empty(tmp))
170 tmp = TARGET_CPUS;
171
172 cpus_and(mask, tmp, CPU_MASK_ALL);
173
174 vector = assign_irq_vector(irq, mask);
175 if (vector < 0)
176 return;
177
178 cpus_clear(tmp);
179 cpu_set(vector >> 8, tmp);
180 dest = cpu_mask_to_apicid(tmp);
181
182 /*
183 * Only the high 8 bits are valid.
184 */
185 dest = SET_APIC_LOGICAL_ID(dest);
186
187 spin_lock_irqsave(&ioapic_lock, flags);
188 __target_IO_APIC_irq(irq, dest, vector & 0xff);
189 set_native_irq_info(irq, mask);
190 spin_unlock_irqrestore(&ioapic_lock, flags);
191 }
192 #endif
193
194 static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
195
196 /*
197 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
198 * shared ISA-space IRQs, so we have to support them. We are super
199 * fast in the common case, and fast for shared ISA-space IRQs.
200 */
201 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
202 {
203 static int first_free_entry = NR_IRQS;
204 struct irq_pin_list *entry = irq_2_pin + irq;
205
206 BUG_ON(irq >= NR_IRQS);
207 while (entry->next)
208 entry = irq_2_pin + entry->next;
209
210 if (entry->pin != -1) {
211 entry->next = first_free_entry;
212 entry = irq_2_pin + entry->next;
213 if (++first_free_entry >= PIN_MAP_SIZE)
214 panic("io_apic.c: ran out of irq_2_pin entries!");
215 }
216 entry->apic = apic;
217 entry->pin = pin;
218 }
219
220
221 #define DO_ACTION(name,R,ACTION, FINAL) \
222 \
223 static void name##_IO_APIC_irq (unsigned int irq) \
224 __DO_ACTION(R, ACTION, FINAL)
225
226 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
227 /* mask = 1 */
228 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
229 /* mask = 0 */
230
231 static void mask_IO_APIC_irq (unsigned int irq)
232 {
233 unsigned long flags;
234
235 spin_lock_irqsave(&ioapic_lock, flags);
236 __mask_IO_APIC_irq(irq);
237 spin_unlock_irqrestore(&ioapic_lock, flags);
238 }
239
240 static void unmask_IO_APIC_irq (unsigned int irq)
241 {
242 unsigned long flags;
243
244 spin_lock_irqsave(&ioapic_lock, flags);
245 __unmask_IO_APIC_irq(irq);
246 spin_unlock_irqrestore(&ioapic_lock, flags);
247 }
248
249 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
250 {
251 struct IO_APIC_route_entry entry;
252
253 /* Check delivery_mode to be sure we're not clearing an SMI pin */
254 entry = ioapic_read_entry(apic, pin);
255 if (entry.delivery_mode == dest_SMI)
256 return;
257 /*
258 * Disable it in the IO-APIC irq-routing table:
259 */
260 memset(&entry, 0, sizeof(entry));
261 entry.mask = 1;
262 ioapic_write_entry(apic, pin, entry);
263 }
264
265 static void clear_IO_APIC (void)
266 {
267 int apic, pin;
268
269 for (apic = 0; apic < nr_ioapics; apic++)
270 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
271 clear_IO_APIC_pin(apic, pin);
272 }
273
274 int skip_ioapic_setup;
275 int ioapic_force;
276
277 /* dummy parsing: see setup.c */
278
279 static int __init disable_ioapic_setup(char *str)
280 {
281 skip_ioapic_setup = 1;
282 return 0;
283 }
284 early_param("noapic", disable_ioapic_setup);
285
286 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
287 static int __init disable_timer_pin_setup(char *arg)
288 {
289 disable_timer_pin_1 = 1;
290 return 1;
291 }
292 __setup("disable_timer_pin_1", disable_timer_pin_setup);
293
294 static int __init setup_disable_8254_timer(char *s)
295 {
296 timer_over_8254 = -1;
297 return 1;
298 }
299 static int __init setup_enable_8254_timer(char *s)
300 {
301 timer_over_8254 = 2;
302 return 1;
303 }
304
305 __setup("disable_8254_timer", setup_disable_8254_timer);
306 __setup("enable_8254_timer", setup_enable_8254_timer);
307
308
309 /*
310 * Find the IRQ entry number of a certain pin.
311 */
312 static int find_irq_entry(int apic, int pin, int type)
313 {
314 int i;
315
316 for (i = 0; i < mp_irq_entries; i++)
317 if (mp_irqs[i].mpc_irqtype == type &&
318 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
319 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
320 mp_irqs[i].mpc_dstirq == pin)
321 return i;
322
323 return -1;
324 }
325
326 /*
327 * Find the pin to which IRQ[irq] (ISA) is connected
328 */
329 static int __init find_isa_irq_pin(int irq, int type)
330 {
331 int i;
332
333 for (i = 0; i < mp_irq_entries; i++) {
334 int lbus = mp_irqs[i].mpc_srcbus;
335
336 if (test_bit(lbus, mp_bus_not_pci) &&
337 (mp_irqs[i].mpc_irqtype == type) &&
338 (mp_irqs[i].mpc_srcbusirq == irq))
339
340 return mp_irqs[i].mpc_dstirq;
341 }
342 return -1;
343 }
344
345 static int __init find_isa_irq_apic(int irq, int type)
346 {
347 int i;
348
349 for (i = 0; i < mp_irq_entries; i++) {
350 int lbus = mp_irqs[i].mpc_srcbus;
351
352 if (test_bit(lbus, mp_bus_not_pci) &&
353 (mp_irqs[i].mpc_irqtype == type) &&
354 (mp_irqs[i].mpc_srcbusirq == irq))
355 break;
356 }
357 if (i < mp_irq_entries) {
358 int apic;
359 for(apic = 0; apic < nr_ioapics; apic++) {
360 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
361 return apic;
362 }
363 }
364
365 return -1;
366 }
367
368 /*
369 * Find a specific PCI IRQ entry.
370 * Not an __init, possibly needed by modules
371 */
372 static int pin_2_irq(int idx, int apic, int pin);
373
374 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
375 {
376 int apic, i, best_guess = -1;
377
378 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
379 bus, slot, pin);
380 if (mp_bus_id_to_pci_bus[bus] == -1) {
381 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
382 return -1;
383 }
384 for (i = 0; i < mp_irq_entries; i++) {
385 int lbus = mp_irqs[i].mpc_srcbus;
386
387 for (apic = 0; apic < nr_ioapics; apic++)
388 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
389 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
390 break;
391
392 if (!test_bit(lbus, mp_bus_not_pci) &&
393 !mp_irqs[i].mpc_irqtype &&
394 (bus == lbus) &&
395 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
396 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
397
398 if (!(apic || IO_APIC_IRQ(irq)))
399 continue;
400
401 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
402 return irq;
403 /*
404 * Use the first all-but-pin matching entry as a
405 * best-guess fuzzy result for broken mptables.
406 */
407 if (best_guess < 0)
408 best_guess = irq;
409 }
410 }
411 BUG_ON(best_guess >= NR_IRQS);
412 return best_guess;
413 }
414
415 /* ISA interrupts are always polarity zero edge triggered,
416 * when listed as conforming in the MP table. */
417
418 #define default_ISA_trigger(idx) (0)
419 #define default_ISA_polarity(idx) (0)
420
421 /* PCI interrupts are always polarity one level triggered,
422 * when listed as conforming in the MP table. */
423
424 #define default_PCI_trigger(idx) (1)
425 #define default_PCI_polarity(idx) (1)
426
427 static int __init MPBIOS_polarity(int idx)
428 {
429 int bus = mp_irqs[idx].mpc_srcbus;
430 int polarity;
431
432 /*
433 * Determine IRQ line polarity (high active or low active):
434 */
435 switch (mp_irqs[idx].mpc_irqflag & 3)
436 {
437 case 0: /* conforms, ie. bus-type dependent polarity */
438 if (test_bit(bus, mp_bus_not_pci))
439 polarity = default_ISA_polarity(idx);
440 else
441 polarity = default_PCI_polarity(idx);
442 break;
443 case 1: /* high active */
444 {
445 polarity = 0;
446 break;
447 }
448 case 2: /* reserved */
449 {
450 printk(KERN_WARNING "broken BIOS!!\n");
451 polarity = 1;
452 break;
453 }
454 case 3: /* low active */
455 {
456 polarity = 1;
457 break;
458 }
459 default: /* invalid */
460 {
461 printk(KERN_WARNING "broken BIOS!!\n");
462 polarity = 1;
463 break;
464 }
465 }
466 return polarity;
467 }
468
469 static int MPBIOS_trigger(int idx)
470 {
471 int bus = mp_irqs[idx].mpc_srcbus;
472 int trigger;
473
474 /*
475 * Determine IRQ trigger mode (edge or level sensitive):
476 */
477 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
478 {
479 case 0: /* conforms, ie. bus-type dependent */
480 if (test_bit(bus, mp_bus_not_pci))
481 trigger = default_ISA_trigger(idx);
482 else
483 trigger = default_PCI_trigger(idx);
484 break;
485 case 1: /* edge */
486 {
487 trigger = 0;
488 break;
489 }
490 case 2: /* reserved */
491 {
492 printk(KERN_WARNING "broken BIOS!!\n");
493 trigger = 1;
494 break;
495 }
496 case 3: /* level */
497 {
498 trigger = 1;
499 break;
500 }
501 default: /* invalid */
502 {
503 printk(KERN_WARNING "broken BIOS!!\n");
504 trigger = 0;
505 break;
506 }
507 }
508 return trigger;
509 }
510
511 static inline int irq_polarity(int idx)
512 {
513 return MPBIOS_polarity(idx);
514 }
515
516 static inline int irq_trigger(int idx)
517 {
518 return MPBIOS_trigger(idx);
519 }
520
521 static int next_irq = 16;
522
523 /*
524 * gsi_irq_sharing -- Name overload! "irq" can be either a legacy IRQ
525 * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
526 * from ACPI, which can reach 800 in large boxen.
527 *
528 * Compact the sparse GSI space into a sequential IRQ series and reuse
529 * vectors if possible.
530 */
531 int gsi_irq_sharing(int gsi)
532 {
533 int i, tries, vector;
534
535 BUG_ON(gsi >= NR_IRQ_VECTORS);
536
537 if (platform_legacy_irq(gsi))
538 return gsi;
539
540 if (gsi_2_irq[gsi] != 0xFF)
541 return (int)gsi_2_irq[gsi];
542
543 tries = NR_IRQS;
544 try_again:
545 vector = assign_irq_vector(gsi, TARGET_CPUS);
546
547 /*
548 * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
549 * use of vector and if found, return that IRQ. However, we never want
550 * to share legacy IRQs, which usually have a different trigger mode
551 * than PCI.
552 */
553 for (i = 0; i < NR_IRQS; i++)
554 if (IO_APIC_VECTOR(i) == vector)
555 break;
556 if (platform_legacy_irq(i)) {
557 if (--tries >= 0) {
558 IO_APIC_VECTOR(i) = 0;
559 goto try_again;
560 }
561 panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
562 }
563 if (i < NR_IRQS) {
564 gsi_2_irq[gsi] = i;
565 printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
566 gsi, vector, i);
567 return i;
568 }
569
570 i = next_irq++;
571 BUG_ON(i >= NR_IRQS);
572 gsi_2_irq[gsi] = i;
573 IO_APIC_VECTOR(i) = vector;
574 printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
575 gsi, vector, i);
576 return i;
577 }
578
579 static int pin_2_irq(int idx, int apic, int pin)
580 {
581 int irq, i;
582 int bus = mp_irqs[idx].mpc_srcbus;
583
584 /*
585 * Debugging check, we are in big trouble if this message pops up!
586 */
587 if (mp_irqs[idx].mpc_dstirq != pin)
588 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
589
590 if (test_bit(bus, mp_bus_not_pci)) {
591 irq = mp_irqs[idx].mpc_srcbusirq;
592 } else {
593 /*
594 * PCI IRQs are mapped in order
595 */
596 i = irq = 0;
597 while (i < apic)
598 irq += nr_ioapic_registers[i++];
599 irq += pin;
600 irq = gsi_irq_sharing(irq);
601 }
602 BUG_ON(irq >= NR_IRQS);
603 return irq;
604 }
605
606 static inline int IO_APIC_irq_trigger(int irq)
607 {
608 int apic, idx, pin;
609
610 for (apic = 0; apic < nr_ioapics; apic++) {
611 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
612 idx = find_irq_entry(apic,pin,mp_INT);
613 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
614 return irq_trigger(idx);
615 }
616 }
617 /*
618 * nonexistent IRQs are edge default
619 */
620 return 0;
621 }
622
623 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
624 unsigned int irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_EXTERNAL_VECTOR, 0 };
625
626 static int __assign_irq_vector(int irq, cpumask_t mask)
627 {
628 /*
629 * NOTE! The local APIC isn't very good at handling
630 * multiple interrupts at the same interrupt level.
631 * As the interrupt level is determined by taking the
632 * vector number and shifting that right by 4, we
633 * want to spread these out a bit so that they don't
634 * all fall in the same interrupt level.
635 *
636 * Also, we've got to be careful not to trash gate
637 * 0x80, because int 0x80 is hm, kind of importantish. ;)
638 */
639 static struct {
640 int vector;
641 int offset;
642 } pos[NR_CPUS] = { [ 0 ... NR_CPUS - 1] = {FIRST_DEVICE_VECTOR, 0} };
643 int old_vector = -1;
644 int cpu;
645
646 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
647
648 if (IO_APIC_VECTOR(irq) > 0)
649 old_vector = IO_APIC_VECTOR(irq);
650 if ((old_vector > 0) && cpu_isset(old_vector >> 8, mask)) {
651 return old_vector;
652 }
653
654 for_each_cpu_mask(cpu, mask) {
655 int vector, offset;
656 vector = pos[cpu].vector;
657 offset = pos[cpu].offset;
658 next:
659 vector += 8;
660 if (vector >= FIRST_SYSTEM_VECTOR) {
661 /* If we run out of vectors on large boxen, must share them. */
662 offset = (offset + 1) % 8;
663 vector = FIRST_DEVICE_VECTOR + offset;
664 }
665 if (unlikely(pos[cpu].vector == vector))
666 continue;
667 if (vector == IA32_SYSCALL_VECTOR)
668 goto next;
669 if (per_cpu(vector_irq, cpu)[vector] != -1)
670 goto next;
671 /* Found one! */
672 pos[cpu].vector = vector;
673 pos[cpu].offset = offset;
674 if (old_vector >= 0) {
675 int old_cpu = old_vector >> 8;
676 old_vector &= 0xff;
677 per_cpu(vector_irq, old_cpu)[old_vector] = -1;
678 }
679 per_cpu(vector_irq, cpu)[vector] = irq;
680 vector |= cpu << 8;
681 IO_APIC_VECTOR(irq) = vector;
682 return vector;
683 }
684 return -ENOSPC;
685 }
686
687 static int assign_irq_vector(int irq, cpumask_t mask)
688 {
689 int vector;
690 unsigned long flags;
691
692 spin_lock_irqsave(&vector_lock, flags);
693 vector = __assign_irq_vector(irq, mask);
694 spin_unlock_irqrestore(&vector_lock, flags);
695 return vector;
696 }
697
698 extern void (*interrupt[NR_IRQS])(void);
699
700 static struct irq_chip ioapic_chip;
701
702 #define IOAPIC_AUTO -1
703 #define IOAPIC_EDGE 0
704 #define IOAPIC_LEVEL 1
705
706 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
707 {
708 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
709 trigger == IOAPIC_LEVEL)
710 set_irq_chip_and_handler(irq, &ioapic_chip,
711 handle_fasteoi_irq);
712 else
713 set_irq_chip_and_handler(irq, &ioapic_chip,
714 handle_edge_irq);
715 }
716
717 static void __init setup_IO_APIC_irqs(void)
718 {
719 struct IO_APIC_route_entry entry;
720 int apic, pin, idx, irq, first_notcon = 1, vector;
721 unsigned long flags;
722
723 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
724
725 for (apic = 0; apic < nr_ioapics; apic++) {
726 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
727
728 /*
729 * add it to the IO-APIC irq-routing table:
730 */
731 memset(&entry,0,sizeof(entry));
732
733 entry.delivery_mode = INT_DELIVERY_MODE;
734 entry.dest_mode = INT_DEST_MODE;
735 entry.mask = 0; /* enable IRQ */
736 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
737
738 idx = find_irq_entry(apic,pin,mp_INT);
739 if (idx == -1) {
740 if (first_notcon) {
741 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
742 first_notcon = 0;
743 } else
744 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
745 continue;
746 }
747
748 entry.trigger = irq_trigger(idx);
749 entry.polarity = irq_polarity(idx);
750
751 if (irq_trigger(idx)) {
752 entry.trigger = 1;
753 entry.mask = 1;
754 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
755 }
756
757 irq = pin_2_irq(idx, apic, pin);
758 add_pin_to_irq(irq, apic, pin);
759
760 if (!apic && !IO_APIC_IRQ(irq))
761 continue;
762
763 if (IO_APIC_IRQ(irq)) {
764 cpumask_t mask;
765 vector = assign_irq_vector(irq, TARGET_CPUS);
766 if (vector < 0)
767 continue;
768
769 cpus_clear(mask);
770 cpu_set(vector >> 8, mask);
771 entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
772 entry.vector = vector & 0xff;
773
774 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
775 if (!apic && (irq < 16))
776 disable_8259A_irq(irq);
777 }
778 ioapic_write_entry(apic, pin, entry);
779
780 spin_lock_irqsave(&ioapic_lock, flags);
781 set_native_irq_info(irq, TARGET_CPUS);
782 spin_unlock_irqrestore(&ioapic_lock, flags);
783 }
784 }
785
786 if (!first_notcon)
787 apic_printk(APIC_VERBOSE," not connected.\n");
788 }
789
790 /*
791 * Set up the 8259A-master output pin as broadcast to all
792 * CPUs.
793 */
794 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
795 {
796 struct IO_APIC_route_entry entry;
797 unsigned long flags;
798
799 memset(&entry,0,sizeof(entry));
800
801 disable_8259A_irq(0);
802
803 /* mask LVT0 */
804 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
805
806 /*
807 * We use logical delivery to get the timer IRQ
808 * to the first CPU.
809 */
810 entry.dest_mode = INT_DEST_MODE;
811 entry.mask = 0; /* unmask IRQ now */
812 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
813 entry.delivery_mode = INT_DELIVERY_MODE;
814 entry.polarity = 0;
815 entry.trigger = 0;
816 entry.vector = vector;
817
818 /*
819 * The timer IRQ doesn't have to know that behind the
820 * scene we have a 8259A-master in AEOI mode ...
821 */
822 set_irq_chip_and_handler(0, &ioapic_chip, handle_edge_irq);
823
824 /*
825 * Add it to the IO-APIC irq-routing table:
826 */
827 spin_lock_irqsave(&ioapic_lock, flags);
828 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
829 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
830 spin_unlock_irqrestore(&ioapic_lock, flags);
831
832 enable_8259A_irq(0);
833 }
834
835 void __init UNEXPECTED_IO_APIC(void)
836 {
837 }
838
839 void __apicdebuginit print_IO_APIC(void)
840 {
841 int apic, i;
842 union IO_APIC_reg_00 reg_00;
843 union IO_APIC_reg_01 reg_01;
844 union IO_APIC_reg_02 reg_02;
845 unsigned long flags;
846
847 if (apic_verbosity == APIC_QUIET)
848 return;
849
850 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
851 for (i = 0; i < nr_ioapics; i++)
852 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
853 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
854
855 /*
856 * We are a bit conservative about what we expect. We have to
857 * know about every hardware change ASAP.
858 */
859 printk(KERN_INFO "testing the IO APIC.......................\n");
860
861 for (apic = 0; apic < nr_ioapics; apic++) {
862
863 spin_lock_irqsave(&ioapic_lock, flags);
864 reg_00.raw = io_apic_read(apic, 0);
865 reg_01.raw = io_apic_read(apic, 1);
866 if (reg_01.bits.version >= 0x10)
867 reg_02.raw = io_apic_read(apic, 2);
868 spin_unlock_irqrestore(&ioapic_lock, flags);
869
870 printk("\n");
871 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
872 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
873 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
874 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
875 UNEXPECTED_IO_APIC();
876
877 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
878 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
879 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
880 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
881 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
882 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
883 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
884 (reg_01.bits.entries != 0x2E) &&
885 (reg_01.bits.entries != 0x3F) &&
886 (reg_01.bits.entries != 0x03)
887 )
888 UNEXPECTED_IO_APIC();
889
890 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
891 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
892 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
893 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
894 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
895 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
896 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
897 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
898 )
899 UNEXPECTED_IO_APIC();
900 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
901 UNEXPECTED_IO_APIC();
902
903 if (reg_01.bits.version >= 0x10) {
904 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
905 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
906 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
907 UNEXPECTED_IO_APIC();
908 }
909
910 printk(KERN_DEBUG ".... IRQ redirection table:\n");
911
912 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
913 " Stat Dest Deli Vect: \n");
914
915 for (i = 0; i <= reg_01.bits.entries; i++) {
916 struct IO_APIC_route_entry entry;
917
918 entry = ioapic_read_entry(apic, i);
919
920 printk(KERN_DEBUG " %02x %03X %02X ",
921 i,
922 entry.dest.logical.logical_dest,
923 entry.dest.physical.physical_dest
924 );
925
926 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
927 entry.mask,
928 entry.trigger,
929 entry.irr,
930 entry.polarity,
931 entry.delivery_status,
932 entry.dest_mode,
933 entry.delivery_mode,
934 entry.vector
935 );
936 }
937 }
938 printk(KERN_DEBUG "IRQ to pin mappings:\n");
939 for (i = 0; i < NR_IRQS; i++) {
940 struct irq_pin_list *entry = irq_2_pin + i;
941 if (entry->pin < 0)
942 continue;
943 printk(KERN_DEBUG "IRQ%d ", i);
944 for (;;) {
945 printk("-> %d:%d", entry->apic, entry->pin);
946 if (!entry->next)
947 break;
948 entry = irq_2_pin + entry->next;
949 }
950 printk("\n");
951 }
952
953 printk(KERN_INFO ".................................... done.\n");
954
955 return;
956 }
957
958 #if 0
959
960 static __apicdebuginit void print_APIC_bitfield (int base)
961 {
962 unsigned int v;
963 int i, j;
964
965 if (apic_verbosity == APIC_QUIET)
966 return;
967
968 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
969 for (i = 0; i < 8; i++) {
970 v = apic_read(base + i*0x10);
971 for (j = 0; j < 32; j++) {
972 if (v & (1<<j))
973 printk("1");
974 else
975 printk("0");
976 }
977 printk("\n");
978 }
979 }
980
981 void __apicdebuginit print_local_APIC(void * dummy)
982 {
983 unsigned int v, ver, maxlvt;
984
985 if (apic_verbosity == APIC_QUIET)
986 return;
987
988 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
989 smp_processor_id(), hard_smp_processor_id());
990 v = apic_read(APIC_ID);
991 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
992 v = apic_read(APIC_LVR);
993 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
994 ver = GET_APIC_VERSION(v);
995 maxlvt = get_maxlvt();
996
997 v = apic_read(APIC_TASKPRI);
998 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
999
1000 v = apic_read(APIC_ARBPRI);
1001 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1002 v & APIC_ARBPRI_MASK);
1003 v = apic_read(APIC_PROCPRI);
1004 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1005
1006 v = apic_read(APIC_EOI);
1007 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1008 v = apic_read(APIC_RRR);
1009 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1010 v = apic_read(APIC_LDR);
1011 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1012 v = apic_read(APIC_DFR);
1013 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1014 v = apic_read(APIC_SPIV);
1015 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1016
1017 printk(KERN_DEBUG "... APIC ISR field:\n");
1018 print_APIC_bitfield(APIC_ISR);
1019 printk(KERN_DEBUG "... APIC TMR field:\n");
1020 print_APIC_bitfield(APIC_TMR);
1021 printk(KERN_DEBUG "... APIC IRR field:\n");
1022 print_APIC_bitfield(APIC_IRR);
1023
1024 v = apic_read(APIC_ESR);
1025 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1026
1027 v = apic_read(APIC_ICR);
1028 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1029 v = apic_read(APIC_ICR2);
1030 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1031
1032 v = apic_read(APIC_LVTT);
1033 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1034
1035 if (maxlvt > 3) { /* PC is LVT#4. */
1036 v = apic_read(APIC_LVTPC);
1037 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1038 }
1039 v = apic_read(APIC_LVT0);
1040 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1041 v = apic_read(APIC_LVT1);
1042 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1043
1044 if (maxlvt > 2) { /* ERR is LVT#3. */
1045 v = apic_read(APIC_LVTERR);
1046 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1047 }
1048
1049 v = apic_read(APIC_TMICT);
1050 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1051 v = apic_read(APIC_TMCCT);
1052 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1053 v = apic_read(APIC_TDCR);
1054 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1055 printk("\n");
1056 }
1057
1058 void print_all_local_APICs (void)
1059 {
1060 on_each_cpu(print_local_APIC, NULL, 1, 1);
1061 }
1062
1063 void __apicdebuginit print_PIC(void)
1064 {
1065 unsigned int v;
1066 unsigned long flags;
1067
1068 if (apic_verbosity == APIC_QUIET)
1069 return;
1070
1071 printk(KERN_DEBUG "\nprinting PIC contents\n");
1072
1073 spin_lock_irqsave(&i8259A_lock, flags);
1074
1075 v = inb(0xa1) << 8 | inb(0x21);
1076 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1077
1078 v = inb(0xa0) << 8 | inb(0x20);
1079 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1080
1081 outb(0x0b,0xa0);
1082 outb(0x0b,0x20);
1083 v = inb(0xa0) << 8 | inb(0x20);
1084 outb(0x0a,0xa0);
1085 outb(0x0a,0x20);
1086
1087 spin_unlock_irqrestore(&i8259A_lock, flags);
1088
1089 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1090
1091 v = inb(0x4d1) << 8 | inb(0x4d0);
1092 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1093 }
1094
1095 #endif /* 0 */
1096
1097 static void __init enable_IO_APIC(void)
1098 {
1099 union IO_APIC_reg_01 reg_01;
1100 int i8259_apic, i8259_pin;
1101 int i, apic;
1102 unsigned long flags;
1103
1104 for (i = 0; i < PIN_MAP_SIZE; i++) {
1105 irq_2_pin[i].pin = -1;
1106 irq_2_pin[i].next = 0;
1107 }
1108
1109 /*
1110 * The number of IO-APIC IRQ registers (== #pins):
1111 */
1112 for (apic = 0; apic < nr_ioapics; apic++) {
1113 spin_lock_irqsave(&ioapic_lock, flags);
1114 reg_01.raw = io_apic_read(apic, 1);
1115 spin_unlock_irqrestore(&ioapic_lock, flags);
1116 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1117 }
1118 for(apic = 0; apic < nr_ioapics; apic++) {
1119 int pin;
1120 /* See if any of the pins is in ExtINT mode */
1121 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1122 struct IO_APIC_route_entry entry;
1123 entry = ioapic_read_entry(apic, pin);
1124
1125 /* If the interrupt line is enabled and in ExtInt mode
1126 * I have found the pin where the i8259 is connected.
1127 */
1128 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1129 ioapic_i8259.apic = apic;
1130 ioapic_i8259.pin = pin;
1131 goto found_i8259;
1132 }
1133 }
1134 }
1135 found_i8259:
1136 /* Look to see what if the MP table has reported the ExtINT */
1137 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1138 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1139 /* Trust the MP table if nothing is setup in the hardware */
1140 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1141 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1142 ioapic_i8259.pin = i8259_pin;
1143 ioapic_i8259.apic = i8259_apic;
1144 }
1145 /* Complain if the MP table and the hardware disagree */
1146 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1147 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1148 {
1149 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1150 }
1151
1152 /*
1153 * Do not trust the IO-APIC being empty at bootup
1154 */
1155 clear_IO_APIC();
1156 }
1157
1158 /*
1159 * Not an __init, needed by the reboot code
1160 */
1161 void disable_IO_APIC(void)
1162 {
1163 /*
1164 * Clear the IO-APIC before rebooting:
1165 */
1166 clear_IO_APIC();
1167
1168 /*
1169 * If the i8259 is routed through an IOAPIC
1170 * Put that IOAPIC in virtual wire mode
1171 * so legacy interrupts can be delivered.
1172 */
1173 if (ioapic_i8259.pin != -1) {
1174 struct IO_APIC_route_entry entry;
1175
1176 memset(&entry, 0, sizeof(entry));
1177 entry.mask = 0; /* Enabled */
1178 entry.trigger = 0; /* Edge */
1179 entry.irr = 0;
1180 entry.polarity = 0; /* High */
1181 entry.delivery_status = 0;
1182 entry.dest_mode = 0; /* Physical */
1183 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1184 entry.vector = 0;
1185 entry.dest.physical.physical_dest =
1186 GET_APIC_ID(apic_read(APIC_ID));
1187
1188 /*
1189 * Add it to the IO-APIC irq-routing table:
1190 */
1191 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1192 }
1193
1194 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1195 }
1196
1197 /*
1198 * There is a nasty bug in some older SMP boards, their mptable lies
1199 * about the timer IRQ. We do the following to work around the situation:
1200 *
1201 * - timer IRQ defaults to IO-APIC IRQ
1202 * - if this function detects that timer IRQs are defunct, then we fall
1203 * back to ISA timer IRQs
1204 */
1205 static int __init timer_irq_works(void)
1206 {
1207 unsigned long t1 = jiffies;
1208
1209 local_irq_enable();
1210 /* Let ten ticks pass... */
1211 mdelay((10 * 1000) / HZ);
1212
1213 /*
1214 * Expect a few ticks at least, to be sure some possible
1215 * glue logic does not lock up after one or two first
1216 * ticks in a non-ExtINT mode. Also the local APIC
1217 * might have cached one ExtINT interrupt. Finally, at
1218 * least one tick may be lost due to delays.
1219 */
1220
1221 /* jiffies wrap? */
1222 if (jiffies - t1 > 4)
1223 return 1;
1224 return 0;
1225 }
1226
1227 /*
1228 * In the SMP+IOAPIC case it might happen that there are an unspecified
1229 * number of pending IRQ events unhandled. These cases are very rare,
1230 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1231 * better to do it this way as thus we do not have to be aware of
1232 * 'pending' interrupts in the IRQ path, except at this point.
1233 */
1234 /*
1235 * Edge triggered needs to resend any interrupt
1236 * that was delayed but this is now handled in the device
1237 * independent code.
1238 */
1239
1240 /*
1241 * Starting up a edge-triggered IO-APIC interrupt is
1242 * nasty - we need to make sure that we get the edge.
1243 * If it is already asserted for some reason, we need
1244 * return 1 to indicate that is was pending.
1245 *
1246 * This is not complete - we should be able to fake
1247 * an edge even if it isn't on the 8259A...
1248 */
1249
1250 static unsigned int startup_ioapic_irq(unsigned int irq)
1251 {
1252 int was_pending = 0;
1253 unsigned long flags;
1254
1255 spin_lock_irqsave(&ioapic_lock, flags);
1256 if (irq < 16) {
1257 disable_8259A_irq(irq);
1258 if (i8259A_irq_pending(irq))
1259 was_pending = 1;
1260 }
1261 __unmask_IO_APIC_irq(irq);
1262 spin_unlock_irqrestore(&ioapic_lock, flags);
1263
1264 return was_pending;
1265 }
1266
1267 static int ioapic_retrigger_irq(unsigned int irq)
1268 {
1269 cpumask_t mask;
1270 unsigned vector;
1271
1272 vector = irq_vector[irq];
1273 cpus_clear(mask);
1274 cpu_set(vector >> 8, mask);
1275
1276 send_IPI_mask(mask, vector & 0xff);
1277
1278 return 1;
1279 }
1280
1281 /*
1282 * Level and edge triggered IO-APIC interrupts need different handling,
1283 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1284 * handled with the level-triggered descriptor, but that one has slightly
1285 * more overhead. Level-triggered interrupts cannot be handled with the
1286 * edge-triggered handler, without risking IRQ storms and other ugly
1287 * races.
1288 */
1289
1290 static void ack_apic_edge(unsigned int irq)
1291 {
1292 move_native_irq(irq);
1293 ack_APIC_irq();
1294 }
1295
1296 static void ack_apic_level(unsigned int irq)
1297 {
1298 int do_unmask_irq = 0;
1299
1300 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1301 /* If we are moving the irq we need to mask it */
1302 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1303 do_unmask_irq = 1;
1304 mask_IO_APIC_irq(irq);
1305 }
1306 #endif
1307
1308 /*
1309 * We must acknowledge the irq before we move it or the acknowledge will
1310 * not propogate properly.
1311 */
1312 ack_APIC_irq();
1313
1314 /* Now we can move and renable the irq */
1315 move_masked_irq(irq);
1316 if (unlikely(do_unmask_irq))
1317 unmask_IO_APIC_irq(irq);
1318 }
1319
1320 static struct irq_chip ioapic_chip __read_mostly = {
1321 .name = "IO-APIC",
1322 .startup = startup_ioapic_irq,
1323 .mask = mask_IO_APIC_irq,
1324 .unmask = unmask_IO_APIC_irq,
1325 .ack = ack_apic_edge,
1326 .eoi = ack_apic_level,
1327 #ifdef CONFIG_SMP
1328 .set_affinity = set_ioapic_affinity_irq,
1329 #endif
1330 .retrigger = ioapic_retrigger_irq,
1331 };
1332
1333 static inline void init_IO_APIC_traps(void)
1334 {
1335 int irq;
1336
1337 /*
1338 * NOTE! The local APIC isn't very good at handling
1339 * multiple interrupts at the same interrupt level.
1340 * As the interrupt level is determined by taking the
1341 * vector number and shifting that right by 4, we
1342 * want to spread these out a bit so that they don't
1343 * all fall in the same interrupt level.
1344 *
1345 * Also, we've got to be careful not to trash gate
1346 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1347 */
1348 for (irq = 0; irq < NR_IRQS ; irq++) {
1349 int tmp = irq;
1350 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1351 /*
1352 * Hmm.. We don't have an entry for this,
1353 * so default to an old-fashioned 8259
1354 * interrupt if we can..
1355 */
1356 if (irq < 16)
1357 make_8259A_irq(irq);
1358 else
1359 /* Strange. Oh, well.. */
1360 irq_desc[irq].chip = &no_irq_chip;
1361 }
1362 }
1363 }
1364
1365 static void enable_lapic_irq (unsigned int irq)
1366 {
1367 unsigned long v;
1368
1369 v = apic_read(APIC_LVT0);
1370 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1371 }
1372
1373 static void disable_lapic_irq (unsigned int irq)
1374 {
1375 unsigned long v;
1376
1377 v = apic_read(APIC_LVT0);
1378 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1379 }
1380
1381 static void ack_lapic_irq (unsigned int irq)
1382 {
1383 ack_APIC_irq();
1384 }
1385
1386 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1387
1388 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1389 .typename = "local-APIC-edge",
1390 .startup = NULL, /* startup_irq() not used for IRQ0 */
1391 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1392 .enable = enable_lapic_irq,
1393 .disable = disable_lapic_irq,
1394 .ack = ack_lapic_irq,
1395 .end = end_lapic_irq,
1396 };
1397
1398 static void setup_nmi (void)
1399 {
1400 /*
1401 * Dirty trick to enable the NMI watchdog ...
1402 * We put the 8259A master into AEOI mode and
1403 * unmask on all local APICs LVT0 as NMI.
1404 *
1405 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1406 * is from Maciej W. Rozycki - so we do not have to EOI from
1407 * the NMI handler or the timer interrupt.
1408 */
1409 printk(KERN_INFO "activating NMI Watchdog ...");
1410
1411 enable_NMI_through_LVT0(NULL);
1412
1413 printk(" done.\n");
1414 }
1415
1416 /*
1417 * This looks a bit hackish but it's about the only one way of sending
1418 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1419 * not support the ExtINT mode, unfortunately. We need to send these
1420 * cycles as some i82489DX-based boards have glue logic that keeps the
1421 * 8259A interrupt line asserted until INTA. --macro
1422 */
1423 static inline void unlock_ExtINT_logic(void)
1424 {
1425 int apic, pin, i;
1426 struct IO_APIC_route_entry entry0, entry1;
1427 unsigned char save_control, save_freq_select;
1428 unsigned long flags;
1429
1430 pin = find_isa_irq_pin(8, mp_INT);
1431 apic = find_isa_irq_apic(8, mp_INT);
1432 if (pin == -1)
1433 return;
1434
1435 spin_lock_irqsave(&ioapic_lock, flags);
1436 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1437 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1438 spin_unlock_irqrestore(&ioapic_lock, flags);
1439 clear_IO_APIC_pin(apic, pin);
1440
1441 memset(&entry1, 0, sizeof(entry1));
1442
1443 entry1.dest_mode = 0; /* physical delivery */
1444 entry1.mask = 0; /* unmask IRQ now */
1445 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1446 entry1.delivery_mode = dest_ExtINT;
1447 entry1.polarity = entry0.polarity;
1448 entry1.trigger = 0;
1449 entry1.vector = 0;
1450
1451 spin_lock_irqsave(&ioapic_lock, flags);
1452 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1453 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1454 spin_unlock_irqrestore(&ioapic_lock, flags);
1455
1456 save_control = CMOS_READ(RTC_CONTROL);
1457 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1458 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1459 RTC_FREQ_SELECT);
1460 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1461
1462 i = 100;
1463 while (i-- > 0) {
1464 mdelay(10);
1465 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1466 i -= 10;
1467 }
1468
1469 CMOS_WRITE(save_control, RTC_CONTROL);
1470 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1471 clear_IO_APIC_pin(apic, pin);
1472
1473 spin_lock_irqsave(&ioapic_lock, flags);
1474 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1475 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1476 spin_unlock_irqrestore(&ioapic_lock, flags);
1477 }
1478
1479 int timer_uses_ioapic_pin_0;
1480
1481 /*
1482 * This code may look a bit paranoid, but it's supposed to cooperate with
1483 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1484 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1485 * fanatically on his truly buggy board.
1486 *
1487 * FIXME: really need to revamp this for modern platforms only.
1488 */
1489 static inline void check_timer(void)
1490 {
1491 int apic1, pin1, apic2, pin2;
1492 int vector;
1493
1494 /*
1495 * get/set the timer IRQ vector:
1496 */
1497 disable_8259A_irq(0);
1498 vector = assign_irq_vector(0, TARGET_CPUS);
1499
1500 /*
1501 * Subtle, code in do_timer_interrupt() expects an AEOI
1502 * mode for the 8259A whenever interrupts are routed
1503 * through I/O APICs. Also IRQ0 has to be enabled in
1504 * the 8259A which implies the virtual wire has to be
1505 * disabled in the local APIC.
1506 */
1507 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1508 init_8259A(1);
1509 if (timer_over_8254 > 0)
1510 enable_8259A_irq(0);
1511
1512 pin1 = find_isa_irq_pin(0, mp_INT);
1513 apic1 = find_isa_irq_apic(0, mp_INT);
1514 pin2 = ioapic_i8259.pin;
1515 apic2 = ioapic_i8259.apic;
1516
1517 if (pin1 == 0)
1518 timer_uses_ioapic_pin_0 = 1;
1519
1520 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1521 vector, apic1, pin1, apic2, pin2);
1522
1523 if (pin1 != -1) {
1524 /*
1525 * Ok, does IRQ0 through the IOAPIC work?
1526 */
1527 unmask_IO_APIC_irq(0);
1528 if (!no_timer_check && timer_irq_works()) {
1529 nmi_watchdog_default();
1530 if (nmi_watchdog == NMI_IO_APIC) {
1531 disable_8259A_irq(0);
1532 setup_nmi();
1533 enable_8259A_irq(0);
1534 }
1535 if (disable_timer_pin_1 > 0)
1536 clear_IO_APIC_pin(0, pin1);
1537 return;
1538 }
1539 clear_IO_APIC_pin(apic1, pin1);
1540 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1541 "connected to IO-APIC\n");
1542 }
1543
1544 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1545 "through the 8259A ... ");
1546 if (pin2 != -1) {
1547 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1548 apic2, pin2);
1549 /*
1550 * legacy devices should be connected to IO APIC #0
1551 */
1552 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1553 if (timer_irq_works()) {
1554 apic_printk(APIC_VERBOSE," works.\n");
1555 nmi_watchdog_default();
1556 if (nmi_watchdog == NMI_IO_APIC) {
1557 setup_nmi();
1558 }
1559 return;
1560 }
1561 /*
1562 * Cleanup, just in case ...
1563 */
1564 clear_IO_APIC_pin(apic2, pin2);
1565 }
1566 apic_printk(APIC_VERBOSE," failed.\n");
1567
1568 if (nmi_watchdog == NMI_IO_APIC) {
1569 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1570 nmi_watchdog = 0;
1571 }
1572
1573 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1574
1575 disable_8259A_irq(0);
1576 irq_desc[0].chip = &lapic_irq_type;
1577 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1578 enable_8259A_irq(0);
1579
1580 if (timer_irq_works()) {
1581 apic_printk(APIC_VERBOSE," works.\n");
1582 return;
1583 }
1584 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1585 apic_printk(APIC_VERBOSE," failed.\n");
1586
1587 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1588
1589 init_8259A(0);
1590 make_8259A_irq(0);
1591 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1592
1593 unlock_ExtINT_logic();
1594
1595 if (timer_irq_works()) {
1596 apic_printk(APIC_VERBOSE," works.\n");
1597 return;
1598 }
1599 apic_printk(APIC_VERBOSE," failed :(.\n");
1600 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1601 }
1602
1603 static int __init notimercheck(char *s)
1604 {
1605 no_timer_check = 1;
1606 return 1;
1607 }
1608 __setup("no_timer_check", notimercheck);
1609
1610 /*
1611 *
1612 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1613 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1614 * Linux doesn't really care, as it's not actually used
1615 * for any interrupt handling anyway.
1616 */
1617 #define PIC_IRQS (1<<2)
1618
1619 void __init setup_IO_APIC(void)
1620 {
1621 enable_IO_APIC();
1622
1623 if (acpi_ioapic)
1624 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1625 else
1626 io_apic_irqs = ~PIC_IRQS;
1627
1628 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1629
1630 sync_Arb_IDs();
1631 setup_IO_APIC_irqs();
1632 init_IO_APIC_traps();
1633 check_timer();
1634 if (!acpi_ioapic)
1635 print_IO_APIC();
1636 }
1637
1638 struct sysfs_ioapic_data {
1639 struct sys_device dev;
1640 struct IO_APIC_route_entry entry[0];
1641 };
1642 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1643
1644 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1645 {
1646 struct IO_APIC_route_entry *entry;
1647 struct sysfs_ioapic_data *data;
1648 int i;
1649
1650 data = container_of(dev, struct sysfs_ioapic_data, dev);
1651 entry = data->entry;
1652 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1653 *entry = ioapic_read_entry(dev->id, i);
1654
1655 return 0;
1656 }
1657
1658 static int ioapic_resume(struct sys_device *dev)
1659 {
1660 struct IO_APIC_route_entry *entry;
1661 struct sysfs_ioapic_data *data;
1662 unsigned long flags;
1663 union IO_APIC_reg_00 reg_00;
1664 int i;
1665
1666 data = container_of(dev, struct sysfs_ioapic_data, dev);
1667 entry = data->entry;
1668
1669 spin_lock_irqsave(&ioapic_lock, flags);
1670 reg_00.raw = io_apic_read(dev->id, 0);
1671 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1672 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1673 io_apic_write(dev->id, 0, reg_00.raw);
1674 }
1675 spin_unlock_irqrestore(&ioapic_lock, flags);
1676 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1677 ioapic_write_entry(dev->id, i, entry[i]);
1678
1679 return 0;
1680 }
1681
1682 static struct sysdev_class ioapic_sysdev_class = {
1683 set_kset_name("ioapic"),
1684 .suspend = ioapic_suspend,
1685 .resume = ioapic_resume,
1686 };
1687
1688 static int __init ioapic_init_sysfs(void)
1689 {
1690 struct sys_device * dev;
1691 int i, size, error = 0;
1692
1693 error = sysdev_class_register(&ioapic_sysdev_class);
1694 if (error)
1695 return error;
1696
1697 for (i = 0; i < nr_ioapics; i++ ) {
1698 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1699 * sizeof(struct IO_APIC_route_entry);
1700 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1701 if (!mp_ioapic_data[i]) {
1702 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1703 continue;
1704 }
1705 memset(mp_ioapic_data[i], 0, size);
1706 dev = &mp_ioapic_data[i]->dev;
1707 dev->id = i;
1708 dev->cls = &ioapic_sysdev_class;
1709 error = sysdev_register(dev);
1710 if (error) {
1711 kfree(mp_ioapic_data[i]);
1712 mp_ioapic_data[i] = NULL;
1713 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1714 continue;
1715 }
1716 }
1717
1718 return 0;
1719 }
1720
1721 device_initcall(ioapic_init_sysfs);
1722
1723 /*
1724 * Dynamic irq allocate and deallocation
1725 */
1726 int create_irq(void)
1727 {
1728 /* Allocate an unused irq */
1729 int irq;
1730 int new;
1731 int vector = 0;
1732 unsigned long flags;
1733
1734 irq = -ENOSPC;
1735 spin_lock_irqsave(&vector_lock, flags);
1736 for (new = (NR_IRQS - 1); new >= 0; new--) {
1737 if (platform_legacy_irq(new))
1738 continue;
1739 if (irq_vector[new] != 0)
1740 continue;
1741 vector = __assign_irq_vector(new, TARGET_CPUS);
1742 if (likely(vector > 0))
1743 irq = new;
1744 break;
1745 }
1746 spin_unlock_irqrestore(&vector_lock, flags);
1747
1748 if (irq >= 0) {
1749 dynamic_irq_init(irq);
1750 }
1751 return irq;
1752 }
1753
1754 void destroy_irq(unsigned int irq)
1755 {
1756 unsigned long flags;
1757
1758 dynamic_irq_cleanup(irq);
1759
1760 spin_lock_irqsave(&vector_lock, flags);
1761 irq_vector[irq] = 0;
1762 spin_unlock_irqrestore(&vector_lock, flags);
1763 }
1764
1765 /*
1766 * MSI mesage composition
1767 */
1768 #ifdef CONFIG_PCI_MSI
1769 static int msi_msg_setup(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1770 {
1771 /* For now always this code always uses physical delivery
1772 * mode.
1773 */
1774 int vector;
1775 unsigned dest;
1776
1777 vector = assign_irq_vector(irq, TARGET_CPUS);
1778 if (vector >= 0) {
1779 cpumask_t tmp;
1780
1781 cpus_clear(tmp);
1782 cpu_set(vector >> 8, tmp);
1783 dest = cpu_mask_to_apicid(tmp);
1784
1785 msg->address_hi = MSI_ADDR_BASE_HI;
1786 msg->address_lo =
1787 MSI_ADDR_BASE_LO |
1788 ((INT_DEST_MODE == 0) ?
1789 MSI_ADDR_DEST_MODE_PHYSICAL:
1790 MSI_ADDR_DEST_MODE_LOGICAL) |
1791 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1792 MSI_ADDR_REDIRECTION_CPU:
1793 MSI_ADDR_REDIRECTION_LOWPRI) |
1794 MSI_ADDR_DEST_ID(dest);
1795
1796 msg->data =
1797 MSI_DATA_TRIGGER_EDGE |
1798 MSI_DATA_LEVEL_ASSERT |
1799 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1800 MSI_DATA_DELIVERY_FIXED:
1801 MSI_DATA_DELIVERY_LOWPRI) |
1802 MSI_DATA_VECTOR(vector);
1803 }
1804 return vector;
1805 }
1806
1807 static void msi_msg_teardown(unsigned int irq)
1808 {
1809 return;
1810 }
1811
1812 static void msi_msg_set_affinity(unsigned int irq, cpumask_t mask, struct msi_msg *msg)
1813 {
1814 int vector;
1815 unsigned dest;
1816
1817 vector = assign_irq_vector(irq, mask);
1818 if (vector > 0) {
1819 cpumask_t tmp;
1820
1821 cpus_clear(tmp);
1822 cpu_set(vector >> 8, tmp);
1823 dest = cpu_mask_to_apicid(tmp);
1824
1825 msg->data &= ~MSI_DATA_VECTOR_MASK;
1826 msg->data |= MSI_DATA_VECTOR(vector);
1827 msg->address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1828 msg->address_lo |= MSI_ADDR_DEST_ID(dest);
1829 }
1830 }
1831
1832 struct msi_ops arch_msi_ops = {
1833 .needs_64bit_address = 0,
1834 .setup = msi_msg_setup,
1835 .teardown = msi_msg_teardown,
1836 .target = msi_msg_set_affinity,
1837 };
1838
1839 #endif
1840
1841 /* --------------------------------------------------------------------------
1842 ACPI-based IOAPIC Configuration
1843 -------------------------------------------------------------------------- */
1844
1845 #ifdef CONFIG_ACPI
1846
1847 #define IO_APIC_MAX_ID 0xFE
1848
1849 int __init io_apic_get_redir_entries (int ioapic)
1850 {
1851 union IO_APIC_reg_01 reg_01;
1852 unsigned long flags;
1853
1854 spin_lock_irqsave(&ioapic_lock, flags);
1855 reg_01.raw = io_apic_read(ioapic, 1);
1856 spin_unlock_irqrestore(&ioapic_lock, flags);
1857
1858 return reg_01.bits.entries;
1859 }
1860
1861
1862 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1863 {
1864 struct IO_APIC_route_entry entry;
1865 unsigned long flags;
1866 int vector;
1867 cpumask_t mask;
1868
1869 if (!IO_APIC_IRQ(irq)) {
1870 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1871 ioapic);
1872 return -EINVAL;
1873 }
1874
1875 irq = gsi_irq_sharing(irq);
1876 /*
1877 * IRQs < 16 are already in the irq_2_pin[] map
1878 */
1879 if (irq >= 16)
1880 add_pin_to_irq(irq, ioapic, pin);
1881
1882
1883 vector = assign_irq_vector(irq, TARGET_CPUS);
1884 if (vector < 0)
1885 return vector;
1886
1887 cpus_clear(mask);
1888 cpu_set(vector >> 8, mask);
1889
1890 /*
1891 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1892 * Note that we mask (disable) IRQs now -- these get enabled when the
1893 * corresponding device driver registers for this IRQ.
1894 */
1895
1896 memset(&entry,0,sizeof(entry));
1897
1898 entry.delivery_mode = INT_DELIVERY_MODE;
1899 entry.dest_mode = INT_DEST_MODE;
1900 entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
1901 entry.trigger = triggering;
1902 entry.polarity = polarity;
1903 entry.mask = 1; /* Disabled (masked) */
1904 entry.vector = vector & 0xff;
1905
1906 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1907 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1908 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1909 triggering, polarity);
1910
1911 ioapic_register_intr(irq, entry.vector, triggering);
1912
1913 if (!ioapic && (irq < 16))
1914 disable_8259A_irq(irq);
1915
1916 ioapic_write_entry(ioapic, pin, entry);
1917
1918 spin_lock_irqsave(&ioapic_lock, flags);
1919 set_native_irq_info(irq, TARGET_CPUS);
1920 spin_unlock_irqrestore(&ioapic_lock, flags);
1921
1922 return 0;
1923 }
1924
1925 #endif /* CONFIG_ACPI */
1926
1927
1928 /*
1929 * This function currently is only a helper for the i386 smp boot process where
1930 * we need to reprogram the ioredtbls to cater for the cpus which have come online
1931 * so mask in all cases should simply be TARGET_CPUS
1932 */
1933 #ifdef CONFIG_SMP
1934 void __init setup_ioapic_dest(void)
1935 {
1936 int pin, ioapic, irq, irq_entry;
1937
1938 if (skip_ioapic_setup == 1)
1939 return;
1940
1941 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
1942 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
1943 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
1944 if (irq_entry == -1)
1945 continue;
1946 irq = pin_2_irq(irq_entry, ioapic, pin);
1947 set_ioapic_affinity_irq(irq, TARGET_CPUS);
1948 }
1949
1950 }
1951 }
1952 #endif
x86 "subsystem" repository