arch/mips/txx9/rbtx4938/setup.c

   1 /*
   2  * Setup pointers to hardware-dependent routines.
   3  * Copyright (C) 2000-2001 Toshiba Corporation
   4  *
   5  * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
   6  * terms of the GNU General Public License version 2. This program is
   7  * licensed "as is" without any warranty of any kind, whether express
   8  * or implied.
   9  *
  10  * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
  11  */
  12 #include <linux/init.h>
  13 #include <linux/types.h>
  14 #include <linux/ioport.h>
  15 #include <linux/delay.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/gpio.h>
  18 #include <linux/mtd/physmap.h>
  19
  20 #include <asm/reboot.h>
  21 #include <asm/io.h>
  22 #include <asm/txx9/generic.h>
  23 #include <asm/txx9/pci.h>
  24 #include <asm/txx9/rbtx4938.h>
  25 #include <linux/spi/spi.h>
  26 #include <asm/txx9/spi.h>
  27 #include <asm/txx9pio.h>
  28
  29 static void rbtx4938_machine_restart(char *command)
  30 {
  31         local_irq_disable();
  32         writeb(1, rbtx4938_softresetlock_addr);
  33         writeb(1, rbtx4938_sfvol_addr);
  34         writeb(1, rbtx4938_softreset_addr);
  35         /* fallback */
  36         (*_machine_halt)();
  37 }
  38
  39 static void __init rbtx4938_pci_setup(void)
  40 {
  41 #ifdef CONFIG_PCI
  42         int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
  43         struct pci_controller *c = &txx9_primary_pcic;
  44
  45         register_pci_controller(c);
  46
  47         if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
  48                 txx9_pci_option =
  49                         (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
  50                         TXX9_PCI_OPT_CLK_66; /* already configured */
  51
  52         /* Reset PCI Bus */
  53         writeb(0, rbtx4938_pcireset_addr);
  54         /* Reset PCIC */
  55         txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
  56         if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
  57             TXX9_PCI_OPT_CLK_66)
  58                 tx4938_pciclk66_setup();
  59         mdelay(10);
  60         /* clear PCIC reset */
  61         txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
  62         writeb(1, rbtx4938_pcireset_addr);
  63         iob();
  64
  65         tx4938_report_pciclk();
  66         tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
  67         if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
  68             TXX9_PCI_OPT_CLK_AUTO &&
  69             txx9_pci66_check(c, 0, 0)) {
  70                 /* Reset PCI Bus */
  71                 writeb(0, rbtx4938_pcireset_addr);
  72                 /* Reset PCIC */
  73                 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
  74                 tx4938_pciclk66_setup();
  75                 mdelay(10);
  76                 /* clear PCIC reset */
  77                 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
  78                 writeb(1, rbtx4938_pcireset_addr);
  79                 iob();
  80                 /* Reinitialize PCIC */
  81                 tx4938_report_pciclk();
  82                 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
  83         }
  84
  85         if (__raw_readq(&tx4938_ccfgptr->pcfg) &
  86             (TX4938_PCFG_ETH0_SEL|TX4938_PCFG_ETH1_SEL)) {
  87                 /* Reset PCIC1 */
  88                 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
  89                 /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
  90                 if (!(__raw_readq(&tx4938_ccfgptr->ccfg)
  91                       & TX4938_CCFG_PCI1DMD))
  92                         tx4938_ccfg_set(TX4938_CCFG_PCI1_66);
  93                 mdelay(10);
  94                 /* clear PCIC1 reset */
  95                 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
  96                 tx4938_report_pci1clk();
  97
  98                 /* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
  99                 c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
 100                 register_pci_controller(c);
 101                 tx4927_pcic_setup(tx4938_pcic1ptr, c, 0);
 102         }
 103         tx4938_setup_pcierr_irq();
 104 #endif /* CONFIG_PCI */
 105 }
 106
 107 /* SPI support */
 108
 109 /* chip select for SPI devices */
 110 #define SEEPROM1_CS     7       /* PIO7 */
 111 #define SEEPROM2_CS     0       /* IOC */
 112 #define SEEPROM3_CS     1       /* IOC */
 113 #define SRTC_CS 2       /* IOC */
 114
 115 static int __init rbtx4938_ethaddr_init(void)
 116 {
 117 #ifdef CONFIG_PCI
 118         unsigned char dat[17];
 119         unsigned char sum;
 120         int i;
 121
 122         /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
 123         if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) {
 124                 printk(KERN_ERR "seeprom: read error.\n");
 125                 return -ENODEV;
 126         } else {
 127                 if (strcmp(dat, "MAC") != 0)
 128                         printk(KERN_WARNING "seeprom: bad signature.\n");
 129                 for (i = 0, sum = 0; i < sizeof(dat); i++)
 130                         sum += dat[i];
 131                 if (sum)
 132                         printk(KERN_WARNING "seeprom: bad checksum.\n");
 133         }
 134         tx4938_ethaddr_init(&dat[4], &dat[4 + 6]);
 135 #endif /* CONFIG_PCI */
 136         return 0;
 137 }
 138
 139 static void __init rbtx4938_spi_setup(void)
 140 {
 141         /* set SPI_SEL */
 142         txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_SPI_SEL);
 143 }
 144
 145 static struct resource rbtx4938_fpga_resource;
 146
 147 static void __init rbtx4938_time_init(void)
 148 {
 149         tx4938_time_init(0);
 150 }
 151
 152 static void __init rbtx4938_mem_setup(void)
 153 {
 154         unsigned long long pcfg;
 155         char *argptr;
 156
 157         if (txx9_master_clock == 0)
 158                 txx9_master_clock = 25000000; /* 25MHz */
 159
 160         tx4938_setup();
 161
 162 #ifdef CONFIG_PCI
 163         txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
 164         txx9_board_pcibios_setup = tx4927_pcibios_setup;
 165 #else
 166         set_io_port_base(RBTX4938_ETHER_BASE);
 167 #endif
 168
 169         tx4938_sio_init(7372800, 0);
 170 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
 171         argptr = prom_getcmdline();
 172         if (!strstr(argptr, "console="))
 173                 strcat(argptr, " console=ttyS0,38400");
 174 #endif
 175
 176 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
 177         printk(KERN_INFO "PIOSEL: disabling both ata and nand selection\n");
 178         txx9_clear64(&tx4938_ccfgptr->pcfg,
 179                      TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
 180 #endif
 181
 182 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
 183         printk(KERN_INFO "PIOSEL: enabling nand selection\n");
 184         txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
 185         txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
 186 #endif
 187
 188 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
 189         printk(KERN_INFO "PIOSEL: enabling ata selection\n");
 190         txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
 191         txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
 192 #endif
 193
 194         rbtx4938_spi_setup();
 195         pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);    /* updated */
 196         /* fixup piosel */
 197         if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
 198             TX4938_PCFG_ATA_SEL)
 199                 writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04,
 200                        rbtx4938_piosel_addr);
 201         else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
 202                  TX4938_PCFG_NDF_SEL)
 203                 writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08,
 204                        rbtx4938_piosel_addr);
 205         else
 206                 writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04),
 207                        rbtx4938_piosel_addr);
 208
 209         rbtx4938_fpga_resource.name = "FPGA Registers";
 210         rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
 211         rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
 212         rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
 213         if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource))
 214                 printk(KERN_ERR "request resource for fpga failed\n");
 215
 216         _machine_restart = rbtx4938_machine_restart;
 217
 218         writeb(0xff, rbtx4938_led_addr);
 219         printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
 220                readb(rbtx4938_fpga_rev_addr),
 221                readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
 222 }
 223
 224 static void __init rbtx4938_ne_init(void)
 225 {
 226         struct resource res[] = {
 227                 {
 228                         .start  = RBTX4938_RTL_8019_BASE,
 229                         .end    = RBTX4938_RTL_8019_BASE + 0x20 - 1,
 230                         .flags  = IORESOURCE_IO,
 231                 }, {
 232                         .start  = RBTX4938_RTL_8019_IRQ,
 233                         .flags  = IORESOURCE_IRQ,
 234                 }
 235         };
 236         platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res));
 237 }
 238
 239 static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
 240
 241 static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset,
 242                                   int value)
 243 {
 244         u8 val;
 245         unsigned long flags;
 246         spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
 247         val = readb(rbtx4938_spics_addr);
 248         if (value)
 249                 val |= 1 << offset;
 250         else
 251                 val &= ~(1 << offset);
 252         writeb(val, rbtx4938_spics_addr);
 253         mmiowb();
 254         spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
 255 }
 256
 257 static int rbtx4938_spi_gpio_dir_out(struct gpio_chip *chip,
 258                                      unsigned int offset, int value)
 259 {
 260         rbtx4938_spi_gpio_set(chip, offset, value);
 261         return 0;
 262 }
 263
 264 static struct gpio_chip rbtx4938_spi_gpio_chip = {
 265         .set = rbtx4938_spi_gpio_set,
 266         .direction_output = rbtx4938_spi_gpio_dir_out,
 267         .label = "RBTX4938-SPICS",
 268         .base = 16,
 269         .ngpio = 3,
 270 };
 271
 272 static int __init rbtx4938_spi_init(void)
 273 {
 274         struct spi_board_info srtc_info = {
 275                 .modalias = "rtc-rs5c348",
 276                 .max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */
 277                 .bus_num = 0,
 278                 .chip_select = 16 + SRTC_CS,
 279                 /* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS  */
 280                 .mode = SPI_MODE_1 | SPI_CS_HIGH,
 281         };
 282         spi_register_board_info(&srtc_info, 1);
 283         spi_eeprom_register(SEEPROM1_CS);
 284         spi_eeprom_register(16 + SEEPROM2_CS);
 285         spi_eeprom_register(16 + SEEPROM3_CS);
 286         gpio_request(16 + SRTC_CS, "rtc-rs5c348");
 287         gpio_direction_output(16 + SRTC_CS, 0);
 288         gpio_request(SEEPROM1_CS, "seeprom1");
 289         gpio_direction_output(SEEPROM1_CS, 1);
 290         gpio_request(16 + SEEPROM2_CS, "seeprom2");
 291         gpio_direction_output(16 + SEEPROM2_CS, 1);
 292         gpio_request(16 + SEEPROM3_CS, "seeprom3");
 293         gpio_direction_output(16 + SEEPROM3_CS, 1);
 294         tx4938_spi_init(0);
 295         return 0;
 296 }
 297
 298 static void __init rbtx4938_mtd_init(void)
 299 {
 300         struct physmap_flash_data pdata = {
 301                 .width = 4,
 302         };
 303
 304         switch (readb(rbtx4938_bdipsw_addr) & 7) {
 305         case 0:
 306                 /* Boot */
 307                 txx9_physmap_flash_init(0, 0x1fc00000, 0x400000, &pdata);
 308                 /* System */
 309                 txx9_physmap_flash_init(1, 0x1e000000, 0x1000000, &pdata);
 310                 break;
 311         case 1:
 312                 /* System */
 313                 txx9_physmap_flash_init(0, 0x1f000000, 0x1000000, &pdata);
 314                 /* Boot */
 315                 txx9_physmap_flash_init(1, 0x1ec00000, 0x400000, &pdata);
 316                 break;
 317         case 2:
 318                 /* Ext */
 319                 txx9_physmap_flash_init(0, 0x1f000000, 0x1000000, &pdata);
 320                 /* System */
 321                 txx9_physmap_flash_init(1, 0x1e000000, 0x1000000, &pdata);
 322                 /* Boot */
 323                 txx9_physmap_flash_init(2, 0x1dc00000, 0x400000, &pdata);
 324                 break;
 325         case 3:
 326                 /* Boot */
 327                 txx9_physmap_flash_init(1, 0x1bc00000, 0x400000, &pdata);
 328                 /* System */
 329                 txx9_physmap_flash_init(2, 0x1a000000, 0x1000000, &pdata);
 330                 break;
 331         }
 332 }
 333
 334 static void __init rbtx4938_arch_init(void)
 335 {
 336         gpiochip_add(&rbtx4938_spi_gpio_chip);
 337         rbtx4938_pci_setup();
 338         rbtx4938_spi_init();
 339 }
 340
 341 static void __init rbtx4938_device_init(void)
 342 {
 343         rbtx4938_ethaddr_init();
 344         rbtx4938_ne_init();
 345         tx4938_wdt_init();
 346         rbtx4938_mtd_init();
 347 }
 348
 349 struct txx9_board_vec rbtx4938_vec __initdata = {
 350         .system = "Toshiba RBTX4938",
 351         .prom_init = rbtx4938_prom_init,
 352         .mem_setup = rbtx4938_mem_setup,
 353         .irq_setup = rbtx4938_irq_setup,
 354         .time_init = rbtx4938_time_init,
 355         .device_init = rbtx4938_device_init,
 356         .arch_init = rbtx4938_arch_init,
 357 #ifdef CONFIG_PCI
 358         .pci_map_irq = rbtx4938_pci_map_irq,
 359 #endif
 360 };