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KVM: VMX: Split up vmx_complete_interrupts()
[linux-2.6/x86.git] / arch / x86 / kvm / vmx.c
blob927d8404505a74cb5a3154f9509217ad734f7719
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affilates.
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
19 #include "irq.h"
20 #include "mmu.h"
21
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
33 #include "x86.h"
34
35 #include <asm/io.h>
36 #include <asm/desc.h>
37 #include <asm/vmx.h>
38 #include <asm/virtext.h>
39 #include <asm/mce.h>
40 #include <asm/i387.h>
41 #include <asm/xcr.h>
42
43 #include "trace.h"
44
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46
47 MODULE_AUTHOR("Qumranet");
48 MODULE_LICENSE("GPL");
49
50 static int __read_mostly bypass_guest_pf = 1;
51 module_param(bypass_guest_pf, bool, S_IRUGO);
52
53 static int __read_mostly enable_vpid = 1;
54 module_param_named(vpid, enable_vpid, bool, 0444);
55
56 static int __read_mostly flexpriority_enabled = 1;
57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
58
59 static int __read_mostly enable_ept = 1;
60 module_param_named(ept, enable_ept, bool, S_IRUGO);
61
62 static int __read_mostly enable_unrestricted_guest = 1;
63 module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
66 static int __read_mostly emulate_invalid_guest_state = 0;
67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
68
69 static int __read_mostly vmm_exclusive = 1;
70 module_param(vmm_exclusive, bool, S_IRUGO);
71
72 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
73 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
74 #define KVM_GUEST_CR0_MASK \
75 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
76 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
77 (X86_CR0_WP | X86_CR0_NE)
78 #define KVM_VM_CR0_ALWAYS_ON \
79 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
80 #define KVM_CR4_GUEST_OWNED_BITS \
81 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
82 | X86_CR4_OSXMMEXCPT)
83
84 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
85 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
86
87 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
88
89 /*
90 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
91 * ple_gap: upper bound on the amount of time between two successive
92 * executions of PAUSE in a loop. Also indicate if ple enabled.
93 * According to test, this time is usually small than 41 cycles.
94 * ple_window: upper bound on the amount of time a guest is allowed to execute
95 * in a PAUSE loop. Tests indicate that most spinlocks are held for
96 * less than 2^12 cycles
97 * Time is measured based on a counter that runs at the same rate as the TSC,
98 * refer SDM volume 3b section 21.6.13 & 22.1.3.
99 */
100 #define KVM_VMX_DEFAULT_PLE_GAP 41
101 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
102 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
103 module_param(ple_gap, int, S_IRUGO);
104
105 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
106 module_param(ple_window, int, S_IRUGO);
107
108 #define NR_AUTOLOAD_MSRS 1
109
110 struct vmcs {
111 u32 revision_id;
112 u32 abort;
113 char data[0];
114 };
115
116 struct shared_msr_entry {
117 unsigned index;
118 u64 data;
119 u64 mask;
120 };
121
122 struct vcpu_vmx {
123 struct kvm_vcpu vcpu;
124 struct list_head local_vcpus_link;
125 unsigned long host_rsp;
126 int launched;
127 u8 fail;
128 u32 exit_intr_info;
129 u32 idt_vectoring_info;
130 struct shared_msr_entry *guest_msrs;
131 int nmsrs;
132 int save_nmsrs;
133 #ifdef CONFIG_X86_64
134 u64 msr_host_kernel_gs_base;
135 u64 msr_guest_kernel_gs_base;
136 #endif
137 struct vmcs *vmcs;
138 struct msr_autoload {
139 unsigned nr;
140 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
141 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
142 } msr_autoload;
143 struct {
144 int loaded;
145 u16 fs_sel, gs_sel, ldt_sel;
146 int gs_ldt_reload_needed;
147 int fs_reload_needed;
148 } host_state;
149 struct {
150 int vm86_active;
151 ulong save_rflags;
152 struct kvm_save_segment {
153 u16 selector;
154 unsigned long base;
155 u32 limit;
156 u32 ar;
157 } tr, es, ds, fs, gs;
158 struct {
159 bool pending;
160 u8 vector;
161 unsigned rip;
162 } irq;
163 } rmode;
164 int vpid;
165 bool emulation_required;
166
167 /* Support for vnmi-less CPUs */
168 int soft_vnmi_blocked;
169 ktime_t entry_time;
170 s64 vnmi_blocked_time;
171 u32 exit_reason;
172
173 bool rdtscp_enabled;
174 };
175
176 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
177 {
178 return container_of(vcpu, struct vcpu_vmx, vcpu);
179 }
180
181 static int init_rmode(struct kvm *kvm);
182 static u64 construct_eptp(unsigned long root_hpa);
183 static void kvm_cpu_vmxon(u64 addr);
184 static void kvm_cpu_vmxoff(void);
185
186 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
187 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
188 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
189 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
190
191 static unsigned long *vmx_io_bitmap_a;
192 static unsigned long *vmx_io_bitmap_b;
193 static unsigned long *vmx_msr_bitmap_legacy;
194 static unsigned long *vmx_msr_bitmap_longmode;
195
196 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
197 static DEFINE_SPINLOCK(vmx_vpid_lock);
198
199 static struct vmcs_config {
200 int size;
201 int order;
202 u32 revision_id;
203 u32 pin_based_exec_ctrl;
204 u32 cpu_based_exec_ctrl;
205 u32 cpu_based_2nd_exec_ctrl;
206 u32 vmexit_ctrl;
207 u32 vmentry_ctrl;
208 } vmcs_config;
209
210 static struct vmx_capability {
211 u32 ept;
212 u32 vpid;
213 } vmx_capability;
214
215 #define VMX_SEGMENT_FIELD(seg) \
216 [VCPU_SREG_##seg] = { \
217 .selector = GUEST_##seg##_SELECTOR, \
218 .base = GUEST_##seg##_BASE, \
219 .limit = GUEST_##seg##_LIMIT, \
220 .ar_bytes = GUEST_##seg##_AR_BYTES, \
221 }
222
223 static struct kvm_vmx_segment_field {
224 unsigned selector;
225 unsigned base;
226 unsigned limit;
227 unsigned ar_bytes;
228 } kvm_vmx_segment_fields[] = {
229 VMX_SEGMENT_FIELD(CS),
230 VMX_SEGMENT_FIELD(DS),
231 VMX_SEGMENT_FIELD(ES),
232 VMX_SEGMENT_FIELD(FS),
233 VMX_SEGMENT_FIELD(GS),
234 VMX_SEGMENT_FIELD(SS),
235 VMX_SEGMENT_FIELD(TR),
236 VMX_SEGMENT_FIELD(LDTR),
237 };
238
239 static u64 host_efer;
240
241 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
242
243 /*
244 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
245 * away by decrementing the array size.
246 */
247 static const u32 vmx_msr_index[] = {
248 #ifdef CONFIG_X86_64
249 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
250 #endif
251 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
252 };
253 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
254
255 static inline bool is_page_fault(u32 intr_info)
256 {
257 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
258 INTR_INFO_VALID_MASK)) ==
259 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
260 }
261
262 static inline bool is_no_device(u32 intr_info)
263 {
264 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
265 INTR_INFO_VALID_MASK)) ==
266 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
267 }
268
269 static inline bool is_invalid_opcode(u32 intr_info)
270 {
271 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
272 INTR_INFO_VALID_MASK)) ==
273 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
274 }
275
276 static inline bool is_external_interrupt(u32 intr_info)
277 {
278 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
279 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
280 }
281
282 static inline bool is_machine_check(u32 intr_info)
283 {
284 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
285 INTR_INFO_VALID_MASK)) ==
286 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
287 }
288
289 static inline bool cpu_has_vmx_msr_bitmap(void)
290 {
291 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
292 }
293
294 static inline bool cpu_has_vmx_tpr_shadow(void)
295 {
296 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
297 }
298
299 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
300 {
301 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
302 }
303
304 static inline bool cpu_has_secondary_exec_ctrls(void)
305 {
306 return vmcs_config.cpu_based_exec_ctrl &
307 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
308 }
309
310 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
311 {
312 return vmcs_config.cpu_based_2nd_exec_ctrl &
313 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
314 }
315
316 static inline bool cpu_has_vmx_flexpriority(void)
317 {
318 return cpu_has_vmx_tpr_shadow() &&
319 cpu_has_vmx_virtualize_apic_accesses();
320 }
321
322 static inline bool cpu_has_vmx_ept_execute_only(void)
323 {
324 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
325 }
326
327 static inline bool cpu_has_vmx_eptp_uncacheable(void)
328 {
329 return vmx_capability.ept & VMX_EPTP_UC_BIT;
330 }
331
332 static inline bool cpu_has_vmx_eptp_writeback(void)
333 {
334 return vmx_capability.ept & VMX_EPTP_WB_BIT;
335 }
336
337 static inline bool cpu_has_vmx_ept_2m_page(void)
338 {
339 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
340 }
341
342 static inline bool cpu_has_vmx_ept_1g_page(void)
343 {
344 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
345 }
346
347 static inline bool cpu_has_vmx_ept_4levels(void)
348 {
349 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
350 }
351
352 static inline bool cpu_has_vmx_invept_individual_addr(void)
353 {
354 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
355 }
356
357 static inline bool cpu_has_vmx_invept_context(void)
358 {
359 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
360 }
361
362 static inline bool cpu_has_vmx_invept_global(void)
363 {
364 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
365 }
366
367 static inline bool cpu_has_vmx_invvpid_single(void)
368 {
369 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
370 }
371
372 static inline bool cpu_has_vmx_invvpid_global(void)
373 {
374 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
375 }
376
377 static inline bool cpu_has_vmx_ept(void)
378 {
379 return vmcs_config.cpu_based_2nd_exec_ctrl &
380 SECONDARY_EXEC_ENABLE_EPT;
381 }
382
383 static inline bool cpu_has_vmx_unrestricted_guest(void)
384 {
385 return vmcs_config.cpu_based_2nd_exec_ctrl &
386 SECONDARY_EXEC_UNRESTRICTED_GUEST;
387 }
388
389 static inline bool cpu_has_vmx_ple(void)
390 {
391 return vmcs_config.cpu_based_2nd_exec_ctrl &
392 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
393 }
394
395 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
396 {
397 return flexpriority_enabled && irqchip_in_kernel(kvm);
398 }
399
400 static inline bool cpu_has_vmx_vpid(void)
401 {
402 return vmcs_config.cpu_based_2nd_exec_ctrl &
403 SECONDARY_EXEC_ENABLE_VPID;
404 }
405
406 static inline bool cpu_has_vmx_rdtscp(void)
407 {
408 return vmcs_config.cpu_based_2nd_exec_ctrl &
409 SECONDARY_EXEC_RDTSCP;
410 }
411
412 static inline bool cpu_has_virtual_nmis(void)
413 {
414 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
415 }
416
417 static inline bool cpu_has_vmx_wbinvd_exit(void)
418 {
419 return vmcs_config.cpu_based_2nd_exec_ctrl &
420 SECONDARY_EXEC_WBINVD_EXITING;
421 }
422
423 static inline bool report_flexpriority(void)
424 {
425 return flexpriority_enabled;
426 }
427
428 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
429 {
430 int i;
431
432 for (i = 0; i < vmx->nmsrs; ++i)
433 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
434 return i;
435 return -1;
436 }
437
438 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
439 {
440 struct {
441 u64 vpid : 16;
442 u64 rsvd : 48;
443 u64 gva;
444 } operand = { vpid, 0, gva };
445
446 asm volatile (__ex(ASM_VMX_INVVPID)
447 /* CF==1 or ZF==1 --> rc = -1 */
448 "; ja 1f ; ud2 ; 1:"
449 : : "a"(&operand), "c"(ext) : "cc", "memory");
450 }
451
452 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
453 {
454 struct {
455 u64 eptp, gpa;
456 } operand = {eptp, gpa};
457
458 asm volatile (__ex(ASM_VMX_INVEPT)
459 /* CF==1 or ZF==1 --> rc = -1 */
460 "; ja 1f ; ud2 ; 1:\n"
461 : : "a" (&operand), "c" (ext) : "cc", "memory");
462 }
463
464 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
465 {
466 int i;
467
468 i = __find_msr_index(vmx, msr);
469 if (i >= 0)
470 return &vmx->guest_msrs[i];
471 return NULL;
472 }
473
474 static void vmcs_clear(struct vmcs *vmcs)
475 {
476 u64 phys_addr = __pa(vmcs);
477 u8 error;
478
479 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
480 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
481 : "cc", "memory");
482 if (error)
483 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
484 vmcs, phys_addr);
485 }
486
487 static void vmcs_load(struct vmcs *vmcs)
488 {
489 u64 phys_addr = __pa(vmcs);
490 u8 error;
491
492 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
493 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
494 : "cc", "memory");
495 if (error)
496 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
497 vmcs, phys_addr);
498 }
499
500 static void __vcpu_clear(void *arg)
501 {
502 struct vcpu_vmx *vmx = arg;
503 int cpu = raw_smp_processor_id();
504
505 if (vmx->vcpu.cpu == cpu)
506 vmcs_clear(vmx->vmcs);
507 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
508 per_cpu(current_vmcs, cpu) = NULL;
509 list_del(&vmx->local_vcpus_link);
510 vmx->vcpu.cpu = -1;
511 vmx->launched = 0;
512 }
513
514 static void vcpu_clear(struct vcpu_vmx *vmx)
515 {
516 if (vmx->vcpu.cpu == -1)
517 return;
518 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
519 }
520
521 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
522 {
523 if (vmx->vpid == 0)
524 return;
525
526 if (cpu_has_vmx_invvpid_single())
527 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
528 }
529
530 static inline void vpid_sync_vcpu_global(void)
531 {
532 if (cpu_has_vmx_invvpid_global())
533 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
534 }
535
536 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
537 {
538 if (cpu_has_vmx_invvpid_single())
539 vpid_sync_vcpu_single(vmx);
540 else
541 vpid_sync_vcpu_global();
542 }
543
544 static inline void ept_sync_global(void)
545 {
546 if (cpu_has_vmx_invept_global())
547 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
548 }
549
550 static inline void ept_sync_context(u64 eptp)
551 {
552 if (enable_ept) {
553 if (cpu_has_vmx_invept_context())
554 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
555 else
556 ept_sync_global();
557 }
558 }
559
560 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
561 {
562 if (enable_ept) {
563 if (cpu_has_vmx_invept_individual_addr())
564 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
565 eptp, gpa);
566 else
567 ept_sync_context(eptp);
568 }
569 }
570
571 static unsigned long vmcs_readl(unsigned long field)
572 {
573 unsigned long value;
574
575 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
576 : "=a"(value) : "d"(field) : "cc");
577 return value;
578 }
579
580 static u16 vmcs_read16(unsigned long field)
581 {
582 return vmcs_readl(field);
583 }
584
585 static u32 vmcs_read32(unsigned long field)
586 {
587 return vmcs_readl(field);
588 }
589
590 static u64 vmcs_read64(unsigned long field)
591 {
592 #ifdef CONFIG_X86_64
593 return vmcs_readl(field);
594 #else
595 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
596 #endif
597 }
598
599 static noinline void vmwrite_error(unsigned long field, unsigned long value)
600 {
601 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
602 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
603 dump_stack();
604 }
605
606 static void vmcs_writel(unsigned long field, unsigned long value)
607 {
608 u8 error;
609
610 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
611 : "=q"(error) : "a"(value), "d"(field) : "cc");
612 if (unlikely(error))
613 vmwrite_error(field, value);
614 }
615
616 static void vmcs_write16(unsigned long field, u16 value)
617 {
618 vmcs_writel(field, value);
619 }
620
621 static void vmcs_write32(unsigned long field, u32 value)
622 {
623 vmcs_writel(field, value);
624 }
625
626 static void vmcs_write64(unsigned long field, u64 value)
627 {
628 vmcs_writel(field, value);
629 #ifndef CONFIG_X86_64
630 asm volatile ("");
631 vmcs_writel(field+1, value >> 32);
632 #endif
633 }
634
635 static void vmcs_clear_bits(unsigned long field, u32 mask)
636 {
637 vmcs_writel(field, vmcs_readl(field) & ~mask);
638 }
639
640 static void vmcs_set_bits(unsigned long field, u32 mask)
641 {
642 vmcs_writel(field, vmcs_readl(field) | mask);
643 }
644
645 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
646 {
647 u32 eb;
648
649 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
650 (1u << NM_VECTOR) | (1u << DB_VECTOR);
651 if ((vcpu->guest_debug &
652 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
653 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
654 eb |= 1u << BP_VECTOR;
655 if (to_vmx(vcpu)->rmode.vm86_active)
656 eb = ~0;
657 if (enable_ept)
658 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
659 if (vcpu->fpu_active)
660 eb &= ~(1u << NM_VECTOR);
661 vmcs_write32(EXCEPTION_BITMAP, eb);
662 }
663
664 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
665 {
666 unsigned i;
667 struct msr_autoload *m = &vmx->msr_autoload;
668
669 for (i = 0; i < m->nr; ++i)
670 if (m->guest[i].index == msr)
671 break;
672
673 if (i == m->nr)
674 return;
675 --m->nr;
676 m->guest[i] = m->guest[m->nr];
677 m->host[i] = m->host[m->nr];
678 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
679 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
680 }
681
682 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
683 u64 guest_val, u64 host_val)
684 {
685 unsigned i;
686 struct msr_autoload *m = &vmx->msr_autoload;
687
688 for (i = 0; i < m->nr; ++i)
689 if (m->guest[i].index == msr)
690 break;
691
692 if (i == m->nr) {
693 ++m->nr;
694 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
695 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
696 }
697
698 m->guest[i].index = msr;
699 m->guest[i].value = guest_val;
700 m->host[i].index = msr;
701 m->host[i].value = host_val;
702 }
703
704 static void reload_tss(void)
705 {
706 /*
707 * VT restores TR but not its size. Useless.
708 */
709 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
710 struct desc_struct *descs;
711
712 descs = (void *)gdt->address;
713 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
714 load_TR_desc();
715 }
716
717 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
718 {
719 u64 guest_efer;
720 u64 ignore_bits;
721
722 guest_efer = vmx->vcpu.arch.efer;
723
724 /*
725 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
726 * outside long mode
727 */
728 ignore_bits = EFER_NX | EFER_SCE;
729 #ifdef CONFIG_X86_64
730 ignore_bits |= EFER_LMA | EFER_LME;
731 /* SCE is meaningful only in long mode on Intel */
732 if (guest_efer & EFER_LMA)
733 ignore_bits &= ~(u64)EFER_SCE;
734 #endif
735 guest_efer &= ~ignore_bits;
736 guest_efer |= host_efer & ignore_bits;
737 vmx->guest_msrs[efer_offset].data = guest_efer;
738 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
739
740 clear_atomic_switch_msr(vmx, MSR_EFER);
741 /* On ept, can't emulate nx, and must switch nx atomically */
742 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
743 guest_efer = vmx->vcpu.arch.efer;
744 if (!(guest_efer & EFER_LMA))
745 guest_efer &= ~EFER_LME;
746 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
747 return false;
748 }
749
750 return true;
751 }
752
753 static unsigned long segment_base(u16 selector)
754 {
755 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
756 struct desc_struct *d;
757 unsigned long table_base;
758 unsigned long v;
759
760 if (!(selector & ~3))
761 return 0;
762
763 table_base = gdt->address;
764
765 if (selector & 4) { /* from ldt */
766 u16 ldt_selector = kvm_read_ldt();
767
768 if (!(ldt_selector & ~3))
769 return 0;
770
771 table_base = segment_base(ldt_selector);
772 }
773 d = (struct desc_struct *)(table_base + (selector & ~7));
774 v = get_desc_base(d);
775 #ifdef CONFIG_X86_64
776 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
777 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
778 #endif
779 return v;
780 }
781
782 static inline unsigned long kvm_read_tr_base(void)
783 {
784 u16 tr;
785 asm("str %0" : "=g"(tr));
786 return segment_base(tr);
787 }
788
789 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
790 {
791 struct vcpu_vmx *vmx = to_vmx(vcpu);
792 int i;
793
794 if (vmx->host_state.loaded)
795 return;
796
797 vmx->host_state.loaded = 1;
798 /*
799 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
800 * allow segment selectors with cpl > 0 or ti == 1.
801 */
802 vmx->host_state.ldt_sel = kvm_read_ldt();
803 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
804 savesegment(fs, vmx->host_state.fs_sel);
805 if (!(vmx->host_state.fs_sel & 7)) {
806 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
807 vmx->host_state.fs_reload_needed = 0;
808 } else {
809 vmcs_write16(HOST_FS_SELECTOR, 0);
810 vmx->host_state.fs_reload_needed = 1;
811 }
812 savesegment(gs, vmx->host_state.gs_sel);
813 if (!(vmx->host_state.gs_sel & 7))
814 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
815 else {
816 vmcs_write16(HOST_GS_SELECTOR, 0);
817 vmx->host_state.gs_ldt_reload_needed = 1;
818 }
819
820 #ifdef CONFIG_X86_64
821 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
822 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
823 #else
824 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
825 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
826 #endif
827
828 #ifdef CONFIG_X86_64
829 if (is_long_mode(&vmx->vcpu)) {
830 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
831 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
832 }
833 #endif
834 for (i = 0; i < vmx->save_nmsrs; ++i)
835 kvm_set_shared_msr(vmx->guest_msrs[i].index,
836 vmx->guest_msrs[i].data,
837 vmx->guest_msrs[i].mask);
838 }
839
840 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
841 {
842 if (!vmx->host_state.loaded)
843 return;
844
845 ++vmx->vcpu.stat.host_state_reload;
846 vmx->host_state.loaded = 0;
847 if (vmx->host_state.fs_reload_needed)
848 loadsegment(fs, vmx->host_state.fs_sel);
849 if (vmx->host_state.gs_ldt_reload_needed) {
850 kvm_load_ldt(vmx->host_state.ldt_sel);
851 #ifdef CONFIG_X86_64
852 load_gs_index(vmx->host_state.gs_sel);
853 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
854 #else
855 loadsegment(gs, vmx->host_state.gs_sel);
856 #endif
857 }
858 reload_tss();
859 #ifdef CONFIG_X86_64
860 if (is_long_mode(&vmx->vcpu)) {
861 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
862 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
863 }
864 #endif
865 if (current_thread_info()->status & TS_USEDFPU)
866 clts();
867 load_gdt(&__get_cpu_var(host_gdt));
868 }
869
870 static void vmx_load_host_state(struct vcpu_vmx *vmx)
871 {
872 preempt_disable();
873 __vmx_load_host_state(vmx);
874 preempt_enable();
875 }
876
877 /*
878 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
879 * vcpu mutex is already taken.
880 */
881 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
882 {
883 struct vcpu_vmx *vmx = to_vmx(vcpu);
884 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
885
886 if (!vmm_exclusive)
887 kvm_cpu_vmxon(phys_addr);
888 else if (vcpu->cpu != cpu)
889 vcpu_clear(vmx);
890
891 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
892 per_cpu(current_vmcs, cpu) = vmx->vmcs;
893 vmcs_load(vmx->vmcs);
894 }
895
896 if (vcpu->cpu != cpu) {
897 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
898 unsigned long sysenter_esp;
899
900 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
901 local_irq_disable();
902 list_add(&vmx->local_vcpus_link,
903 &per_cpu(vcpus_on_cpu, cpu));
904 local_irq_enable();
905
906 /*
907 * Linux uses per-cpu TSS and GDT, so set these when switching
908 * processors.
909 */
910 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
911 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
912
913 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
914 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
915 }
916 }
917
918 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
919 {
920 __vmx_load_host_state(to_vmx(vcpu));
921 if (!vmm_exclusive) {
922 __vcpu_clear(to_vmx(vcpu));
923 kvm_cpu_vmxoff();
924 }
925 }
926
927 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
928 {
929 ulong cr0;
930
931 if (vcpu->fpu_active)
932 return;
933 vcpu->fpu_active = 1;
934 cr0 = vmcs_readl(GUEST_CR0);
935 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
936 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
937 vmcs_writel(GUEST_CR0, cr0);
938 update_exception_bitmap(vcpu);
939 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
940 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
941 }
942
943 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
944
945 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
946 {
947 vmx_decache_cr0_guest_bits(vcpu);
948 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
949 update_exception_bitmap(vcpu);
950 vcpu->arch.cr0_guest_owned_bits = 0;
951 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
952 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
953 }
954
955 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
956 {
957 unsigned long rflags, save_rflags;
958
959 rflags = vmcs_readl(GUEST_RFLAGS);
960 if (to_vmx(vcpu)->rmode.vm86_active) {
961 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
962 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
963 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
964 }
965 return rflags;
966 }
967
968 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
969 {
970 if (to_vmx(vcpu)->rmode.vm86_active) {
971 to_vmx(vcpu)->rmode.save_rflags = rflags;
972 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
973 }
974 vmcs_writel(GUEST_RFLAGS, rflags);
975 }
976
977 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
978 {
979 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
980 int ret = 0;
981
982 if (interruptibility & GUEST_INTR_STATE_STI)
983 ret |= KVM_X86_SHADOW_INT_STI;
984 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
985 ret |= KVM_X86_SHADOW_INT_MOV_SS;
986
987 return ret & mask;
988 }
989
990 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
991 {
992 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
993 u32 interruptibility = interruptibility_old;
994
995 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
996
997 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
998 interruptibility |= GUEST_INTR_STATE_MOV_SS;
999 else if (mask & KVM_X86_SHADOW_INT_STI)
1000 interruptibility |= GUEST_INTR_STATE_STI;
1001
1002 if ((interruptibility != interruptibility_old))
1003 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1004 }
1005
1006 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1007 {
1008 unsigned long rip;
1009
1010 rip = kvm_rip_read(vcpu);
1011 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1012 kvm_rip_write(vcpu, rip);
1013
1014 /* skipping an emulated instruction also counts */
1015 vmx_set_interrupt_shadow(vcpu, 0);
1016 }
1017
1018 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1019 bool has_error_code, u32 error_code,
1020 bool reinject)
1021 {
1022 struct vcpu_vmx *vmx = to_vmx(vcpu);
1023 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1024
1025 if (has_error_code) {
1026 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1027 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1028 }
1029
1030 if (vmx->rmode.vm86_active) {
1031 vmx->rmode.irq.pending = true;
1032 vmx->rmode.irq.vector = nr;
1033 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
1034 if (kvm_exception_is_soft(nr))
1035 vmx->rmode.irq.rip +=
1036 vmx->vcpu.arch.event_exit_inst_len;
1037 intr_info |= INTR_TYPE_SOFT_INTR;
1038 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1039 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1040 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1041 return;
1042 }
1043
1044 if (kvm_exception_is_soft(nr)) {
1045 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1046 vmx->vcpu.arch.event_exit_inst_len);
1047 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1048 } else
1049 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1050
1051 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1052 }
1053
1054 static bool vmx_rdtscp_supported(void)
1055 {
1056 return cpu_has_vmx_rdtscp();
1057 }
1058
1059 /*
1060 * Swap MSR entry in host/guest MSR entry array.
1061 */
1062 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1063 {
1064 struct shared_msr_entry tmp;
1065
1066 tmp = vmx->guest_msrs[to];
1067 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1068 vmx->guest_msrs[from] = tmp;
1069 }
1070
1071 /*
1072 * Set up the vmcs to automatically save and restore system
1073 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1074 * mode, as fiddling with msrs is very expensive.
1075 */
1076 static void setup_msrs(struct vcpu_vmx *vmx)
1077 {
1078 int save_nmsrs, index;
1079 unsigned long *msr_bitmap;
1080
1081 vmx_load_host_state(vmx);
1082 save_nmsrs = 0;
1083 #ifdef CONFIG_X86_64
1084 if (is_long_mode(&vmx->vcpu)) {
1085 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1086 if (index >= 0)
1087 move_msr_up(vmx, index, save_nmsrs++);
1088 index = __find_msr_index(vmx, MSR_LSTAR);
1089 if (index >= 0)
1090 move_msr_up(vmx, index, save_nmsrs++);
1091 index = __find_msr_index(vmx, MSR_CSTAR);
1092 if (index >= 0)
1093 move_msr_up(vmx, index, save_nmsrs++);
1094 index = __find_msr_index(vmx, MSR_TSC_AUX);
1095 if (index >= 0 && vmx->rdtscp_enabled)
1096 move_msr_up(vmx, index, save_nmsrs++);
1097 /*
1098 * MSR_STAR is only needed on long mode guests, and only
1099 * if efer.sce is enabled.
1100 */
1101 index = __find_msr_index(vmx, MSR_STAR);
1102 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1103 move_msr_up(vmx, index, save_nmsrs++);
1104 }
1105 #endif
1106 index = __find_msr_index(vmx, MSR_EFER);
1107 if (index >= 0 && update_transition_efer(vmx, index))
1108 move_msr_up(vmx, index, save_nmsrs++);
1109
1110 vmx->save_nmsrs = save_nmsrs;
1111
1112 if (cpu_has_vmx_msr_bitmap()) {
1113 if (is_long_mode(&vmx->vcpu))
1114 msr_bitmap = vmx_msr_bitmap_longmode;
1115 else
1116 msr_bitmap = vmx_msr_bitmap_legacy;
1117
1118 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1119 }
1120 }
1121
1122 /*
1123 * reads and returns guest's timestamp counter "register"
1124 * guest_tsc = host_tsc + tsc_offset -- 21.3
1125 */
1126 static u64 guest_read_tsc(void)
1127 {
1128 u64 host_tsc, tsc_offset;
1129
1130 rdtscll(host_tsc);
1131 tsc_offset = vmcs_read64(TSC_OFFSET);
1132 return host_tsc + tsc_offset;
1133 }
1134
1135 /*
1136 * writes 'offset' into guest's timestamp counter offset register
1137 */
1138 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1139 {
1140 vmcs_write64(TSC_OFFSET, offset);
1141 }
1142
1143 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1144 {
1145 u64 offset = vmcs_read64(TSC_OFFSET);
1146 vmcs_write64(TSC_OFFSET, offset + adjustment);
1147 }
1148
1149 /*
1150 * Reads an msr value (of 'msr_index') into 'pdata'.
1151 * Returns 0 on success, non-0 otherwise.
1152 * Assumes vcpu_load() was already called.
1153 */
1154 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1155 {
1156 u64 data;
1157 struct shared_msr_entry *msr;
1158
1159 if (!pdata) {
1160 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1161 return -EINVAL;
1162 }
1163
1164 switch (msr_index) {
1165 #ifdef CONFIG_X86_64
1166 case MSR_FS_BASE:
1167 data = vmcs_readl(GUEST_FS_BASE);
1168 break;
1169 case MSR_GS_BASE:
1170 data = vmcs_readl(GUEST_GS_BASE);
1171 break;
1172 case MSR_KERNEL_GS_BASE:
1173 vmx_load_host_state(to_vmx(vcpu));
1174 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1175 break;
1176 #endif
1177 case MSR_EFER:
1178 return kvm_get_msr_common(vcpu, msr_index, pdata);
1179 case MSR_IA32_TSC:
1180 data = guest_read_tsc();
1181 break;
1182 case MSR_IA32_SYSENTER_CS:
1183 data = vmcs_read32(GUEST_SYSENTER_CS);
1184 break;
1185 case MSR_IA32_SYSENTER_EIP:
1186 data = vmcs_readl(GUEST_SYSENTER_EIP);
1187 break;
1188 case MSR_IA32_SYSENTER_ESP:
1189 data = vmcs_readl(GUEST_SYSENTER_ESP);
1190 break;
1191 case MSR_TSC_AUX:
1192 if (!to_vmx(vcpu)->rdtscp_enabled)
1193 return 1;
1194 /* Otherwise falls through */
1195 default:
1196 vmx_load_host_state(to_vmx(vcpu));
1197 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1198 if (msr) {
1199 vmx_load_host_state(to_vmx(vcpu));
1200 data = msr->data;
1201 break;
1202 }
1203 return kvm_get_msr_common(vcpu, msr_index, pdata);
1204 }
1205
1206 *pdata = data;
1207 return 0;
1208 }
1209
1210 /*
1211 * Writes msr value into into the appropriate "register".
1212 * Returns 0 on success, non-0 otherwise.
1213 * Assumes vcpu_load() was already called.
1214 */
1215 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1216 {
1217 struct vcpu_vmx *vmx = to_vmx(vcpu);
1218 struct shared_msr_entry *msr;
1219 int ret = 0;
1220
1221 switch (msr_index) {
1222 case MSR_EFER:
1223 vmx_load_host_state(vmx);
1224 ret = kvm_set_msr_common(vcpu, msr_index, data);
1225 break;
1226 #ifdef CONFIG_X86_64
1227 case MSR_FS_BASE:
1228 vmcs_writel(GUEST_FS_BASE, data);
1229 break;
1230 case MSR_GS_BASE:
1231 vmcs_writel(GUEST_GS_BASE, data);
1232 break;
1233 case MSR_KERNEL_GS_BASE:
1234 vmx_load_host_state(vmx);
1235 vmx->msr_guest_kernel_gs_base = data;
1236 break;
1237 #endif
1238 case MSR_IA32_SYSENTER_CS:
1239 vmcs_write32(GUEST_SYSENTER_CS, data);
1240 break;
1241 case MSR_IA32_SYSENTER_EIP:
1242 vmcs_writel(GUEST_SYSENTER_EIP, data);
1243 break;
1244 case MSR_IA32_SYSENTER_ESP:
1245 vmcs_writel(GUEST_SYSENTER_ESP, data);
1246 break;
1247 case MSR_IA32_TSC:
1248 kvm_write_tsc(vcpu, data);
1249 break;
1250 case MSR_IA32_CR_PAT:
1251 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1252 vmcs_write64(GUEST_IA32_PAT, data);
1253 vcpu->arch.pat = data;
1254 break;
1255 }
1256 ret = kvm_set_msr_common(vcpu, msr_index, data);
1257 break;
1258 case MSR_TSC_AUX:
1259 if (!vmx->rdtscp_enabled)
1260 return 1;
1261 /* Check reserved bit, higher 32 bits should be zero */
1262 if ((data >> 32) != 0)
1263 return 1;
1264 /* Otherwise falls through */
1265 default:
1266 msr = find_msr_entry(vmx, msr_index);
1267 if (msr) {
1268 vmx_load_host_state(vmx);
1269 msr->data = data;
1270 break;
1271 }
1272 ret = kvm_set_msr_common(vcpu, msr_index, data);
1273 }
1274
1275 return ret;
1276 }
1277
1278 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1279 {
1280 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1281 switch (reg) {
1282 case VCPU_REGS_RSP:
1283 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1284 break;
1285 case VCPU_REGS_RIP:
1286 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1287 break;
1288 case VCPU_EXREG_PDPTR:
1289 if (enable_ept)
1290 ept_save_pdptrs(vcpu);
1291 break;
1292 default:
1293 break;
1294 }
1295 }
1296
1297 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1298 {
1299 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1300 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1301 else
1302 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1303
1304 update_exception_bitmap(vcpu);
1305 }
1306
1307 static __init int cpu_has_kvm_support(void)
1308 {
1309 return cpu_has_vmx();
1310 }
1311
1312 static __init int vmx_disabled_by_bios(void)
1313 {
1314 u64 msr;
1315
1316 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1317 if (msr & FEATURE_CONTROL_LOCKED) {
1318 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1319 && tboot_enabled())
1320 return 1;
1321 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1322 && !tboot_enabled())
1323 return 1;
1324 }
1325
1326 return 0;
1327 /* locked but not enabled */
1328 }
1329
1330 static void kvm_cpu_vmxon(u64 addr)
1331 {
1332 asm volatile (ASM_VMX_VMXON_RAX
1333 : : "a"(&addr), "m"(addr)
1334 : "memory", "cc");
1335 }
1336
1337 static int hardware_enable(void *garbage)
1338 {
1339 int cpu = raw_smp_processor_id();
1340 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1341 u64 old, test_bits;
1342
1343 if (read_cr4() & X86_CR4_VMXE)
1344 return -EBUSY;
1345
1346 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1347 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1348
1349 test_bits = FEATURE_CONTROL_LOCKED;
1350 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1351 if (tboot_enabled())
1352 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1353
1354 if ((old & test_bits) != test_bits) {
1355 /* enable and lock */
1356 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1357 }
1358 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1359
1360 if (vmm_exclusive) {
1361 kvm_cpu_vmxon(phys_addr);
1362 ept_sync_global();
1363 }
1364
1365 store_gdt(&__get_cpu_var(host_gdt));
1366
1367 return 0;
1368 }
1369
1370 static void vmclear_local_vcpus(void)
1371 {
1372 int cpu = raw_smp_processor_id();
1373 struct vcpu_vmx *vmx, *n;
1374
1375 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1376 local_vcpus_link)
1377 __vcpu_clear(vmx);
1378 }
1379
1380
1381 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1382 * tricks.
1383 */
1384 static void kvm_cpu_vmxoff(void)
1385 {
1386 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1387 }
1388
1389 static void hardware_disable(void *garbage)
1390 {
1391 if (vmm_exclusive) {
1392 vmclear_local_vcpus();
1393 kvm_cpu_vmxoff();
1394 }
1395 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1396 }
1397
1398 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1399 u32 msr, u32 *result)
1400 {
1401 u32 vmx_msr_low, vmx_msr_high;
1402 u32 ctl = ctl_min | ctl_opt;
1403
1404 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1405
1406 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1407 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1408
1409 /* Ensure minimum (required) set of control bits are supported. */
1410 if (ctl_min & ~ctl)
1411 return -EIO;
1412
1413 *result = ctl;
1414 return 0;
1415 }
1416
1417 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1418 {
1419 u32 vmx_msr_low, vmx_msr_high;
1420 u32 min, opt, min2, opt2;
1421 u32 _pin_based_exec_control = 0;
1422 u32 _cpu_based_exec_control = 0;
1423 u32 _cpu_based_2nd_exec_control = 0;
1424 u32 _vmexit_control = 0;
1425 u32 _vmentry_control = 0;
1426
1427 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1428 opt = PIN_BASED_VIRTUAL_NMIS;
1429 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1430 &_pin_based_exec_control) < 0)
1431 return -EIO;
1432
1433 min = CPU_BASED_HLT_EXITING |
1434 #ifdef CONFIG_X86_64
1435 CPU_BASED_CR8_LOAD_EXITING |
1436 CPU_BASED_CR8_STORE_EXITING |
1437 #endif
1438 CPU_BASED_CR3_LOAD_EXITING |
1439 CPU_BASED_CR3_STORE_EXITING |
1440 CPU_BASED_USE_IO_BITMAPS |
1441 CPU_BASED_MOV_DR_EXITING |
1442 CPU_BASED_USE_TSC_OFFSETING |
1443 CPU_BASED_MWAIT_EXITING |
1444 CPU_BASED_MONITOR_EXITING |
1445 CPU_BASED_INVLPG_EXITING;
1446 opt = CPU_BASED_TPR_SHADOW |
1447 CPU_BASED_USE_MSR_BITMAPS |
1448 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1449 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1450 &_cpu_based_exec_control) < 0)
1451 return -EIO;
1452 #ifdef CONFIG_X86_64
1453 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1454 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1455 ~CPU_BASED_CR8_STORE_EXITING;
1456 #endif
1457 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1458 min2 = 0;
1459 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1460 SECONDARY_EXEC_WBINVD_EXITING |
1461 SECONDARY_EXEC_ENABLE_VPID |
1462 SECONDARY_EXEC_ENABLE_EPT |
1463 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1464 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1465 SECONDARY_EXEC_RDTSCP;
1466 if (adjust_vmx_controls(min2, opt2,
1467 MSR_IA32_VMX_PROCBASED_CTLS2,
1468 &_cpu_based_2nd_exec_control) < 0)
1469 return -EIO;
1470 }
1471 #ifndef CONFIG_X86_64
1472 if (!(_cpu_based_2nd_exec_control &
1473 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1474 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1475 #endif
1476 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1477 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1478 enabled */
1479 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1480 CPU_BASED_CR3_STORE_EXITING |
1481 CPU_BASED_INVLPG_EXITING);
1482 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1483 vmx_capability.ept, vmx_capability.vpid);
1484 }
1485
1486 min = 0;
1487 #ifdef CONFIG_X86_64
1488 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1489 #endif
1490 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1491 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1492 &_vmexit_control) < 0)
1493 return -EIO;
1494
1495 min = 0;
1496 opt = VM_ENTRY_LOAD_IA32_PAT;
1497 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1498 &_vmentry_control) < 0)
1499 return -EIO;
1500
1501 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1502
1503 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1504 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1505 return -EIO;
1506
1507 #ifdef CONFIG_X86_64
1508 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1509 if (vmx_msr_high & (1u<<16))
1510 return -EIO;
1511 #endif
1512
1513 /* Require Write-Back (WB) memory type for VMCS accesses. */
1514 if (((vmx_msr_high >> 18) & 15) != 6)
1515 return -EIO;
1516
1517 vmcs_conf->size = vmx_msr_high & 0x1fff;
1518 vmcs_conf->order = get_order(vmcs_config.size);
1519 vmcs_conf->revision_id = vmx_msr_low;
1520
1521 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1522 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1523 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1524 vmcs_conf->vmexit_ctrl = _vmexit_control;
1525 vmcs_conf->vmentry_ctrl = _vmentry_control;
1526
1527 return 0;
1528 }
1529
1530 static struct vmcs *alloc_vmcs_cpu(int cpu)
1531 {
1532 int node = cpu_to_node(cpu);
1533 struct page *pages;
1534 struct vmcs *vmcs;
1535
1536 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1537 if (!pages)
1538 return NULL;
1539 vmcs = page_address(pages);
1540 memset(vmcs, 0, vmcs_config.size);
1541 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1542 return vmcs;
1543 }
1544
1545 static struct vmcs *alloc_vmcs(void)
1546 {
1547 return alloc_vmcs_cpu(raw_smp_processor_id());
1548 }
1549
1550 static void free_vmcs(struct vmcs *vmcs)
1551 {
1552 free_pages((unsigned long)vmcs, vmcs_config.order);
1553 }
1554
1555 static void free_kvm_area(void)
1556 {
1557 int cpu;
1558
1559 for_each_possible_cpu(cpu) {
1560 free_vmcs(per_cpu(vmxarea, cpu));
1561 per_cpu(vmxarea, cpu) = NULL;
1562 }
1563 }
1564
1565 static __init int alloc_kvm_area(void)
1566 {
1567 int cpu;
1568
1569 for_each_possible_cpu(cpu) {
1570 struct vmcs *vmcs;
1571
1572 vmcs = alloc_vmcs_cpu(cpu);
1573 if (!vmcs) {
1574 free_kvm_area();
1575 return -ENOMEM;
1576 }
1577
1578 per_cpu(vmxarea, cpu) = vmcs;
1579 }
1580 return 0;
1581 }
1582
1583 static __init int hardware_setup(void)
1584 {
1585 if (setup_vmcs_config(&vmcs_config) < 0)
1586 return -EIO;
1587
1588 if (boot_cpu_has(X86_FEATURE_NX))
1589 kvm_enable_efer_bits(EFER_NX);
1590
1591 if (!cpu_has_vmx_vpid())
1592 enable_vpid = 0;
1593
1594 if (!cpu_has_vmx_ept() ||
1595 !cpu_has_vmx_ept_4levels()) {
1596 enable_ept = 0;
1597 enable_unrestricted_guest = 0;
1598 }
1599
1600 if (!cpu_has_vmx_unrestricted_guest())
1601 enable_unrestricted_guest = 0;
1602
1603 if (!cpu_has_vmx_flexpriority())
1604 flexpriority_enabled = 0;
1605
1606 if (!cpu_has_vmx_tpr_shadow())
1607 kvm_x86_ops->update_cr8_intercept = NULL;
1608
1609 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1610 kvm_disable_largepages();
1611
1612 if (!cpu_has_vmx_ple())
1613 ple_gap = 0;
1614
1615 return alloc_kvm_area();
1616 }
1617
1618 static __exit void hardware_unsetup(void)
1619 {
1620 free_kvm_area();
1621 }
1622
1623 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1624 {
1625 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1626
1627 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1628 vmcs_write16(sf->selector, save->selector);
1629 vmcs_writel(sf->base, save->base);
1630 vmcs_write32(sf->limit, save->limit);
1631 vmcs_write32(sf->ar_bytes, save->ar);
1632 } else {
1633 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1634 << AR_DPL_SHIFT;
1635 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1636 }
1637 }
1638
1639 static void enter_pmode(struct kvm_vcpu *vcpu)
1640 {
1641 unsigned long flags;
1642 struct vcpu_vmx *vmx = to_vmx(vcpu);
1643
1644 vmx->emulation_required = 1;
1645 vmx->rmode.vm86_active = 0;
1646
1647 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1648 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1649 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1650
1651 flags = vmcs_readl(GUEST_RFLAGS);
1652 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1653 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1654 vmcs_writel(GUEST_RFLAGS, flags);
1655
1656 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1657 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1658
1659 update_exception_bitmap(vcpu);
1660
1661 if (emulate_invalid_guest_state)
1662 return;
1663
1664 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1665 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1666 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1667 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1668
1669 vmcs_write16(GUEST_SS_SELECTOR, 0);
1670 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1671
1672 vmcs_write16(GUEST_CS_SELECTOR,
1673 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1674 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1675 }
1676
1677 static gva_t rmode_tss_base(struct kvm *kvm)
1678 {
1679 if (!kvm->arch.tss_addr) {
1680 struct kvm_memslots *slots;
1681 gfn_t base_gfn;
1682
1683 slots = kvm_memslots(kvm);
1684 base_gfn = slots->memslots[0].base_gfn +
1685 kvm->memslots->memslots[0].npages - 3;
1686 return base_gfn << PAGE_SHIFT;
1687 }
1688 return kvm->arch.tss_addr;
1689 }
1690
1691 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1692 {
1693 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1694
1695 save->selector = vmcs_read16(sf->selector);
1696 save->base = vmcs_readl(sf->base);
1697 save->limit = vmcs_read32(sf->limit);
1698 save->ar = vmcs_read32(sf->ar_bytes);
1699 vmcs_write16(sf->selector, save->base >> 4);
1700 vmcs_write32(sf->base, save->base & 0xfffff);
1701 vmcs_write32(sf->limit, 0xffff);
1702 vmcs_write32(sf->ar_bytes, 0xf3);
1703 }
1704
1705 static void enter_rmode(struct kvm_vcpu *vcpu)
1706 {
1707 unsigned long flags;
1708 struct vcpu_vmx *vmx = to_vmx(vcpu);
1709
1710 if (enable_unrestricted_guest)
1711 return;
1712
1713 vmx->emulation_required = 1;
1714 vmx->rmode.vm86_active = 1;
1715
1716 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1717 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1718
1719 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1720 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1721
1722 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1723 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1724
1725 flags = vmcs_readl(GUEST_RFLAGS);
1726 vmx->rmode.save_rflags = flags;
1727
1728 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1729
1730 vmcs_writel(GUEST_RFLAGS, flags);
1731 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1732 update_exception_bitmap(vcpu);
1733
1734 if (emulate_invalid_guest_state)
1735 goto continue_rmode;
1736
1737 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1738 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1739 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1740
1741 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1742 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1743 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1744 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1745 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1746
1747 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1748 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1749 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1750 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1751
1752 continue_rmode:
1753 kvm_mmu_reset_context(vcpu);
1754 init_rmode(vcpu->kvm);
1755 }
1756
1757 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1758 {
1759 struct vcpu_vmx *vmx = to_vmx(vcpu);
1760 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1761
1762 if (!msr)
1763 return;
1764
1765 /*
1766 * Force kernel_gs_base reloading before EFER changes, as control
1767 * of this msr depends on is_long_mode().
1768 */
1769 vmx_load_host_state(to_vmx(vcpu));
1770 vcpu->arch.efer = efer;
1771 if (efer & EFER_LMA) {
1772 vmcs_write32(VM_ENTRY_CONTROLS,
1773 vmcs_read32(VM_ENTRY_CONTROLS) |
1774 VM_ENTRY_IA32E_MODE);
1775 msr->data = efer;
1776 } else {
1777 vmcs_write32(VM_ENTRY_CONTROLS,
1778 vmcs_read32(VM_ENTRY_CONTROLS) &
1779 ~VM_ENTRY_IA32E_MODE);
1780
1781 msr->data = efer & ~EFER_LME;
1782 }
1783 setup_msrs(vmx);
1784 }
1785
1786 #ifdef CONFIG_X86_64
1787
1788 static void enter_lmode(struct kvm_vcpu *vcpu)
1789 {
1790 u32 guest_tr_ar;
1791
1792 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1793 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1794 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1795 __func__);
1796 vmcs_write32(GUEST_TR_AR_BYTES,
1797 (guest_tr_ar & ~AR_TYPE_MASK)
1798 | AR_TYPE_BUSY_64_TSS);
1799 }
1800 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1801 }
1802
1803 static void exit_lmode(struct kvm_vcpu *vcpu)
1804 {
1805 vmcs_write32(VM_ENTRY_CONTROLS,
1806 vmcs_read32(VM_ENTRY_CONTROLS)
1807 & ~VM_ENTRY_IA32E_MODE);
1808 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1809 }
1810
1811 #endif
1812
1813 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1814 {
1815 vpid_sync_context(to_vmx(vcpu));
1816 if (enable_ept) {
1817 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1818 return;
1819 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1820 }
1821 }
1822
1823 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1824 {
1825 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1826
1827 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1828 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1829 }
1830
1831 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1832 {
1833 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1834
1835 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1836 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1837 }
1838
1839 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1840 {
1841 if (!test_bit(VCPU_EXREG_PDPTR,
1842 (unsigned long *)&vcpu->arch.regs_dirty))
1843 return;
1844
1845 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1846 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1847 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1848 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1849 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1850 }
1851 }
1852
1853 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1854 {
1855 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1856 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1857 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1858 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1859 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1860 }
1861
1862 __set_bit(VCPU_EXREG_PDPTR,
1863 (unsigned long *)&vcpu->arch.regs_avail);
1864 __set_bit(VCPU_EXREG_PDPTR,
1865 (unsigned long *)&vcpu->arch.regs_dirty);
1866 }
1867
1868 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1869
1870 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1871 unsigned long cr0,
1872 struct kvm_vcpu *vcpu)
1873 {
1874 if (!(cr0 & X86_CR0_PG)) {
1875 /* From paging/starting to nonpaging */
1876 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1877 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1878 (CPU_BASED_CR3_LOAD_EXITING |
1879 CPU_BASED_CR3_STORE_EXITING));
1880 vcpu->arch.cr0 = cr0;
1881 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1882 } else if (!is_paging(vcpu)) {
1883 /* From nonpaging to paging */
1884 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1885 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1886 ~(CPU_BASED_CR3_LOAD_EXITING |
1887 CPU_BASED_CR3_STORE_EXITING));
1888 vcpu->arch.cr0 = cr0;
1889 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1890 }
1891
1892 if (!(cr0 & X86_CR0_WP))
1893 *hw_cr0 &= ~X86_CR0_WP;
1894 }
1895
1896 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1897 {
1898 struct vcpu_vmx *vmx = to_vmx(vcpu);
1899 unsigned long hw_cr0;
1900
1901 if (enable_unrestricted_guest)
1902 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1903 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1904 else
1905 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1906
1907 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1908 enter_pmode(vcpu);
1909
1910 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1911 enter_rmode(vcpu);
1912
1913 #ifdef CONFIG_X86_64
1914 if (vcpu->arch.efer & EFER_LME) {
1915 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1916 enter_lmode(vcpu);
1917 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1918 exit_lmode(vcpu);
1919 }
1920 #endif
1921
1922 if (enable_ept)
1923 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1924
1925 if (!vcpu->fpu_active)
1926 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1927
1928 vmcs_writel(CR0_READ_SHADOW, cr0);
1929 vmcs_writel(GUEST_CR0, hw_cr0);
1930 vcpu->arch.cr0 = cr0;
1931 }
1932
1933 static u64 construct_eptp(unsigned long root_hpa)
1934 {
1935 u64 eptp;
1936
1937 /* TODO write the value reading from MSR */
1938 eptp = VMX_EPT_DEFAULT_MT |
1939 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1940 eptp |= (root_hpa & PAGE_MASK);
1941
1942 return eptp;
1943 }
1944
1945 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1946 {
1947 unsigned long guest_cr3;
1948 u64 eptp;
1949
1950 guest_cr3 = cr3;
1951 if (enable_ept) {
1952 eptp = construct_eptp(cr3);
1953 vmcs_write64(EPT_POINTER, eptp);
1954 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1955 vcpu->kvm->arch.ept_identity_map_addr;
1956 ept_load_pdptrs(vcpu);
1957 }
1958
1959 vmx_flush_tlb(vcpu);
1960 vmcs_writel(GUEST_CR3, guest_cr3);
1961 }
1962
1963 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1964 {
1965 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1966 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1967
1968 vcpu->arch.cr4 = cr4;
1969 if (enable_ept) {
1970 if (!is_paging(vcpu)) {
1971 hw_cr4 &= ~X86_CR4_PAE;
1972 hw_cr4 |= X86_CR4_PSE;
1973 } else if (!(cr4 & X86_CR4_PAE)) {
1974 hw_cr4 &= ~X86_CR4_PAE;
1975 }
1976 }
1977
1978 vmcs_writel(CR4_READ_SHADOW, cr4);
1979 vmcs_writel(GUEST_CR4, hw_cr4);
1980 }
1981
1982 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1983 {
1984 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1985
1986 return vmcs_readl(sf->base);
1987 }
1988
1989 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1990 struct kvm_segment *var, int seg)
1991 {
1992 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1993 u32 ar;
1994
1995 var->base = vmcs_readl(sf->base);
1996 var->limit = vmcs_read32(sf->limit);
1997 var->selector = vmcs_read16(sf->selector);
1998 ar = vmcs_read32(sf->ar_bytes);
1999 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2000 ar = 0;
2001 var->type = ar & 15;
2002 var->s = (ar >> 4) & 1;
2003 var->dpl = (ar >> 5) & 3;
2004 var->present = (ar >> 7) & 1;
2005 var->avl = (ar >> 12) & 1;
2006 var->l = (ar >> 13) & 1;
2007 var->db = (ar >> 14) & 1;
2008 var->g = (ar >> 15) & 1;
2009 var->unusable = (ar >> 16) & 1;
2010 }
2011
2012 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2013 {
2014 if (!is_protmode(vcpu))
2015 return 0;
2016
2017 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2018 return 3;
2019
2020 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2021 }
2022
2023 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2024 {
2025 u32 ar;
2026
2027 if (var->unusable)
2028 ar = 1 << 16;
2029 else {
2030 ar = var->type & 15;
2031 ar |= (var->s & 1) << 4;
2032 ar |= (var->dpl & 3) << 5;
2033 ar |= (var->present & 1) << 7;
2034 ar |= (var->avl & 1) << 12;
2035 ar |= (var->l & 1) << 13;
2036 ar |= (var->db & 1) << 14;
2037 ar |= (var->g & 1) << 15;
2038 }
2039 if (ar == 0) /* a 0 value means unusable */
2040 ar = AR_UNUSABLE_MASK;
2041
2042 return ar;
2043 }
2044
2045 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2046 struct kvm_segment *var, int seg)
2047 {
2048 struct vcpu_vmx *vmx = to_vmx(vcpu);
2049 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2050 u32 ar;
2051
2052 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2053 vmx->rmode.tr.selector = var->selector;
2054 vmx->rmode.tr.base = var->base;
2055 vmx->rmode.tr.limit = var->limit;
2056 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2057 return;
2058 }
2059 vmcs_writel(sf->base, var->base);
2060 vmcs_write32(sf->limit, var->limit);
2061 vmcs_write16(sf->selector, var->selector);
2062 if (vmx->rmode.vm86_active && var->s) {
2063 /*
2064 * Hack real-mode segments into vm86 compatibility.
2065 */
2066 if (var->base == 0xffff0000 && var->selector == 0xf000)
2067 vmcs_writel(sf->base, 0xf0000);
2068 ar = 0xf3;
2069 } else
2070 ar = vmx_segment_access_rights(var);
2071
2072 /*
2073 * Fix the "Accessed" bit in AR field of segment registers for older
2074 * qemu binaries.
2075 * IA32 arch specifies that at the time of processor reset the
2076 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2077 * is setting it to 0 in the usedland code. This causes invalid guest
2078 * state vmexit when "unrestricted guest" mode is turned on.
2079 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2080 * tree. Newer qemu binaries with that qemu fix would not need this
2081 * kvm hack.
2082 */
2083 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2084 ar |= 0x1; /* Accessed */
2085
2086 vmcs_write32(sf->ar_bytes, ar);
2087 }
2088
2089 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2090 {
2091 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2092
2093 *db = (ar >> 14) & 1;
2094 *l = (ar >> 13) & 1;
2095 }
2096
2097 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2098 {
2099 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2100 dt->address = vmcs_readl(GUEST_IDTR_BASE);
2101 }
2102
2103 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2104 {
2105 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2106 vmcs_writel(GUEST_IDTR_BASE, dt->address);
2107 }
2108
2109 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2110 {
2111 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2112 dt->address = vmcs_readl(GUEST_GDTR_BASE);
2113 }
2114
2115 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2116 {
2117 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2118 vmcs_writel(GUEST_GDTR_BASE, dt->address);
2119 }
2120
2121 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2122 {
2123 struct kvm_segment var;
2124 u32 ar;
2125
2126 vmx_get_segment(vcpu, &var, seg);
2127 ar = vmx_segment_access_rights(&var);
2128
2129 if (var.base != (var.selector << 4))
2130 return false;
2131 if (var.limit != 0xffff)
2132 return false;
2133 if (ar != 0xf3)
2134 return false;
2135
2136 return true;
2137 }
2138
2139 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2140 {
2141 struct kvm_segment cs;
2142 unsigned int cs_rpl;
2143
2144 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2145 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2146
2147 if (cs.unusable)
2148 return false;
2149 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2150 return false;
2151 if (!cs.s)
2152 return false;
2153 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2154 if (cs.dpl > cs_rpl)
2155 return false;
2156 } else {
2157 if (cs.dpl != cs_rpl)
2158 return false;
2159 }
2160 if (!cs.present)
2161 return false;
2162
2163 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2164 return true;
2165 }
2166
2167 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2168 {
2169 struct kvm_segment ss;
2170 unsigned int ss_rpl;
2171
2172 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2173 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2174
2175 if (ss.unusable)
2176 return true;
2177 if (ss.type != 3 && ss.type != 7)
2178 return false;
2179 if (!ss.s)
2180 return false;
2181 if (ss.dpl != ss_rpl) /* DPL != RPL */
2182 return false;
2183 if (!ss.present)
2184 return false;
2185
2186 return true;
2187 }
2188
2189 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2190 {
2191 struct kvm_segment var;
2192 unsigned int rpl;
2193
2194 vmx_get_segment(vcpu, &var, seg);
2195 rpl = var.selector & SELECTOR_RPL_MASK;
2196
2197 if (var.unusable)
2198 return true;
2199 if (!var.s)
2200 return false;
2201 if (!var.present)
2202 return false;
2203 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2204 if (var.dpl < rpl) /* DPL < RPL */
2205 return false;
2206 }
2207
2208 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2209 * rights flags
2210 */
2211 return true;
2212 }
2213
2214 static bool tr_valid(struct kvm_vcpu *vcpu)
2215 {
2216 struct kvm_segment tr;
2217
2218 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2219
2220 if (tr.unusable)
2221 return false;
2222 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2223 return false;
2224 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2225 return false;
2226 if (!tr.present)
2227 return false;
2228
2229 return true;
2230 }
2231
2232 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2233 {
2234 struct kvm_segment ldtr;
2235
2236 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2237
2238 if (ldtr.unusable)
2239 return true;
2240 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2241 return false;
2242 if (ldtr.type != 2)
2243 return false;
2244 if (!ldtr.present)
2245 return false;
2246
2247 return true;
2248 }
2249
2250 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2251 {
2252 struct kvm_segment cs, ss;
2253
2254 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2255 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2256
2257 return ((cs.selector & SELECTOR_RPL_MASK) ==
2258 (ss.selector & SELECTOR_RPL_MASK));
2259 }
2260
2261 /*
2262 * Check if guest state is valid. Returns true if valid, false if
2263 * not.
2264 * We assume that registers are always usable
2265 */
2266 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2267 {
2268 /* real mode guest state checks */
2269 if (!is_protmode(vcpu)) {
2270 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2271 return false;
2272 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2273 return false;
2274 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2275 return false;
2276 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2277 return false;
2278 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2279 return false;
2280 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2281 return false;
2282 } else {
2283 /* protected mode guest state checks */
2284 if (!cs_ss_rpl_check(vcpu))
2285 return false;
2286 if (!code_segment_valid(vcpu))
2287 return false;
2288 if (!stack_segment_valid(vcpu))
2289 return false;
2290 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2291 return false;
2292 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2293 return false;
2294 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2295 return false;
2296 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2297 return false;
2298 if (!tr_valid(vcpu))
2299 return false;
2300 if (!ldtr_valid(vcpu))
2301 return false;
2302 }
2303 /* TODO:
2304 * - Add checks on RIP
2305 * - Add checks on RFLAGS
2306 */
2307
2308 return true;
2309 }
2310
2311 static int init_rmode_tss(struct kvm *kvm)
2312 {
2313 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2314 u16 data = 0;
2315 int ret = 0;
2316 int r;
2317
2318 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2319 if (r < 0)
2320 goto out;
2321 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2322 r = kvm_write_guest_page(kvm, fn++, &data,
2323 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2324 if (r < 0)
2325 goto out;
2326 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2327 if (r < 0)
2328 goto out;
2329 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2330 if (r < 0)
2331 goto out;
2332 data = ~0;
2333 r = kvm_write_guest_page(kvm, fn, &data,
2334 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2335 sizeof(u8));
2336 if (r < 0)
2337 goto out;
2338
2339 ret = 1;
2340 out:
2341 return ret;
2342 }
2343
2344 static int init_rmode_identity_map(struct kvm *kvm)
2345 {
2346 int i, r, ret;
2347 pfn_t identity_map_pfn;
2348 u32 tmp;
2349
2350 if (!enable_ept)
2351 return 1;
2352 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2353 printk(KERN_ERR "EPT: identity-mapping pagetable "
2354 "haven't been allocated!\n");
2355 return 0;
2356 }
2357 if (likely(kvm->arch.ept_identity_pagetable_done))
2358 return 1;
2359 ret = 0;
2360 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2361 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2362 if (r < 0)
2363 goto out;
2364 /* Set up identity-mapping pagetable for EPT in real mode */
2365 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2366 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2367 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2368 r = kvm_write_guest_page(kvm, identity_map_pfn,
2369 &tmp, i * sizeof(tmp), sizeof(tmp));
2370 if (r < 0)
2371 goto out;
2372 }
2373 kvm->arch.ept_identity_pagetable_done = true;
2374 ret = 1;
2375 out:
2376 return ret;
2377 }
2378
2379 static void seg_setup(int seg)
2380 {
2381 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2382 unsigned int ar;
2383
2384 vmcs_write16(sf->selector, 0);
2385 vmcs_writel(sf->base, 0);
2386 vmcs_write32(sf->limit, 0xffff);
2387 if (enable_unrestricted_guest) {
2388 ar = 0x93;
2389 if (seg == VCPU_SREG_CS)
2390 ar |= 0x08; /* code segment */
2391 } else
2392 ar = 0xf3;
2393
2394 vmcs_write32(sf->ar_bytes, ar);
2395 }
2396
2397 static int alloc_apic_access_page(struct kvm *kvm)
2398 {
2399 struct kvm_userspace_memory_region kvm_userspace_mem;
2400 int r = 0;
2401
2402 mutex_lock(&kvm->slots_lock);
2403 if (kvm->arch.apic_access_page)
2404 goto out;
2405 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2406 kvm_userspace_mem.flags = 0;
2407 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2408 kvm_userspace_mem.memory_size = PAGE_SIZE;
2409 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2410 if (r)
2411 goto out;
2412
2413 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2414 out:
2415 mutex_unlock(&kvm->slots_lock);
2416 return r;
2417 }
2418
2419 static int alloc_identity_pagetable(struct kvm *kvm)
2420 {
2421 struct kvm_userspace_memory_region kvm_userspace_mem;
2422 int r = 0;
2423
2424 mutex_lock(&kvm->slots_lock);
2425 if (kvm->arch.ept_identity_pagetable)
2426 goto out;
2427 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2428 kvm_userspace_mem.flags = 0;
2429 kvm_userspace_mem.guest_phys_addr =
2430 kvm->arch.ept_identity_map_addr;
2431 kvm_userspace_mem.memory_size = PAGE_SIZE;
2432 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2433 if (r)
2434 goto out;
2435
2436 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2437 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2438 out:
2439 mutex_unlock(&kvm->slots_lock);
2440 return r;
2441 }
2442
2443 static void allocate_vpid(struct vcpu_vmx *vmx)
2444 {
2445 int vpid;
2446
2447 vmx->vpid = 0;
2448 if (!enable_vpid)
2449 return;
2450 spin_lock(&vmx_vpid_lock);
2451 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2452 if (vpid < VMX_NR_VPIDS) {
2453 vmx->vpid = vpid;
2454 __set_bit(vpid, vmx_vpid_bitmap);
2455 }
2456 spin_unlock(&vmx_vpid_lock);
2457 }
2458
2459 static void free_vpid(struct vcpu_vmx *vmx)
2460 {
2461 if (!enable_vpid)
2462 return;
2463 spin_lock(&vmx_vpid_lock);
2464 if (vmx->vpid != 0)
2465 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2466 spin_unlock(&vmx_vpid_lock);
2467 }
2468
2469 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2470 {
2471 int f = sizeof(unsigned long);
2472
2473 if (!cpu_has_vmx_msr_bitmap())
2474 return;
2475
2476 /*
2477 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2478 * have the write-low and read-high bitmap offsets the wrong way round.
2479 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2480 */
2481 if (msr <= 0x1fff) {
2482 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2483 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2484 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2485 msr &= 0x1fff;
2486 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2487 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2488 }
2489 }
2490
2491 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2492 {
2493 if (!longmode_only)
2494 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2495 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2496 }
2497
2498 /*
2499 * Sets up the vmcs for emulated real mode.
2500 */
2501 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2502 {
2503 u32 host_sysenter_cs, msr_low, msr_high;
2504 u32 junk;
2505 u64 host_pat;
2506 unsigned long a;
2507 struct desc_ptr dt;
2508 int i;
2509 unsigned long kvm_vmx_return;
2510 u32 exec_control;
2511
2512 /* I/O */
2513 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2514 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2515
2516 if (cpu_has_vmx_msr_bitmap())
2517 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2518
2519 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2520
2521 /* Control */
2522 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2523 vmcs_config.pin_based_exec_ctrl);
2524
2525 exec_control = vmcs_config.cpu_based_exec_ctrl;
2526 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2527 exec_control &= ~CPU_BASED_TPR_SHADOW;
2528 #ifdef CONFIG_X86_64
2529 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2530 CPU_BASED_CR8_LOAD_EXITING;
2531 #endif
2532 }
2533 if (!enable_ept)
2534 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2535 CPU_BASED_CR3_LOAD_EXITING |
2536 CPU_BASED_INVLPG_EXITING;
2537 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2538
2539 if (cpu_has_secondary_exec_ctrls()) {
2540 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2541 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2542 exec_control &=
2543 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2544 if (vmx->vpid == 0)
2545 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2546 if (!enable_ept) {
2547 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2548 enable_unrestricted_guest = 0;
2549 }
2550 if (!enable_unrestricted_guest)
2551 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2552 if (!ple_gap)
2553 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2554 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2555 }
2556
2557 if (ple_gap) {
2558 vmcs_write32(PLE_GAP, ple_gap);
2559 vmcs_write32(PLE_WINDOW, ple_window);
2560 }
2561
2562 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2563 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2564 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2565
2566 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
2567 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2568 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2569
2570 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2571 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2572 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2573 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2574 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
2575 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2576 #ifdef CONFIG_X86_64
2577 rdmsrl(MSR_FS_BASE, a);
2578 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2579 rdmsrl(MSR_GS_BASE, a);
2580 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2581 #else
2582 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2583 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2584 #endif
2585
2586 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2587
2588 native_store_idt(&dt);
2589 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
2590
2591 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2592 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2593 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2594 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2595 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2596 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2597 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2598
2599 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2600 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2601 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2602 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2603 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2604 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2605
2606 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2607 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2608 host_pat = msr_low | ((u64) msr_high << 32);
2609 vmcs_write64(HOST_IA32_PAT, host_pat);
2610 }
2611 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2612 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2613 host_pat = msr_low | ((u64) msr_high << 32);
2614 /* Write the default value follow host pat */
2615 vmcs_write64(GUEST_IA32_PAT, host_pat);
2616 /* Keep arch.pat sync with GUEST_IA32_PAT */
2617 vmx->vcpu.arch.pat = host_pat;
2618 }
2619
2620 for (i = 0; i < NR_VMX_MSR; ++i) {
2621 u32 index = vmx_msr_index[i];
2622 u32 data_low, data_high;
2623 int j = vmx->nmsrs;
2624
2625 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2626 continue;
2627 if (wrmsr_safe(index, data_low, data_high) < 0)
2628 continue;
2629 vmx->guest_msrs[j].index = i;
2630 vmx->guest_msrs[j].data = 0;
2631 vmx->guest_msrs[j].mask = -1ull;
2632 ++vmx->nmsrs;
2633 }
2634
2635 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2636
2637 /* 22.2.1, 20.8.1 */
2638 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2639
2640 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2641 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2642 if (enable_ept)
2643 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2644 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2645
2646 kvm_write_tsc(&vmx->vcpu, 0);
2647
2648 return 0;
2649 }
2650
2651 static int init_rmode(struct kvm *kvm)
2652 {
2653 int idx, ret = 0;
2654
2655 idx = srcu_read_lock(&kvm->srcu);
2656 if (!init_rmode_tss(kvm))
2657 goto exit;
2658 if (!init_rmode_identity_map(kvm))
2659 goto exit;
2660
2661 ret = 1;
2662 exit:
2663 srcu_read_unlock(&kvm->srcu, idx);
2664 return ret;
2665 }
2666
2667 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2668 {
2669 struct vcpu_vmx *vmx = to_vmx(vcpu);
2670 u64 msr;
2671 int ret;
2672
2673 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2674 if (!init_rmode(vmx->vcpu.kvm)) {
2675 ret = -ENOMEM;
2676 goto out;
2677 }
2678
2679 vmx->rmode.vm86_active = 0;
2680
2681 vmx->soft_vnmi_blocked = 0;
2682
2683 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2684 kvm_set_cr8(&vmx->vcpu, 0);
2685 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2686 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2687 msr |= MSR_IA32_APICBASE_BSP;
2688 kvm_set_apic_base(&vmx->vcpu, msr);
2689
2690 ret = fx_init(&vmx->vcpu);
2691 if (ret != 0)
2692 goto out;
2693
2694 seg_setup(VCPU_SREG_CS);
2695 /*
2696 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2697 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2698 */
2699 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2700 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2701 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2702 } else {
2703 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2704 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2705 }
2706
2707 seg_setup(VCPU_SREG_DS);
2708 seg_setup(VCPU_SREG_ES);
2709 seg_setup(VCPU_SREG_FS);
2710 seg_setup(VCPU_SREG_GS);
2711 seg_setup(VCPU_SREG_SS);
2712
2713 vmcs_write16(GUEST_TR_SELECTOR, 0);
2714 vmcs_writel(GUEST_TR_BASE, 0);
2715 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2716 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2717
2718 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2719 vmcs_writel(GUEST_LDTR_BASE, 0);
2720 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2721 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2722
2723 vmcs_write32(GUEST_SYSENTER_CS, 0);
2724 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2725 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2726
2727 vmcs_writel(GUEST_RFLAGS, 0x02);
2728 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2729 kvm_rip_write(vcpu, 0xfff0);
2730 else
2731 kvm_rip_write(vcpu, 0);
2732 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2733
2734 vmcs_writel(GUEST_DR7, 0x400);
2735
2736 vmcs_writel(GUEST_GDTR_BASE, 0);
2737 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2738
2739 vmcs_writel(GUEST_IDTR_BASE, 0);
2740 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2741
2742 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2743 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2744 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2745
2746 /* Special registers */
2747 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2748
2749 setup_msrs(vmx);
2750
2751 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2752
2753 if (cpu_has_vmx_tpr_shadow()) {
2754 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2755 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2756 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2757 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2758 vmcs_write32(TPR_THRESHOLD, 0);
2759 }
2760
2761 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2762 vmcs_write64(APIC_ACCESS_ADDR,
2763 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2764
2765 if (vmx->vpid != 0)
2766 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2767
2768 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2769 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2770 vmx_set_cr4(&vmx->vcpu, 0);
2771 vmx_set_efer(&vmx->vcpu, 0);
2772 vmx_fpu_activate(&vmx->vcpu);
2773 update_exception_bitmap(&vmx->vcpu);
2774
2775 vpid_sync_context(vmx);
2776
2777 ret = 0;
2778
2779 /* HACK: Don't enable emulation on guest boot/reset */
2780 vmx->emulation_required = 0;
2781
2782 out:
2783 return ret;
2784 }
2785
2786 static void enable_irq_window(struct kvm_vcpu *vcpu)
2787 {
2788 u32 cpu_based_vm_exec_control;
2789
2790 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2791 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2792 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2793 }
2794
2795 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2796 {
2797 u32 cpu_based_vm_exec_control;
2798
2799 if (!cpu_has_virtual_nmis()) {
2800 enable_irq_window(vcpu);
2801 return;
2802 }
2803
2804 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2805 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2806 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2807 }
2808
2809 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2810 {
2811 struct vcpu_vmx *vmx = to_vmx(vcpu);
2812 uint32_t intr;
2813 int irq = vcpu->arch.interrupt.nr;
2814
2815 trace_kvm_inj_virq(irq);
2816
2817 ++vcpu->stat.irq_injections;
2818 if (vmx->rmode.vm86_active) {
2819 vmx->rmode.irq.pending = true;
2820 vmx->rmode.irq.vector = irq;
2821 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2822 if (vcpu->arch.interrupt.soft)
2823 vmx->rmode.irq.rip +=
2824 vmx->vcpu.arch.event_exit_inst_len;
2825 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2826 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2827 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2828 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2829 return;
2830 }
2831 intr = irq | INTR_INFO_VALID_MASK;
2832 if (vcpu->arch.interrupt.soft) {
2833 intr |= INTR_TYPE_SOFT_INTR;
2834 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2835 vmx->vcpu.arch.event_exit_inst_len);
2836 } else
2837 intr |= INTR_TYPE_EXT_INTR;
2838 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2839 }
2840
2841 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2842 {
2843 struct vcpu_vmx *vmx = to_vmx(vcpu);
2844
2845 if (!cpu_has_virtual_nmis()) {
2846 /*
2847 * Tracking the NMI-blocked state in software is built upon
2848 * finding the next open IRQ window. This, in turn, depends on
2849 * well-behaving guests: They have to keep IRQs disabled at
2850 * least as long as the NMI handler runs. Otherwise we may
2851 * cause NMI nesting, maybe breaking the guest. But as this is
2852 * highly unlikely, we can live with the residual risk.
2853 */
2854 vmx->soft_vnmi_blocked = 1;
2855 vmx->vnmi_blocked_time = 0;
2856 }
2857
2858 ++vcpu->stat.nmi_injections;
2859 if (vmx->rmode.vm86_active) {
2860 vmx->rmode.irq.pending = true;
2861 vmx->rmode.irq.vector = NMI_VECTOR;
2862 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2863 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2864 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2865 INTR_INFO_VALID_MASK);
2866 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2867 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2868 return;
2869 }
2870 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2871 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2872 }
2873
2874 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2875 {
2876 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2877 return 0;
2878
2879 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2880 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
2881 }
2882
2883 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2884 {
2885 if (!cpu_has_virtual_nmis())
2886 return to_vmx(vcpu)->soft_vnmi_blocked;
2887 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
2888 }
2889
2890 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2891 {
2892 struct vcpu_vmx *vmx = to_vmx(vcpu);
2893
2894 if (!cpu_has_virtual_nmis()) {
2895 if (vmx->soft_vnmi_blocked != masked) {
2896 vmx->soft_vnmi_blocked = masked;
2897 vmx->vnmi_blocked_time = 0;
2898 }
2899 } else {
2900 if (masked)
2901 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2902 GUEST_INTR_STATE_NMI);
2903 else
2904 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2905 GUEST_INTR_STATE_NMI);
2906 }
2907 }
2908
2909 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2910 {
2911 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2912 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2913 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2914 }
2915
2916 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2917 {
2918 int ret;
2919 struct kvm_userspace_memory_region tss_mem = {
2920 .slot = TSS_PRIVATE_MEMSLOT,
2921 .guest_phys_addr = addr,
2922 .memory_size = PAGE_SIZE * 3,
2923 .flags = 0,
2924 };
2925
2926 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2927 if (ret)
2928 return ret;
2929 kvm->arch.tss_addr = addr;
2930 return 0;
2931 }
2932
2933 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2934 int vec, u32 err_code)
2935 {
2936 /*
2937 * Instruction with address size override prefix opcode 0x67
2938 * Cause the #SS fault with 0 error code in VM86 mode.
2939 */
2940 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2941 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2942 return 1;
2943 /*
2944 * Forward all other exceptions that are valid in real mode.
2945 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2946 * the required debugging infrastructure rework.
2947 */
2948 switch (vec) {
2949 case DB_VECTOR:
2950 if (vcpu->guest_debug &
2951 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2952 return 0;
2953 kvm_queue_exception(vcpu, vec);
2954 return 1;
2955 case BP_VECTOR:
2956 /*
2957 * Update instruction length as we may reinject the exception
2958 * from user space while in guest debugging mode.
2959 */
2960 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2961 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2962 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2963 return 0;
2964 /* fall through */
2965 case DE_VECTOR:
2966 case OF_VECTOR:
2967 case BR_VECTOR:
2968 case UD_VECTOR:
2969 case DF_VECTOR:
2970 case SS_VECTOR:
2971 case GP_VECTOR:
2972 case MF_VECTOR:
2973 kvm_queue_exception(vcpu, vec);
2974 return 1;
2975 }
2976 return 0;
2977 }
2978
2979 /*
2980 * Trigger machine check on the host. We assume all the MSRs are already set up
2981 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2982 * We pass a fake environment to the machine check handler because we want
2983 * the guest to be always treated like user space, no matter what context
2984 * it used internally.
2985 */
2986 static void kvm_machine_check(void)
2987 {
2988 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2989 struct pt_regs regs = {
2990 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2991 .flags = X86_EFLAGS_IF,
2992 };
2993
2994 do_machine_check(&regs, 0);
2995 #endif
2996 }
2997
2998 static int handle_machine_check(struct kvm_vcpu *vcpu)
2999 {
3000 /* already handled by vcpu_run */
3001 return 1;
3002 }
3003
3004 static int handle_exception(struct kvm_vcpu *vcpu)
3005 {
3006 struct vcpu_vmx *vmx = to_vmx(vcpu);
3007 struct kvm_run *kvm_run = vcpu->run;
3008 u32 intr_info, ex_no, error_code;
3009 unsigned long cr2, rip, dr6;
3010 u32 vect_info;
3011 enum emulation_result er;
3012
3013 vect_info = vmx->idt_vectoring_info;
3014 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3015
3016 if (is_machine_check(intr_info))
3017 return handle_machine_check(vcpu);
3018
3019 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3020 !is_page_fault(intr_info)) {
3021 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3022 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3023 vcpu->run->internal.ndata = 2;
3024 vcpu->run->internal.data[0] = vect_info;
3025 vcpu->run->internal.data[1] = intr_info;
3026 return 0;
3027 }
3028
3029 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3030 return 1; /* already handled by vmx_vcpu_run() */
3031
3032 if (is_no_device(intr_info)) {
3033 vmx_fpu_activate(vcpu);
3034 return 1;
3035 }
3036
3037 if (is_invalid_opcode(intr_info)) {
3038 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
3039 if (er != EMULATE_DONE)
3040 kvm_queue_exception(vcpu, UD_VECTOR);
3041 return 1;
3042 }
3043
3044 error_code = 0;
3045 rip = kvm_rip_read(vcpu);
3046 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3047 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3048 if (is_page_fault(intr_info)) {
3049 /* EPT won't cause page fault directly */
3050 if (enable_ept)
3051 BUG();
3052 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3053 trace_kvm_page_fault(cr2, error_code);
3054
3055 if (kvm_event_needs_reinjection(vcpu))
3056 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3057 return kvm_mmu_page_fault(vcpu, cr2, error_code);
3058 }
3059
3060 if (vmx->rmode.vm86_active &&
3061 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3062 error_code)) {
3063 if (vcpu->arch.halt_request) {
3064 vcpu->arch.halt_request = 0;
3065 return kvm_emulate_halt(vcpu);
3066 }
3067 return 1;
3068 }
3069
3070 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3071 switch (ex_no) {
3072 case DB_VECTOR:
3073 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3074 if (!(vcpu->guest_debug &
3075 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3076 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3077 kvm_queue_exception(vcpu, DB_VECTOR);
3078 return 1;
3079 }
3080 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3081 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3082 /* fall through */
3083 case BP_VECTOR:
3084 /*
3085 * Update instruction length as we may reinject #BP from
3086 * user space while in guest debugging mode. Reading it for
3087 * #DB as well causes no harm, it is not used in that case.
3088 */
3089 vmx->vcpu.arch.event_exit_inst_len =
3090 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3091 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3092 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3093 kvm_run->debug.arch.exception = ex_no;
3094 break;
3095 default:
3096 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3097 kvm_run->ex.exception = ex_no;
3098 kvm_run->ex.error_code = error_code;
3099 break;
3100 }
3101 return 0;
3102 }
3103
3104 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3105 {
3106 ++vcpu->stat.irq_exits;
3107 return 1;
3108 }
3109
3110 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3111 {
3112 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3113 return 0;
3114 }
3115
3116 static int handle_io(struct kvm_vcpu *vcpu)
3117 {
3118 unsigned long exit_qualification;
3119 int size, in, string;
3120 unsigned port;
3121
3122 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3123 string = (exit_qualification & 16) != 0;
3124 in = (exit_qualification & 8) != 0;
3125
3126 ++vcpu->stat.io_exits;
3127
3128 if (string || in)
3129 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3130
3131 port = exit_qualification >> 16;
3132 size = (exit_qualification & 7) + 1;
3133 skip_emulated_instruction(vcpu);
3134
3135 return kvm_fast_pio_out(vcpu, size, port);
3136 }
3137
3138 static void
3139 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3140 {
3141 /*
3142 * Patch in the VMCALL instruction:
3143 */
3144 hypercall[0] = 0x0f;
3145 hypercall[1] = 0x01;
3146 hypercall[2] = 0xc1;
3147 }
3148
3149 static void complete_insn_gp(struct kvm_vcpu *vcpu, int err)
3150 {
3151 if (err)
3152 kvm_inject_gp(vcpu, 0);
3153 else
3154 skip_emulated_instruction(vcpu);
3155 }
3156
3157 static int handle_cr(struct kvm_vcpu *vcpu)
3158 {
3159 unsigned long exit_qualification, val;
3160 int cr;
3161 int reg;
3162 int err;
3163
3164 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3165 cr = exit_qualification & 15;
3166 reg = (exit_qualification >> 8) & 15;
3167 switch ((exit_qualification >> 4) & 3) {
3168 case 0: /* mov to cr */
3169 val = kvm_register_read(vcpu, reg);
3170 trace_kvm_cr_write(cr, val);
3171 switch (cr) {
3172 case 0:
3173 err = kvm_set_cr0(vcpu, val);
3174 complete_insn_gp(vcpu, err);
3175 return 1;
3176 case 3:
3177 err = kvm_set_cr3(vcpu, val);
3178 complete_insn_gp(vcpu, err);
3179 return 1;
3180 case 4:
3181 err = kvm_set_cr4(vcpu, val);
3182 complete_insn_gp(vcpu, err);
3183 return 1;
3184 case 8: {
3185 u8 cr8_prev = kvm_get_cr8(vcpu);
3186 u8 cr8 = kvm_register_read(vcpu, reg);
3187 kvm_set_cr8(vcpu, cr8);
3188 skip_emulated_instruction(vcpu);
3189 if (irqchip_in_kernel(vcpu->kvm))
3190 return 1;
3191 if (cr8_prev <= cr8)
3192 return 1;
3193 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3194 return 0;
3195 }
3196 };
3197 break;
3198 case 2: /* clts */
3199 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3200 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3201 skip_emulated_instruction(vcpu);
3202 vmx_fpu_activate(vcpu);
3203 return 1;
3204 case 1: /*mov from cr*/
3205 switch (cr) {
3206 case 3:
3207 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3208 trace_kvm_cr_read(cr, vcpu->arch.cr3);
3209 skip_emulated_instruction(vcpu);
3210 return 1;
3211 case 8:
3212 val = kvm_get_cr8(vcpu);
3213 kvm_register_write(vcpu, reg, val);
3214 trace_kvm_cr_read(cr, val);
3215 skip_emulated_instruction(vcpu);
3216 return 1;
3217 }
3218 break;
3219 case 3: /* lmsw */
3220 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3221 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3222 kvm_lmsw(vcpu, val);
3223
3224 skip_emulated_instruction(vcpu);
3225 return 1;
3226 default:
3227 break;
3228 }
3229 vcpu->run->exit_reason = 0;
3230 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3231 (int)(exit_qualification >> 4) & 3, cr);
3232 return 0;
3233 }
3234
3235 static int handle_dr(struct kvm_vcpu *vcpu)
3236 {
3237 unsigned long exit_qualification;
3238 int dr, reg;
3239
3240 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3241 if (!kvm_require_cpl(vcpu, 0))
3242 return 1;
3243 dr = vmcs_readl(GUEST_DR7);
3244 if (dr & DR7_GD) {
3245 /*
3246 * As the vm-exit takes precedence over the debug trap, we
3247 * need to emulate the latter, either for the host or the
3248 * guest debugging itself.
3249 */
3250 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3251 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3252 vcpu->run->debug.arch.dr7 = dr;
3253 vcpu->run->debug.arch.pc =
3254 vmcs_readl(GUEST_CS_BASE) +
3255 vmcs_readl(GUEST_RIP);
3256 vcpu->run->debug.arch.exception = DB_VECTOR;
3257 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3258 return 0;
3259 } else {
3260 vcpu->arch.dr7 &= ~DR7_GD;
3261 vcpu->arch.dr6 |= DR6_BD;
3262 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3263 kvm_queue_exception(vcpu, DB_VECTOR);
3264 return 1;
3265 }
3266 }
3267
3268 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3269 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3270 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3271 if (exit_qualification & TYPE_MOV_FROM_DR) {
3272 unsigned long val;
3273 if (!kvm_get_dr(vcpu, dr, &val))
3274 kvm_register_write(vcpu, reg, val);
3275 } else
3276 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3277 skip_emulated_instruction(vcpu);
3278 return 1;
3279 }
3280
3281 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3282 {
3283 vmcs_writel(GUEST_DR7, val);
3284 }
3285
3286 static int handle_cpuid(struct kvm_vcpu *vcpu)
3287 {
3288 kvm_emulate_cpuid(vcpu);
3289 return 1;
3290 }
3291
3292 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3293 {
3294 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3295 u64 data;
3296
3297 if (vmx_get_msr(vcpu, ecx, &data)) {
3298 trace_kvm_msr_read_ex(ecx);
3299 kvm_inject_gp(vcpu, 0);
3300 return 1;
3301 }
3302
3303 trace_kvm_msr_read(ecx, data);
3304
3305 /* FIXME: handling of bits 32:63 of rax, rdx */
3306 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3307 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3308 skip_emulated_instruction(vcpu);
3309 return 1;
3310 }
3311
3312 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3313 {
3314 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3315 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3316 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3317
3318 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3319 trace_kvm_msr_write_ex(ecx, data);
3320 kvm_inject_gp(vcpu, 0);
3321 return 1;
3322 }
3323
3324 trace_kvm_msr_write(ecx, data);
3325 skip_emulated_instruction(vcpu);
3326 return 1;
3327 }
3328
3329 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3330 {
3331 kvm_make_request(KVM_REQ_EVENT, vcpu);
3332 return 1;
3333 }
3334
3335 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3336 {
3337 u32 cpu_based_vm_exec_control;
3338
3339 /* clear pending irq */
3340 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3341 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3342 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3343
3344 kvm_make_request(KVM_REQ_EVENT, vcpu);
3345
3346 ++vcpu->stat.irq_window_exits;
3347
3348 /*
3349 * If the user space waits to inject interrupts, exit as soon as
3350 * possible
3351 */
3352 if (!irqchip_in_kernel(vcpu->kvm) &&
3353 vcpu->run->request_interrupt_window &&
3354 !kvm_cpu_has_interrupt(vcpu)) {
3355 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3356 return 0;
3357 }
3358 return 1;
3359 }
3360
3361 static int handle_halt(struct kvm_vcpu *vcpu)
3362 {
3363 skip_emulated_instruction(vcpu);
3364 return kvm_emulate_halt(vcpu);
3365 }
3366
3367 static int handle_vmcall(struct kvm_vcpu *vcpu)
3368 {
3369 skip_emulated_instruction(vcpu);
3370 kvm_emulate_hypercall(vcpu);
3371 return 1;
3372 }
3373
3374 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3375 {
3376 kvm_queue_exception(vcpu, UD_VECTOR);
3377 return 1;
3378 }
3379
3380 static int handle_invlpg(struct kvm_vcpu *vcpu)
3381 {
3382 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3383
3384 kvm_mmu_invlpg(vcpu, exit_qualification);
3385 skip_emulated_instruction(vcpu);
3386 return 1;
3387 }
3388
3389 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3390 {
3391 skip_emulated_instruction(vcpu);
3392 kvm_emulate_wbinvd(vcpu);
3393 return 1;
3394 }
3395
3396 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3397 {
3398 u64 new_bv = kvm_read_edx_eax(vcpu);
3399 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3400
3401 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3402 skip_emulated_instruction(vcpu);
3403 return 1;
3404 }
3405
3406 static int handle_apic_access(struct kvm_vcpu *vcpu)
3407 {
3408 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3409 }
3410
3411 static int handle_task_switch(struct kvm_vcpu *vcpu)
3412 {
3413 struct vcpu_vmx *vmx = to_vmx(vcpu);
3414 unsigned long exit_qualification;
3415 bool has_error_code = false;
3416 u32 error_code = 0;
3417 u16 tss_selector;
3418 int reason, type, idt_v;
3419
3420 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3421 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3422
3423 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3424
3425 reason = (u32)exit_qualification >> 30;
3426 if (reason == TASK_SWITCH_GATE && idt_v) {
3427 switch (type) {
3428 case INTR_TYPE_NMI_INTR:
3429 vcpu->arch.nmi_injected = false;
3430 if (cpu_has_virtual_nmis())
3431 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3432 GUEST_INTR_STATE_NMI);
3433 break;
3434 case INTR_TYPE_EXT_INTR:
3435 case INTR_TYPE_SOFT_INTR:
3436 kvm_clear_interrupt_queue(vcpu);
3437 break;
3438 case INTR_TYPE_HARD_EXCEPTION:
3439 if (vmx->idt_vectoring_info &
3440 VECTORING_INFO_DELIVER_CODE_MASK) {
3441 has_error_code = true;
3442 error_code =
3443 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3444 }
3445 /* fall through */
3446 case INTR_TYPE_SOFT_EXCEPTION:
3447 kvm_clear_exception_queue(vcpu);
3448 break;
3449 default:
3450 break;
3451 }
3452 }
3453 tss_selector = exit_qualification;
3454
3455 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3456 type != INTR_TYPE_EXT_INTR &&
3457 type != INTR_TYPE_NMI_INTR))
3458 skip_emulated_instruction(vcpu);
3459
3460 if (kvm_task_switch(vcpu, tss_selector, reason,
3461 has_error_code, error_code) == EMULATE_FAIL) {
3462 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3463 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3464 vcpu->run->internal.ndata = 0;
3465 return 0;
3466 }
3467
3468 /* clear all local breakpoint enable flags */
3469 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3470
3471 /*
3472 * TODO: What about debug traps on tss switch?
3473 * Are we supposed to inject them and update dr6?
3474 */
3475
3476 return 1;
3477 }
3478
3479 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3480 {
3481 unsigned long exit_qualification;
3482 gpa_t gpa;
3483 int gla_validity;
3484
3485 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3486
3487 if (exit_qualification & (1 << 6)) {
3488 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3489 return -EINVAL;
3490 }
3491
3492 gla_validity = (exit_qualification >> 7) & 0x3;
3493 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3494 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3495 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3496 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3497 vmcs_readl(GUEST_LINEAR_ADDRESS));
3498 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3499 (long unsigned int)exit_qualification);
3500 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3501 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3502 return 0;
3503 }
3504
3505 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3506 trace_kvm_page_fault(gpa, exit_qualification);
3507 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3508 }
3509
3510 static u64 ept_rsvd_mask(u64 spte, int level)
3511 {
3512 int i;
3513 u64 mask = 0;
3514
3515 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3516 mask |= (1ULL << i);
3517
3518 if (level > 2)
3519 /* bits 7:3 reserved */
3520 mask |= 0xf8;
3521 else if (level == 2) {
3522 if (spte & (1ULL << 7))
3523 /* 2MB ref, bits 20:12 reserved */
3524 mask |= 0x1ff000;
3525 else
3526 /* bits 6:3 reserved */
3527 mask |= 0x78;
3528 }
3529
3530 return mask;
3531 }
3532
3533 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3534 int level)
3535 {
3536 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3537
3538 /* 010b (write-only) */
3539 WARN_ON((spte & 0x7) == 0x2);
3540
3541 /* 110b (write/execute) */
3542 WARN_ON((spte & 0x7) == 0x6);
3543
3544 /* 100b (execute-only) and value not supported by logical processor */
3545 if (!cpu_has_vmx_ept_execute_only())
3546 WARN_ON((spte & 0x7) == 0x4);
3547
3548 /* not 000b */
3549 if ((spte & 0x7)) {
3550 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3551
3552 if (rsvd_bits != 0) {
3553 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3554 __func__, rsvd_bits);
3555 WARN_ON(1);
3556 }
3557
3558 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3559 u64 ept_mem_type = (spte & 0x38) >> 3;
3560
3561 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3562 ept_mem_type == 7) {
3563 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3564 __func__, ept_mem_type);
3565 WARN_ON(1);
3566 }
3567 }
3568 }
3569 }
3570
3571 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3572 {
3573 u64 sptes[4];
3574 int nr_sptes, i;
3575 gpa_t gpa;
3576
3577 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3578
3579 printk(KERN_ERR "EPT: Misconfiguration.\n");
3580 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3581
3582 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3583
3584 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3585 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3586
3587 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3588 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3589
3590 return 0;
3591 }
3592
3593 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3594 {
3595 u32 cpu_based_vm_exec_control;
3596
3597 /* clear pending NMI */
3598 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3599 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3600 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3601 ++vcpu->stat.nmi_window_exits;
3602 kvm_make_request(KVM_REQ_EVENT, vcpu);
3603
3604 return 1;
3605 }
3606
3607 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3608 {
3609 struct vcpu_vmx *vmx = to_vmx(vcpu);
3610 enum emulation_result err = EMULATE_DONE;
3611 int ret = 1;
3612
3613 while (!guest_state_valid(vcpu)) {
3614 err = emulate_instruction(vcpu, 0, 0, 0);
3615
3616 if (err == EMULATE_DO_MMIO) {
3617 ret = 0;
3618 goto out;
3619 }
3620
3621 if (err != EMULATE_DONE)
3622 return 0;
3623
3624 if (signal_pending(current))
3625 goto out;
3626 if (need_resched())
3627 schedule();
3628 }
3629
3630 vmx->emulation_required = 0;
3631 out:
3632 return ret;
3633 }
3634
3635 /*
3636 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3637 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3638 */
3639 static int handle_pause(struct kvm_vcpu *vcpu)
3640 {
3641 skip_emulated_instruction(vcpu);
3642 kvm_vcpu_on_spin(vcpu);
3643
3644 return 1;
3645 }
3646
3647 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3648 {
3649 kvm_queue_exception(vcpu, UD_VECTOR);
3650 return 1;
3651 }
3652
3653 /*
3654 * The exit handlers return 1 if the exit was handled fully and guest execution
3655 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3656 * to be done to userspace and return 0.
3657 */
3658 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3659 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3660 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3661 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3662 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3663 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3664 [EXIT_REASON_CR_ACCESS] = handle_cr,
3665 [EXIT_REASON_DR_ACCESS] = handle_dr,
3666 [EXIT_REASON_CPUID] = handle_cpuid,
3667 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3668 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3669 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3670 [EXIT_REASON_HLT] = handle_halt,
3671 [EXIT_REASON_INVLPG] = handle_invlpg,
3672 [EXIT_REASON_VMCALL] = handle_vmcall,
3673 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3674 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3675 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3676 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3677 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3678 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3679 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3680 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3681 [EXIT_REASON_VMON] = handle_vmx_insn,
3682 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3683 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3684 [EXIT_REASON_WBINVD] = handle_wbinvd,
3685 [EXIT_REASON_XSETBV] = handle_xsetbv,
3686 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3687 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3688 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3689 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3690 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
3691 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3692 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
3693 };
3694
3695 static const int kvm_vmx_max_exit_handlers =
3696 ARRAY_SIZE(kvm_vmx_exit_handlers);
3697
3698 /*
3699 * The guest has exited. See if we can fix it or if we need userspace
3700 * assistance.
3701 */
3702 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3703 {
3704 struct vcpu_vmx *vmx = to_vmx(vcpu);
3705 u32 exit_reason = vmx->exit_reason;
3706 u32 vectoring_info = vmx->idt_vectoring_info;
3707
3708 trace_kvm_exit(exit_reason, vcpu);
3709
3710 /* If guest state is invalid, start emulating */
3711 if (vmx->emulation_required && emulate_invalid_guest_state)
3712 return handle_invalid_guest_state(vcpu);
3713
3714 /* Access CR3 don't cause VMExit in paging mode, so we need
3715 * to sync with guest real CR3. */
3716 if (enable_ept && is_paging(vcpu))
3717 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3718
3719 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3720 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3721 vcpu->run->fail_entry.hardware_entry_failure_reason
3722 = exit_reason;
3723 return 0;
3724 }
3725
3726 if (unlikely(vmx->fail)) {
3727 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3728 vcpu->run->fail_entry.hardware_entry_failure_reason
3729 = vmcs_read32(VM_INSTRUCTION_ERROR);
3730 return 0;
3731 }
3732
3733 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3734 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3735 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3736 exit_reason != EXIT_REASON_TASK_SWITCH))
3737 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3738 "(0x%x) and exit reason is 0x%x\n",
3739 __func__, vectoring_info, exit_reason);
3740
3741 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3742 if (vmx_interrupt_allowed(vcpu)) {
3743 vmx->soft_vnmi_blocked = 0;
3744 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3745 vcpu->arch.nmi_pending) {
3746 /*
3747 * This CPU don't support us in finding the end of an
3748 * NMI-blocked window if the guest runs with IRQs
3749 * disabled. So we pull the trigger after 1 s of
3750 * futile waiting, but inform the user about this.
3751 */
3752 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3753 "state on VCPU %d after 1 s timeout\n",
3754 __func__, vcpu->vcpu_id);
3755 vmx->soft_vnmi_blocked = 0;
3756 }
3757 }
3758
3759 if (exit_reason < kvm_vmx_max_exit_handlers
3760 && kvm_vmx_exit_handlers[exit_reason])
3761 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3762 else {
3763 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3764 vcpu->run->hw.hardware_exit_reason = exit_reason;
3765 }
3766 return 0;
3767 }
3768
3769 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3770 {
3771 if (irr == -1 || tpr < irr) {
3772 vmcs_write32(TPR_THRESHOLD, 0);
3773 return;
3774 }
3775
3776 vmcs_write32(TPR_THRESHOLD, irr);
3777 }
3778
3779 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
3780 {
3781 u32 exit_intr_info = vmx->exit_intr_info;
3782
3783 /* Handle machine checks before interrupts are enabled */
3784 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3785 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3786 && is_machine_check(exit_intr_info)))
3787 kvm_machine_check();
3788
3789 /* We need to handle NMIs before interrupts are enabled */
3790 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3791 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3792 kvm_before_handle_nmi(&vmx->vcpu);
3793 asm("int $2");
3794 kvm_after_handle_nmi(&vmx->vcpu);
3795 }
3796 }
3797
3798 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3799 {
3800 u32 exit_intr_info = vmx->exit_intr_info;
3801 bool unblock_nmi;
3802 u8 vector;
3803 bool idtv_info_valid;
3804
3805 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3806
3807 if (cpu_has_virtual_nmis()) {
3808 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3809 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3810 /*
3811 * SDM 3: 27.7.1.2 (September 2008)
3812 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3813 * a guest IRET fault.
3814 * SDM 3: 23.2.2 (September 2008)
3815 * Bit 12 is undefined in any of the following cases:
3816 * If the VM exit sets the valid bit in the IDT-vectoring
3817 * information field.
3818 * If the VM exit is due to a double fault.
3819 */
3820 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3821 vector != DF_VECTOR && !idtv_info_valid)
3822 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3823 GUEST_INTR_STATE_NMI);
3824 } else if (unlikely(vmx->soft_vnmi_blocked))
3825 vmx->vnmi_blocked_time +=
3826 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3827 }
3828
3829 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3830 {
3831 u32 idt_vectoring_info = vmx->idt_vectoring_info;
3832 u8 vector;
3833 int type;
3834 bool idtv_info_valid;
3835
3836 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3837
3838 vmx->vcpu.arch.nmi_injected = false;
3839 kvm_clear_exception_queue(&vmx->vcpu);
3840 kvm_clear_interrupt_queue(&vmx->vcpu);
3841
3842 if (!idtv_info_valid)
3843 return;
3844
3845 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3846
3847 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3848 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3849
3850 switch (type) {
3851 case INTR_TYPE_NMI_INTR:
3852 vmx->vcpu.arch.nmi_injected = true;
3853 /*
3854 * SDM 3: 27.7.1.2 (September 2008)
3855 * Clear bit "block by NMI" before VM entry if a NMI
3856 * delivery faulted.
3857 */
3858 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3859 GUEST_INTR_STATE_NMI);
3860 break;
3861 case INTR_TYPE_SOFT_EXCEPTION:
3862 vmx->vcpu.arch.event_exit_inst_len =
3863 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3864 /* fall through */
3865 case INTR_TYPE_HARD_EXCEPTION:
3866 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3867 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3868 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3869 } else
3870 kvm_queue_exception(&vmx->vcpu, vector);
3871 break;
3872 case INTR_TYPE_SOFT_INTR:
3873 vmx->vcpu.arch.event_exit_inst_len =
3874 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3875 /* fall through */
3876 case INTR_TYPE_EXT_INTR:
3877 kvm_queue_interrupt(&vmx->vcpu, vector,
3878 type == INTR_TYPE_SOFT_INTR);
3879 break;
3880 default:
3881 break;
3882 }
3883 }
3884
3885 /*
3886 * Failure to inject an interrupt should give us the information
3887 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3888 * when fetching the interrupt redirection bitmap in the real-mode
3889 * tss, this doesn't happen. So we do it ourselves.
3890 */
3891 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3892 {
3893 vmx->rmode.irq.pending = 0;
3894 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3895 return;
3896 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3897 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3898 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3899 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3900 return;
3901 }
3902 vmx->idt_vectoring_info =
3903 VECTORING_INFO_VALID_MASK
3904 | INTR_TYPE_EXT_INTR
3905 | vmx->rmode.irq.vector;
3906 }
3907
3908 #ifdef CONFIG_X86_64
3909 #define R "r"
3910 #define Q "q"
3911 #else
3912 #define R "e"
3913 #define Q "l"
3914 #endif
3915
3916 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3917 {
3918 struct vcpu_vmx *vmx = to_vmx(vcpu);
3919
3920 /* Record the guest's net vcpu time for enforced NMI injections. */
3921 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3922 vmx->entry_time = ktime_get();
3923
3924 /* Don't enter VMX if guest state is invalid, let the exit handler
3925 start emulation until we arrive back to a valid state */
3926 if (vmx->emulation_required && emulate_invalid_guest_state)
3927 return;
3928
3929 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3930 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3931 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3932 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3933
3934 /* When single-stepping over STI and MOV SS, we must clear the
3935 * corresponding interruptibility bits in the guest state. Otherwise
3936 * vmentry fails as it then expects bit 14 (BS) in pending debug
3937 * exceptions being set, but that's not correct for the guest debugging
3938 * case. */
3939 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3940 vmx_set_interrupt_shadow(vcpu, 0);
3941
3942 asm(
3943 /* Store host registers */
3944 "push %%"R"dx; push %%"R"bp;"
3945 "push %%"R"cx \n\t"
3946 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3947 "je 1f \n\t"
3948 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3949 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3950 "1: \n\t"
3951 /* Reload cr2 if changed */
3952 "mov %c[cr2](%0), %%"R"ax \n\t"
3953 "mov %%cr2, %%"R"dx \n\t"
3954 "cmp %%"R"ax, %%"R"dx \n\t"
3955 "je 2f \n\t"
3956 "mov %%"R"ax, %%cr2 \n\t"
3957 "2: \n\t"
3958 /* Check if vmlaunch of vmresume is needed */
3959 "cmpl $0, %c[launched](%0) \n\t"
3960 /* Load guest registers. Don't clobber flags. */
3961 "mov %c[rax](%0), %%"R"ax \n\t"
3962 "mov %c[rbx](%0), %%"R"bx \n\t"
3963 "mov %c[rdx](%0), %%"R"dx \n\t"
3964 "mov %c[rsi](%0), %%"R"si \n\t"
3965 "mov %c[rdi](%0), %%"R"di \n\t"
3966 "mov %c[rbp](%0), %%"R"bp \n\t"
3967 #ifdef CONFIG_X86_64
3968 "mov %c[r8](%0), %%r8 \n\t"
3969 "mov %c[r9](%0), %%r9 \n\t"
3970 "mov %c[r10](%0), %%r10 \n\t"
3971 "mov %c[r11](%0), %%r11 \n\t"
3972 "mov %c[r12](%0), %%r12 \n\t"
3973 "mov %c[r13](%0), %%r13 \n\t"
3974 "mov %c[r14](%0), %%r14 \n\t"
3975 "mov %c[r15](%0), %%r15 \n\t"
3976 #endif
3977 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3978
3979 /* Enter guest mode */
3980 "jne .Llaunched \n\t"
3981 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3982 "jmp .Lkvm_vmx_return \n\t"
3983 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3984 ".Lkvm_vmx_return: "
3985 /* Save guest registers, load host registers, keep flags */
3986 "xchg %0, (%%"R"sp) \n\t"
3987 "mov %%"R"ax, %c[rax](%0) \n\t"
3988 "mov %%"R"bx, %c[rbx](%0) \n\t"
3989 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3990 "mov %%"R"dx, %c[rdx](%0) \n\t"
3991 "mov %%"R"si, %c[rsi](%0) \n\t"
3992 "mov %%"R"di, %c[rdi](%0) \n\t"
3993 "mov %%"R"bp, %c[rbp](%0) \n\t"
3994 #ifdef CONFIG_X86_64
3995 "mov %%r8, %c[r8](%0) \n\t"
3996 "mov %%r9, %c[r9](%0) \n\t"
3997 "mov %%r10, %c[r10](%0) \n\t"
3998 "mov %%r11, %c[r11](%0) \n\t"
3999 "mov %%r12, %c[r12](%0) \n\t"
4000 "mov %%r13, %c[r13](%0) \n\t"
4001 "mov %%r14, %c[r14](%0) \n\t"
4002 "mov %%r15, %c[r15](%0) \n\t"
4003 #endif
4004 "mov %%cr2, %%"R"ax \n\t"
4005 "mov %%"R"ax, %c[cr2](%0) \n\t"
4006
4007 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
4008 "setbe %c[fail](%0) \n\t"
4009 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4010 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4011 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
4012 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
4013 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4014 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4015 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4016 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4017 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4018 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4019 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4020 #ifdef CONFIG_X86_64
4021 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4022 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4023 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4024 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4025 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4026 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4027 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4028 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4029 #endif
4030 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
4031 : "cc", "memory"
4032 , R"bx", R"di", R"si"
4033 #ifdef CONFIG_X86_64
4034 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4035 #endif
4036 );
4037
4038 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4039 | (1 << VCPU_EXREG_PDPTR));
4040 vcpu->arch.regs_dirty = 0;
4041
4042 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4043 if (vmx->rmode.irq.pending)
4044 fixup_rmode_irq(vmx);
4045
4046 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4047 vmx->launched = 1;
4048
4049 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4050 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4051
4052 vmx_complete_atomic_exit(vmx);
4053 vmx_recover_nmi_blocking(vmx);
4054 vmx_complete_interrupts(vmx);
4055 }
4056
4057 #undef R
4058 #undef Q
4059
4060 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4061 {
4062 struct vcpu_vmx *vmx = to_vmx(vcpu);
4063
4064 if (vmx->vmcs) {
4065 vcpu_clear(vmx);
4066 free_vmcs(vmx->vmcs);
4067 vmx->vmcs = NULL;
4068 }
4069 }
4070
4071 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4072 {
4073 struct vcpu_vmx *vmx = to_vmx(vcpu);
4074
4075 free_vpid(vmx);
4076 vmx_free_vmcs(vcpu);
4077 kfree(vmx->guest_msrs);
4078 kvm_vcpu_uninit(vcpu);
4079 kmem_cache_free(kvm_vcpu_cache, vmx);
4080 }
4081
4082 static inline void vmcs_init(struct vmcs *vmcs)
4083 {
4084 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4085
4086 if (!vmm_exclusive)
4087 kvm_cpu_vmxon(phys_addr);
4088
4089 vmcs_clear(vmcs);
4090
4091 if (!vmm_exclusive)
4092 kvm_cpu_vmxoff();
4093 }
4094
4095 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4096 {
4097 int err;
4098 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4099 int cpu;
4100
4101 if (!vmx)
4102 return ERR_PTR(-ENOMEM);
4103
4104 allocate_vpid(vmx);
4105
4106 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4107 if (err)
4108 goto free_vcpu;
4109
4110 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4111 if (!vmx->guest_msrs) {
4112 err = -ENOMEM;
4113 goto uninit_vcpu;
4114 }
4115
4116 vmx->vmcs = alloc_vmcs();
4117 if (!vmx->vmcs)
4118 goto free_msrs;
4119
4120 vmcs_init(vmx->vmcs);
4121
4122 cpu = get_cpu();
4123 vmx_vcpu_load(&vmx->vcpu, cpu);
4124 vmx->vcpu.cpu = cpu;
4125 err = vmx_vcpu_setup(vmx);
4126 vmx_vcpu_put(&vmx->vcpu);
4127 put_cpu();
4128 if (err)
4129 goto free_vmcs;
4130 if (vm_need_virtualize_apic_accesses(kvm))
4131 if (alloc_apic_access_page(kvm) != 0)
4132 goto free_vmcs;
4133
4134 if (enable_ept) {
4135 if (!kvm->arch.ept_identity_map_addr)
4136 kvm->arch.ept_identity_map_addr =
4137 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4138 if (alloc_identity_pagetable(kvm) != 0)
4139 goto free_vmcs;
4140 }
4141
4142 return &vmx->vcpu;
4143
4144 free_vmcs:
4145 free_vmcs(vmx->vmcs);
4146 free_msrs:
4147 kfree(vmx->guest_msrs);
4148 uninit_vcpu:
4149 kvm_vcpu_uninit(&vmx->vcpu);
4150 free_vcpu:
4151 free_vpid(vmx);
4152 kmem_cache_free(kvm_vcpu_cache, vmx);
4153 return ERR_PTR(err);
4154 }
4155
4156 static void __init vmx_check_processor_compat(void *rtn)
4157 {
4158 struct vmcs_config vmcs_conf;
4159
4160 *(int *)rtn = 0;
4161 if (setup_vmcs_config(&vmcs_conf) < 0)
4162 *(int *)rtn = -EIO;
4163 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4164 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4165 smp_processor_id());
4166 *(int *)rtn = -EIO;
4167 }
4168 }
4169
4170 static int get_ept_level(void)
4171 {
4172 return VMX_EPT_DEFAULT_GAW + 1;
4173 }
4174
4175 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4176 {
4177 u64 ret;
4178
4179 /* For VT-d and EPT combination
4180 * 1. MMIO: always map as UC
4181 * 2. EPT with VT-d:
4182 * a. VT-d without snooping control feature: can't guarantee the
4183 * result, try to trust guest.
4184 * b. VT-d with snooping control feature: snooping control feature of
4185 * VT-d engine can guarantee the cache correctness. Just set it
4186 * to WB to keep consistent with host. So the same as item 3.
4187 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4188 * consistent with host MTRR
4189 */
4190 if (is_mmio)
4191 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4192 else if (vcpu->kvm->arch.iommu_domain &&
4193 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4194 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4195 VMX_EPT_MT_EPTE_SHIFT;
4196 else
4197 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4198 | VMX_EPT_IPAT_BIT;
4199
4200 return ret;
4201 }
4202
4203 #define _ER(x) { EXIT_REASON_##x, #x }
4204
4205 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4206 _ER(EXCEPTION_NMI),
4207 _ER(EXTERNAL_INTERRUPT),
4208 _ER(TRIPLE_FAULT),
4209 _ER(PENDING_INTERRUPT),
4210 _ER(NMI_WINDOW),
4211 _ER(TASK_SWITCH),
4212 _ER(CPUID),
4213 _ER(HLT),
4214 _ER(INVLPG),
4215 _ER(RDPMC),
4216 _ER(RDTSC),
4217 _ER(VMCALL),
4218 _ER(VMCLEAR),
4219 _ER(VMLAUNCH),
4220 _ER(VMPTRLD),
4221 _ER(VMPTRST),
4222 _ER(VMREAD),
4223 _ER(VMRESUME),
4224 _ER(VMWRITE),
4225 _ER(VMOFF),
4226 _ER(VMON),
4227 _ER(CR_ACCESS),
4228 _ER(DR_ACCESS),
4229 _ER(IO_INSTRUCTION),
4230 _ER(MSR_READ),
4231 _ER(MSR_WRITE),
4232 _ER(MWAIT_INSTRUCTION),
4233 _ER(MONITOR_INSTRUCTION),
4234 _ER(PAUSE_INSTRUCTION),
4235 _ER(MCE_DURING_VMENTRY),
4236 _ER(TPR_BELOW_THRESHOLD),
4237 _ER(APIC_ACCESS),
4238 _ER(EPT_VIOLATION),
4239 _ER(EPT_MISCONFIG),
4240 _ER(WBINVD),
4241 { -1, NULL }
4242 };
4243
4244 #undef _ER
4245
4246 static int vmx_get_lpage_level(void)
4247 {
4248 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4249 return PT_DIRECTORY_LEVEL;
4250 else
4251 /* For shadow and EPT supported 1GB page */
4252 return PT_PDPE_LEVEL;
4253 }
4254
4255 static inline u32 bit(int bitno)
4256 {
4257 return 1 << (bitno & 31);
4258 }
4259
4260 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4261 {
4262 struct kvm_cpuid_entry2 *best;
4263 struct vcpu_vmx *vmx = to_vmx(vcpu);
4264 u32 exec_control;
4265
4266 vmx->rdtscp_enabled = false;
4267 if (vmx_rdtscp_supported()) {
4268 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4269 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4270 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4271 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4272 vmx->rdtscp_enabled = true;
4273 else {
4274 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4275 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4276 exec_control);
4277 }
4278 }
4279 }
4280 }
4281
4282 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4283 {
4284 }
4285
4286 static struct kvm_x86_ops vmx_x86_ops = {
4287 .cpu_has_kvm_support = cpu_has_kvm_support,
4288 .disabled_by_bios = vmx_disabled_by_bios,
4289 .hardware_setup = hardware_setup,
4290 .hardware_unsetup = hardware_unsetup,
4291 .check_processor_compatibility = vmx_check_processor_compat,
4292 .hardware_enable = hardware_enable,
4293 .hardware_disable = hardware_disable,
4294 .cpu_has_accelerated_tpr = report_flexpriority,
4295
4296 .vcpu_create = vmx_create_vcpu,
4297 .vcpu_free = vmx_free_vcpu,
4298 .vcpu_reset = vmx_vcpu_reset,
4299
4300 .prepare_guest_switch = vmx_save_host_state,
4301 .vcpu_load = vmx_vcpu_load,
4302 .vcpu_put = vmx_vcpu_put,
4303
4304 .set_guest_debug = set_guest_debug,
4305 .get_msr = vmx_get_msr,
4306 .set_msr = vmx_set_msr,
4307 .get_segment_base = vmx_get_segment_base,
4308 .get_segment = vmx_get_segment,
4309 .set_segment = vmx_set_segment,
4310 .get_cpl = vmx_get_cpl,
4311 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4312 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4313 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4314 .set_cr0 = vmx_set_cr0,
4315 .set_cr3 = vmx_set_cr3,
4316 .set_cr4 = vmx_set_cr4,
4317 .set_efer = vmx_set_efer,
4318 .get_idt = vmx_get_idt,
4319 .set_idt = vmx_set_idt,
4320 .get_gdt = vmx_get_gdt,
4321 .set_gdt = vmx_set_gdt,
4322 .set_dr7 = vmx_set_dr7,
4323 .cache_reg = vmx_cache_reg,
4324 .get_rflags = vmx_get_rflags,
4325 .set_rflags = vmx_set_rflags,
4326 .fpu_activate = vmx_fpu_activate,
4327 .fpu_deactivate = vmx_fpu_deactivate,
4328
4329 .tlb_flush = vmx_flush_tlb,
4330
4331 .run = vmx_vcpu_run,
4332 .handle_exit = vmx_handle_exit,
4333 .skip_emulated_instruction = skip_emulated_instruction,
4334 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4335 .get_interrupt_shadow = vmx_get_interrupt_shadow,
4336 .patch_hypercall = vmx_patch_hypercall,
4337 .set_irq = vmx_inject_irq,
4338 .set_nmi = vmx_inject_nmi,
4339 .queue_exception = vmx_queue_exception,
4340 .interrupt_allowed = vmx_interrupt_allowed,
4341 .nmi_allowed = vmx_nmi_allowed,
4342 .get_nmi_mask = vmx_get_nmi_mask,
4343 .set_nmi_mask = vmx_set_nmi_mask,
4344 .enable_nmi_window = enable_nmi_window,
4345 .enable_irq_window = enable_irq_window,
4346 .update_cr8_intercept = update_cr8_intercept,
4347
4348 .set_tss_addr = vmx_set_tss_addr,
4349 .get_tdp_level = get_ept_level,
4350 .get_mt_mask = vmx_get_mt_mask,
4351
4352 .exit_reasons_str = vmx_exit_reasons_str,
4353 .get_lpage_level = vmx_get_lpage_level,
4354
4355 .cpuid_update = vmx_cpuid_update,
4356
4357 .rdtscp_supported = vmx_rdtscp_supported,
4358
4359 .set_supported_cpuid = vmx_set_supported_cpuid,
4360
4361 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4362
4363 .write_tsc_offset = vmx_write_tsc_offset,
4364 .adjust_tsc_offset = vmx_adjust_tsc_offset,
4365
4366 .set_tdp_cr3 = vmx_set_cr3,
4367 };
4368
4369 static int __init vmx_init(void)
4370 {
4371 int r, i;
4372
4373 rdmsrl_safe(MSR_EFER, &host_efer);
4374
4375 for (i = 0; i < NR_VMX_MSR; ++i)
4376 kvm_define_shared_msr(i, vmx_msr_index[i]);
4377
4378 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4379 if (!vmx_io_bitmap_a)
4380 return -ENOMEM;
4381
4382 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4383 if (!vmx_io_bitmap_b) {
4384 r = -ENOMEM;
4385 goto out;
4386 }
4387
4388 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4389 if (!vmx_msr_bitmap_legacy) {
4390 r = -ENOMEM;
4391 goto out1;
4392 }
4393
4394 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4395 if (!vmx_msr_bitmap_longmode) {
4396 r = -ENOMEM;
4397 goto out2;
4398 }
4399
4400 /*
4401 * Allow direct access to the PC debug port (it is often used for I/O
4402 * delays, but the vmexits simply slow things down).
4403 */
4404 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4405 clear_bit(0x80, vmx_io_bitmap_a);
4406
4407 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4408
4409 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4410 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4411
4412 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4413
4414 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4415 __alignof__(struct vcpu_vmx), THIS_MODULE);
4416 if (r)
4417 goto out3;
4418
4419 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4420 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4421 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4422 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4423 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4424 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4425
4426 if (enable_ept) {
4427 bypass_guest_pf = 0;
4428 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4429 VMX_EPT_WRITABLE_MASK);
4430 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4431 VMX_EPT_EXECUTABLE_MASK);
4432 kvm_enable_tdp();
4433 } else
4434 kvm_disable_tdp();
4435
4436 if (bypass_guest_pf)
4437 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4438
4439 return 0;
4440
4441 out3:
4442 free_page((unsigned long)vmx_msr_bitmap_longmode);
4443 out2:
4444 free_page((unsigned long)vmx_msr_bitmap_legacy);
4445 out1:
4446 free_page((unsigned long)vmx_io_bitmap_b);
4447 out:
4448 free_page((unsigned long)vmx_io_bitmap_a);
4449 return r;
4450 }
4451
4452 static void __exit vmx_exit(void)
4453 {
4454 free_page((unsigned long)vmx_msr_bitmap_legacy);
4455 free_page((unsigned long)vmx_msr_bitmap_longmode);
4456 free_page((unsigned long)vmx_io_bitmap_b);
4457 free_page((unsigned long)vmx_io_bitmap_a);
4458
4459 kvm_exit();
4460 }
4461
4462 module_init(vmx_init)
4463 module_exit(vmx_exit)
x86 "subsystem" repository