arch/ppc/platforms/ev64360.c

   1 /*
   2  * arch/ppc/platforms/ev64360.c
   3  *
   4  * Board setup routines for the Marvell EV-64360-BP Evaluation Board.
   5  *
   6  * Author: Lee Nicks <allinux@gmail.com>
   7  *
   8  * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
   9  * Based on code done by - Mark A. Greer <mgreer@mvista.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms of the GNU General Public License as published by the
  13  * Free Software Foundation; either version 2 of the License, or (at your
  14  * option) any later version.
  15  */
  16 #include <linux/config.h>
  17 #include <linux/kernel.h>
  18 #include <linux/pci.h>
  19 #include <linux/kdev_t.h>
  20 #include <linux/console.h>
  21 #include <linux/initrd.h>
  22 #include <linux/root_dev.h>
  23 #include <linux/delay.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/bootmem.h>
  26 #include <linux/mtd/physmap.h>
  27 #include <linux/mv643xx.h>
  28 #include <linux/platform_device.h>
  29 #ifdef CONFIG_BOOTIMG
  30 #include <linux/bootimg.h>
  31 #endif
  32 #include <asm/page.h>
  33 #include <asm/time.h>
  34 #include <asm/smp.h>
  35 #include <asm/todc.h>
  36 #include <asm/bootinfo.h>
  37 #include <asm/ppcboot.h>
  38 #include <asm/mv64x60.h>
  39 #include <asm/machdep.h>
  40 #include <platforms/ev64360.h>
  41
  42 #define BOARD_VENDOR    "Marvell"
  43 #define BOARD_MACHINE   "EV-64360-BP"
  44
  45 static struct           mv64x60_handle bh;
  46 static void __iomem     *sram_base;
  47
  48 static u32              ev64360_flash_size_0;
  49 static u32              ev64360_flash_size_1;
  50
  51 static u32              ev64360_bus_frequency;
  52
  53 unsigned char   __res[sizeof(bd_t)];
  54
  55 static int __init
  56 ev64360_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  57 {
  58         return 0;
  59 }
  60
  61 static void __init
  62 ev64360_setup_bridge(void)
  63 {
  64         struct mv64x60_setup_info si;
  65         int i;
  66
  67         memset(&si, 0, sizeof(si));
  68
  69         si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
  70
  71         #ifdef CONFIG_PCI
  72         si.pci_1.enable_bus = 1;
  73         si.pci_1.pci_io.cpu_base = EV64360_PCI1_IO_START_PROC_ADDR;
  74         si.pci_1.pci_io.pci_base_hi = 0;
  75         si.pci_1.pci_io.pci_base_lo = EV64360_PCI1_IO_START_PCI_ADDR;
  76         si.pci_1.pci_io.size = EV64360_PCI1_IO_SIZE;
  77         si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
  78         si.pci_1.pci_mem[0].cpu_base = EV64360_PCI1_MEM_START_PROC_ADDR;
  79         si.pci_1.pci_mem[0].pci_base_hi = EV64360_PCI1_MEM_START_PCI_HI_ADDR;
  80         si.pci_1.pci_mem[0].pci_base_lo = EV64360_PCI1_MEM_START_PCI_LO_ADDR;
  81         si.pci_1.pci_mem[0].size = EV64360_PCI1_MEM_SIZE;
  82         si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
  83         si.pci_1.pci_cmd_bits = 0;
  84         si.pci_1.latency_timer = 0x80;
  85         #else
  86         si.pci_0.enable_bus = 0;
  87         si.pci_1.enable_bus = 0;
  88         #endif
  89
  90         for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
  91 #if defined(CONFIG_NOT_COHERENT_CACHE)
  92                 si.cpu_prot_options[i] = 0;
  93                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
  94                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
  95                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
  96
  97                 si.pci_1.acc_cntl_options[i] =
  98                     MV64360_PCI_ACC_CNTL_SNOOP_NONE |
  99                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
 100                     MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
 101                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
 102 #else
 103                 si.cpu_prot_options[i] = 0;
 104                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
 105                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
 106                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
 107
 108                 si.pci_1.acc_cntl_options[i] =
 109                     MV64360_PCI_ACC_CNTL_SNOOP_WB |
 110                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
 111                     MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
 112                     MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
 113 #endif
 114         }
 115
 116         if (mv64x60_init(&bh, &si))
 117                 printk(KERN_WARNING "Bridge initialization failed.\n");
 118
 119         #ifdef CONFIG_PCI
 120         pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
 121         ppc_md.pci_swizzle = common_swizzle;
 122         ppc_md.pci_map_irq = ev64360_map_irq;
 123         ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
 124
 125         mv64x60_set_bus(&bh, 1, 0);
 126         bh.hose_b->first_busno = 0;
 127         bh.hose_b->last_busno = 0xff;
 128         #endif
 129 }
 130
 131 /* Bridge & platform setup routines */
 132 void __init
 133 ev64360_intr_setup(void)
 134 {
 135         /* MPP 8, 9, and 10 */
 136         mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff);
 137
 138         /*
 139          * Define GPP 8,9,and 10 interrupt polarity as active low
 140          * input signal and level triggered
 141          */
 142         mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700);
 143         mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700);
 144
 145         /* Config GPP intr ctlr to respond to level trigger */
 146         mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10));
 147
 148         /* Erranum FEr PCI-#8 */
 149         mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1<<5) | (1<<9));
 150         mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<5) | (1<<9));
 151
 152         /*
 153          * Dismiss and then enable interrupt on GPP interrupt cause
 154          * for CPU #0
 155          */
 156         mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700);
 157         mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700);
 158
 159         /*
 160          * Dismiss and then enable interrupt on CPU #0 high cause reg
 161          * BIT25 summarizes GPP interrupts 8-15
 162          */
 163         mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25));
 164 }
 165
 166 void __init
 167 ev64360_setup_peripherals(void)
 168 {
 169         u32 base;
 170
 171         /* Set up window for boot CS */
 172         mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
 173                  EV64360_BOOT_WINDOW_BASE, EV64360_BOOT_WINDOW_SIZE, 0);
 174         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
 175
 176         /* We only use the 32-bit flash */
 177         mv64x60_get_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, &base,
 178                 &ev64360_flash_size_0);
 179         ev64360_flash_size_1 = 0;
 180
 181         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
 182                  EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE, 0);
 183         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
 184
 185         mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
 186                  EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
 187         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
 188         sram_base = ioremap(EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
 189
 190         /* Set up Enet->SRAM window */
 191         mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
 192                 EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
 193         bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
 194
 195         /* Give enet r/w access to memory region */
 196         mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
 197         mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
 198         mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
 199
 200         mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
 201         mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
 202                          ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
 203
 204 #if defined(CONFIG_NOT_COHERENT_CACHE)
 205         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
 206 #else
 207         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
 208 #endif
 209
 210         /*
 211          * Setting the SRAM to 0. Note that this generates parity errors on
 212          * internal data path in SRAM since it's first time accessing it
 213          * while after reset it's not configured.
 214          */
 215         memset(sram_base, 0, MV64360_SRAM_SIZE);
 216
 217         /* set up PCI interrupt controller */
 218         ev64360_intr_setup();
 219 }
 220
 221 static void __init
 222 ev64360_setup_arch(void)
 223 {
 224         if (ppc_md.progress)
 225                 ppc_md.progress("ev64360_setup_arch: enter", 0);
 226
 227         set_tb(0, 0);
 228
 229 #ifdef CONFIG_BLK_DEV_INITRD
 230         if (initrd_start)
 231                 ROOT_DEV = Root_RAM0;
 232         else
 233 #endif
 234 #ifdef   CONFIG_ROOT_NFS
 235                 ROOT_DEV = Root_NFS;
 236 #else
 237                 ROOT_DEV = Root_SDA2;
 238 #endif
 239
 240         /*
 241          * Set up the L2CR register.
 242          */
 243         _set_L2CR(L2CR_L2E | L2CR_L2PE);
 244
 245         if (ppc_md.progress)
 246                 ppc_md.progress("ev64360_setup_arch: calling setup_bridge", 0);
 247
 248         ev64360_setup_bridge();
 249         ev64360_setup_peripherals();
 250         ev64360_bus_frequency = ev64360_bus_freq();
 251
 252         printk(KERN_INFO "%s %s port (C) 2005 Lee Nicks "
 253                 "(allinux@gmail.com)\n", BOARD_VENDOR, BOARD_MACHINE);
 254         if (ppc_md.progress)
 255                 ppc_md.progress("ev64360_setup_arch: exit", 0);
 256 }
 257
 258 /* Platform device data fixup routines. */
 259 #if defined(CONFIG_SERIAL_MPSC)
 260 static void __init
 261 ev64360_fixup_mpsc_pdata(struct platform_device *pdev)
 262 {
 263         struct mpsc_pdata *pdata;
 264
 265         pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
 266
 267         pdata->max_idle = 40;
 268         pdata->default_baud = EV64360_DEFAULT_BAUD;
 269         pdata->brg_clk_src = EV64360_MPSC_CLK_SRC;
 270         /*
 271          * TCLK (not SysCLk) is routed to BRG, then to the MPSC.  On most parts,
 272          * TCLK == SysCLK but on 64460, they are separate pins.
 273          * SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz.
 274          */
 275         pdata->brg_clk_freq = min(ev64360_bus_frequency, MV64x60_TCLK_FREQ_MAX);
 276 }
 277 #endif
 278
 279 #if defined(CONFIG_MV643XX_ETH)
 280 static void __init
 281 ev64360_fixup_eth_pdata(struct platform_device *pdev)
 282 {
 283         struct mv643xx_eth_platform_data *eth_pd;
 284         static u16 phy_addr[] = {
 285                 EV64360_ETH0_PHY_ADDR,
 286                 EV64360_ETH1_PHY_ADDR,
 287                 EV64360_ETH2_PHY_ADDR,
 288         };
 289
 290         eth_pd = pdev->dev.platform_data;
 291         eth_pd->force_phy_addr = 1;
 292         eth_pd->phy_addr = phy_addr[pdev->id];
 293         eth_pd->tx_queue_size = EV64360_ETH_TX_QUEUE_SIZE;
 294         eth_pd->rx_queue_size = EV64360_ETH_RX_QUEUE_SIZE;
 295 }
 296 #endif
 297
 298 static int __init
 299 ev64360_platform_notify(struct device *dev)
 300 {
 301         static struct {
 302                 char    *bus_id;
 303                 void    ((*rtn)(struct platform_device *pdev));
 304         } dev_map[] = {
 305 #if defined(CONFIG_SERIAL_MPSC)
 306                 { MPSC_CTLR_NAME ".0", ev64360_fixup_mpsc_pdata },
 307                 { MPSC_CTLR_NAME ".1", ev64360_fixup_mpsc_pdata },
 308 #endif
 309 #if defined(CONFIG_MV643XX_ETH)
 310                 { MV643XX_ETH_NAME ".0", ev64360_fixup_eth_pdata },
 311                 { MV643XX_ETH_NAME ".1", ev64360_fixup_eth_pdata },
 312                 { MV643XX_ETH_NAME ".2", ev64360_fixup_eth_pdata },
 313 #endif
 314         };
 315         struct platform_device  *pdev;
 316         int     i;
 317
 318         if (dev && dev->bus_id)
 319                 for (i=0; i<ARRAY_SIZE(dev_map); i++)
 320                         if (!strncmp(dev->bus_id, dev_map[i].bus_id,
 321                                 BUS_ID_SIZE)) {
 322
 323                                 pdev = container_of(dev,
 324                                         struct platform_device, dev);
 325                                 dev_map[i].rtn(pdev);
 326                         }
 327
 328         return 0;
 329 }
 330
 331 #ifdef CONFIG_MTD_PHYSMAP
 332
 333 #ifndef MB
 334 #define MB      (1 << 20)
 335 #endif
 336
 337 /*
 338  * MTD Layout.
 339  *
 340  * FLASH Amount:        0xff000000 - 0xffffffff
 341  * -------------        -----------------------
 342  * Reserved:            0xff000000 - 0xff03ffff
 343  * JFFS2 file system:   0xff040000 - 0xffefffff
 344  * U-boot:              0xfff00000 - 0xffffffff
 345  */
 346 static int __init
 347 ev64360_setup_mtd(void)
 348 {
 349         u32     size;
 350         int     ptbl_entries;
 351         static struct mtd_partition     *ptbl;
 352
 353         size = ev64360_flash_size_0 + ev64360_flash_size_1;
 354         if (!size)
 355                 return -ENOMEM;
 356
 357         ptbl_entries = 3;
 358
 359         if ((ptbl = kmalloc(ptbl_entries * sizeof(struct mtd_partition),
 360                 GFP_KERNEL)) == NULL) {
 361
 362                 printk(KERN_WARNING "Can't alloc MTD partition table\n");
 363                 return -ENOMEM;
 364         }
 365         memset(ptbl, 0, ptbl_entries * sizeof(struct mtd_partition));
 366
 367         ptbl[0].name = "reserved";
 368         ptbl[0].offset = 0;
 369         ptbl[0].size = EV64360_MTD_RESERVED_SIZE;
 370         ptbl[1].name = "jffs2";
 371         ptbl[1].offset = EV64360_MTD_RESERVED_SIZE;
 372         ptbl[1].size = EV64360_MTD_JFFS2_SIZE;
 373         ptbl[2].name = "U-BOOT";
 374         ptbl[2].offset = EV64360_MTD_RESERVED_SIZE + EV64360_MTD_JFFS2_SIZE;
 375         ptbl[2].size = EV64360_MTD_UBOOT_SIZE;
 376
 377         physmap_map.size = size;
 378         physmap_set_partitions(ptbl, ptbl_entries);
 379         return 0;
 380 }
 381
 382 arch_initcall(ev64360_setup_mtd);
 383 #endif
 384
 385 static void
 386 ev64360_restart(char *cmd)
 387 {
 388         ulong   i = 0xffffffff;
 389         volatile unsigned char * rtc_base = ioremap(EV64360_RTC_WINDOW_BASE,0x4000);
 390
 391         /* issue hard reset */
 392         rtc_base[0xf] = 0x80;
 393         rtc_base[0xc] = 0x00;
 394         rtc_base[0xd] = 0x01;
 395         rtc_base[0xf] = 0x83;
 396
 397         while (i-- > 0) ;
 398         panic("restart failed\n");
 399 }
 400
 401 static void
 402 ev64360_halt(void)
 403 {
 404         while (1) ;
 405         /* NOTREACHED */
 406 }
 407
 408 static void
 409 ev64360_power_off(void)
 410 {
 411         ev64360_halt();
 412         /* NOTREACHED */
 413 }
 414
 415 static int
 416 ev64360_show_cpuinfo(struct seq_file *m)
 417 {
 418         seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
 419         seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
 420         seq_printf(m, "bus speed\t: %dMHz\n", ev64360_bus_frequency/1000/1000);
 421
 422         return 0;
 423 }
 424
 425 static void __init
 426 ev64360_calibrate_decr(void)
 427 {
 428         u32 freq;
 429
 430         freq = ev64360_bus_frequency / 4;
 431
 432         printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
 433                (long)freq / 1000000, (long)freq % 1000000);
 434
 435         tb_ticks_per_jiffy = freq / HZ;
 436         tb_to_us = mulhwu_scale_factor(freq, 1000000);
 437 }
 438
 439 unsigned long __init
 440 ev64360_find_end_of_memory(void)
 441 {
 442         return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
 443                 MV64x60_TYPE_MV64360);
 444 }
 445
 446 static inline void
 447 ev64360_set_bat(void)
 448 {
 449         mb();
 450         mtspr(SPRN_DBAT2U, 0xf0001ffe);
 451         mtspr(SPRN_DBAT2L, 0xf000002a);
 452         mb();
 453 }
 454
 455 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
 456 static void __init
 457 ev64360_map_io(void)
 458 {
 459         io_block_mapping(CONFIG_MV64X60_NEW_BASE, \
 460                          CONFIG_MV64X60_NEW_BASE, \
 461                          0x00020000, _PAGE_IO);
 462 }
 463 #endif
 464
 465 void __init
 466 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 467               unsigned long r6, unsigned long r7)
 468 {
 469         parse_bootinfo(find_bootinfo());
 470
 471         /* ASSUMPTION:  If both r3 (bd_t pointer) and r6 (cmdline pointer)
 472          * are non-zero, then we should use the board info from the bd_t
 473          * structure and the cmdline pointed to by r6 instead of the
 474          * information from birecs, if any.  Otherwise, use the information
 475          * from birecs as discovered by the preceeding call to
 476          * parse_bootinfo().  This rule should work with both PPCBoot, which
 477          * uses a bd_t board info structure, and the kernel boot wrapper,
 478          * which uses birecs.
 479          */
 480         if (r3 && r6) {
 481                 /* copy board info structure */
 482                 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
 483                 /* copy command line */
 484                 *(char *)(r7+KERNELBASE) = 0;
 485                 strcpy(cmd_line, (char *)(r6+KERNELBASE));
 486         }
 487         #ifdef CONFIG_ISA
 488         isa_mem_base = 0;
 489         #endif
 490
 491         ppc_md.setup_arch = ev64360_setup_arch;
 492         ppc_md.show_cpuinfo = ev64360_show_cpuinfo;
 493         ppc_md.init_IRQ = mv64360_init_irq;
 494         ppc_md.get_irq = mv64360_get_irq;
 495         ppc_md.restart = ev64360_restart;
 496         ppc_md.power_off = ev64360_power_off;
 497         ppc_md.halt = ev64360_halt;
 498         ppc_md.find_end_of_memory = ev64360_find_end_of_memory;
 499         ppc_md.calibrate_decr = ev64360_calibrate_decr;
 500
 501 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
 502         ppc_md.setup_io_mappings = ev64360_map_io;
 503         ppc_md.progress = mv64x60_mpsc_progress;
 504         mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
 505 #endif
 506
 507 #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
 508         platform_notify = ev64360_platform_notify;
 509 #endif
 510
 511         ev64360_set_bat(); /* Need for ev64360_find_end_of_memory and progress */
 512 }