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sparc64: Implement IRQ stacks.
[linux-2.6/x86.git] / arch / sparc64 / mm / init.c
blob217de3ea29e842cff4c0eff6be2b82c5a13f25fe
1 /*
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
14 #include <linux/mm.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
21 #include <linux/fs.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26 #include <linux/percpu.h>
27 #include <linux/lmb.h>
28 #include <linux/mmzone.h>
29
30 #include <asm/head.h>
31 #include <asm/system.h>
32 #include <asm/page.h>
33 #include <asm/pgalloc.h>
34 #include <asm/pgtable.h>
35 #include <asm/oplib.h>
36 #include <asm/iommu.h>
37 #include <asm/io.h>
38 #include <asm/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/tlbflush.h>
41 #include <asm/dma.h>
42 #include <asm/starfire.h>
43 #include <asm/tlb.h>
44 #include <asm/spitfire.h>
45 #include <asm/sections.h>
46 #include <asm/tsb.h>
47 #include <asm/hypervisor.h>
48 #include <asm/prom.h>
49 #include <asm/sstate.h>
50 #include <asm/mdesc.h>
51 #include <asm/cpudata.h>
52 #include <asm/irq.h>
53
54 #define MAX_PHYS_ADDRESS (1UL << 42UL)
55 #define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
56 #define KPTE_BITMAP_BYTES \
57 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
58
59 unsigned long kern_linear_pte_xor[2] __read_mostly;
60
61 /* A bitmap, one bit for every 256MB of physical memory. If the bit
62 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
63 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
64 */
65 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
66
67 #ifndef CONFIG_DEBUG_PAGEALLOC
68 /* A special kernel TSB for 4MB and 256MB linear mappings.
69 * Space is allocated for this right after the trap table
70 * in arch/sparc64/kernel/head.S
71 */
72 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
73 #endif
74
75 #define MAX_BANKS 32
76
77 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
78 static int pavail_ents __initdata;
79
80 static int cmp_p64(const void *a, const void *b)
81 {
82 const struct linux_prom64_registers *x = a, *y = b;
83
84 if (x->phys_addr > y->phys_addr)
85 return 1;
86 if (x->phys_addr < y->phys_addr)
87 return -1;
88 return 0;
89 }
90
91 static void __init read_obp_memory(const char *property,
92 struct linux_prom64_registers *regs,
93 int *num_ents)
94 {
95 int node = prom_finddevice("/memory");
96 int prop_size = prom_getproplen(node, property);
97 int ents, ret, i;
98
99 ents = prop_size / sizeof(struct linux_prom64_registers);
100 if (ents > MAX_BANKS) {
101 prom_printf("The machine has more %s property entries than "
102 "this kernel can support (%d).\n",
103 property, MAX_BANKS);
104 prom_halt();
105 }
106
107 ret = prom_getproperty(node, property, (char *) regs, prop_size);
108 if (ret == -1) {
109 prom_printf("Couldn't get %s property from /memory.\n");
110 prom_halt();
111 }
112
113 /* Sanitize what we got from the firmware, by page aligning
114 * everything.
115 */
116 for (i = 0; i < ents; i++) {
117 unsigned long base, size;
118
119 base = regs[i].phys_addr;
120 size = regs[i].reg_size;
121
122 size &= PAGE_MASK;
123 if (base & ~PAGE_MASK) {
124 unsigned long new_base = PAGE_ALIGN(base);
125
126 size -= new_base - base;
127 if ((long) size < 0L)
128 size = 0UL;
129 base = new_base;
130 }
131 if (size == 0UL) {
132 /* If it is empty, simply get rid of it.
133 * This simplifies the logic of the other
134 * functions that process these arrays.
135 */
136 memmove(&regs[i], &regs[i + 1],
137 (ents - i - 1) * sizeof(regs[0]));
138 i--;
139 ents--;
140 continue;
141 }
142 regs[i].phys_addr = base;
143 regs[i].reg_size = size;
144 }
145
146 *num_ents = ents;
147
148 sort(regs, ents, sizeof(struct linux_prom64_registers),
149 cmp_p64, NULL);
150 }
151
152 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
153
154 /* Kernel physical address base and size in bytes. */
155 unsigned long kern_base __read_mostly;
156 unsigned long kern_size __read_mostly;
157
158 /* Initial ramdisk setup */
159 extern unsigned long sparc_ramdisk_image64;
160 extern unsigned int sparc_ramdisk_image;
161 extern unsigned int sparc_ramdisk_size;
162
163 struct page *mem_map_zero __read_mostly;
164 EXPORT_SYMBOL(mem_map_zero);
165
166 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
167
168 unsigned long sparc64_kern_pri_context __read_mostly;
169 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
170 unsigned long sparc64_kern_sec_context __read_mostly;
171
172 int num_kernel_image_mappings;
173
174 #ifdef CONFIG_DEBUG_DCFLUSH
175 atomic_t dcpage_flushes = ATOMIC_INIT(0);
176 #ifdef CONFIG_SMP
177 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
178 #endif
179 #endif
180
181 inline void flush_dcache_page_impl(struct page *page)
182 {
183 BUG_ON(tlb_type == hypervisor);
184 #ifdef CONFIG_DEBUG_DCFLUSH
185 atomic_inc(&dcpage_flushes);
186 #endif
187
188 #ifdef DCACHE_ALIASING_POSSIBLE
189 __flush_dcache_page(page_address(page),
190 ((tlb_type == spitfire) &&
191 page_mapping(page) != NULL));
192 #else
193 if (page_mapping(page) != NULL &&
194 tlb_type == spitfire)
195 __flush_icache_page(__pa(page_address(page)));
196 #endif
197 }
198
199 #define PG_dcache_dirty PG_arch_1
200 #define PG_dcache_cpu_shift 32UL
201 #define PG_dcache_cpu_mask \
202 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
203
204 #define dcache_dirty_cpu(page) \
205 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
206
207 static inline void set_dcache_dirty(struct page *page, int this_cpu)
208 {
209 unsigned long mask = this_cpu;
210 unsigned long non_cpu_bits;
211
212 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
213 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
214
215 __asm__ __volatile__("1:\n\t"
216 "ldx [%2], %%g7\n\t"
217 "and %%g7, %1, %%g1\n\t"
218 "or %%g1, %0, %%g1\n\t"
219 "casx [%2], %%g7, %%g1\n\t"
220 "cmp %%g7, %%g1\n\t"
221 "membar #StoreLoad | #StoreStore\n\t"
222 "bne,pn %%xcc, 1b\n\t"
223 " nop"
224 : /* no outputs */
225 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
226 : "g1", "g7");
227 }
228
229 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
230 {
231 unsigned long mask = (1UL << PG_dcache_dirty);
232
233 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
234 "1:\n\t"
235 "ldx [%2], %%g7\n\t"
236 "srlx %%g7, %4, %%g1\n\t"
237 "and %%g1, %3, %%g1\n\t"
238 "cmp %%g1, %0\n\t"
239 "bne,pn %%icc, 2f\n\t"
240 " andn %%g7, %1, %%g1\n\t"
241 "casx [%2], %%g7, %%g1\n\t"
242 "cmp %%g7, %%g1\n\t"
243 "membar #StoreLoad | #StoreStore\n\t"
244 "bne,pn %%xcc, 1b\n\t"
245 " nop\n"
246 "2:"
247 : /* no outputs */
248 : "r" (cpu), "r" (mask), "r" (&page->flags),
249 "i" (PG_dcache_cpu_mask),
250 "i" (PG_dcache_cpu_shift)
251 : "g1", "g7");
252 }
253
254 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
255 {
256 unsigned long tsb_addr = (unsigned long) ent;
257
258 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
259 tsb_addr = __pa(tsb_addr);
260
261 __tsb_insert(tsb_addr, tag, pte);
262 }
263
264 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
265 unsigned long _PAGE_SZBITS __read_mostly;
266
267 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
268 {
269 struct mm_struct *mm;
270 struct tsb *tsb;
271 unsigned long tag, flags;
272 unsigned long tsb_index, tsb_hash_shift;
273
274 if (tlb_type != hypervisor) {
275 unsigned long pfn = pte_pfn(pte);
276 unsigned long pg_flags;
277 struct page *page;
278
279 if (pfn_valid(pfn) &&
280 (page = pfn_to_page(pfn), page_mapping(page)) &&
281 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
282 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
283 PG_dcache_cpu_mask);
284 int this_cpu = get_cpu();
285
286 /* This is just to optimize away some function calls
287 * in the SMP case.
288 */
289 if (cpu == this_cpu)
290 flush_dcache_page_impl(page);
291 else
292 smp_flush_dcache_page_impl(page, cpu);
293
294 clear_dcache_dirty_cpu(page, cpu);
295
296 put_cpu();
297 }
298 }
299
300 mm = vma->vm_mm;
301
302 tsb_index = MM_TSB_BASE;
303 tsb_hash_shift = PAGE_SHIFT;
304
305 spin_lock_irqsave(&mm->context.lock, flags);
306
307 #ifdef CONFIG_HUGETLB_PAGE
308 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
309 if ((tlb_type == hypervisor &&
310 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
311 (tlb_type != hypervisor &&
312 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
313 tsb_index = MM_TSB_HUGE;
314 tsb_hash_shift = HPAGE_SHIFT;
315 }
316 }
317 #endif
318
319 tsb = mm->context.tsb_block[tsb_index].tsb;
320 tsb += ((address >> tsb_hash_shift) &
321 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
322 tag = (address >> 22UL);
323 tsb_insert(tsb, tag, pte_val(pte));
324
325 spin_unlock_irqrestore(&mm->context.lock, flags);
326 }
327
328 void flush_dcache_page(struct page *page)
329 {
330 struct address_space *mapping;
331 int this_cpu;
332
333 if (tlb_type == hypervisor)
334 return;
335
336 /* Do not bother with the expensive D-cache flush if it
337 * is merely the zero page. The 'bigcore' testcase in GDB
338 * causes this case to run millions of times.
339 */
340 if (page == ZERO_PAGE(0))
341 return;
342
343 this_cpu = get_cpu();
344
345 mapping = page_mapping(page);
346 if (mapping && !mapping_mapped(mapping)) {
347 int dirty = test_bit(PG_dcache_dirty, &page->flags);
348 if (dirty) {
349 int dirty_cpu = dcache_dirty_cpu(page);
350
351 if (dirty_cpu == this_cpu)
352 goto out;
353 smp_flush_dcache_page_impl(page, dirty_cpu);
354 }
355 set_dcache_dirty(page, this_cpu);
356 } else {
357 /* We could delay the flush for the !page_mapping
358 * case too. But that case is for exec env/arg
359 * pages and those are %99 certainly going to get
360 * faulted into the tlb (and thus flushed) anyways.
361 */
362 flush_dcache_page_impl(page);
363 }
364
365 out:
366 put_cpu();
367 }
368
369 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
370 {
371 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
372 if (tlb_type == spitfire) {
373 unsigned long kaddr;
374
375 /* This code only runs on Spitfire cpus so this is
376 * why we can assume _PAGE_PADDR_4U.
377 */
378 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
379 unsigned long paddr, mask = _PAGE_PADDR_4U;
380
381 if (kaddr >= PAGE_OFFSET)
382 paddr = kaddr & mask;
383 else {
384 pgd_t *pgdp = pgd_offset_k(kaddr);
385 pud_t *pudp = pud_offset(pgdp, kaddr);
386 pmd_t *pmdp = pmd_offset(pudp, kaddr);
387 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
388
389 paddr = pte_val(*ptep) & mask;
390 }
391 __flush_icache_page(paddr);
392 }
393 }
394 }
395
396 void mmu_info(struct seq_file *m)
397 {
398 if (tlb_type == cheetah)
399 seq_printf(m, "MMU Type\t: Cheetah\n");
400 else if (tlb_type == cheetah_plus)
401 seq_printf(m, "MMU Type\t: Cheetah+\n");
402 else if (tlb_type == spitfire)
403 seq_printf(m, "MMU Type\t: Spitfire\n");
404 else if (tlb_type == hypervisor)
405 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
406 else
407 seq_printf(m, "MMU Type\t: ???\n");
408
409 #ifdef CONFIG_DEBUG_DCFLUSH
410 seq_printf(m, "DCPageFlushes\t: %d\n",
411 atomic_read(&dcpage_flushes));
412 #ifdef CONFIG_SMP
413 seq_printf(m, "DCPageFlushesXC\t: %d\n",
414 atomic_read(&dcpage_flushes_xcall));
415 #endif /* CONFIG_SMP */
416 #endif /* CONFIG_DEBUG_DCFLUSH */
417 }
418
419 struct linux_prom_translation {
420 unsigned long virt;
421 unsigned long size;
422 unsigned long data;
423 };
424
425 /* Exported for kernel TLB miss handling in ktlb.S */
426 struct linux_prom_translation prom_trans[512] __read_mostly;
427 unsigned int prom_trans_ents __read_mostly;
428
429 /* Exported for SMP bootup purposes. */
430 unsigned long kern_locked_tte_data;
431
432 /* The obp translations are saved based on 8k pagesize, since obp can
433 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
434 * HI_OBP_ADDRESS range are handled in ktlb.S.
435 */
436 static inline int in_obp_range(unsigned long vaddr)
437 {
438 return (vaddr >= LOW_OBP_ADDRESS &&
439 vaddr < HI_OBP_ADDRESS);
440 }
441
442 static int cmp_ptrans(const void *a, const void *b)
443 {
444 const struct linux_prom_translation *x = a, *y = b;
445
446 if (x->virt > y->virt)
447 return 1;
448 if (x->virt < y->virt)
449 return -1;
450 return 0;
451 }
452
453 /* Read OBP translations property into 'prom_trans[]'. */
454 static void __init read_obp_translations(void)
455 {
456 int n, node, ents, first, last, i;
457
458 node = prom_finddevice("/virtual-memory");
459 n = prom_getproplen(node, "translations");
460 if (unlikely(n == 0 || n == -1)) {
461 prom_printf("prom_mappings: Couldn't get size.\n");
462 prom_halt();
463 }
464 if (unlikely(n > sizeof(prom_trans))) {
465 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
466 prom_halt();
467 }
468
469 if ((n = prom_getproperty(node, "translations",
470 (char *)&prom_trans[0],
471 sizeof(prom_trans))) == -1) {
472 prom_printf("prom_mappings: Couldn't get property.\n");
473 prom_halt();
474 }
475
476 n = n / sizeof(struct linux_prom_translation);
477
478 ents = n;
479
480 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
481 cmp_ptrans, NULL);
482
483 /* Now kick out all the non-OBP entries. */
484 for (i = 0; i < ents; i++) {
485 if (in_obp_range(prom_trans[i].virt))
486 break;
487 }
488 first = i;
489 for (; i < ents; i++) {
490 if (!in_obp_range(prom_trans[i].virt))
491 break;
492 }
493 last = i;
494
495 for (i = 0; i < (last - first); i++) {
496 struct linux_prom_translation *src = &prom_trans[i + first];
497 struct linux_prom_translation *dest = &prom_trans[i];
498
499 *dest = *src;
500 }
501 for (; i < ents; i++) {
502 struct linux_prom_translation *dest = &prom_trans[i];
503 dest->virt = dest->size = dest->data = 0x0UL;
504 }
505
506 prom_trans_ents = last - first;
507
508 if (tlb_type == spitfire) {
509 /* Clear diag TTE bits. */
510 for (i = 0; i < prom_trans_ents; i++)
511 prom_trans[i].data &= ~0x0003fe0000000000UL;
512 }
513 }
514
515 static void __init hypervisor_tlb_lock(unsigned long vaddr,
516 unsigned long pte,
517 unsigned long mmu)
518 {
519 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
520
521 if (ret != 0) {
522 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
523 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
524 prom_halt();
525 }
526 }
527
528 static unsigned long kern_large_tte(unsigned long paddr);
529
530 static void __init remap_kernel(void)
531 {
532 unsigned long phys_page, tte_vaddr, tte_data;
533 int i, tlb_ent = sparc64_highest_locked_tlbent();
534
535 tte_vaddr = (unsigned long) KERNBASE;
536 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
537 tte_data = kern_large_tte(phys_page);
538
539 kern_locked_tte_data = tte_data;
540
541 /* Now lock us into the TLBs via Hypervisor or OBP. */
542 if (tlb_type == hypervisor) {
543 for (i = 0; i < num_kernel_image_mappings; i++) {
544 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
545 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
546 tte_vaddr += 0x400000;
547 tte_data += 0x400000;
548 }
549 } else {
550 for (i = 0; i < num_kernel_image_mappings; i++) {
551 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
552 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
553 tte_vaddr += 0x400000;
554 tte_data += 0x400000;
555 }
556 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
557 }
558 if (tlb_type == cheetah_plus) {
559 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
560 CTX_CHEETAH_PLUS_NUC);
561 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
562 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
563 }
564 }
565
566
567 static void __init inherit_prom_mappings(void)
568 {
569 /* Now fixup OBP's idea about where we really are mapped. */
570 printk("Remapping the kernel... ");
571 remap_kernel();
572 printk("done.\n");
573 }
574
575 void prom_world(int enter)
576 {
577 if (!enter)
578 set_fs((mm_segment_t) { get_thread_current_ds() });
579
580 __asm__ __volatile__("flushw");
581 }
582
583 void __flush_dcache_range(unsigned long start, unsigned long end)
584 {
585 unsigned long va;
586
587 if (tlb_type == spitfire) {
588 int n = 0;
589
590 for (va = start; va < end; va += 32) {
591 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
592 if (++n >= 512)
593 break;
594 }
595 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
596 start = __pa(start);
597 end = __pa(end);
598 for (va = start; va < end; va += 32)
599 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
600 "membar #Sync"
601 : /* no outputs */
602 : "r" (va),
603 "i" (ASI_DCACHE_INVALIDATE));
604 }
605 }
606
607 /* get_new_mmu_context() uses "cache + 1". */
608 DEFINE_SPINLOCK(ctx_alloc_lock);
609 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
610 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
611 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
612 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
613
614 /* Caller does TLB context flushing on local CPU if necessary.
615 * The caller also ensures that CTX_VALID(mm->context) is false.
616 *
617 * We must be careful about boundary cases so that we never
618 * let the user have CTX 0 (nucleus) or we ever use a CTX
619 * version of zero (and thus NO_CONTEXT would not be caught
620 * by version mis-match tests in mmu_context.h).
621 *
622 * Always invoked with interrupts disabled.
623 */
624 void get_new_mmu_context(struct mm_struct *mm)
625 {
626 unsigned long ctx, new_ctx;
627 unsigned long orig_pgsz_bits;
628 unsigned long flags;
629 int new_version;
630
631 spin_lock_irqsave(&ctx_alloc_lock, flags);
632 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
633 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
634 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
635 new_version = 0;
636 if (new_ctx >= (1 << CTX_NR_BITS)) {
637 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
638 if (new_ctx >= ctx) {
639 int i;
640 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
641 CTX_FIRST_VERSION;
642 if (new_ctx == 1)
643 new_ctx = CTX_FIRST_VERSION;
644
645 /* Don't call memset, for 16 entries that's just
646 * plain silly...
647 */
648 mmu_context_bmap[0] = 3;
649 mmu_context_bmap[1] = 0;
650 mmu_context_bmap[2] = 0;
651 mmu_context_bmap[3] = 0;
652 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
653 mmu_context_bmap[i + 0] = 0;
654 mmu_context_bmap[i + 1] = 0;
655 mmu_context_bmap[i + 2] = 0;
656 mmu_context_bmap[i + 3] = 0;
657 }
658 new_version = 1;
659 goto out;
660 }
661 }
662 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
663 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
664 out:
665 tlb_context_cache = new_ctx;
666 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
667 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
668
669 if (unlikely(new_version))
670 smp_new_mmu_context_version();
671 }
672
673 static int numa_enabled = 1;
674 static int numa_debug;
675
676 static int __init early_numa(char *p)
677 {
678 if (!p)
679 return 0;
680
681 if (strstr(p, "off"))
682 numa_enabled = 0;
683
684 if (strstr(p, "debug"))
685 numa_debug = 1;
686
687 return 0;
688 }
689 early_param("numa", early_numa);
690
691 #define numadbg(f, a...) \
692 do { if (numa_debug) \
693 printk(KERN_INFO f, ## a); \
694 } while (0)
695
696 static void __init find_ramdisk(unsigned long phys_base)
697 {
698 #ifdef CONFIG_BLK_DEV_INITRD
699 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
700 unsigned long ramdisk_image;
701
702 /* Older versions of the bootloader only supported a
703 * 32-bit physical address for the ramdisk image
704 * location, stored at sparc_ramdisk_image. Newer
705 * SILO versions set sparc_ramdisk_image to zero and
706 * provide a full 64-bit physical address at
707 * sparc_ramdisk_image64.
708 */
709 ramdisk_image = sparc_ramdisk_image;
710 if (!ramdisk_image)
711 ramdisk_image = sparc_ramdisk_image64;
712
713 /* Another bootloader quirk. The bootloader normalizes
714 * the physical address to KERNBASE, so we have to
715 * factor that back out and add in the lowest valid
716 * physical page address to get the true physical address.
717 */
718 ramdisk_image -= KERNBASE;
719 ramdisk_image += phys_base;
720
721 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
722 ramdisk_image, sparc_ramdisk_size);
723
724 initrd_start = ramdisk_image;
725 initrd_end = ramdisk_image + sparc_ramdisk_size;
726
727 lmb_reserve(initrd_start, sparc_ramdisk_size);
728
729 initrd_start += PAGE_OFFSET;
730 initrd_end += PAGE_OFFSET;
731 }
732 #endif
733 }
734
735 struct node_mem_mask {
736 unsigned long mask;
737 unsigned long val;
738 unsigned long bootmem_paddr;
739 };
740 static struct node_mem_mask node_masks[MAX_NUMNODES];
741 static int num_node_masks;
742
743 int numa_cpu_lookup_table[NR_CPUS];
744 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
745
746 #ifdef CONFIG_NEED_MULTIPLE_NODES
747
748 struct mdesc_mblock {
749 u64 base;
750 u64 size;
751 u64 offset; /* RA-to-PA */
752 };
753 static struct mdesc_mblock *mblocks;
754 static int num_mblocks;
755
756 static unsigned long ra_to_pa(unsigned long addr)
757 {
758 int i;
759
760 for (i = 0; i < num_mblocks; i++) {
761 struct mdesc_mblock *m = &mblocks[i];
762
763 if (addr >= m->base &&
764 addr < (m->base + m->size)) {
765 addr += m->offset;
766 break;
767 }
768 }
769 return addr;
770 }
771
772 static int find_node(unsigned long addr)
773 {
774 int i;
775
776 addr = ra_to_pa(addr);
777 for (i = 0; i < num_node_masks; i++) {
778 struct node_mem_mask *p = &node_masks[i];
779
780 if ((addr & p->mask) == p->val)
781 return i;
782 }
783 return -1;
784 }
785
786 static unsigned long nid_range(unsigned long start, unsigned long end,
787 int *nid)
788 {
789 *nid = find_node(start);
790 start += PAGE_SIZE;
791 while (start < end) {
792 int n = find_node(start);
793
794 if (n != *nid)
795 break;
796 start += PAGE_SIZE;
797 }
798
799 return start;
800 }
801 #else
802 static unsigned long nid_range(unsigned long start, unsigned long end,
803 int *nid)
804 {
805 *nid = 0;
806 return end;
807 }
808 #endif
809
810 /* This must be invoked after performing all of the necessary
811 * add_active_range() calls for 'nid'. We need to be able to get
812 * correct data from get_pfn_range_for_nid().
813 */
814 static void __init allocate_node_data(int nid)
815 {
816 unsigned long paddr, num_pages, start_pfn, end_pfn;
817 struct pglist_data *p;
818
819 #ifdef CONFIG_NEED_MULTIPLE_NODES
820 paddr = lmb_alloc_nid(sizeof(struct pglist_data),
821 SMP_CACHE_BYTES, nid, nid_range);
822 if (!paddr) {
823 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
824 prom_halt();
825 }
826 NODE_DATA(nid) = __va(paddr);
827 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
828
829 NODE_DATA(nid)->bdata = &bootmem_node_data[nid];
830 #endif
831
832 p = NODE_DATA(nid);
833
834 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
835 p->node_start_pfn = start_pfn;
836 p->node_spanned_pages = end_pfn - start_pfn;
837
838 if (p->node_spanned_pages) {
839 num_pages = bootmem_bootmap_pages(p->node_spanned_pages);
840
841 paddr = lmb_alloc_nid(num_pages << PAGE_SHIFT, PAGE_SIZE, nid,
842 nid_range);
843 if (!paddr) {
844 prom_printf("Cannot allocate bootmap for nid[%d]\n",
845 nid);
846 prom_halt();
847 }
848 node_masks[nid].bootmem_paddr = paddr;
849 }
850 }
851
852 static void init_node_masks_nonnuma(void)
853 {
854 int i;
855
856 numadbg("Initializing tables for non-numa.\n");
857
858 node_masks[0].mask = node_masks[0].val = 0;
859 num_node_masks = 1;
860
861 for (i = 0; i < NR_CPUS; i++)
862 numa_cpu_lookup_table[i] = 0;
863
864 numa_cpumask_lookup_table[0] = CPU_MASK_ALL;
865 }
866
867 #ifdef CONFIG_NEED_MULTIPLE_NODES
868 struct pglist_data *node_data[MAX_NUMNODES];
869
870 EXPORT_SYMBOL(numa_cpu_lookup_table);
871 EXPORT_SYMBOL(numa_cpumask_lookup_table);
872 EXPORT_SYMBOL(node_data);
873
874 struct mdesc_mlgroup {
875 u64 node;
876 u64 latency;
877 u64 match;
878 u64 mask;
879 };
880 static struct mdesc_mlgroup *mlgroups;
881 static int num_mlgroups;
882
883 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
884 u32 cfg_handle)
885 {
886 u64 arc;
887
888 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
889 u64 target = mdesc_arc_target(md, arc);
890 const u64 *val;
891
892 val = mdesc_get_property(md, target,
893 "cfg-handle", NULL);
894 if (val && *val == cfg_handle)
895 return 0;
896 }
897 return -ENODEV;
898 }
899
900 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
901 u32 cfg_handle)
902 {
903 u64 arc, candidate, best_latency = ~(u64)0;
904
905 candidate = MDESC_NODE_NULL;
906 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
907 u64 target = mdesc_arc_target(md, arc);
908 const char *name = mdesc_node_name(md, target);
909 const u64 *val;
910
911 if (strcmp(name, "pio-latency-group"))
912 continue;
913
914 val = mdesc_get_property(md, target, "latency", NULL);
915 if (!val)
916 continue;
917
918 if (*val < best_latency) {
919 candidate = target;
920 best_latency = *val;
921 }
922 }
923
924 if (candidate == MDESC_NODE_NULL)
925 return -ENODEV;
926
927 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
928 }
929
930 int of_node_to_nid(struct device_node *dp)
931 {
932 const struct linux_prom64_registers *regs;
933 struct mdesc_handle *md;
934 u32 cfg_handle;
935 int count, nid;
936 u64 grp;
937
938 if (!mlgroups)
939 return -1;
940
941 regs = of_get_property(dp, "reg", NULL);
942 if (!regs)
943 return -1;
944
945 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
946
947 md = mdesc_grab();
948
949 count = 0;
950 nid = -1;
951 mdesc_for_each_node_by_name(md, grp, "group") {
952 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
953 nid = count;
954 break;
955 }
956 count++;
957 }
958
959 mdesc_release(md);
960
961 return nid;
962 }
963
964 static void add_node_ranges(void)
965 {
966 int i;
967
968 for (i = 0; i < lmb.memory.cnt; i++) {
969 unsigned long size = lmb_size_bytes(&lmb.memory, i);
970 unsigned long start, end;
971
972 start = lmb.memory.region[i].base;
973 end = start + size;
974 while (start < end) {
975 unsigned long this_end;
976 int nid;
977
978 this_end = nid_range(start, end, &nid);
979
980 numadbg("Adding active range nid[%d] "
981 "start[%lx] end[%lx]\n",
982 nid, start, this_end);
983
984 add_active_range(nid,
985 start >> PAGE_SHIFT,
986 this_end >> PAGE_SHIFT);
987
988 start = this_end;
989 }
990 }
991 }
992
993 static int __init grab_mlgroups(struct mdesc_handle *md)
994 {
995 unsigned long paddr;
996 int count = 0;
997 u64 node;
998
999 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1000 count++;
1001 if (!count)
1002 return -ENOENT;
1003
1004 paddr = lmb_alloc(count * sizeof(struct mdesc_mlgroup),
1005 SMP_CACHE_BYTES);
1006 if (!paddr)
1007 return -ENOMEM;
1008
1009 mlgroups = __va(paddr);
1010 num_mlgroups = count;
1011
1012 count = 0;
1013 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1014 struct mdesc_mlgroup *m = &mlgroups[count++];
1015 const u64 *val;
1016
1017 m->node = node;
1018
1019 val = mdesc_get_property(md, node, "latency", NULL);
1020 m->latency = *val;
1021 val = mdesc_get_property(md, node, "address-match", NULL);
1022 m->match = *val;
1023 val = mdesc_get_property(md, node, "address-mask", NULL);
1024 m->mask = *val;
1025
1026 numadbg("MLGROUP[%d]: node[%lx] latency[%lx] "
1027 "match[%lx] mask[%lx]\n",
1028 count - 1, m->node, m->latency, m->match, m->mask);
1029 }
1030
1031 return 0;
1032 }
1033
1034 static int __init grab_mblocks(struct mdesc_handle *md)
1035 {
1036 unsigned long paddr;
1037 int count = 0;
1038 u64 node;
1039
1040 mdesc_for_each_node_by_name(md, node, "mblock")
1041 count++;
1042 if (!count)
1043 return -ENOENT;
1044
1045 paddr = lmb_alloc(count * sizeof(struct mdesc_mblock),
1046 SMP_CACHE_BYTES);
1047 if (!paddr)
1048 return -ENOMEM;
1049
1050 mblocks = __va(paddr);
1051 num_mblocks = count;
1052
1053 count = 0;
1054 mdesc_for_each_node_by_name(md, node, "mblock") {
1055 struct mdesc_mblock *m = &mblocks[count++];
1056 const u64 *val;
1057
1058 val = mdesc_get_property(md, node, "base", NULL);
1059 m->base = *val;
1060 val = mdesc_get_property(md, node, "size", NULL);
1061 m->size = *val;
1062 val = mdesc_get_property(md, node,
1063 "address-congruence-offset", NULL);
1064 m->offset = *val;
1065
1066 numadbg("MBLOCK[%d]: base[%lx] size[%lx] offset[%lx]\n",
1067 count - 1, m->base, m->size, m->offset);
1068 }
1069
1070 return 0;
1071 }
1072
1073 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1074 u64 grp, cpumask_t *mask)
1075 {
1076 u64 arc;
1077
1078 cpus_clear(*mask);
1079
1080 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1081 u64 target = mdesc_arc_target(md, arc);
1082 const char *name = mdesc_node_name(md, target);
1083 const u64 *id;
1084
1085 if (strcmp(name, "cpu"))
1086 continue;
1087 id = mdesc_get_property(md, target, "id", NULL);
1088 if (*id < NR_CPUS)
1089 cpu_set(*id, *mask);
1090 }
1091 }
1092
1093 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1094 {
1095 int i;
1096
1097 for (i = 0; i < num_mlgroups; i++) {
1098 struct mdesc_mlgroup *m = &mlgroups[i];
1099 if (m->node == node)
1100 return m;
1101 }
1102 return NULL;
1103 }
1104
1105 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1106 int index)
1107 {
1108 struct mdesc_mlgroup *candidate = NULL;
1109 u64 arc, best_latency = ~(u64)0;
1110 struct node_mem_mask *n;
1111
1112 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1113 u64 target = mdesc_arc_target(md, arc);
1114 struct mdesc_mlgroup *m = find_mlgroup(target);
1115 if (!m)
1116 continue;
1117 if (m->latency < best_latency) {
1118 candidate = m;
1119 best_latency = m->latency;
1120 }
1121 }
1122 if (!candidate)
1123 return -ENOENT;
1124
1125 if (num_node_masks != index) {
1126 printk(KERN_ERR "Inconsistent NUMA state, "
1127 "index[%d] != num_node_masks[%d]\n",
1128 index, num_node_masks);
1129 return -EINVAL;
1130 }
1131
1132 n = &node_masks[num_node_masks++];
1133
1134 n->mask = candidate->mask;
1135 n->val = candidate->match;
1136
1137 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%lx])\n",
1138 index, n->mask, n->val, candidate->latency);
1139
1140 return 0;
1141 }
1142
1143 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1144 int index)
1145 {
1146 cpumask_t mask;
1147 int cpu;
1148
1149 numa_parse_mdesc_group_cpus(md, grp, &mask);
1150
1151 for_each_cpu_mask(cpu, mask)
1152 numa_cpu_lookup_table[cpu] = index;
1153 numa_cpumask_lookup_table[index] = mask;
1154
1155 if (numa_debug) {
1156 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1157 for_each_cpu_mask(cpu, mask)
1158 printk("%d ", cpu);
1159 printk("]\n");
1160 }
1161
1162 return numa_attach_mlgroup(md, grp, index);
1163 }
1164
1165 static int __init numa_parse_mdesc(void)
1166 {
1167 struct mdesc_handle *md = mdesc_grab();
1168 int i, err, count;
1169 u64 node;
1170
1171 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1172 if (node == MDESC_NODE_NULL) {
1173 mdesc_release(md);
1174 return -ENOENT;
1175 }
1176
1177 err = grab_mblocks(md);
1178 if (err < 0)
1179 goto out;
1180
1181 err = grab_mlgroups(md);
1182 if (err < 0)
1183 goto out;
1184
1185 count = 0;
1186 mdesc_for_each_node_by_name(md, node, "group") {
1187 err = numa_parse_mdesc_group(md, node, count);
1188 if (err < 0)
1189 break;
1190 count++;
1191 }
1192
1193 add_node_ranges();
1194
1195 for (i = 0; i < num_node_masks; i++) {
1196 allocate_node_data(i);
1197 node_set_online(i);
1198 }
1199
1200 err = 0;
1201 out:
1202 mdesc_release(md);
1203 return err;
1204 }
1205
1206 static int __init numa_parse_sun4u(void)
1207 {
1208 return -1;
1209 }
1210
1211 static int __init bootmem_init_numa(void)
1212 {
1213 int err = -1;
1214
1215 numadbg("bootmem_init_numa()\n");
1216
1217 if (numa_enabled) {
1218 if (tlb_type == hypervisor)
1219 err = numa_parse_mdesc();
1220 else
1221 err = numa_parse_sun4u();
1222 }
1223 return err;
1224 }
1225
1226 #else
1227
1228 static int bootmem_init_numa(void)
1229 {
1230 return -1;
1231 }
1232
1233 #endif
1234
1235 static void __init bootmem_init_nonnuma(void)
1236 {
1237 unsigned long top_of_ram = lmb_end_of_DRAM();
1238 unsigned long total_ram = lmb_phys_mem_size();
1239 unsigned int i;
1240
1241 numadbg("bootmem_init_nonnuma()\n");
1242
1243 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1244 top_of_ram, total_ram);
1245 printk(KERN_INFO "Memory hole size: %ldMB\n",
1246 (top_of_ram - total_ram) >> 20);
1247
1248 init_node_masks_nonnuma();
1249
1250 for (i = 0; i < lmb.memory.cnt; i++) {
1251 unsigned long size = lmb_size_bytes(&lmb.memory, i);
1252 unsigned long start_pfn, end_pfn;
1253
1254 if (!size)
1255 continue;
1256
1257 start_pfn = lmb.memory.region[i].base >> PAGE_SHIFT;
1258 end_pfn = start_pfn + lmb_size_pages(&lmb.memory, i);
1259 add_active_range(0, start_pfn, end_pfn);
1260 }
1261
1262 allocate_node_data(0);
1263
1264 node_set_online(0);
1265 }
1266
1267 static void __init reserve_range_in_node(int nid, unsigned long start,
1268 unsigned long end)
1269 {
1270 numadbg(" reserve_range_in_node(nid[%d],start[%lx],end[%lx]\n",
1271 nid, start, end);
1272 while (start < end) {
1273 unsigned long this_end;
1274 int n;
1275
1276 this_end = nid_range(start, end, &n);
1277 if (n == nid) {
1278 numadbg(" MATCH reserving range [%lx:%lx]\n",
1279 start, this_end);
1280 reserve_bootmem_node(NODE_DATA(nid), start,
1281 (this_end - start), BOOTMEM_DEFAULT);
1282 } else
1283 numadbg(" NO MATCH, advancing start to %lx\n",
1284 this_end);
1285
1286 start = this_end;
1287 }
1288 }
1289
1290 static void __init trim_reserved_in_node(int nid)
1291 {
1292 int i;
1293
1294 numadbg(" trim_reserved_in_node(%d)\n", nid);
1295
1296 for (i = 0; i < lmb.reserved.cnt; i++) {
1297 unsigned long start = lmb.reserved.region[i].base;
1298 unsigned long size = lmb_size_bytes(&lmb.reserved, i);
1299 unsigned long end = start + size;
1300
1301 reserve_range_in_node(nid, start, end);
1302 }
1303 }
1304
1305 static void __init bootmem_init_one_node(int nid)
1306 {
1307 struct pglist_data *p;
1308
1309 numadbg("bootmem_init_one_node(%d)\n", nid);
1310
1311 p = NODE_DATA(nid);
1312
1313 if (p->node_spanned_pages) {
1314 unsigned long paddr = node_masks[nid].bootmem_paddr;
1315 unsigned long end_pfn;
1316
1317 end_pfn = p->node_start_pfn + p->node_spanned_pages;
1318
1319 numadbg(" init_bootmem_node(%d, %lx, %lx, %lx)\n",
1320 nid, paddr >> PAGE_SHIFT, p->node_start_pfn, end_pfn);
1321
1322 init_bootmem_node(p, paddr >> PAGE_SHIFT,
1323 p->node_start_pfn, end_pfn);
1324
1325 numadbg(" free_bootmem_with_active_regions(%d, %lx)\n",
1326 nid, end_pfn);
1327 free_bootmem_with_active_regions(nid, end_pfn);
1328
1329 trim_reserved_in_node(nid);
1330
1331 numadbg(" sparse_memory_present_with_active_regions(%d)\n",
1332 nid);
1333 sparse_memory_present_with_active_regions(nid);
1334 }
1335 }
1336
1337 static unsigned long __init bootmem_init(unsigned long phys_base)
1338 {
1339 unsigned long end_pfn;
1340 int nid;
1341
1342 end_pfn = lmb_end_of_DRAM() >> PAGE_SHIFT;
1343 max_pfn = max_low_pfn = end_pfn;
1344 min_low_pfn = (phys_base >> PAGE_SHIFT);
1345
1346 if (bootmem_init_numa() < 0)
1347 bootmem_init_nonnuma();
1348
1349 /* XXX cpu notifier XXX */
1350
1351 for_each_online_node(nid)
1352 bootmem_init_one_node(nid);
1353
1354 sparse_init();
1355
1356 return end_pfn;
1357 }
1358
1359 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1360 static int pall_ents __initdata;
1361
1362 #ifdef CONFIG_DEBUG_PAGEALLOC
1363 static unsigned long __ref kernel_map_range(unsigned long pstart,
1364 unsigned long pend, pgprot_t prot)
1365 {
1366 unsigned long vstart = PAGE_OFFSET + pstart;
1367 unsigned long vend = PAGE_OFFSET + pend;
1368 unsigned long alloc_bytes = 0UL;
1369
1370 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1371 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1372 vstart, vend);
1373 prom_halt();
1374 }
1375
1376 while (vstart < vend) {
1377 unsigned long this_end, paddr = __pa(vstart);
1378 pgd_t *pgd = pgd_offset_k(vstart);
1379 pud_t *pud;
1380 pmd_t *pmd;
1381 pte_t *pte;
1382
1383 pud = pud_offset(pgd, vstart);
1384 if (pud_none(*pud)) {
1385 pmd_t *new;
1386
1387 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1388 alloc_bytes += PAGE_SIZE;
1389 pud_populate(&init_mm, pud, new);
1390 }
1391
1392 pmd = pmd_offset(pud, vstart);
1393 if (!pmd_present(*pmd)) {
1394 pte_t *new;
1395
1396 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1397 alloc_bytes += PAGE_SIZE;
1398 pmd_populate_kernel(&init_mm, pmd, new);
1399 }
1400
1401 pte = pte_offset_kernel(pmd, vstart);
1402 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1403 if (this_end > vend)
1404 this_end = vend;
1405
1406 while (vstart < this_end) {
1407 pte_val(*pte) = (paddr | pgprot_val(prot));
1408
1409 vstart += PAGE_SIZE;
1410 paddr += PAGE_SIZE;
1411 pte++;
1412 }
1413 }
1414
1415 return alloc_bytes;
1416 }
1417
1418 extern unsigned int kvmap_linear_patch[1];
1419 #endif /* CONFIG_DEBUG_PAGEALLOC */
1420
1421 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1422 {
1423 const unsigned long shift_256MB = 28;
1424 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1425 const unsigned long size_256MB = (1UL << shift_256MB);
1426
1427 while (start < end) {
1428 long remains;
1429
1430 remains = end - start;
1431 if (remains < size_256MB)
1432 break;
1433
1434 if (start & mask_256MB) {
1435 start = (start + size_256MB) & ~mask_256MB;
1436 continue;
1437 }
1438
1439 while (remains >= size_256MB) {
1440 unsigned long index = start >> shift_256MB;
1441
1442 __set_bit(index, kpte_linear_bitmap);
1443
1444 start += size_256MB;
1445 remains -= size_256MB;
1446 }
1447 }
1448 }
1449
1450 static void __init init_kpte_bitmap(void)
1451 {
1452 unsigned long i;
1453
1454 for (i = 0; i < pall_ents; i++) {
1455 unsigned long phys_start, phys_end;
1456
1457 phys_start = pall[i].phys_addr;
1458 phys_end = phys_start + pall[i].reg_size;
1459
1460 mark_kpte_bitmap(phys_start, phys_end);
1461 }
1462 }
1463
1464 static void __init kernel_physical_mapping_init(void)
1465 {
1466 #ifdef CONFIG_DEBUG_PAGEALLOC
1467 unsigned long i, mem_alloced = 0UL;
1468
1469 for (i = 0; i < pall_ents; i++) {
1470 unsigned long phys_start, phys_end;
1471
1472 phys_start = pall[i].phys_addr;
1473 phys_end = phys_start + pall[i].reg_size;
1474
1475 mem_alloced += kernel_map_range(phys_start, phys_end,
1476 PAGE_KERNEL);
1477 }
1478
1479 printk("Allocated %ld bytes for kernel page tables.\n",
1480 mem_alloced);
1481
1482 kvmap_linear_patch[0] = 0x01000000; /* nop */
1483 flushi(&kvmap_linear_patch[0]);
1484
1485 __flush_tlb_all();
1486 #endif
1487 }
1488
1489 #ifdef CONFIG_DEBUG_PAGEALLOC
1490 void kernel_map_pages(struct page *page, int numpages, int enable)
1491 {
1492 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1493 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1494
1495 kernel_map_range(phys_start, phys_end,
1496 (enable ? PAGE_KERNEL : __pgprot(0)));
1497
1498 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1499 PAGE_OFFSET + phys_end);
1500
1501 /* we should perform an IPI and flush all tlbs,
1502 * but that can deadlock->flush only current cpu.
1503 */
1504 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1505 PAGE_OFFSET + phys_end);
1506 }
1507 #endif
1508
1509 unsigned long __init find_ecache_flush_span(unsigned long size)
1510 {
1511 int i;
1512
1513 for (i = 0; i < pavail_ents; i++) {
1514 if (pavail[i].reg_size >= size)
1515 return pavail[i].phys_addr;
1516 }
1517
1518 return ~0UL;
1519 }
1520
1521 static void __init tsb_phys_patch(void)
1522 {
1523 struct tsb_ldquad_phys_patch_entry *pquad;
1524 struct tsb_phys_patch_entry *p;
1525
1526 pquad = &__tsb_ldquad_phys_patch;
1527 while (pquad < &__tsb_ldquad_phys_patch_end) {
1528 unsigned long addr = pquad->addr;
1529
1530 if (tlb_type == hypervisor)
1531 *(unsigned int *) addr = pquad->sun4v_insn;
1532 else
1533 *(unsigned int *) addr = pquad->sun4u_insn;
1534 wmb();
1535 __asm__ __volatile__("flush %0"
1536 : /* no outputs */
1537 : "r" (addr));
1538
1539 pquad++;
1540 }
1541
1542 p = &__tsb_phys_patch;
1543 while (p < &__tsb_phys_patch_end) {
1544 unsigned long addr = p->addr;
1545
1546 *(unsigned int *) addr = p->insn;
1547 wmb();
1548 __asm__ __volatile__("flush %0"
1549 : /* no outputs */
1550 : "r" (addr));
1551
1552 p++;
1553 }
1554 }
1555
1556 /* Don't mark as init, we give this to the Hypervisor. */
1557 #ifndef CONFIG_DEBUG_PAGEALLOC
1558 #define NUM_KTSB_DESCR 2
1559 #else
1560 #define NUM_KTSB_DESCR 1
1561 #endif
1562 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1563 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1564
1565 static void __init sun4v_ktsb_init(void)
1566 {
1567 unsigned long ktsb_pa;
1568
1569 /* First KTSB for PAGE_SIZE mappings. */
1570 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1571
1572 switch (PAGE_SIZE) {
1573 case 8 * 1024:
1574 default:
1575 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1576 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1577 break;
1578
1579 case 64 * 1024:
1580 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1581 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1582 break;
1583
1584 case 512 * 1024:
1585 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1586 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1587 break;
1588
1589 case 4 * 1024 * 1024:
1590 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1591 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1592 break;
1593 };
1594
1595 ktsb_descr[0].assoc = 1;
1596 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1597 ktsb_descr[0].ctx_idx = 0;
1598 ktsb_descr[0].tsb_base = ktsb_pa;
1599 ktsb_descr[0].resv = 0;
1600
1601 #ifndef CONFIG_DEBUG_PAGEALLOC
1602 /* Second KTSB for 4MB/256MB mappings. */
1603 ktsb_pa = (kern_base +
1604 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1605
1606 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1607 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1608 HV_PGSZ_MASK_256MB);
1609 ktsb_descr[1].assoc = 1;
1610 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1611 ktsb_descr[1].ctx_idx = 0;
1612 ktsb_descr[1].tsb_base = ktsb_pa;
1613 ktsb_descr[1].resv = 0;
1614 #endif
1615 }
1616
1617 void __cpuinit sun4v_ktsb_register(void)
1618 {
1619 unsigned long pa, ret;
1620
1621 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1622
1623 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1624 if (ret != 0) {
1625 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1626 "errors with %lx\n", pa, ret);
1627 prom_halt();
1628 }
1629 }
1630
1631 /* paging_init() sets up the page tables */
1632
1633 extern void central_probe(void);
1634
1635 static unsigned long last_valid_pfn;
1636 pgd_t swapper_pg_dir[2048];
1637
1638 static void sun4u_pgprot_init(void);
1639 static void sun4v_pgprot_init(void);
1640
1641 /* Dummy function */
1642 void __init setup_per_cpu_areas(void)
1643 {
1644 }
1645
1646 void __init paging_init(void)
1647 {
1648 unsigned long end_pfn, shift, phys_base;
1649 unsigned long real_end, i;
1650
1651 /* These build time checkes make sure that the dcache_dirty_cpu()
1652 * page->flags usage will work.
1653 *
1654 * When a page gets marked as dcache-dirty, we store the
1655 * cpu number starting at bit 32 in the page->flags. Also,
1656 * functions like clear_dcache_dirty_cpu use the cpu mask
1657 * in 13-bit signed-immediate instruction fields.
1658 */
1659
1660 /*
1661 * Page flags must not reach into upper 32 bits that are used
1662 * for the cpu number
1663 */
1664 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1665
1666 /*
1667 * The bit fields placed in the high range must not reach below
1668 * the 32 bit boundary. Otherwise we cannot place the cpu field
1669 * at the 32 bit boundary.
1670 */
1671 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1672 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1673
1674 BUILD_BUG_ON(NR_CPUS > 4096);
1675
1676 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1677 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1678
1679 sstate_booting();
1680
1681 /* Invalidate both kernel TSBs. */
1682 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1683 #ifndef CONFIG_DEBUG_PAGEALLOC
1684 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1685 #endif
1686
1687 if (tlb_type == hypervisor)
1688 sun4v_pgprot_init();
1689 else
1690 sun4u_pgprot_init();
1691
1692 if (tlb_type == cheetah_plus ||
1693 tlb_type == hypervisor)
1694 tsb_phys_patch();
1695
1696 if (tlb_type == hypervisor) {
1697 sun4v_patch_tlb_handlers();
1698 sun4v_ktsb_init();
1699 }
1700
1701 lmb_init();
1702
1703 /* Find available physical memory...
1704 *
1705 * Read it twice in order to work around a bug in openfirmware.
1706 * The call to grab this table itself can cause openfirmware to
1707 * allocate memory, which in turn can take away some space from
1708 * the list of available memory. Reading it twice makes sure
1709 * we really do get the final value.
1710 */
1711 read_obp_translations();
1712 read_obp_memory("reg", &pall[0], &pall_ents);
1713 read_obp_memory("available", &pavail[0], &pavail_ents);
1714 read_obp_memory("available", &pavail[0], &pavail_ents);
1715
1716 phys_base = 0xffffffffffffffffUL;
1717 for (i = 0; i < pavail_ents; i++) {
1718 phys_base = min(phys_base, pavail[i].phys_addr);
1719 lmb_add(pavail[i].phys_addr, pavail[i].reg_size);
1720 }
1721
1722 lmb_reserve(kern_base, kern_size);
1723
1724 find_ramdisk(phys_base);
1725
1726 if (cmdline_memory_size)
1727 lmb_enforce_memory_limit(phys_base + cmdline_memory_size);
1728
1729 lmb_analyze();
1730 lmb_dump_all();
1731
1732 set_bit(0, mmu_context_bmap);
1733
1734 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1735
1736 real_end = (unsigned long)_end;
1737 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1738 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1739 num_kernel_image_mappings);
1740
1741 /* Set kernel pgd to upper alias so physical page computations
1742 * work.
1743 */
1744 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1745
1746 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1747
1748 /* Now can init the kernel/bad page tables. */
1749 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1750 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1751
1752 inherit_prom_mappings();
1753
1754 init_kpte_bitmap();
1755
1756 /* Ok, we can use our TLB miss and window trap handlers safely. */
1757 setup_tba();
1758
1759 __flush_tlb_all();
1760
1761 if (tlb_type == hypervisor)
1762 sun4v_ktsb_register();
1763
1764 /* We must setup the per-cpu areas before we pull in the
1765 * PROM and the MDESC. The code there fills in cpu and
1766 * other information into per-cpu data structures.
1767 */
1768 real_setup_per_cpu_areas();
1769
1770 prom_build_devicetree();
1771
1772 if (tlb_type == hypervisor)
1773 sun4v_mdesc_init();
1774
1775 /* Once the OF device tree and MDESC have been setup, we know
1776 * the list of possible cpus. Therefore we can allocate the
1777 * IRQ stacks.
1778 */
1779 for_each_possible_cpu(i) {
1780 /* XXX Use node local allocations... XXX */
1781 softirq_stack[i] = __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
1782 hardirq_stack[i] = __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
1783 }
1784
1785 /* Setup bootmem... */
1786 last_valid_pfn = end_pfn = bootmem_init(phys_base);
1787
1788 #ifndef CONFIG_NEED_MULTIPLE_NODES
1789 max_mapnr = last_valid_pfn;
1790 #endif
1791 kernel_physical_mapping_init();
1792
1793 {
1794 unsigned long max_zone_pfns[MAX_NR_ZONES];
1795
1796 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1797
1798 max_zone_pfns[ZONE_NORMAL] = end_pfn;
1799
1800 free_area_init_nodes(max_zone_pfns);
1801 }
1802
1803 printk("Booting Linux...\n");
1804
1805 central_probe();
1806 cpu_probe();
1807 }
1808
1809 int __init page_in_phys_avail(unsigned long paddr)
1810 {
1811 int i;
1812
1813 paddr &= PAGE_MASK;
1814
1815 for (i = 0; i < pavail_ents; i++) {
1816 unsigned long start, end;
1817
1818 start = pavail[i].phys_addr;
1819 end = start + pavail[i].reg_size;
1820
1821 if (paddr >= start && paddr < end)
1822 return 1;
1823 }
1824 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1825 return 1;
1826 #ifdef CONFIG_BLK_DEV_INITRD
1827 if (paddr >= __pa(initrd_start) &&
1828 paddr < __pa(PAGE_ALIGN(initrd_end)))
1829 return 1;
1830 #endif
1831
1832 return 0;
1833 }
1834
1835 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
1836 static int pavail_rescan_ents __initdata;
1837
1838 /* Certain OBP calls, such as fetching "available" properties, can
1839 * claim physical memory. So, along with initializing the valid
1840 * address bitmap, what we do here is refetch the physical available
1841 * memory list again, and make sure it provides at least as much
1842 * memory as 'pavail' does.
1843 */
1844 static void setup_valid_addr_bitmap_from_pavail(void)
1845 {
1846 int i;
1847
1848 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1849
1850 for (i = 0; i < pavail_ents; i++) {
1851 unsigned long old_start, old_end;
1852
1853 old_start = pavail[i].phys_addr;
1854 old_end = old_start + pavail[i].reg_size;
1855 while (old_start < old_end) {
1856 int n;
1857
1858 for (n = 0; n < pavail_rescan_ents; n++) {
1859 unsigned long new_start, new_end;
1860
1861 new_start = pavail_rescan[n].phys_addr;
1862 new_end = new_start +
1863 pavail_rescan[n].reg_size;
1864
1865 if (new_start <= old_start &&
1866 new_end >= (old_start + PAGE_SIZE)) {
1867 set_bit(old_start >> 22,
1868 sparc64_valid_addr_bitmap);
1869 goto do_next_page;
1870 }
1871 }
1872
1873 prom_printf("mem_init: Lost memory in pavail\n");
1874 prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
1875 pavail[i].phys_addr,
1876 pavail[i].reg_size);
1877 prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
1878 pavail_rescan[i].phys_addr,
1879 pavail_rescan[i].reg_size);
1880 prom_printf("mem_init: Cannot continue, aborting.\n");
1881 prom_halt();
1882
1883 do_next_page:
1884 old_start += PAGE_SIZE;
1885 }
1886 }
1887 }
1888
1889 void __init mem_init(void)
1890 {
1891 unsigned long codepages, datapages, initpages;
1892 unsigned long addr, last;
1893 int i;
1894
1895 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1896 i += 1;
1897 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1898 if (sparc64_valid_addr_bitmap == NULL) {
1899 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1900 prom_halt();
1901 }
1902 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1903
1904 addr = PAGE_OFFSET + kern_base;
1905 last = PAGE_ALIGN(kern_size) + addr;
1906 while (addr < last) {
1907 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1908 addr += PAGE_SIZE;
1909 }
1910
1911 setup_valid_addr_bitmap_from_pavail();
1912
1913 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1914
1915 #ifdef CONFIG_NEED_MULTIPLE_NODES
1916 for_each_online_node(i) {
1917 if (NODE_DATA(i)->node_spanned_pages != 0) {
1918 totalram_pages +=
1919 free_all_bootmem_node(NODE_DATA(i));
1920 }
1921 }
1922 #else
1923 totalram_pages = free_all_bootmem();
1924 #endif
1925
1926 /* We subtract one to account for the mem_map_zero page
1927 * allocated below.
1928 */
1929 totalram_pages -= 1;
1930 num_physpages = totalram_pages;
1931
1932 /*
1933 * Set up the zero page, mark it reserved, so that page count
1934 * is not manipulated when freeing the page from user ptes.
1935 */
1936 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1937 if (mem_map_zero == NULL) {
1938 prom_printf("paging_init: Cannot alloc zero page.\n");
1939 prom_halt();
1940 }
1941 SetPageReserved(mem_map_zero);
1942
1943 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1944 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1945 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1946 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1947 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1948 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1949
1950 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1951 nr_free_pages() << (PAGE_SHIFT-10),
1952 codepages << (PAGE_SHIFT-10),
1953 datapages << (PAGE_SHIFT-10),
1954 initpages << (PAGE_SHIFT-10),
1955 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1956
1957 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1958 cheetah_ecache_flush_init();
1959 }
1960
1961 void free_initmem(void)
1962 {
1963 unsigned long addr, initend;
1964
1965 /*
1966 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1967 */
1968 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1969 initend = (unsigned long)(__init_end) & PAGE_MASK;
1970 for (; addr < initend; addr += PAGE_SIZE) {
1971 unsigned long page;
1972 struct page *p;
1973
1974 page = (addr +
1975 ((unsigned long) __va(kern_base)) -
1976 ((unsigned long) KERNBASE));
1977 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1978 p = virt_to_page(page);
1979
1980 ClearPageReserved(p);
1981 init_page_count(p);
1982 __free_page(p);
1983 num_physpages++;
1984 totalram_pages++;
1985 }
1986 }
1987
1988 #ifdef CONFIG_BLK_DEV_INITRD
1989 void free_initrd_mem(unsigned long start, unsigned long end)
1990 {
1991 if (start < end)
1992 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1993 for (; start < end; start += PAGE_SIZE) {
1994 struct page *p = virt_to_page(start);
1995
1996 ClearPageReserved(p);
1997 init_page_count(p);
1998 __free_page(p);
1999 num_physpages++;
2000 totalram_pages++;
2001 }
2002 }
2003 #endif
2004
2005 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2006 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2007 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2008 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2009 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2010 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2011
2012 pgprot_t PAGE_KERNEL __read_mostly;
2013 EXPORT_SYMBOL(PAGE_KERNEL);
2014
2015 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2016 pgprot_t PAGE_COPY __read_mostly;
2017
2018 pgprot_t PAGE_SHARED __read_mostly;
2019 EXPORT_SYMBOL(PAGE_SHARED);
2020
2021 pgprot_t PAGE_EXEC __read_mostly;
2022 unsigned long pg_iobits __read_mostly;
2023
2024 unsigned long _PAGE_IE __read_mostly;
2025 EXPORT_SYMBOL(_PAGE_IE);
2026
2027 unsigned long _PAGE_E __read_mostly;
2028 EXPORT_SYMBOL(_PAGE_E);
2029
2030 unsigned long _PAGE_CACHE __read_mostly;
2031 EXPORT_SYMBOL(_PAGE_CACHE);
2032
2033 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2034
2035 #define VMEMMAP_CHUNK_SHIFT 22
2036 #define VMEMMAP_CHUNK (1UL << VMEMMAP_CHUNK_SHIFT)
2037 #define VMEMMAP_CHUNK_MASK ~(VMEMMAP_CHUNK - 1UL)
2038 #define VMEMMAP_ALIGN(x) (((x)+VMEMMAP_CHUNK-1UL)&VMEMMAP_CHUNK_MASK)
2039
2040 #define VMEMMAP_SIZE ((((1UL << MAX_PHYSADDR_BITS) >> PAGE_SHIFT) * \
2041 sizeof(struct page *)) >> VMEMMAP_CHUNK_SHIFT)
2042 unsigned long vmemmap_table[VMEMMAP_SIZE];
2043
2044 int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
2045 {
2046 unsigned long vstart = (unsigned long) start;
2047 unsigned long vend = (unsigned long) (start + nr);
2048 unsigned long phys_start = (vstart - VMEMMAP_BASE);
2049 unsigned long phys_end = (vend - VMEMMAP_BASE);
2050 unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2051 unsigned long end = VMEMMAP_ALIGN(phys_end);
2052 unsigned long pte_base;
2053
2054 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2055 _PAGE_CP_4U | _PAGE_CV_4U |
2056 _PAGE_P_4U | _PAGE_W_4U);
2057 if (tlb_type == hypervisor)
2058 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2059 _PAGE_CP_4V | _PAGE_CV_4V |
2060 _PAGE_P_4V | _PAGE_W_4V);
2061
2062 for (; addr < end; addr += VMEMMAP_CHUNK) {
2063 unsigned long *vmem_pp =
2064 vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2065 void *block;
2066
2067 if (!(*vmem_pp & _PAGE_VALID)) {
2068 block = vmemmap_alloc_block(1UL << 22, node);
2069 if (!block)
2070 return -ENOMEM;
2071
2072 *vmem_pp = pte_base | __pa(block);
2073
2074 printk(KERN_INFO "[%p-%p] page_structs=%lu "
2075 "node=%d entry=%lu/%lu\n", start, block, nr,
2076 node,
2077 addr >> VMEMMAP_CHUNK_SHIFT,
2078 VMEMMAP_SIZE >> VMEMMAP_CHUNK_SHIFT);
2079 }
2080 }
2081 return 0;
2082 }
2083 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2084
2085 static void prot_init_common(unsigned long page_none,
2086 unsigned long page_shared,
2087 unsigned long page_copy,
2088 unsigned long page_readonly,
2089 unsigned long page_exec_bit)
2090 {
2091 PAGE_COPY = __pgprot(page_copy);
2092 PAGE_SHARED = __pgprot(page_shared);
2093
2094 protection_map[0x0] = __pgprot(page_none);
2095 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2096 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2097 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2098 protection_map[0x4] = __pgprot(page_readonly);
2099 protection_map[0x5] = __pgprot(page_readonly);
2100 protection_map[0x6] = __pgprot(page_copy);
2101 protection_map[0x7] = __pgprot(page_copy);
2102 protection_map[0x8] = __pgprot(page_none);
2103 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2104 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2105 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2106 protection_map[0xc] = __pgprot(page_readonly);
2107 protection_map[0xd] = __pgprot(page_readonly);
2108 protection_map[0xe] = __pgprot(page_shared);
2109 protection_map[0xf] = __pgprot(page_shared);
2110 }
2111
2112 static void __init sun4u_pgprot_init(void)
2113 {
2114 unsigned long page_none, page_shared, page_copy, page_readonly;
2115 unsigned long page_exec_bit;
2116
2117 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2118 _PAGE_CACHE_4U | _PAGE_P_4U |
2119 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2120 _PAGE_EXEC_4U);
2121 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2122 _PAGE_CACHE_4U | _PAGE_P_4U |
2123 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2124 _PAGE_EXEC_4U | _PAGE_L_4U);
2125 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
2126
2127 _PAGE_IE = _PAGE_IE_4U;
2128 _PAGE_E = _PAGE_E_4U;
2129 _PAGE_CACHE = _PAGE_CACHE_4U;
2130
2131 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2132 __ACCESS_BITS_4U | _PAGE_E_4U);
2133
2134 #ifdef CONFIG_DEBUG_PAGEALLOC
2135 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
2136 0xfffff80000000000;
2137 #else
2138 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2139 0xfffff80000000000;
2140 #endif
2141 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2142 _PAGE_P_4U | _PAGE_W_4U);
2143
2144 /* XXX Should use 256MB on Panther. XXX */
2145 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2146
2147 _PAGE_SZBITS = _PAGE_SZBITS_4U;
2148 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2149 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2150 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2151
2152
2153 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2154 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2155 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2156 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2157 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2158 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2159 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2160
2161 page_exec_bit = _PAGE_EXEC_4U;
2162
2163 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2164 page_exec_bit);
2165 }
2166
2167 static void __init sun4v_pgprot_init(void)
2168 {
2169 unsigned long page_none, page_shared, page_copy, page_readonly;
2170 unsigned long page_exec_bit;
2171
2172 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2173 _PAGE_CACHE_4V | _PAGE_P_4V |
2174 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2175 _PAGE_EXEC_4V);
2176 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2177 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
2178
2179 _PAGE_IE = _PAGE_IE_4V;
2180 _PAGE_E = _PAGE_E_4V;
2181 _PAGE_CACHE = _PAGE_CACHE_4V;
2182
2183 #ifdef CONFIG_DEBUG_PAGEALLOC
2184 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2185 0xfffff80000000000;
2186 #else
2187 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2188 0xfffff80000000000;
2189 #endif
2190 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2191 _PAGE_P_4V | _PAGE_W_4V);
2192
2193 #ifdef CONFIG_DEBUG_PAGEALLOC
2194 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2195 0xfffff80000000000;
2196 #else
2197 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2198 0xfffff80000000000;
2199 #endif
2200 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2201 _PAGE_P_4V | _PAGE_W_4V);
2202
2203 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2204 __ACCESS_BITS_4V | _PAGE_E_4V);
2205
2206 _PAGE_SZBITS = _PAGE_SZBITS_4V;
2207 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2208 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2209 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2210 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2211
2212 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2213 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2214 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2215 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2216 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2217 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2218 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2219
2220 page_exec_bit = _PAGE_EXEC_4V;
2221
2222 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2223 page_exec_bit);
2224 }
2225
2226 unsigned long pte_sz_bits(unsigned long sz)
2227 {
2228 if (tlb_type == hypervisor) {
2229 switch (sz) {
2230 case 8 * 1024:
2231 default:
2232 return _PAGE_SZ8K_4V;
2233 case 64 * 1024:
2234 return _PAGE_SZ64K_4V;
2235 case 512 * 1024:
2236 return _PAGE_SZ512K_4V;
2237 case 4 * 1024 * 1024:
2238 return _PAGE_SZ4MB_4V;
2239 };
2240 } else {
2241 switch (sz) {
2242 case 8 * 1024:
2243 default:
2244 return _PAGE_SZ8K_4U;
2245 case 64 * 1024:
2246 return _PAGE_SZ64K_4U;
2247 case 512 * 1024:
2248 return _PAGE_SZ512K_4U;
2249 case 4 * 1024 * 1024:
2250 return _PAGE_SZ4MB_4U;
2251 };
2252 }
2253 }
2254
2255 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2256 {
2257 pte_t pte;
2258
2259 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2260 pte_val(pte) |= (((unsigned long)space) << 32);
2261 pte_val(pte) |= pte_sz_bits(page_size);
2262
2263 return pte;
2264 }
2265
2266 static unsigned long kern_large_tte(unsigned long paddr)
2267 {
2268 unsigned long val;
2269
2270 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2271 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2272 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2273 if (tlb_type == hypervisor)
2274 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2275 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2276 _PAGE_EXEC_4V | _PAGE_W_4V);
2277
2278 return val | paddr;
2279 }
2280
2281 /* If not locked, zap it. */
2282 void __flush_tlb_all(void)
2283 {
2284 unsigned long pstate;
2285 int i;
2286
2287 __asm__ __volatile__("flushw\n\t"
2288 "rdpr %%pstate, %0\n\t"
2289 "wrpr %0, %1, %%pstate"
2290 : "=r" (pstate)
2291 : "i" (PSTATE_IE));
2292 if (tlb_type == hypervisor) {
2293 sun4v_mmu_demap_all();
2294 } else if (tlb_type == spitfire) {
2295 for (i = 0; i < 64; i++) {
2296 /* Spitfire Errata #32 workaround */
2297 /* NOTE: Always runs on spitfire, so no
2298 * cheetah+ page size encodings.
2299 */
2300 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2301 "flush %%g6"
2302 : /* No outputs */
2303 : "r" (0),
2304 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2305
2306 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2307 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2308 "membar #Sync"
2309 : /* no outputs */
2310 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2311 spitfire_put_dtlb_data(i, 0x0UL);
2312 }
2313
2314 /* Spitfire Errata #32 workaround */
2315 /* NOTE: Always runs on spitfire, so no
2316 * cheetah+ page size encodings.
2317 */
2318 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2319 "flush %%g6"
2320 : /* No outputs */
2321 : "r" (0),
2322 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2323
2324 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2325 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2326 "membar #Sync"
2327 : /* no outputs */
2328 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2329 spitfire_put_itlb_data(i, 0x0UL);
2330 }
2331 }
2332 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2333 cheetah_flush_dtlb_all();
2334 cheetah_flush_itlb_all();
2335 }
2336 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2337 : : "r" (pstate));
2338 }
x86 "subsystem" repository